ispLeverCORETM IP Module Evaluation Tutorial Table Of Contents Getting Started................................................................................................................................. 2 Evaluation Pack Directory Structure................................................................................................ 3 Evaluation Tutorial Flow .................................................................................................................. 4 Instantiating the Evaluation Core..................................................................................................... 5 Running Functional Simulation Using ModelSim ............................................................................ 6 Running Synthesis Using Synplify................................................................................................... 6 Running Synthesis Using LeonardoSpectrum................................................................................. 7 Implementing the IP Module Using ispLEVER ................................................................................ 7 Purchasing an ispLeverCORE......................................................................................................... 9 Getting Technical Assistance ........................................................................................................ 15 (c) 2003 Lattice Semiconductor ispLeverCORE Module IP Evaluation Tutorial Getting Started Lattice's ispLeverCORETM IP modules are large, modular design blocks that can be reused and easily placed within your programmable logic design. This tutorial is designed to help you evaluate and purchase the IP module package you have chosen as quickly as possible. Admittedly, it is brief and intended for users that are familiar with all the required tools and processes. If you need a more detailed tutorial, please view it from the Lattice website. Online Version An online version of this tutorial is available from the Lattice website. A more detailed tutorial is also available on the Lattice website. (http://www.latticesemi.com/products/devtools/ip/eval_flow.cfm) Supported Technologies Lattice ispLeverCORE IP modules are available for CPLD, ispXPGA, ORCA4 FPGA, and ORCA FPSC technologies. This tutorial is written to support all device technologies, with differences noted where important. Directory Path Description To accommodate all ispLeverCORE IP module download packages, the directory paths are described as <variables>. For example, the actual directory path for the Reed-Solomon Encoder for an ORCA4 device is: reeds_enco_o4_1_004\orca4\ver1\source However, the path name in the tutorial would be represented as: <download_name>\<device>\<version>\source (c) 2003 Lattice Semiconductor 2 ispLeverCORE Module IP Evaluation Tutorial Evaluation Pack Directory Structure The directory structure for the Lattice ispLeverCORE evaluation package is shown below and includes the basic description of the contents. <download_name> | |--\readme.htm (Contains specific instructions for using the ispLeverCORE.) |--\default.css (Style sheet for the readme file) | |--\<device> | |--\<version> | |--source Contents: | (1) Verilog or VHDL top-level source files for instantiation and synthesis | (2) Parameter file(s) that contain IP-specific configuration values | |--\eval (Customer RTL functional simulation directory for evaluation) | | | |--\testbench Contents: testbench for evaluation | | | |--\tests Contents: Stimulus file(s) | | | |--\simulation (Run/execute functional RTL simulation here. | Example: do script\runsim_rtl.do) | | | |--\scripts Contents: ModelSim macro (*.do) to run simulation | |--\gui_script Contents: module_gen.zip See Note below) | |--\par Contents: | (1) .lpc file specifying IP module configuration | (2) One of the following database/constraint file pairs: | ispXPGA - .ld2 database file and .lct constraint file | ORCA 4 - .ngo or .nmc database file and .prf constraint file | ispXPLD - .bl1 database file and .lct constraint file | |--\lib | |--\modelsim | |--\work (Compiled simulation models for ModelSim) (c) 2003 Lattice Semiconductor 3 ispLeverCORE Module IP Evaluation Tutorial Note: If the gui_script\module_gen.zip file is present in this release package, it is because the ispLEVER software does not contain the utility that allows for the configuration of this specific IP module using the Module/IP Manager. The gui_script\module_gen.zip file contains a directory of files that allows for the configuration of this IP module using the Module/IP Manager. To configure the IP module using the ispLEVER Module/IP Manager: 1. Go to the directory in where the ispLEVER software is installed, for example C:\ispTOOLS. 2. Unzipped the module_gen.zip file into the \ispcpld folder. 3. If the ispLEVER Project Navigator is open, exit and rerun the tool. The IP module will be included in the list when the Module/IP Manager is run. Evaluation Tutorial Flow You must run this tutorial in its organized sequence. The only flow option is the synthesis tool you are using. (c) 2003 Lattice Semiconductor 4 ispLeverCORE Module IP Evaluation Tutorial Instantiating the Evaluation Core The IP module evaluation package includes a top-level RTL source (Verilog or VHDL) that can be used as an instantiation template for the IP core. Verilog Designs To instantiate a Verilog module: 1. Using a text editor, open your top-level design file. 2. Open the top-level RTL source located in the \source directory of the Evaluation Pack and copy the contents into your top-level design. 3. Connect the ports to the IP module by replacing the default port names in the I/O section of the instantiation template with the actual port names from your design. Note: If the top-level RTL source in the package contains any instantiated PLL and/or specific I/O types, those modules must also be instantiated in your top-level design. 4. Save your top-level design file. Note: If you want to check the core implementation result for core evaluation purposes, the included top-level RTL source can be used as your top-level design without modification. VHDL Designs To instantiate a VHDL module: 1. Using a text editor, open your top-level design file. 2. Open the top-level RTL source located in the \source directory of the Evaluation Pack and copy the contents into your top-level design. 3. Connect the ports to the IP module by replacing the default port names in the I/O section of the instantiation template with the actual port names from your design. Note: If the top-level RTL source in the package contains any instantiated PLL and/or specific I/O types, those modules must also be instantiated in your top-level design. 4. Include attribute statements for Synplify or Leonardo Spectrum synthesis by typing one of the following, depending upon the synthesis tool you have chosen: ----------------This is an attribute for Synplify-------------------attribute syn_black_box: boolean; attribute syn_black_box of <module_component>: component is true; -----------------------------------------------------------------------------------This is an attribute for Leonardo Spectrum-------------------attribute noopt: boolean; attribute noopt of <module_component>: component is true; --------------------------------------------------------------------5. Save your top-level design file. Note: If you want to check the core implementation result for evaluation purposes, you can use the included top-level RTL source as your top-level design without modification. (c) 2003 Lattice Semiconductor 5 ispLeverCORE Module IP Evaluation Tutorial Running Functional Simulation Using ModelSim A simulation script file is provided in the eval directory for functional RTL simulation. The script file <modelsim_macro_name>.do uses pre-compiled models provided with this package. The pre-compiled library of models are located in the directory <download_name>\<device>\<version>\lib\modelsim\work. Note: This procedure is applicable ONLY when using ModelSim SE for simulation. The Lattice Edition of ModelSim that comes with the ispLEVER software does not support the pre-compiled models necessary for functional simulation. To run functional simulation using ModelSim: 1. Open ModelSim. 2. Choose File > Change Directory and go to the <download_name>\<device>\<version>\eval\simulation directory. 3. Run the ModelSim DO (macro) file: ! If you are running version 5.5e or earlier, choose Macro > Execute Macro and select the file: scripts\<modelsim_macro_name>.do. ! If you are running version 5.6a or later, choose Tools > Execute Macro and select the file: scripts\<modelsim_macro_name>.do. The ModelSim macro executes an evaluation testbench designed to show some example transactions or functions associated with the core. Using the precompiled libraries, you can build your own testbenches. 4. View the waveform results in the Wave window. Running Synthesis Using Synplify This procedure shows you how to use Synplicity's Synplify outside the ispLEVER Project Navigator to synthesize your ispLeverCORE IP module and create an EDIF file. Note: For implementation instructions, please refer to the readme.htm file for the specific core that you want to evaluate. To run synthesis using Synplify: 1. Create a new working directory for synthesis. 2. Open Synplify. 3. Add the design files specified in your IP download readme.htm file. 4. Set the Implementation Options that are specified in your IP download readme.htm file. 5. Click Run to generate an EDIF file. Note: For more detailed information, refer to the Synplify for Lattice User Guide and the ispLEVER online Help and tutorials. (c) 2003 Lattice Semiconductor 6 ispLeverCORE Module IP Evaluation Tutorial Running Synthesis Using LeonardoSpectrum This procedure shows you how to use Mentor Graphics LeonardoSpectrum outside the ispLEVER Project Navigator to synthesize your ispLeverCORE IP module and create an EDIF file. Note: For implementation instructions, please refer to the readme.htm file for the specific core that you want to evaluate. To run synthesis using LeonardoSpectrum: 1. Open LeonardoSpectrum. 2. Select the target device and options specified in your IP download readme.htm file. 3. Set the Working Directory path pointing to the <download_name>\<device>\<version>\source directory. 4. Add the design files specified in your IP download readme.htm file. 5. Set any other options that are specified in your IP download readme.htm file. 6. Click Run Flow to generate an EDIF file. Note: For more detailed information, refer to the LeonardoSpectrum for Lattice User's Manual and the ispLEVER online Help and tutorials. Implementing the IP Module Using ispLEVER This procedure shows you how to implement the IP module using the ispLEVER Project Navigator and read the timing report. Note: For implementation instructions, please refer to the readme.htm file for the specific core that you want to evaluate. To implement the IP module and generate the timing report: 1. Open ispLEVER and create an EDIF project in a new place & route directory. 2. Select the target device specified in your IP download readme.htm file (same as you used for synthesis). 3. Delete the existing constraint file. This is the constraint file that was created when the new project was started. Constraint File Note: CPLD = .lct XPGA = .lct ORGA FPGA = .prf For new CPLD and ispXPGA projects, the ispLEVER software creates a temporary constraint file (.lct), which is a working copy of the project constraint file (.lci) and used to specify constraints such as location and path delay information in a textual form. The ispLEVER software uses the LCT file when placing and routing the design. When you save the design (File > Save), the contents of the LCT file are saved to the LCI file. ORCA devices use a preference file (.prf), which contains preferences (placement, routing, and/or timing constraints) specified during design entry and preferences added by the user. The PRF file is an optional input to the MAP, PAR, EPIC, and TRACE processes. (c) 2003 Lattice Semiconductor 7 ispLeverCORE Module IP Evaluation Tutorial 4. Copy the evaluation database and the constraint files from the <download_name>\<device>\<version>\par directory to your place & route directory. These files are specified in your IP download readme.htm file Database Note: CPLD = .bl1 ispXPGA = .ld2 ORCA FPGA = .ngo, .nmc The BL1 file is the initial CPLD database file. The LD2 file is a post-pack database file generated by running the Pack & Place Design process in the Project Navigator. The NGO file contains all of the data in the input NGD (pre-map logical database) file as well as information in the NCD (post-map physical database) file produced by mapping. The NMC file is an EPIC physical macro file that contains placement and routing information as well as component and net information. 5. Rename the copied constraint file to the same name as your project. For example, if your project is named "demo.syn," then the constraint file must be named demo.lct or demo.prf. 6. Choose Source > Import and select the EDIF netlist file. For CPLD Devices 7. Double-click the Timing Report process to open the Timing Report. 8. You are finished with the evaluation tutorial. For ispXPGA Devices 7. Double-click the Post-Route Timing Report process to open the Timing Report. 8. You are finished with the evaluation tutorial. For ORCA Devices 7. Choose Tools > Timing Checkpoint Options and set the options as specified in your IP download readme.htm file. 8. Select the Place & Route Design process, right-click to open the Properties dialog box, and then set the properties as specified in your IP download readme.htm file. 9. Double-click the Place & Route Trace Report process to run place and route and to open the Timing Report. Note: For some ORCA4 ispLeverCOREs, the Cycle Stealing Process may be required to achieve the required timing specification. Check the ispLeverCORE Readme file to see if this additional process step is necessary. 10. When you open the timing report, it is possible that you will see some timing violations due to over-constrains. Do the following steps to obtain a correct timing report: ! Copy the preference file (usually referred to as post_route_trace.prf) that is located in the \par directory to the place & route directory (step 1). ! Open a DOS command window and change its directory to the place & route directory (step 1). ! Type: trce -v 1 -c -o post_route_trace.twr <your project_name>.ncd post_route_trace.prf. ! The new timing report is generated in the post_route_trace.twr file. 11. You are finished with the evaluation tutorial. (c) 2003 Lattice Semiconductor 8 ispLeverCORE Module IP Evaluation Tutorial Purchasing an ispLeverCORE If you are satisfied with the results of the evaluation you may purchase Lattice's ispLeverCORE Intellectual Property modules from our online store. The process is easy and safe, using our secure transaction servers. Lattice's ispLeverCORE IP modules are sold in either bitstream format (for part numbers ending in "B"), or 1 configuration of a post-synthesis, gate-level netlist (part numbers ending in ("N"). Each ispLeverCORE is sold with 1 year or 10 hours of technical support, whichever comes first. Extended service contracts are also available. After going to the Lattice Online Store, in general you will follow these steps: 1. Scroll to the Intellectual Property (IP) section of the web page, identify the IP module that you want to purchase, specify the quantity, and then click Add to Cart. Follow the onscreen instructions to continue purchasing. 2. Review, sign, and fax the license agreement to Lattice and choose the method for delivery. 3. Select the parameters for your IP module and send us the configuration file. After Purchasing After you have purchased and licensed your ispLeverCORE, you can continue the implementation and programming flow. You will be able to perform full timing simulation and generate a bitstream file for programming your Lattice device. Configuring your ispLeverCORE You can use Lattice's Module/IP Manager tool (included with Lattice's ispLEVER software) to specify the IP module parameter settings. This will generate a Lattice Parameter Configuration file (.lpc). You must send us this LPC file before we can send you your configured IP module. Please send it to the Lattice location listed in the confirmation e-mail. As soon as we get this file, we will e-mail you a confirmation of receipt and a scheduled ship date. The Lattice IP parameterization tool, Module/IP Manager, is incorporated in the ispLEVER software. It provides a GUI for entering the required parameters to configure the core. After all required parameters have been entered, the following file are generated: ! Parameter file (<IPname>.lpc) This file contains the configuration parameters you entered via the Module/IP Manager GUI. Usually the Module/IP Manager is run from the ispLEVER Project Navigator. However, for generating your IP module configuration file, you will run the Module/IP Manager in standalone mode. Note: This procedure uses the Reed-Solomon Encoder for a Verilog design implemented in a Lattice ORCA 4 device as an example. Your specific settings will be different. (c) 2003 Lattice Semiconductor 9 ispLeverCORE Module IP Evaluation Tutorial To use the Module/IP Manager to generate an LPC file: 1. Go to the directory where your Module/IP Manager application is installed, for example: <isplever_install_path>\ispcpld\bin 2. Double-click ispmg.exe. (c) 2003 Lattice Semiconductor 10 ispLeverCORE Module IP Evaluation Tutorial 3. In the Open Project dialog box, do the following: * Select To start a new design. * Set the directory path for the Lattice Parameter Configuration file (.lpc). This can be any location. * Select the netlist format. * Select your target device. (c) 2003 Lattice Semiconductor 11 ispLeverCORE Module IP Evaluation Tutorial 4. Click Continue to load your selections into the Module/IP Manager and open the GUI. In the GUI, do the following: ! Expand tree for the device family you have selected and select the IP module that you want to configure and purchase. ! Under Module Name, type a name for your IP module. This can be any name you choose. Special characters are allowed. (c) 2003 Lattice Semiconductor 12 ispLeverCORE Module IP Evaluation Tutorial 5. Click Customize to open the configuration screen for your chosen IP module. Set the desires options and then click Generate. (c) 2003 Lattice Semiconductor 13 ispLeverCORE Module IP Evaluation Tutorial The Module/IP Manager generates the Lattice Parameter Configuration file to the specified location. You must send us this LPC file before we can send you your configured IP module. Please send it to the Lattice location listed in the confirmation e-mail. As soon as we get this file, we will e-mail you a confirmation of receipt and a scheduled ship date. (c) 2003 Lattice Semiconductor 14 ispLeverCORE Module IP Evaluation Tutorial Getting Technical Assistance For technical assistance, please contact Lattice Applications at: Hotline 1-800-LATTICE (Domestic) 1-408-826-6002 (International) E-mail techsupport@latticesemi.com Internet http://www.latticesemi.com Evaluating Other IP Modules To evaluate IP module configurations that are not included in the Evaluation Packages, contact your local Lattice sales office. (c) 2003 Lattice Semiconductor 15