See mechanical drawings for dimensions.
DBV PACKAGE
(TOP VIEW)
2
GND VCC
5
34
B1 A
6
1
B2 S
DCK PACKAGE
(TOP VIEW)
34
B1
2
GND
A
5
1
B2
VCC
6S
DRL PACKAGE
(TOP VIEW)
2
GND VCC
5
1
B2
34
B1 A
6S
YZP PACKAGE
(BOTTOM VIEW)
VCC
GND
B2
B1
2
1
3A
5
4
6S
DRY PACKAGE
(TOP VIEW)
GND VCC
B2 6
5
4
2
3
B1 A
S
1C1
B1
A1
C2
B2
A2
B2
B1
DSF PACKAGE
(TOP VIEW)
GND
S
A
VCC
6
5
4
2
3
1
SN74LVC1G3157
www.ti.com
SCES424H JANUARY 2003REVISED MAY 2012
SINGLE-POLE DOUBLE-THROW ANALOG SWITCH
Check for Samples: SN74LVC1G3157
1FEATURES Low On-State Resistance, Typically 6
(VCC = 4.5 V)
2 1.65-V to 5.5-V VCC Operation Latch-Up Performance Exceeds 100 mA Per
Useful for Both Analog and Digital JESD 78, Class II
Applications ESD Protection Exceeds JESD 22
Specified Break-Before-Make Switching 2000-V Human-Body Model (A114-A)
Rail-to-Rail Signal Handling 200-V Machine Model (A115-A)
High Degree of Linearity 1000-V Charged-Device Model (C101)
High Speed, Typically 0.5 ns
(VCC =3V,CL= 50 pF)
DESCRIPTION/ORDERING INFORMATION
This single-pole double-throw (SPDT) analog switch is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G3157 can handle both analog and digital signals. The device permits signals with amplitudes of
up to VCC (peak) to be transmitted in either direction.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for
analog-to-digital and digital-to-analog conversion systems.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2003–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
B2
S
1
4
6
A
3
B1
SN74LVC1G3157
SCES424H JANUARY 2003REVISED MAY 2012
www.ti.com
ORDERING INFORMATION
TAPACKAGE(1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING(3)
NanoFree™ WCSP (DSBGA) Reel of 3000 SN74LVC1G3157YZPR _ _ _ C5_
0.23-mm Large Bump YZP (Pb-free)
SON DRY Reel of 5000 SN74LVC1G3157DRYR C5
SON DSF Reel of 5000 SN74LVC1G3157DSFR C5
–40°C to 85°C SOT (SOT-23) DBV Reel of 3000 SN74LVC1G3157DBVR CC5_
SOT (SC-70) DCK Reel of 3000 SN74LVC1G3157DCKR C5_
SOT (SOT-553) DRL Reel of 4000 SN74LVC1G3157DRLR C5_
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(3) DBV/DCK/DRL/DRY: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
Table 1. FUNCTION TABLE
CONTROL ON
INPUT CHANNEL
S
L B1
H B2
LOGIC DIAGRAM (POSITIVE LOGIC)
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SCES424H JANUARY 2003REVISED MAY 2012
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VCC Supply voltage range(2) –0.5 6.5 V
VIN Control input voltage range(2) (3) –0.5 6.5 V
VI/O Switch I/O voltage range(2) (3) (4) (5) –0.5 VCC + 0.5 V
IIK Control input clamp current VIN < 0 –50 mA
II/O I/O port diode current VI/O < 0 or VI/O > VCC ±50 mA
II/O On-state switch current(6) VI/O = 0 to VCC ±128 mA
Continuous current through VCC or GND ±100 mA
DBV package 165
DCK package 259
θJA Package thermal impedance(7) DRL package 142 °C/W
DRY package 234
YZP package 123
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground unless otherwise specified.
(3) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(4) This value is limited to 5.5 V maximum.
(5) VI, VO, VA, and VBn are used to denote specific conditions for VI/O.
(6) II, IO, IA, and IBn are used to denote specific conditions for II/O.
(7) The package thermal impedance is calculated in accordance with JESD 51-7.
Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback 3
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SCES424H JANUARY 2003REVISED MAY 2012
www.ti.com
Recommended Operating Conditions(1)
MIN MAX UNIT
VCC Supply voltage 1.65 5.5 V
VI/O Switch input/output voltage 0 VCC V
VIN Control input voltage 0 5.5 V
VCC = 1.65 V to 1.95 V VCC × 0.75
VIH High-level input voltage, control input V
VCC = 2.3 V to 5.5 V VCC × 0.7
VCC = 1.65 V to 1.95 V VCC × 0.25
VIL Low-level input voltage, control input V
VCC = 2.3 V to 5.5 V VCC × 0.3
VCC = 1.65 V to 1.95 V 20
VCC = 2.3 V to 2.7 V 20
Δt/Δv Input transition rise or fall rate ns/V
VCC = 3 V to 3.6 V 10
VCC= 4.5 V to 5.5 V 10
TAOperating free-air temperature –40 85 °C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT
VI= 0 V IO= 4 mA 11 20
1.65 V
VI= 1.65 V IO= –4 mA 15 50
VI= 0 V IO= 8 mA 8 12
2.3 V
VI= 2.3 V IO= –8 mA 11 30
See Figure 1
ron On-state switch resistance(2) VI= 0 V IO= 24 mA 7 9
and Figure 2 3 V
VI= 3 V IO= –24 mA 9 20
VI= 0 V IO= 30 mA 6 7
VI= 2.4 V IO= –30 mA 4.5 V 7 12
VI= 4.5 V IO= –30 mA 7 15
IA= –4 mA 1.65 V 140
IA= –8 mA 2.3 V 45
On-state switch resistance 0 VBn VCC
rrange
over signal range(2) (3) (see Figure 1 and Figure 2)IA= –24 mA 3 V 18
IA= –30 mA 4.5 V 10
VBn = 1.15 V IA= –4 mA 1.65 V 0.5
Difference of on-state VBn = 1.6 V IA= –8 mA 2.3 V 0.1
Δron resistance between See Figure 1
VBn = 2.1 V IA= 24 mA 3 V 0.1
switches(2) (4) (5)
VBn = 3.15 V IA= –30 mA 4.5 V 0.1
IA= –4 mA 1.65 V 110
IA= –8 mA 2.3 V 26
ron(flat) ON resistance flatness(2) (4) (6) 0VBn VCC
IA= –24 mA 3 V 9
IA= –30 mA 4.5 V 4 ±1
Off-state switch leakage 1.65 V to
Ioff (7) 0VI, VOVCC (see Figure 3 )μA
current 5.5 V ±0.05 ±1(1)
(1) TA= 25°C
(2) Measured by the voltage drop between I/O pins at the indicated current through the switch. On-state resistance is determined by the
lower of the voltages on the two (A or B) ports.
(3) Specified by design
(4) Δron = ron(max) ron(min) measured at identical VCC, temperature, and voltage levels
(5) This parameter is characterized, but not production tested.
(6) Flatness is defined as the difference between the maximum and minimum values of on-state resistance over the specified range of
conditions.
(7) Ioff is the same as IS(off) (off-state switch leakage current).
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SCES424H JANUARY 2003REVISED MAY 2012
Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT
±1
On-state switch leakage VI= VCC or GND, VO= Open
IS(on) 5.5 V μA
current (see Figure 4)±0.1(1)
±1
0 V to
IIN Control input current 0 VIN VCC μA
5.5 V ±0.05 ±1(1)
ICC Supply current S = VCC or GND 5.5 V 1 10 μA
ΔICC Supply-current change S = VCC 0.6 V 5.5 V 500 μA
Control input
CiS 5 V 2.7 pF
capacitance
Switch input/ouput
Cio(off) Bn 5 V 5.2 pF
capacitance Bn 17.3
Switch input/ouput
Cio(on) 5 V pF
capacitance A 17.3
Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): SN74LVC1G3157
SN74LVC1G3157
SCES424H JANUARY 2003REVISED MAY 2012
www.ti.com
Analog Switch Characteristics
TA= 25°C FROM TO
PARAMETER TEST CONDITIONS VCC TYP UNIT
(INPUT) (OUTPUT)
1.65 V 300
Frequency 2.3 V 300
RL= 50 , fin = sine wave
response(1) A or Bn Bn or A MHz
(see Figure 6 )3 V 300
(switch on) 4.5 V 300
1.65 V –54
2.3 V –54
Crosstalk(2) RL= 50 , fin = 10 MHz (sine wave)
B1 or B2 B2 or B1 dB
(between switches) (see Figure 7 )3 V –54
4.5 V –54
1.65 V –57
Feed through CL= 5 pF, RL= 50 ,2.3 V –57
attenuation(2) A or Bn Bn or A fin = 10 MHz (sine wave) dB
3 V –57
(switch off) (see Figure 8 )4.5 V –57
3.3 V 3
CL= 0.1 nF, RL= 1 M
Charge injection(3) S A pC
(see Figure 9 )5 V 7
1.65 V 0.1
VI= 0.5 Vp-p, RL= 600 ,2.3 V 0.025
Total harmonic A or Bn Bn or A fin = 600 Hz to 20 kHz (sine wave) %
distortion 3 V 0.015
(see Figure 10 )4.5 V 0.01
(1) Adjust fin voltage to obtain 0 dBm at output. Increase fin frequency until dB meter reads –3 dB.
(2) Adjust fin voltage to obtain 0 dBm at input.
(3) Specified by design
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5 and Figure 11)
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
FROM TO ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
PARAMETER UNIT
(INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX MIN MAX
tpd (1) A or Bn Bn or A 2 1.2 0.8 0.3 ns
ten (2) 7 24 3.5 14 2.5 7.6 1.7 5.7
S Bn ns
tdis (3) 3 13 2 7.5 1.5 5.3 0.8 3.8
tB-M (4) 0.5 0.5 0.5 0.5 ns
(1) tpd is the slower of tPLH or tPHL. The propagation delay is calculated RC time constant of the typical on-state resistance of the switch and
the specified load capacitance when driven by an ideal voltage source (zero output impedance).
(2) ten is the slower of tPZL or tPZH.
(3) tdis is the slower of tPLZ or tPHZ.
(4) Specified by design
6Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC1G3157
0
20
40
60
80
100
120
012345
on
r
VCC = 1.65 V
VCC = 2.3 V
VCC = 3 V
VCC = 4.5 V
VI- V
V V
I O
ron =Ω
IO
SN74LVC1G3157
www.ti.com
SCES424H JANUARY 2003REVISED MAY 2012
PARAMETER MEASUREMENT INFORMATION
Figure 1. On-State Resistance Test Circuit
Figure 2. Typical ron as a Function of Input Voltage (VI) for VI=0toVCC
Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): SN74LVC1G3157
SW
1
2
S
VIL
VIH
B1
B2
S
A
VCC
VCC
SW
1
2
GND
VIL or VIH
VO
VIA
VO= Open
VI= VCC or GND
SN74LVC1G3157
SCES424H JANUARY 2003REVISED MAY 2012
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 3. Off-State Switch Leakage-Current Test Circuit
Figure 4. On-State Switch Leakage-Current Test Circuit
8Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC1G3157
th
tsu
FromOutput
UnderTest
C
(seeNote A)
L
LOADCIRCUIT
S1
VLOAD
Open
GND
RL
DataInput
TimingInput
0V
0V
0V
tW
Input
0V
Input
Output
Waveform1
S1atV
(seeNoteB)
LOAD
Output
Waveform2
S1atGND
(seeNoteB)
VOL
VOH
0V
»0V
Output
Output
TEST S1
t /t
PLH PHL Open
Output
Control
VM
VMVM
VM
VM
1.8V 0.15V±
2.5V 0.2V±
3.3V 0.3V±
5V 0.5V±
500 W
500 W
500 W
500 W
VCC RL
2× VCC
2× VCC
2×VCC
2× VCC
VLOAD CL
50pF
50pF
50pF
50pF
0.3V
0.3V
0.3V
0.3V
VD
VCC
VI
VCC/2
VCC/2
V /2
CC
VCC/2
VM
£2ns
£2ns
£2.5ns
£2.5ns
INPUTS
RL
t /t
r f
VCC
VCC
VCC
VLOAD
t /t
PLZ PZL
GND
t /t
PHZ PZH
VOLTAGEWAVEFORMS
ENABLE ANDDISABLETIMES
LOW- ANDHIGH-LEVEL ENABLING
VOLTAGEWAVEFORMS
PROPAGATIONDELAY TIMES
INVERTING ANDNONINVERTINGOUTPUTS
NOTES: A. C includesprobeandjigcapacitance.
B. Waveform1isforanoutputwithinternalconditionssuchthattheoutputislow,exceptwhendisabledbytheoutputcontrol.
Waveform2isforanoutputwithinternalconditionssuchthattheoutputishigh,exceptwhendisabledbytheoutputcontrol.
C. Allinputpulsesaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR 10MHz,Z =50 .
D. Theoutputsaremeasuredoneatatime,withonetransitionpermeasurement.
E. t andt arethesameast .
F. t andt arethesameast .
G. t andt arethesameast .
H. Allparametersandwaveformsarenotapplicabletoalldevices.
L
O
PLZ PHZ dis
PZL PZH en
PLH PHL pd
£ W
VOLTAGEWAVEFORMS
PULSEDURATION
VOLTAGEWAVEFORMS
SETUP ANDHOLDTIMES
VI
VI
VI
VM
VM
V /2
LOAD
tPZL tPLZ
tPHZ
tPZH
V V
OH D
V +V
OL D
VM
VMVM
VM
VOL
VOH
VI
VI
VOH
VOL
VM
VM
VM
VM
tPLH tPHL
tPLH
tPHL
SN74LVC1G3157
www.ti.com
SCES424H JANUARY 2003REVISED MAY 2012
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 5. Load Circuit and Voltage Waveforms
Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): SN74LVC1G3157
B1
B2
S
A
VCC
VCC
GND
50
VIL or VIH VB1
fin
VB2 Analyzer
S
VIL
VIH
TEST CONDITION
20log10(VO2/VI)
20log10(VO1/VI)
RL= 50
RL
50
R =50
L
SN74LVC1G3157
SCES424H JANUARY 2003REVISED MAY 2012
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 6. Frequency Response (Switch On)
Figure 7. Crosstalk (Between Switches)
10 Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC1G3157
50
R =50
L
SN74LVC1G3157
www.ti.com
SCES424H JANUARY 2003REVISED MAY 2012
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 8. Feedthrough
Figure 9. Charge-Injection Test
Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): SN74LVC1G3157
VI= VCC/2
B1
B2
RL
S
A
VO
CLRL/CL= 50 /35 pF
0.9 x VO
VO
tD
VS
VCC
VCC
GND
600
10k
SN74LVC1G3157
SCES424H JANUARY 2003REVISED MAY 2012
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 10. Total Harmonic Distortion
Figure 11. Break-Before-Make Internal Timing
12 Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC1G3157
SN74LVC1G3157
www.ti.com
SCES424H JANUARY 2003REVISED MAY 2012
REVISION HISTORY
Changes from Revision G (September 2011) to Revision H Page
Changed YZP with correct pin labels. .................................................................................................................................. 1
Changed to remove _ for DRY marking ............................................................................................................................... 2
Changed to correct Pin Label "S" ......................................................................................................................................... 5
Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): SN74LVC1G3157
PACKAGE OPTION ADDENDUM
www.ti.com 18-Oct-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
74LVC1G3157DBVRE4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (CC52 ~ CC55 ~
CC5F ~ CC5K ~
CC5R)
74LVC1G3157DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (CC52 ~ CC55 ~
CC5F ~ CC5K ~
CC5R)
74LVC1G3157DCKRE4 ACTIVE SC70 DCK 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (C55 ~ C5F ~ C5K ~
C5R)
74LVC1G3157DCKRG4 ACTIVE SC70 DCK 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (C55 ~ C5F ~ C5K ~
C5R)
74LVC1G3157DRLRG4 ACTIVE SOT DRL 6 4000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (C57 ~ C5R)
74LVC1G3157DRYRG4 ACTIVE SON DRY 6 5000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 C5
SN74LVC1G3157DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (CC52 ~ CC55 ~
CC5F ~ CC5K ~
CC5R)
SN74LVC1G3157DCKR ACTIVE SC70 DCK 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (C55 ~ C5F ~ C5K ~
C5R)
SN74LVC1G3157DRLR ACTIVE SOT DRL 6 4000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (C57 ~ C5R)
SN74LVC1G3157DRY2 ACTIVE SON DRY 6 5000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 C5
SN74LVC1G3157DRYR ACTIVE SON DRY 6 5000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 C5
SN74LVC1G3157DSFR ACTIVE SON DSF 6 5000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 C5
SN74LVC1G3157YZPR ACTIVE DSBGA YZP 6 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 (C57 ~ C5N)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Oct-2013
Addendum-Page 2
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
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OTHER QUALIFIED VERSIONS OF SN74LVC1G3157 :
Automotive: SN74LVC1G3157-Q1
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC1G3157DBVR SOT-23 DBV 6 3000 180.0 9.2 3.17 3.23 1.37 4.0 8.0 Q3
SN74LVC1G3157DBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G3157DBVR SOT-23 DBV 6 3000 178.0 9.2 3.3 3.2 1.55 4.0 8.0 Q3
SN74LVC1G3157DCKR SC70 DCK 6 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74LVC1G3157DCKR SC70 DCK 6 3000 180.0 9.2 2.3 2.55 1.2 4.0 8.0 Q3
SN74LVC1G3157DRLR SOT DRL 6 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3
SN74LVC1G3157DRLR SOT DRL 6 4000 180.0 9.5 1.78 1.78 0.69 4.0 8.0 Q3
SN74LVC1G3157DRY2 SON DRY 6 5000 180.0 8.4 1.65 1.2 0.7 4.0 8.0 Q3
SN74LVC1G3157DRY2 SON DRY 6 5000 180.0 9.5 1.6 1.15 0.75 4.0 8.0 Q3
SN74LVC1G3157DRYR SON DRY 6 5000 179.0 8.4 1.2 1.65 0.7 4.0 8.0 Q1
SN74LVC1G3157DSFR SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
SN74LVC1G3157YZPR DSBGA YZP 6 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Oct-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC1G3157DBVR SOT-23 DBV 6 3000 205.0 200.0 33.0
SN74LVC1G3157DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0
SN74LVC1G3157DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0
SN74LVC1G3157DCKR SC70 DCK 6 3000 180.0 180.0 18.0
SN74LVC1G3157DCKR SC70 DCK 6 3000 205.0 200.0 33.0
SN74LVC1G3157DRLR SOT DRL 6 4000 202.0 201.0 28.0
SN74LVC1G3157DRLR SOT DRL 6 4000 180.0 180.0 30.0
SN74LVC1G3157DRY2 SON DRY 6 5000 202.0 201.0 28.0
SN74LVC1G3157DRY2 SON DRY 6 5000 180.0 180.0 30.0
SN74LVC1G3157DRYR SON DRY 6 5000 203.0 203.0 35.0
SN74LVC1G3157DSFR SON DSF 6 5000 180.0 180.0 30.0
SN74LVC1G3157YZPR DSBGA YZP 6 3000 220.0 220.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Oct-2013
Pack Materials-Page 2