IDT74FCT162373ATPVG - Integrated Device Technology

IDT74FCT162373AT/CT/ET

FAST CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE

JUNE 2006

IDT74FCT162373AT/CT/ET

INDUSTRIAL TEMPERATURE RANGE

FAST CMOS 16-BIT

TRANSPARENT

LATCH

DESCRIPTION:

The FCT162373T 16-bit transparent D-type latch is built using advanced

dual metal CMOS technology. This high-speed, low-power latch is ideal for

temporary storage of data. It can be used for implementing memory address

latches, I/O ports, and bus drivers. The Output Enable and Latch Enable controls

are organized to operate each device as two 8-bit latches, or one 16-bit latch.

Flow-through organization of signal pins simplifies layout. All inputs are designed

with hysteresis for improved noise margin.

The FCT162373T has balanced output drive with current limiting resistors.

This offers low ground bounce, minimal undershoot, and controlled output fall

times–reducing the need for external series terminating resistors. The

FCT162373T is a plug-in replacement for the FCT16373T and ABT16373 for

on-board interface applications.

2O1

2OE

2LE

2D1

TO SEVEN OTHER CHANNELS

1OE

1LE

1O1

1D1

TO SEVEN OTHER CHANNELS

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FEATURES:

• 0.5 MICRON CMOS Technology

• High-speed, low-power CMOS replacement for ABT functions

• Typical tSK(o) (Output Skew) < 250ps

• Low input and output leakage ≤≤

≤≤

≤1µA (max.)

•VCC = 5V ±10%

• Balanced Output Drivers: ±24mA

• Reduced system switching noise

• Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V,

TA = 25°C

• Available in SSOP and TSSOP packages

FUNCTIONAL BLOCK DIAGRAM

INDUSTRIAL TEMPERATURE RANGE

IDT74FCT162373AT/CT/ET

FAST CMOS 16-BIT TRANSPARENT LATCH

SSOP/ TSSOP

TOP VIEW

PIN CONFIGURATION

1O1

GND

1O3

VCC

1OE

GND

2O2

GND

VCC

GND

1O2

1O4

1O5

1O6

1O7

1O8

2O1

2O3

2O4

2O5

2O7

2O8

2O6

2OE

1LE

1D1

1D2

GND

1D3

1D4

VCC

1D5

1D6

1D7

1D8

2D1

2D2

2D3

2D4

VCC

2D5

2D7

2D8

2D6

2LE

GND

Symbol Description Max Unit

VTERM(2) Terminal Voltage with Respect to GND –0.5 to +7 V

VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V

TSTG Storage Temperature –65 to +150 °C

IOUT DC Output Current –60 to +120 mA

ABSOLUTE MAXIMUM RATINGS(1)(1)

(1)(1)

(1)

NOTES:

1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

2. All device terminals except FCT162XXX Output and I/O terminals.

3. Output and I/O terminals terminals for FCT162XXX.

Symbol Parameter(1) Conditions Typ. Max. Unit

CIN Input Capacitance VIN = 0V 3.5 6 pF

COUT Output Capacitance VOUT = 0V 3.5 8 pF

CAPA CITANCE (TA = +25°C, F = 1.0MHz)

NOTE:

1. This parameter is measured at characterization but not tested.

Pin Names Description

xDx Data Inputs

xLE Latch Enable Input (Active HIGH)

xOE Outputs Enable Input (Active LOW)

xOx 3-State Outputs

PIN DESCRIPTION

NOTE:

1 . H = HIGH Voltage Level

X = Don’t Care

L = LOW Voltage Level

Z = High-Impedance

Inputs Outputs

xDx xLE xOE xOx

HHLH

LHLL

XXHZ

FUNCTION TABLE(1)

IDT74FCT162373AT/CT/ET

FAST CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE

Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit

VIH Input HIGH Level Guaranteed Logic HIGH Level 2 — — V

VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V

IIH Input HIGH Current (Input pins)(5) VCC = Max. VI = VCC ——±1µA

Input HIGH Current (I/O pins)(5) ——±1

IIL Input LOW Current (Input pins)(5) VCC = Max. VI = GND — — ±1µA

Input LOW Current (I/O pins)(5) ——±1

IOZH High Impedance Output Current VCC = Max. VO = 2.7V — — ±1µA

IOZL (3-State Output pins)(5) VO = 0.5V — — ±1

VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V

IOS Short Circuit Current VCC = Max., VO = GND(3) –80 –140 –250 mA

VHInput Hysteresis — — 100 — mV

ICCL Quiescent Power Supply Current VCC = Max. — 5 500 µA

ICCH VIN = GND or VCC

ICCZ

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:

Industrial: TA = –40°C to +85°C, VCC = 5.0V ±10%

Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit

IODL Output LOW Current VCC = 5V, VIN = VIH or VIL, VO = 1.5V(3) 60 115 200 mA

IODH Output HIGH Current VCC = 5V, VIN = VIH or VIL, VO = 1.5V(3) –60 –115 –200 mA

VOH Output HIGH Voltage VCC = Min IOH = –24mA 2 . 4 3 . 3 — V

VIN = VIH or VIL

VOL Output LOW Voltage VCC = Min IOL = 24mA — 0.3 0.55 V

VIN = VIH or VIL

OUTPUT DRIVE CHARACTERISTICS

NOTES:

1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at VCC = 5.0V, +25°C ambient.

3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.

4. Duration of the condition can not exceed one second.

5. The test limit for this parameter is ±5µA at TA = –55°C.

INDUSTRIAL TEMPERATURE RANGE

IDT74FCT162373AT/CT/ET

FAST CMOS 16-BIT TRANSPARENT LATCH

Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit

ΔICC Quiescent Power Supply Current VCC = Max. — 0.5 1.5 mA

TTL Inputs HIGH VIN = 3.4V(3)

ICCD Dynamic Power Supply VCC = Max. VIN = VCC — 60 100 µA/

Current(4) Outputs Open VIN = GND M Hz

xOE = GND

One Input Togging

50% Duty Cycle

ICTotal Power Supply Current(6) VCC = Max. VIN = VCC — 0.6 1.5 mA

Outputs Open VIN = GND

fi = 10MHz

50% Duty Cycle VIN = 3.4V — 0.9 2.3

xOE = GND VIN = GND

xLE = VCC

One Bit Togging

VCC = Max. VIN = VCC — 2.4 4.5(5)

Outputs Open VIN = GND

fi = 2.5MHz

50% Duty Cycle

xOE = GND VIN = 3.4V — 6.4 16.5(5)

xLE = VCC VIN = GND

Sixteen Bits Togging

POWER SUPPLY CHARACTERISTICS

NOTES:

1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at VCC = 5.0V, +25°C ambient.

3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.

4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.

6. IC = IQUIESCENT + IINPUTS + IDYNAMIC

IC = ICC + ΔICC DHNT + ICCD (fCPNCP/2 + fiNi)

ICC = Quiescent Current (ICCL, ICCH and ICCZ)

ΔICC = Power Supply Current for a TTL High Input (VIN = 3.4V)

DH = Duty Cycle for TTL Inputs High

NT = Number of TTL Inputs at DH

ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL)

fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)

NCP = Number of Clock Inputs at fCP

fi = Input Frequency

Ni = Number of Inputs at fi

IDT74FCT162373AT/CT/ET

FAST CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE

74FCT162373AT 74FCT162373CT 74FCT162373ET

Symbol Parameter Condition(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit

tPLH Propagation Delay CL = 50pF 1.5 5.2 1.5 4.2 1.5 3.4 ns

tPHL xDx to xOx RL = 500Ω

tPLH Propagation Delay 2 8.5 2 5.5 1.5 3.7 ns

tPHL xLE to xOx

tPZL Output Enable Time 1.5 6.5 1.5 5.5 1.5 4.4 ns

tPZH

tPHZ Output Disable Time 1.5 5.5 1.5 5 1.5 3.6 ns

tPLZ

tSU Set-up Time HIGH or LOW, xDx to xLE 2 — 2 — 1 — ns

tHHold Time HIGH or LOW, xDx to xLE 1.5 — 1.5 — 1 — ns

tWxLE Pulse Width HIGH 5 — 5 — 3(4) —ns

tSK(o) Output Skew(3) — 0.5 — 0.5 — 0.5 ns

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

NOTES:

1. See test circuit and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

4. This limit is guaranteed but not tested.

INDUSTRIAL TEMPERATURE RANGE

IDT74FCT162373AT/CT/ET

FAST CMOS 16-BIT TRANSPARENT LATCH

Pulse

Generator

D.U.T.

VCC

VIN

VOUT

50pF 500Ω

500Ω

7.0V

1.5V

DATA

INPUT

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

tSU tH

tREM

tSU tH

PRESET

CLEAR

CLOCK ENABLE

ETC.

HIGH-LOW-HIGH

PULSE

LOW-HIGH-LOW

PULSE

1.5V

SAME PHASE

INPUT TRANSITION

1.5V

VOH

tPLH

OUTPUT

OPPOSITE PHASE

INPUT TRANSITION

1.5V

tPLH tPHL

tPHL

VOL

CONTROL

INPUT

1.5V

3.5V

OUTPUT

NORMALLY

LOW

OUTPUT

NORMALLY

HIGH

SWITCH

CLOSED

SWITCH

OPEN

VOL

0.3V

tPLZtPZL

tPZH tPHZ

3.5V

1.5V

ENABLE DISABLE

VOH

TEST CIRCUITS AND WAVEFORMS

Propagation Delay

Test Circuits for All Outputs

Enable and Disable Times

Set-up, Hold, and Release Times

Pulse Width

Test Switch

Open Drain

Disable Low Closed

Enable Low

All Other Tests Open

SWITCH POSITION

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

IDT74FCT162373AT/CT/ET

FAST CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE

ORDERING INFORMATION

IDT XX

Temp. Range

XXXX

Device Type

Package

PVG

PAG

Shrink Small Outline Package

SSOP - Green

Thin Shrink Small Outline Package

TSSOP - Green

16-Bit Transparent Latch

74 – 40°C to +85°C

162 Double-Density, 5 Volt, Balanced Drive

FCT XXX

Family

373AT

373CT

373ET

CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 logichelp@idt.com

San Jose, CA 95138 fax: 408-284-2775