ICS664G-01LFTR - Integrated Device Technology

DATASHEET

DIGITAL VIDEO CLOCK SOURCE ICS664-01

IDT™ / ICS™

DIGITAL VIDEO CLOCK SOURCE 1

ICS664-01 REV C 082307

Description

The ICS664-01 provides clock generation and co nversion

for clock rates commonly needed in HDTV digital video

equipment. The ICS664-01 uses the latest PLL technology

to provide excellent phase noise and long term jitter

performance for superior synchronization and S/N r atio.

F or audio sampling cloc ks gen erated f rom 27 MHz, use the

ICS661.

Please contact IDT if you have a requirement for an input

and output frequency not included in this document. IDT

can rapidly modify this product to meet special

requirements.

Features

•Packaged in 16-pin TSSO P

•Availab le in Pb (lead) free package

•Clock or crystal input provides flexibility

•Low phase noise supports enhanced SNR

•Lowest jitter in class at 100 ps

•Exact (0 ppm) multiplication ratios

•Power-down mode lowers power consumption

•Improved phase noise over ICS660

•Supports SMTE 292M HD-SDI standard for HDTV

broadcast

Block Diagram

PLL Clock

Synthesis

SELIN

Crystal

Oscillator

X1/REFIN

VDD (P2) VDD (P14)

CLK

GND (P6) GND (P5) GND (P13)

S3:0 4

VDD (P3) VDDO

ICS664-01

DIGITAL VIDEO CLOCK SOURCE CLOCK SYNTHESIZER

IDT™ / ICS™

DIGITAL VIDEO CLOCK SOURCE 2

ICS664-01 REV C 082307

Pin Assignment

16-pin TSSOP

Output Clock Selection Table

Pin Descriptions

X1/REFIN X2

VDD

N/C

VDD

GND

SELIN

VDDO

S3 S1

S2 CLK

S3 S2 S1 S0 Input

Frequency

(MHz)

Output

Frequency

(MHz)

0000 Power down

0001Pass thru Input Freq

0010 27 74.25

0011 27 74.175824

0100 13.5 74.25

0101 13.5 74.175824

0110RESERVEDRESERVED

0111RESERVEDRESERVED

1000 74.25 54

100174.175824 54

1010RESERVEDRESERVED

1011RESERVEDRESERVED

1100 54 74.25

1101 54 74.175824

1110 54 13.5

1111 27 13.5

Number Pin

Name Pin

Type Pin Description

1 X1/REFIN Input Connect this pin to a crystal or clock input

2 VDD Power Power supply for crystal oscillator.

3 VDD Power Power supply for PLL.

4 S0 Input Output frequency selection. Determines output frequency per table abov e . On chip pull up .

5 GND Power Ground for PLL.

6 GND Power Ground for crystal oscillator.

7 S3 Input Output frequency selection. Determines output frequency per table abov e . On chip pull up .

8 S2 Input Output frequency selection. Determines output frequency per table abov e . On chip pull up .

9 CLK Output Clock output.

10 S1 Input Output frequency selection. Determines output frequency per table abov e . On chip pull up .

11 VDDO Power Power supply for output stage.

12 SEL Input Low for clock input, high for crystal. On chip pull up.

13 GND Power Ground for output.

14 VDD Power Power supply.

15 NC — No connect. Do not connect to anything.

16 X2 Input Connect this pin to a crystal. Leave open if using a clock input.

ICS664-01

DIGITAL VIDEO CLOCK SOURCE CLOCK SYNTHESIZER

IDT™ / ICS™

DIGITAL VIDEO CLOCK SOURCE 3

ICS664-01 REV C 082307

Application Information

Series Termination Resistor

Clock output traces should use series termination. To series

terminate a 50Ω trace (a commonly u sed trace impedance),

place a 33Ω resistor in series with the cloc k line, as close to

the clock outpu t pin as possible. The nom inal impedance of

the clock output is 20Ω.

Decoupling Capacitors

As with any high-perf ormance mixed-signal IC, the

ICS664-01 must be isolated from system power supply

noise to perform optimally.

Decoupling capacitors of 0.01µF must be connect ed

between each VDD and the PCB ground plane. To fur ther

guard against interfering system supply noise, the

ICS664-01 should u se one common connection t o the PCB

pow er plane as sho wn in the diag ram on the ne xt page . The

f errite bead and bulk cap acitor help reduce low er frequency

noise in the supply that can lead to output clock ph ase

modulation.

Recommended Power Supply Connection for

Optimal Devi ce Performance

All power supply pins must be connected to th e sa me

v olta ge, e xcept VDDO, which may be connecte d to a lower

voltage in order to chan ge the output lev el.

To achieve the absolute minimum jitter, pow e r the part with

a dedicated LDO regulator , which will provide high isolation

from power supply noise. Many companies produce very

small, inexpensive regulators; an example is the National

Semiconductor LP2985.

Crystal Load Capacitors

If a crystal is used, the device crystal connections should

include pads for capacitors from X1 to ground and from X2

to ground. These capacitors are used to adjust the stray

capacitance of the board to match the nominally required

crystal load capacitance. To reduce possible noise pickup,

use very short PCB traces (and no vias) been the crystal

and device.

The v alue of the load capacito rs can be roughly determined

by the formula C = 2(CL - 6) where C is the load capacitor

connected to X1 and X2, and CL is the specified value of the

load capacitance for the crystal. A typical crystal CL is 18 pF,

so C = 2(18 - 6) = 24 pF. Because these capacitors adjust

the stray capacitance of the PCB, check the output

frequency using your final layout to see if the value of C

should be changed.

PCB Layout Recommendations

For optimum device performance and lowest output phase

noise, the following guidelines should be observed.

1) Each 0.01µF decoupling capacitor should be mounted on

the component side of the board as close to the VDD pin as

possible. No vias should be used between decoupling

capacitor and VDD pin. The PCB trace to VDD pin should

be k ept as short as possible , as should the PCB trace to the

ground via . Distance of the f errite bead and b ulk decoupling

from the device is less critical.

2) The external crystal should be mounted next to the device

with short traces. The X1 and X2 traces should not be

routed next to each other with minimum spaces, instead

they should be separated and away from other traces.

3) To minimize EMI and obtain the best signal integrity, the

33Ω series termination resistor should be placed close to

the clock output.

4) An optimum layout is one with all components on the

same side of the board, minimizing vias through other signal

layers (the ferrite bead and bulk decoupling capacitor can be

mounted on the b ack). Other signa l traces should be routed

away from the ICS664-01. This includes signal traces just

underneath the device, or on layers adjacent to the ground

plane layer used by the device.

C onnection to 3.3V

Power Plane

Ferrite

Bead

Bulk D ec oupling C apacitor

(such as 1 F T antalum )

VDD Pin

0.01 F D ecoupling C apac itors

ICS664-01

DIGITAL VIDEO CLOCK SOURCE CLOCK SYNTHESIZER

IDT™ / ICS™

DIGITAL VIDEO CLOCK SOURCE 4

ICS664-01 REV C 082307

Absolute Maximum Ratings

Stresses above the ratings listed belo w can ca use permanent damage to th e ICS664- 01. The se r ating s , which are

standard v alues for IDT commercially rated parts, are stress ratings only. Functional operation of the de vice at these

or any other conditions above those indicated in the operational sections of the specifications is not implied.

Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical

parameters are guaranteed only over the recommended operating temperature range.

Recommended Operation Conditions

DC Electrical Characteristics

Unless stated otherwise, VDD = VDDO = 3.3 V ±10%, Ambient Temperature -40 to +85° C

Item Rating

Supply Voltage, VDD 5.5 V

All Inputs and Outputs -0.5 V to VDD+0.5 V

Ambient Operating Temperature 0 to +70°C

Storage Temperature -65 to +150°C

Junction Temperature 125°C

Soldering Temperature 260°C

Parameter Min. Typ. Max. Units

Ambient Operating Temperature -40 +85 °C

Power Supply Voltage (measured in respect to GND) +3.0 +3.6 V

Parameter Symbol Conditions Min. Typ. Max. Units

Operating Voltage VDD 3.0 3.6 V

VDDO 2.5 VDD V

Supply Current IDD No Load 35 mA

Input High Voltage VIH 2V

Input Low Voltage VIL 0.8 V

Output High Voltage VOH IOH = -4 mA VDD-0.4 V

Output High Voltage VOH IOH = -20 mA 2.4 V

Output Low Voltage VOL IOL = 20 mA 0.4 V

Short Circuit Current IOS Each output ±65 mA

Nominal Outp ut Imped a nce ZOUT 20 Ω

Input Capacitance CIN Input pins 7 pF

Internal Pull-up Resistor RPU 120 kΩ

ICS664-01

DIGITAL VIDEO CLOCK SOURCE CLOCK SYNTHESIZER

IDT™ / ICS™

DIGITAL VIDEO CLOCK SOURCE 5

ICS664-01 REV C 082307

AC Electrical Characteristics

Unless stated otherwise, VDD = VDDO = 3.3 V ±10%, Ambient Temperature -40 to +85° C

Thermal Characteristics

Parameter Symbol Conditions Min. Typ. Max. Units

Crystal Frequency 28 MHz

Output Clock Rise Time tOR 20% to 80%, 15 pF load 1.5 ns

Output Clock Fall Time tOF 80% to 20%, 15 p F load 1.5 ns

Output Duty Cycle tOD at VDD/2, 15 pF load 40 49 to 51 60 %

Power-up Time tPU Valid power on to valid

output 1ms

Power-down Time tPD P ower off to clock

disable 10 µs

Jitter, short term 100 ps p-p

Jitter, long term 10 µs delay 200 ps p-p

Single Sideband Phase

Noise 10 kHz offset -120 dBc

Actual Mean Frequency

Error versus Target 0ppm

Parameter Symbol Conditions Min. Typ. Max. Units

Thermal Resistance Junction to

Ambient θJA Still air 78 °C/W

θJA 1 m/s air flow 70 °C/W

θJA 3 m/s air flow 68 °C/W

Thermal Resistance J unction to Case θJC 37 °C/W

ICS664-01

DIGITAL VIDEO CLOCK SOURCE CLOCK SYNTHESIZER

IDT™ / ICS™

DIGITAL VIDEO CLOCK SOURCE 6

ICS664-01 REV C 082307

Package Outline and Package Dimensions (16-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch)

Package dimensions are kept current with JEDEC Publication No. 95, MO-153

Ordering Information

Parts that are ordered with a “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes

no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No

other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications

such as those requir ing extended temperature range, high reliability, or other extraordinary environmental requirements are not

recommended without additional processin g by IDT. IDT reser ves the right to change any circuitry or specifications without notice. IDT

does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.

Part / Order Number Marking Shipping Packaging Package Temperature

ICS664G-01 664G-01 Tubes 16-pin TSSOP 0 to +70° C

ICS664G-0 1T R 664G-01 Tape an d Re el 16-pin TSSOP 0 to +70° C

ICS664G-01LF 664G-01L Tubes 16-pin TSSOP 0 to +70° C

ICS664G-01LFTR 664G-01L Tape and Reel 16-pin TSSOP 0 to +70° C

ICS664GI-01LF 664GI01L Tubes 16-pin TSSOP -40 to +85° C

ICS664GI-01LFT 664GI01L Tape and Reel 16-pin TSSOP -40 to +85° C

INDEX

AREA

1 2

E1 E

SEATING

PLANE

- C -

aaa C

Millimeters Inches

Symbol Min Max Min Max

A--1.20--0.047

A1 0.05 0.15 0.002 0.006

A2 0.80 1.05 0.032 0.041

b 0.19 0.30 0.007 0.012

C 0.09 0.20 0.0035 0.008

D 4.90 5.1 0.193 0.201

E 6.40 BASIC 0.252 BASIC

E1 4.30 4.50 0.169 0.177

e 0.65 Basic 0.0256 Basic

L 0.45 0.75 0.018 0.030

α0°8°0°8°

aaa -- 0.10 -- 0.004

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trademarks used to identify products or services of their respective owners.

Printed in USA

Corporate Headquarters

Integrated Device Technology, Inc.

www.idt.com

For Sales

800-345-7015

408-284-8200

Fax: 408-284-2775

For Tech Support

408-284-4522

www.idt.com/go/clockhelp

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ICS664-01

DIGITAL VIDEO CLOCK SOURCE CLOCK SYNTHESIZER