Intel387 DX - Intel - Datasheet.Directory

*Other brands and names are the property of their respective owners.

Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or

copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make

changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

March 1992

Order Number: 240448-005

Intel387TM DX

MATH COPROCESSOR

YHigh Performance 80-Bit Internal

Architecture

YImplements ANSI/IEEE Standard 754-

1985 for Binary Floating-Point

Arithmetic

YExpands Intel386TM DX CPU Data

Types to Include 32-, 64-, 80-Bit

Floating Point, 32-, 64-Bit Integers and

18-Digit BCD Operands

YDirectly Extends Intel386TM DX CPU

Instruction Set to Include

Trigonometric, Logarithmic,

Exponential and Arithmetic Instructions

for All Data Types

YUpward Object-Code Compatible from

8087 and 80287

YFull-Range Transcendental Operations

for SINE, COSINE, TANGENT,

ARCTANGENT and LOGARITHM

YBuilt-In Exception Handling

YOperates Independently of Real,

Protected and Virtual-8086 Modes of

the Intel386TM DX Microprocessor

YEight 80-Bit Numeric Registers, Usable

as Individually Addressable General

Registers or as a Register Stack

YAvailable in 68-Pin PGA Package

YOne Version Supports 16 MHz–33 MHz

Speeds

(See Packaging Spec: Order Ý231369)

The Intel387TM DX Math CoProcessor (MCP) is an extension of the Intel386TM microprocessor architecture.

The combination of the Intel387 DX MCP with the Intel386TM DX Microprocessor dramatically increases the

processing speed of computer application software which utilize mathematical operations. This makes an ideal

computer workstation platform for applications such as financial modeling and spreadsheets, CAD/CAM, or

graphics.

The Intel387 DX Math CoProcessor adds over seventy mnemonics to the Intel386 DX Microprocessor instruc-

tion set. Specific Intel387 DX MCP math operations include logarithmic, arithmetic, exponential, and trigono-

metric functions. The Intel387 DX MCP supports integer, extended integer, floating point and BCD data

formats, and fully conforms to the ANSI/IEEE floating point standard.

The Intel387 DX Math CoProcessor is object code compatible with the Intel387 SX MCP, and upward object

code compatible from the 80287 and 8087 math coprocessors. Object code for Intel386 DX/Intel387 DX is

also compatible with the Intel486TM microprocessor. The Intel387 DX MCP is manufactured on 1 micron,

CHMOS IV technology and packaged in a 68-pin PGA package.

240448–1

Figure 0.1. Intel387TM DX Math CoProcessor Block Diagram

Intel387TM DX Math CoProcessor

CONTENTS PAGE

1.0 FUNCTIONAL DESCRIPTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5

2.0 PROGRAMMING INTERFACE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6

2.1 Data Types ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6

2.2 Numeric Operands ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6

2.3 Register Set ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8

2.3.1 Data Registers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8

2.3.2 Tag Word ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8

2.3.3 Status Word ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9

2.3.4 Instruction and Data Pointers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12

2.3.5 Control Word ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14

2.4 Interrupt Description ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14

2.5 Exception Handling ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15

2.6 Initialization ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15

2.7 8087 and 80287 Compatibility ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 16

2.7.1 General Differences ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 16

2.7.2 Exceptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 17

3.0 HARDWARE INTERFACE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 17

3.1 Signal Description ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 17

3.1.1 Intel386TM DX CPU Clock 2 (CPUCLK2) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 20

3.1.2 Intel387TM DX MCP Clock 2 (NUMCLK2) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 20

3.1.3 Intel387TM DX MCP Clocking Mode (CKM) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 20

3.1.4 System Reset (RESETIN) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21

3.1.5 Processor Extension Request (PEREQ) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21

3.1.6 Busy Status (BUSYÝ)ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21

3.1.7 Error Status (ERRORÝ)ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21

3.1.8 Data Pins (D31–D0) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21

3.1.9 Write/Read Bus Cycle (W/RÝ)ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21

3.1.10 Address Strobe (ADSÝ)ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21

3.1.11 Bus Ready Input (READYÝ)ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22

3.1.12 Ready Output (READYOÝ)ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22

3.1.13 Status Enable (STEN) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22

3.1.14 MCP Select Ý1 (NPS1Ý)ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22

3.1.15 MCP Select Ý2 (NPS2) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22

3.1.16 Command (CMD0Ý)ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22

CONTENTS PAGE

3.2 Processor Architecture ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22

3.2.1 Bus Control Logic ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23

3.2.2 Data Interface and Control Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23

3.2.3 Floating Point Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23

3.3 System Configuration ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23

3.3.1 Bus Cycle Tracking ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24

3.3.2 MCP Addressing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24

3.3.3 Function Select ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24

3.3.4 CPU/MCP Synchronization ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24

3.3.5 Synchronous or Asynchronous Modes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25

3.3.6 Automatic Bus Cycle Termination ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25

3.4 Bus Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25

3.4.1 Nonpipelined Bus Cycles ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 26

3.4.1.1 Write Cycle ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 26

3.4.1.2 Read Cycle ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 26

3.4.2 Pipelined Bus Cycles ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 27

3.4.3 Bus Cycles of Mixed Type ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 28

3.4.4 BUSYÝand PEREQ Timing Relationship ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 28

4.0 ELECTRICAL DATA ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 30

4.1 Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 30

4.2 DC Characteristics ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 30

4.3 AC Characteristics ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 31

5.0 Intel387TM DX MCP EXTENSIONS TO THE Intel386TM DX CPU INSTRUCTION

SET ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36

APPENDIX AÐCOMPATIBILITY BETWEEN THE 80287 MCP AND THE 8087 ÀÀÀÀÀÀÀÀÀÀÀÀÀ A-1

FIGURES

Figure 0.1 Intel387TM DX Math Coprocessor Block Diagram ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 1

Figure 1.1 Intel386TM DX Microprocessor and Intel387TM DX Math Coprocessor Register

Set ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5

Figure 2.1 Intel387TM DX MCP Tag Word ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8

Figure 2.2 MCP Status Word ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9

Figure 2.3 Protected Mode Intel387TM DX MCP Instruction and Data Pointer Image in

Memory, 32-Bit Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12

Figure 2.4 Real Mode Intel387TM DX MCP Instruction and Data Pointer Image in Memory, 32-

Bit Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13

Figure 2.5 Protected Mode Intel387TM DX MCP Instruction and Data Pointer Image in

Memory, 16-Bit Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13

Figure 2.6 Real Mode Intel387TM DX MCP Instruction and Data Pointer Image in Memory, 16-

Bit Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13

Figure 2.7 Intel387TM DX MCP Control Word ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14

Figure 3.1 Intel387TM DX MCP Pin Configuration ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 19

CONTENTS PAGE

FIGURES (Continued)

Figure 3.2 Asynchronous Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 20

Figure 3.3 Intel386TM DX Microprocessor and Intel387TM DX MCP Coprocessor System

Configuration ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23

Figure 3.4 Bus State Diagram ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25

Figure 3.5 Nonpipelined Read and Write Cycles ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 27

Figure 3.6 Fastest Transitions to and from Pipelined Cycles ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 28

Figure 3.7 Pipelined Cycles with Wait States ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 29

Figure 3.8 STEN, BUSYÝand PEREQ Timing Relationship ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 29

Figure 4.0a Typical Output Valid Delay vs Load Capacitance at Max Operating

Temperature ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 32

Figure 4.0b Typical Output Rise Time vs Load Capacitance at Max Operating

Temperature ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 32

Figure 4.1 CPUCLK2/NUMCLK2 Waveform and Measurement Points for Input/Output A.C.

Specifications ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 33

Figure 4.2 Output Signals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 33

Figure 4.3 Input and I/O Signals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 34

Figure 4.4 RESET Signal ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 34

Figure 4.5 Float from STEN ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 34

Figure 4.6 Other Parameters ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 35

TABLES

Table 2.1 Intel387TM DX MCP Data Type Representation in Memory ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7

Table 2.2 Condition Code Interpretation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10

Table 2.3 Condition Code Interpretation after FPREM and FPREM1 Instructions ÀÀÀÀÀÀÀÀÀÀÀÀÀ 11

Table 2.4 Condition Code Resulting from Comparison ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11

Table 2.5 Condition Code Defining Operand Class ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11

Table 2.6 Intel386TM DX Microprocessor Interrupt Vectors Reserved for MCP ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15

Table 2.7 Exceptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 16

Table 3.1 Intel387TM DX MCP Pin Summary ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 18

Table 3.2 Intel387TM DX MCP Pin Cross-Reference ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 18

Table 3.3 Output Pin Status after Reset ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21

Table 3.4 Bus Cycles Definition ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24

Table 4.1 DC Specifications ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 30

Table 4.2a Combinations of Bus Interface and Execution Speeds ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 31

Table 4.2b Timing Requirements of the Execution Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 31

Table 4.2c Timing Requirements of the Bus Interface Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 31

Table 4.3 Other Parameters ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 35

Intel387TM DX MATH COPROCESSOR

Intel386TM DX Microprocessor Registers

GENERAL REGISTERS

31 15 0

EAX AX

AH AL

EBX BX

BH BL

ECX CX

CH CL

EDX DX

DH DL

ESI SI

EDI DI

EBP BP

ESP SP

SEGMENT REGISTERS

15 0

31 0

EIP

EFLAGS

Intel387TM DX MCP Data Registers

Tag

Field

79 78 64 63 0 1 0

R0 Sign Exponent Significand

15 0 47 0

Control Register Instruction Pointer (in i386TM DX CPU)

Status Register Data Pointer (in i386TM DX CPU)

Tag Word

Figure 1.1. Intel386TM DX Microprocessor and Intel387TM DX Math Coprocessor Register Set

1.0 FUNCTIONAL DESCRIPTION

The Intel387TM DX Math Coprocessor provides

arithmetic instructions for a variety of numeric data

types in Intel386TM DX Microprocessor systems. It

also executes numerous built-in transcendental

functions (e.g. tangent, sine, cosine, and log func-

tions). The Intel387 DX MCP effectively extends the

processor system for existing data types and adds

several new data types as well. Figure 1.1 shows the

model of registers visible to programs. Essentially,

the Intel387 DX MCP can be treated as an additional

resource or an extension to the Intel386 DX Micro-

processor. The Intel386 DX Microprocessor togeth-

er with a Intel387 DX MCP can be used as a single

unified system.

The Intel387 DX MCP works the same whether the

Intel386 DX Microprocessor is executing in real-ad-

dress mode, protected mode, or virtual-8086 mode.

All memory access is handled by the Intel386 DX

Microprocessor; the Intel387 DX MCP merely oper-

ates on instructions and values passed to it by the

Intel386 DX Microprocessor. Therefore, the Intel387

DX MCP is not sensitive to the processing mode of

the Intel386 DX Microprocessor.

In real-address mode and virtual-8086 mode, the In-

tel386 DX Microprocessor and Intel387 DX MCP are

completely upward compatible with software for

8086/8087, 80286/80287 real-address mode, and

Intel386 DX Microprocessor and 80287 Coproces-

sor real-address mode systems.

In protected mode, the Intel386 DX Microprocessor

and Intel387 DX MCP are completely upward com-

patible with software for 80286/80287 protected

mode, and Intel386 DX Microprocessor and 80287

Coprocessor protected mode systems.

The only differences of operation that may appear

when 8086/8087 programs are ported to a protect-

ed-mode Intel386 DX Microprocessor and Intel387

DX MCP system (

not

using virtual-8086 mode), is in

the format of operands for the administrative instruc-

tions FLDENV, FSTENV, FRSTOR and FSAVE.

These instructions are normally used only by excep-

tion handlers and operating systems, not by applica-

tions programs.

The Intel387 DX MCP contains three functional units

that can operate in parallel to increase system per-

formance. The Intel386 DX Microprocessor can be

transferring commands and data to the MCP

bus

control logic

for the next instruction while the MCP

floating-point unit

is performing the current numeric

instruction.

Intel387TM DX MATH COPROCESSOR

2.0 PROGRAMMING INTERFACE

The MCP adds to the Intel386 DX Microprocessor

system additional data types, registers, instructions,

and interrupts specifically designed to facilitate high-

speed numerics processing. To use the MCP re-

quires no special programming tools, because all

new instructions and data types are directly support-

ed by the Intel386 DX CPU assembler and compilers

for high-level languages. All 8086/8088 develop-

ment tools that support the 8087 can also be used

to develop software for the Intel386 DX Microproc-

essor and Intel387 DX Math Coprocessor in real-ad-

dress mode or virtual-8086 mode. All 80286 devel-

opment tools that support the 80287 can also be

used to develop software for the Intel386 DX Micro-

processor and Intel387 DX Math Coprocessor.

All communication between the Intel386 DX Micro-

processor and the MCP is transparent to applica-

tions software. The CPU automatically controls the

MCP whenever a numerics instruction is executed.

All physical memory and virtual memory of the CPU

are available for storage of the instructions and op-

erands of programs that use the MCP. All memory

addressing modes, including use of displacement,

base register, index register, and scaling, are avail-

able for addressing numerics operands.

Section 6 at the end of this data sheet lists by class

the instructions that the MCP adds to the instruction

set of the Intel386 DX Microprocessor system.

2.1 Data Types

Table 2.1 lists the seven data types that the Intel387

DX MCP supports and presents the format for each

type. Operands are stored in memory with the least

significant digit at the lowest memory address. Pro-

grams retrieve these values by generating the low-

est address. For maximum system performance, all

operands should start at physical-memory address-

es evenly divisible by four (doubleword boundaries);

operands may begin at any other addresses, but will

require extra memory cycles to access the entire op-

erand.

Internally, the Intel387 DX MCP holds all numbers in

the extended-precision real format. Instructions that

load operands from memory automatically convert

operands represented in memory as 16-, 32-, or 64-

bit integers, 32- or 64-bit floating-point numbers, or

18-digit packed BCD numbers into extended-preci-

sion real format. Instructions that store operands in

memory perform the inverse type conversion.

2.2 Numeric Operands

A typical MCP instruction accepts one or two oper-

ands and produces a single result. In two-operand

instructions, one operand is the contents of an MCP

The operands of some instructions are predefined;

for example FSQRT always takes the square root of

the number in the top stack element.

Intel387TM DX MATH COPROCESSOR

Table 2.1. Intel387TM DX MCP Data Type Representation in Memory

240448–2

NOTES:

(1) S eSign bit (0 epositive, 1 enegative)

(2) dneDecimal digit (two per byte)

(3) X eBits have no significance; Intel387TM DX MCP ignores when loading, zeros when storing

(4)UePosition of implicit binary point

(5) I eInteger bit of significand; stored in temporary real, implicit in single and double precision

(6) Exponent Bias (normalized values):

Single: 127 (7FH)

Double: 1023 (3FFH)

Extended Real: 16383 (3FFFH)

(7) Packed BCD: (b1)S(D17...D0)

(8) Real: (b1)S(2E-BIAS)(F

...)

Intel387TM DX MATH COPROCESSOR

15 0

TAG (7) TAG (6) TAG (5) TAG (4) TAG (3) TAG (2) TAG (1) TAG (0)

NOTE:

The index i of tag(i) is not top-relative. A program typically uses the ‘‘top’’ field of Status Word to determine which tag(i)

field refers to logical top of stack.

TAG VALUES:

00 eValid

01 eZero

10 eQNaN, SNaN, Infinity, Denormal and Unsupported Formats

11 eEmpty

Figure 2.1. Intel387TM DX MCP Tag Word

2.3 Register Set

Figure 1.1 shows the Intel387 DX MCP register set.

When an MCP is present in a system, programmers

may use these registers in addition to the registers

normally available on the Intel386 DX CPU.

2.3.1 DATA REGISTERS

Intel387 DX MCP computations use the MCP’s data

registers. These eight 80-bit registers provide the

equivalent capacity of twenty 32-bit registers. Each

of the eight data registers in the MCP is 80 bits wide

and is divided into ‘‘fields’’ corresponding to the

MCPs extended-precision real data type.

The Intel387 DX MCP register set can be accessed

either as a stack, with instructions operating on the

top one or two stack elements, or as a fixed register

set, with instructions operating on explicitly designat-

ed registers. The TOP field in the status word identi-

fies the current top-of-stack register. A ‘‘push’’ oper-

ation decrements TOP by one and loads a value into

the new top register. A ‘‘pop’’ operation stores the

value from the current top register and then incre-

ments TOP by one. Like the Intel386 DX Microproc-

essor stacks in memory, the MCP register stack

grows ‘‘down’’ toward lower-addressed registers.

Instructions may address the data registers either

implicitly or explicitly. Many instructions operate on

the register at the TOP of the stack. These instruc-

tions implicitly address the register at which TOP

points. Other instructions allow the programmer to

explicitly specify which register to user. This explicit

2.3.2 TAG WORD

The tag word marks the content of each numeric

data register, as Figure 2.1 shows. Each two-bit tag

represents one of the eight numerics registers. The

principal function of the tag word is to optimize the

MCPs performance and stack handling by making it

possible to distinguish between empty and nonemp-

ty register locations. It also enables exception han-

dlers to check the contents of a stack location with-

out the need to perform complex decoding of the

actual data.

Intel387TM DX MATH COPROCESSOR

240448–3

ES is set if any unmasked exception bit is set; cleared otherwise.

See Table 2.2 for interpretation of condition code.

TOP values:

000 eRegister 0 is Top of Stack

001 eRegister 1 is Top of Stack

111 eRegister 7 is Top of Stack

For definitions of exceptions, refer to the section entitled

‘‘Exception Handling’’

Figure 2.2. MCP Status Word

2.3.3 STATUS WORD

The 16-bit status word (in the status register) shown

in Figure 2.2 reflects the overall state of the MCP. It

may be read and inspected by CPU code.

Bit 15, the B-bit (busy bit) is included for 8087 com-

patibility only. It reflects the contents of the ES bit

(bit 7 of the status word), not the status of the

BUSYÝoutput of the Intel387 DX MCP.

Bits 13–11 (TOP) point to the Intel387 DX MCP reg-

ister that is the current top-of-stack.

The four numeric condition code bits (C3–C0) are

similar to the flags in a CPU; instructions that per-

form arithmetic operations update these bits to re-

flect the outcome. The effects of these instructions

on the condition code are summarized in Tables 2.2

through 2.5.

Bit 7 is the error summary (ES) status bit. This bit is

set if any unmasked exception bit is set; it is clear

otherwise. If this bit is set, the ERRORÝsignal is

asserted.

Bit 6 is the stack flag (SF). This bit is used to distin-

guish invalid operations due to stack overflow or un-

derflow from other kinds of invalid operations. When

SF is set, bit 9 (C1) distinguishes between stack

overflow (C1e1) and underflow (C1e0).

Figure 2.2 shows the six exception flags in bits 5–0

of the status word. Bits 5–0 are set to indicate that

the MCP has detected an exception while executing

an instruction. A later section entitled ‘‘Exception

Handling’’ explains how they are set and used.

Note that when a new value is loaded into the status

word by the FLDENV or FRSTOR instruction, the

value of ES (bit 7) and its reflection in the B-bit (bit

15) are not derived from the values loaded from

memory but rather are dependent upon the values of

the exception flags (bits 5–0) in the status word and

their corresponding masks in the control word. If ES

is set in such a case, the ERRORÝoutput of the

MCP is activated immediately.

Intel387TM DX MATH COPROCESSOR

Table 2.2. Condition Code Interpretation

Instruction C0 (S) C3 (Z) C1 (A) C2 (C)

FPREM, FPREM1 Three least significant bits Reduction

(see Table 2.3) of quotient 0ecomplete

Q2 Q0 Q1 1eincomplete

or O/UÝ

FCOM, FCOMP,

FCOMPP, FTST, Result of comparison Zero Operand is not

FUCOM, FUCOMP, (see Table 2.4) or O/UÝcomparable

FUCOMPP, FICOM, (Table 2.4)

FICOMP

FXAM Operand class Sign Operand class

(see Table 2.5) or O/UÝ(Table 2.5)

FCHS, FABS, FXCH,

FINCSTP, FDECSTP, Zero

Constant loads, UNDEFINED UNDEFINED

FXTRACT, FLD, or O/UÝ

FILD, FBLD,

FSTP (ext real)

FIST, FBSTP,

FRNDINT, FST,

FSTP, FADD, FMUL, Roundup

FDIV, FDIVR, UNDEFINED UNDEFINED

FSUB, FSUBR, or O/UÝ

FSCALE, FSQRT,

FPATAN, F2XM1,

FYL2X, FYL2XP1

FPTAN, FSIN Roundup Reduction

FCOS, FSINCOS UNDEFINED or O/UÝ,0

complete

undefined 1 eincomplete

if C2 e1

FLDENV, FRSTOR Each bit loaded from memory

FLDCW, FSTENV,

FSTCW, FSTSW, UNDEFINED

FCLEX, FINIT,

FSAVE

O/UÝWhen both IE and SF bits of status word are set, indicating a stack exception, this bit

distinguishes between stack overflow (C1 e1) and underflow (C1 e0).

Reduction If FPREM or FPREM1 produces a remainder that is less than the modulus, reduction is

complete. When reduction is incomplete the value at the top of the stack is a partial

remainder, which can be used as input to further reduction. For FPTAN, FSIN, FCOS, and

FSINCOS, the reduction bit is set if the operand at the top of the stack is too large. In this

case the original operand remains at the top of the stack.

Roundup When the PE bit of the status word is set, this bit indicates whether the last rounding in the

instruction was upward.

UNDEFINED Do not rely on finding any specific value in these bits.

Intel387TM DX MATH COPROCESSOR

Table 2.3. Condition Code Interpretation after FPREM and FPREM1 Instructions

Condition Code Interpretation after FPREM and FPREM1

C2 C3 C1 C0

Incomplete Reduction:

1 X X X further interation required

for complete reduction

Q1 Q0 Q2 Q MOD8

000 0

010 1 Complete Reduction:

0100 2 C0, C3, C1 contain three least

110 3 significant bits of quotient

001 4

011 5

101 6

111 7

Table 2.4. Condition Code Resulting from Comparison

Order C3 C2 C0

TOP lOperand 0 0 0

TOP kOperand 0 0 1

TOP eOperand 1 0 0

Unordered 1 1 1

Table 2.5. Condition Code Defining Operand Class

C3 C2 C1 C0 Value at TOP

0000

Unsupported

0001

NaN

0010

Unsupported

0011

NaN

0100

Normal

0101

Infinity

0110

Normal

0111

Infinity

1000

1001

Empty

1010

1011

Empty

1100

Denormal

1110

Denormal

Intel387TM DX MATH COPROCESSOR

2.3.4 INSTRUCTION AND DATA POINTERS

Because the MCP operates in parallel with the CPU,

any errors detected by the MCP may be reported

after the CPU has executed the ESC instruction

which caused it. To allow identification of the failing

numeric instruction, the Intel386 DX Microprocessor

and Intel387 DX Math CoProcessor contains two

pointer registers that supply the address of the fail-

ing numeric instruction and the address of its numer-

ic memory operand (if appropriate).

The instruction and data pointers are provided for

user-written error handlers. These registers are ac-

tually located in the Intel386 DX CPU, but appear to

be located in the MCP because they are accessed

by the ESC instructions FLDENV, FSTENV, FSAVE,

and FRSTOR. (In the 8086/8087 and 80286/80287,

these registers are located in the MCP.) Whenever

the Intel386 DX CPU decodes a new ESC instruc-

tion, it saves the address of the instruction (including

any prefixes that may be present), the address of

the operand (if present), and the opcode.

The instruction and data pointers appear in one of

four formats depending on the operating mode of

the Intel386 DX Microprocessor (protected mode or

real-address mode) and depending on the operand-

size attribute in effect (32-bit operand or 16-bit oper-

and). When the Intel386 DX Microprocessor is in vir-

tual-8086 mode, the real-address mode formats are

used. (See Figures 2.3 through 2.6.) The ESC in-

structions FLDENV, FSTENV, FSAVE, and FRSTOR

are used to transfer these values between the In-

tel386 DX Microprocessor registers and memory.

Note that the value of the data pointer is

undefined

the prior ESC instruction did not have a memory op-

erand.

32-BIT PROTECTED MODE FORMAT

31 23 15 7 0

RESERVED CONTROL WORD 0

RESERVED STATUS WORD 4

RESERVED TAG WORD 8

IP OFFSET C

00000 OPCODE 10..0 CS SELECTOR 10

DATA OPERAND OFFSET 14

RESERVED OPERAND SELECTOR 18

Figure 2.3. Protected Mode Intel387TM DX MCP Instruction and

Data Pointer Image in Memory, 32-Bit Format

Intel387TM DX MATH COPROCESSOR

32-BIT REAL-ADDRESS MODE FORMAT

31 23 15 7 0

RESERVED CONTROL WORD 0

RESERVED STATUS WORD 4

RESERVED TAG WORD 8

RESERVED INSTRUCTION POINTER 15..0 C

0000 INSTRUCTION POINTER 31..16 0 OPCODE 10..0 10

RESERVED OPERAND POINTER 15..0 14

0000 OPERAND POINTER 31..16 0000 00000000 18

Figure 2.4. Real Mode Intel387TM DX MCP Instruction and Data Pointer Image in Memory, 32-Bit Format

16-BIT PROTECTED MODE FORMAT

15 7 0

CONTROL WORD 0

STATUS WORD 2

TAG WORD 4

IP OFFSET 6

CS SELECTOR 8

OPERAND OFFSET A

OPERAND SELECTOR C

Figure 2.5. Protected Mode Intel387TM DX MCP

Instruction and Data Pointer

Image in Memory, 16-Bit Format

16-BIT REAL-ADDRESS MODE AND

VIRTUAL-8086 MODE FORMAT

15 7 0

CONTROL WORD 0

STATUS WORD 2

TAG WORD 4

INSTRUCTION POINTER 15..0 6

IP19.16 0 OPCODE 10..0 8

OPERAND POINTER 15..0 A

DP 19.16 00000000000 0 C

Figure 2.6. Real Mode Intel387TM DX MCP

Instruction and Data Pointer

Image in Memory, 16-Bit Format

Intel387TM DX MATH COPROCESSOR

240448–4

Precision Control Rounding Control

00Ð24 bits (single precision) 00ÐRound to nearest or even

01Ð(reserved) 01ÐRound down (toward b%)

10Ð53 bits (double precision) 10ÐRound up (toward a%)

11Ð64 bits (extended precision) 11ÐChop (truncate toward zero)

Figure 2.7. Intel387TM DX MCP Control Word

2.3.5 CONTROL WORD

The MCP provides several processing options that

are selected by loading a control word from memory

into the control register. Figure 2.7 shows the format

and encoding of fields in the control word.

The low-order byte of this control word configures

the MCP error and exception masking. Bits 5–0 of

the control word contain individual masks for each of

the six exceptions that the MCP recognizes.

The high-order byte of the control word configures

the MCP operating mode, including precision and

rounding.

#Bit 12 no longer defines infinity control and is a

reserved bit. Only affine closure is supported for

infinity arithmetic. The bit is initialized to zero after

RESET or FINIT and is changeable upon loading

the CW. Programs must ignore this bit.

#The rounding control (RC) bits (bits 11–10) pro-

vide for directed rounding and true chop, as well

as the unbiased round to nearest even mode

specified in the IEEE standard. Rounding control

affects only those instructions that perform

rounding at the end of the operation (and thus

can generate a precision exception); namely,

FST, FSTP, FIST, all arithmetic instructions (ex-

cept FPREM, FPREM1, FXTRACT, FABS, and

FCHS), and all transcendental instructions.

#The precision control (PC) bits (bits 9–8) can be

used to set the MCP internal operating precision

of the significand at less than the default of 64

bits (extended precision). This can be useful in

providing compatibility with early generation arith-

metic processors of smaller precision. PC affects

only the instructions ADD, SUB, DIV, MUL, and

SQRT. For all other instructions, either the preci-

sion is determined by the opcode or extended

precision is used.

2.4 Interrupt Description

Several interrupts of the Intel386 DX CPU are used

to report exceptional conditions while executing nu-

meric programs in either real or protected mode. Ta-

ble 2.6 shows these interrupts and their causes.

Intel387TM DX MATH COPROCESSOR

Table 2.6. Intel386TM DX Microprocessor Interrupt Vectors Reserved for MCP

Interrupt Cause of Interrupt

Number

7 An ESC instruction was encountered when EM or TS of the Intel386TM DX CPU control

required. When TS is set, either an ESC or WAIT instruction causes interrupt 7. This

indicates that the current MCP context may not belong to the current task.

9 An operand of a coprocessor instruction wrapped around an addressing limit (0FFFFH for

small segments, 0FFFFFFFFH for big segments, zero for expand-down segments) and

spanned inaccessible addresses(1). The failing numerics instruction is not restartable. The

address of the failing numerics instruction and data operand may be lost; an FSTENV does

not return reliable addresses. As with the 80286/80287, the segment overrun exception

should be handled by executing an FNINIT instruction (i.e. an FINIT without a preceding

WAIT). The return address on the stack does not necessarily point to the failing instruction

nor to the following instruction. The interrupt can be avoided by never allowing numeric

data to start within 108 bytes of the end of a segment.

13 The first word or doubleword of a numeric operand is not entirely within the limit of its

segment. The return address pushed onto the stack of the exception handler points at the

ESC instruction that caused the exception, including any prefixes. The Intel387TM DX MCP

has not executed this instruction; the instruction pointer and data pointer register refer to a

previous, correctly executed instruction.

16 The previous numerics instruction caused an unmasked exception. The address of the

faulty instruction and the address of its operand are stored in the instruction pointer and

data pointer registers. Only ESC and WAIT instructions can cause this interrupt. The

Intel386TM DX CPU return address pushed onto the stack of the exception handler points

to a WAIT or ESC instruction (including prefixes). This instruction can be restarted after

clearing the exception condition in the MCP. FNINIT, FNCLEX, FNSTSW, FNSTENV, and

FNSAVE cannot cause this interrupt.

1. An operand may wrap around an addressing limit when the segment limit is near an addressing limit and the operand is near the largest valid

address in the segment. Because of the wrap-around, the beginning and ending addresses of such an operand will be at opposite ends of the

segment. There are two ways that such an operand may also span inaccessible addresses: 1) if the segment limit is not equal to the addressing

limit (e.g. addressing limit is FFFFH and segment limit is FFFDH) the operand will span addresses that are not within the segment (e.g. an 8-byte

operand that starts at valid offset FFFC will span addresses FFFC–FFFF and 0000-0003; however addresses FFFE and FFFF are not valid,

because they exceed the limit); 2) if the operand begins and ends in present and accessible pages but intermediate bytes of the operand fall in a

not-present page or a page to which the procedure does not have access rights.

2.5 Exception Handling

The Intel387 DX MCP detects six different exception

conditions that can occur during instruction execu-

tion. Table 2.7 lists the exception conditions in order

of precedence, showing for each the cause and the

default action taken by the MCP if the exception is

masked by its corresponding mask bit in the control

word.

Any exception that is not masked by the control

word sets the corresponding exception flag of the

status word, sets the ES bit of the status word, and

asserts the ERRORÝsignal. When the CPU at-

tempts to execute another ESC instruction or WAIT,

exception 7 occurs. The exception condition must

be resolved via an interrupt service routine. The In-

tel386 DX Microprocessor saves the address of the

floating-point instruction that caused the excep-

tion and the address of any memory operand re-

quired by that instruction.

2.6 Initialization

Intel387 DX MCP initialization software must exe-

cute an FNINIT instruction (i.e. an FINIT without a

preceding WAIT) to clear ERRORÝ. After a hardware

RESET, the ERRORÝoutput is asserted to indicate

that a Intel387 DX MCP is present. To accomplish

this, the IE and ES bits of the status word are set,

and the IM bit in the control word is reset. After

FNINIT, the status word and the control word have

the same values as in an 80287 after RESET.

Intel387TM DX MATH COPROCESSOR

2.7 8087 and 80287 Compatibility

This section summarizes the differences between

the Intel387 DX MCP and the 80287. Any migration

from the 8087 directly to the Intel387 DX MCP must

also take into account the differences between the

8087 and the 80287 as listed in Appendix A.

Many changes have been designed into the Intel387

DX MCP to directly support the IEEE standard in

hardware. These changes result in increased per-

formance by eliminating the need for software that

supports the standard.

2.7.1 GENERAL DIFFERENCES

The Intel387 DX MCP supports only affine closure

for infinity arithmetic, not projective closure. Bit 12 of

the Control Word (CW) no longer defines infinity

control. It is a reserved bit; but it is initialized to zero

after RESET or FINIT and is changeable upon load-

ing the CW. Programs must ignore this bit.

Operands for FSCALE and FPATAN are no longer

restricted in range (except for g%); F2XM1 and

FPTAN accept a wider range of operands.

The results of transcendental operations may be

slightly different from those computed by 80287.

In the case of FPTAN, the Intel387 DX MCP supplies

a true tangent result in ST(1), and (always) a floating

point 1 in ST.

Rounding control is in effect for FLD

constant

Software cannot change entries of the tag word to

values (other than empty) that do not reflect the ac-

tual register contents.

After reset, FINIT, and incomplete FPREM, the In-

tel387 DX MCP resets to zero the condition code

bits C3–C0of the status word.

In conformance with the IEEE standard, the Intel387

DX MCP does not support the special data formats:

pseudozero, pseudo-NaN, pseudoinfinity, and un-

normal.

Table 2.7. Exceptions

Exception Cause Default Action

(if exception is masked)

Invalid Operation on a signaling NaN, unsupported format, Result is a quiet NaN, integer

Operation indeterminate form (0*%, 0/0, (a%)a(b%), etc.), or indefinite, or BCD indefinite

stack overflow/underflow (SF is also set).

Denormalized At least one of the operands is denormalized, i.e. it has Normal processing

Operand the smallest exponent but a nonzero significand. continues

Zero Divisor The divisor is zero while the dividend is a noninfinite, Result is %

nonzero number.

Overflow The result is too large in magnitude to fit in the specified Result is largest finite value

format. or %

Underflow The true result is nonzero but too small to be Result is denormalized or

represented in the specified format, and, if underflow zero

exception is masked, denormalization causes loss of

accuracy.

Inexact The true result is not exactly representable in the Normal processing

Result specified format (e.g. 1/3); the result is rounded continues

(Precision) according to the rounding mode.

Intel387TM DX MATH COPROCESSOR

2.7.2 EXCEPTIONS

A number of differences exist due to changes in the

IEEE standard and to functional improvements to

the architecture of the Intel387 DX MCP:

1. When the overflow or underflow exception is

masked, the Intel387 DX MCP differs from the

80287 in rounding when overflow or underflow

occurs. The Intel387 DX MCP produces results

that are consistent with the rounding mode.

2. When the underflow exception is masked, the

Intel387 DX MCP sets its underflow flag only if

there is also a loss of accuracy during denormali-

zation.

3. Fewer invalid-operation exceptions due to de-

normal operands, because the instructions

FSQRT, FDIV, FPREM, and conversions to BCD

or to integer normalize denormal operands be-

fore proceeding.

4. The FSQRT, FBSTP, and FPREM instructions

may cause underflow, because they support de-

normal operands.

5. The denormal exception can occur during the

transcendental instructions and the FXTRACT

instruction.

6. The denormal exception no longer takes prece-

dence over all other exceptions.

7. When the denormal exception is masked, the In-

tel387 DX MCP automatically normalizes denor-

mal operands. The 8087/80287 performs unnor-

mal arithmetic, which might produce an unnor-

mal result.

8. When the operand is zero, the FXTRACT in-

struction reports a zero-divide exception and

leaves b%in ST(1).

9. The status word has a new bit (SF) that signals

when invalid-operation exceptions are due to

stack underflow or overflow.

10. FLD

extended precision

no longer reports denor-

mal exceptions, because the instruction is not

numeric.

11. FLD

single/double precision

when the operand

is denormal converts the number to extended

precision and signals the denormalized operand

exception. When loading a signaling NaN, FLD

single/double precision

signals an invalid-oper-

and exception.

12. The Intel387 DX MCP only generates quiet

NaNs (as on the 80287); however, the Intel387

DX MCP distinguishes between quiet NaNs and

signaling NaNs. Signaling NaNs trigger excep-

tions when they are used as operands; quiet

NaNs do not (except for FCOM, FIST, and

FBSTP which also raise IE for quiet NaNs).

13. When stack overflow occurs during FPTAN and

overflow is masked, both ST(0) and ST(1) con-

tain quiet NaNs. The 80287/8087 leaves the

original operand in ST(1) intact.

14. When the scaling factor is g%, the FSCALE

(ST(0), ST(1)) instruction behaves as follows

(ST(0) and ST(1) contain the scaled and scaling

operands respectively):

#FSCALE(0,%) generates the invalid operation

exception.

#FSCALE(finite, b%) generates zero with the

same sign as the scaled operand.

#FSCALE(finite, a%) generates %with the

same sign as the scaled operand.

The 8087/80287 returns zero in the first case

and raises the invalid-operation exception in the

other cases.

15. The Intel387 DX MCP returns signed infinity/

zero as the unmasked response to massive

overflow/underflow. The 8087 and 80287 sup-

port a limited range for the scaling factor; within

this range either massive overflow/underflow do

not occur or undefined results are produced.

3.0 HARDWARE INTERFACE

In the following description of hardware interface,

the Ýsymbol at the end of a signal name indicates

that the active or asserted state occurs when the

signal is at a low voltage. When no Ýis present after

the signal name, the signal is asserted when at the

high voltage level.

3.1 Signal Description

In the following signal descriptions, the Intel387 DX

Math Coprocessor pins are grouped by function as

follows:

1. Execution controlÐCPUCLK2, NUMCLK2, CKM,

RESETIN

2. MCP handshakeÐPEREQ, BUSYÝ, ERRORÝ

3. Bus interface pinsÐD31–D0, W/RÝ, ADSÝ,

READYÝ, READYOÝ

4. Chip/Port SelectÐSTEN, NPS1Ý, NPS2,

CMD0Ý

5. Power suppliesÐVCC,V

Table 3.1 lists every pin by its identifier, gives a brief

description of its function, and lists some of its char-

acteristics. All output signals are tristate; they leave

floating state only when STEN is active. The output

buffers of the bidirectional data pins D31–D0 are

also tristate; they leave floating state only in read

cycles when the MCP is selected (i.e. when STEN,

NPS1Ý, and NPS2 are all active).

Figure 3.1 and Table 3.2 together show the location

of every pin in the pin grid array.

Intel387TM DX MATH COPROCESSOR

Table 3.1. Intel387TM DX MCP Pin Summary

Pin Function Active Input/ Referenced

Name State Output To

CPUCLK2 Intel386TM DX CPU CLocK 2 I

NUMCLK2 Intel387TM DX MCP CLocK 2 I

CKM Intel387TM DX MCP CLocKing Mode I

RESETIN System reset High I CPUCLK2

PEREQ Processor Extension High O CPUCLK2/STEN

REQuest

BUSYÝBusy status Low O CPUCLK2/STEN

ERRORÝError status Low O NUMCLK2/STEN

D31–D0 Data pins High I/O CPUCLK2

W/RÝWrite/Read bus cycle Hi/Lo I CPUCLK2

ADSÝADdress Strobe Low I CPUCLK2

READYÝBus ready input Low I CPUCLK2

READYOÝReady output Low O CPUCLK2/STEN

STEN STatus ENable High I CPUCLK2

NPS1ÝMCP select Ý1 Low I CPUCLK2

NPS2 MCP select Ý2 High I CPUCLK2

CMD0ÝCoMmanD Low I CPUCLK2

VCC I

VSS I

NOTE:

STEN is referenced to only when getting the output pins into or out of tristate mode.

Table 3.2. Intel387TM DX MCP Pin Cross-Reference

ADSÝÐK7

BUSYÝÐK2

CKM Ð J11

CPUCLK24 Ð K10

CMD0ÝÐL8

D0 Ð H2

D1 Ð H1

D2 Ð G2

D3 Ð G1

D4 Ð D2

D5 Ð D1

D6 Ð C2

D7 Ð C1

D8 Ð B1

D9 Ð A2

D10 Ð B3

D11 Ð A3

D12 Ð A4

D13 Ð B5

D14 Ð A5

D15 Ð B6

D16 Ð A7

D17 Ð B8

D18 Ð A8

D19 Ð B9

D20 Ð B10

D21 Ð A10

D22 Ð B11

D23 Ð C10

D24 Ð D10

D25 Ð D11

D26 Ð E10

D27 Ð E11

D28 Ð G10

D29 Ð G11

D30 Ð H10

D31 Ð H11

ERRORÝÐL2

NPS1ÝÐL6

NPS2 Ð K6

NUMCLK2 Ð K11

PEREQ Ð K1

READYÝÐK8

READYOÝÐL3

RESETIN Ð L10

STEN Ð L4

W/RÝÐK4

CC Ð A6, A9, B4,

E1, F1, F10,

J2, K5,

VSS Ð B2, B7, C11,

E2, F2, F11,

J1, J10, L5

NO CONNECT Ð K9

TIE HIGH Ð K3, L9*

*Tie high pins may either be tied high with a pullup resistor or connected to VCC.

Intel387TM DX MATH COPROCESSOR

240448–5

*Pin 1

240448–6

*Pin 1

Figure 3.1. Intel387TM DX MCP Pin Configuration

Intel387TM DX MATH COPROCESSOR

3.1.1 Intel386TM DX CPU CLOCK 2 (CPUCLK2)

This input uses the Intel386 DX CPU CLK2 signal to

time the bus control logic. Several other MCP sig-

nals are referenced to the rising edge of this signal.

When CKM e1 (synchronous mode) this pin also

clocks the data interface and control unit and the

floating-point unit of the MCP. This pin requires

MOS-level input. The signal on this pin is divided by

two to produce the internal clock signal CLK.

3.1.2 Intel387TM DX MCP CLOCK 2 (NUMCLK2)

When CKM e0 (asynchronous mode) this pin pro-

vides the clock for the data interface and control unit

and the floating-point unit of the MCP. In this case,

the ratio of the frequency of NUMCLK2 to the fre-

quency of CPUCLK2 must lie within the range 10:16

to 14:10. When CKM e1 (synchronous mode) this

pin is ignored; CPUCLK2 is used instead for the data

interface and control unit and the floating-point unit.

This pin requires TTL-level input.

3.1.3 Intel387TM DX MCP CLOCKING MODE

(CKM)

This pin is a strapping option. When it is strapped to

VCC, the MCP operates in synchronous mode; when

strapped to VSS, the MCP operates in asynchronous

mode. These modes relate to clocking of the data

interface and control unit and the floating-point unit

only; the bus control logic always operates synchro-

nously with respect to the Intel386 DX Microproces-

sor.

240448–7

Figure 3.2. Asynchronous Operation

Intel387TM DX MATH COPROCESSOR

3.1.4 SYSTEM RESET (RESETIN)

A LOW to HIGH transition on this pin causes the

MCP to terminate its present activity and to enter a

dormant state. RESETIN must remain HIGH for at

least 40 NUMCLK2 periods. The HIGH to LOW tran-

sitions of RESETIN must be synchronous with

CPUCLK2, so that the phase of the internal clock of

the bus control logic (which is the CPUCLK2 divided

by 2) is the same as the phase of the internal clock

of the Intel386 DX CPU. After RESETIN goes LOW,

at least 50 NUMCLK2 periods must pass before the

first MCP instruction is written into the Intel387 DX

MCP. This pin should be connected to the Intel386

DX CPU RESET pin. Table 3.3 shows the status of

other pins after a reset.

Table 3.3. Output Pin Status During Reset

Pin Value Pin Name

HIGH READYOÝ, BUSYÝ

LOW PEREQ, ERRORÝ

Tri-State OFF D31–D0

3.1.5 PROCESSOR EXTENSION REQUEST

(PEREQ)

When active, this pin signals to the Intel386 DX CPU

that the MCP is ready for data transfer to/from its

data FIFO. When all data is written to or read from

the data FIFO, PEREQ is deactivated. This signal

always goes inactive before BUSYÝgoes inactive.

This signal is referenced to CPUCLK2. It should be

connected to the Intel386 DX CPU PEREQ input.

3.1.6 BUSY STATUS (BUSYÝ)

When active, this pin signals to the Intel386 DX CPU

that the MCP is currently executing an instruction.

This signal is referenced to CPUCLK2. It should be

connected to the Intel386 DX CPU BUSYÝpin.

3.1.7 ERROR STATUS (ERRORÝ)

This pin reflects the ES bits of the status register.

When active, it indicates that an unmasked excep-

tion has occurred (except that, immediately after a

reset, it indicates to the Intel386 DX Microprocessor

that a Intel387 DX MCP is present in the system).

This signal can be changed to inactive state only by

the following instructions (without a preceding

WAIT): FNINIT, FNCLEX, FNSTENV, and FNSAVE.

This signal is referenced to NUMCLK2. It should be

connected to the Intel386 DX CPU ERRORÝpin.

3.1.8 DATA PINS (D31–D0)

These bidirectional pins are used to transfer data

and opcodes between the Intel386 DX CPU and In-

tel387 DX MCP. They are normally connected direct-

ly to the corresponding Intel386 DX CPU data pins.

HIGH state indicates a value of one. D0 is the least

significant data bit. Timings are referenced to

CPUCLK2.

3.1.9 WRITE/READ BUS CYCLE (W/RÝ)

This signal indicates to the MCP whether the In-

tel386 DX CPU bus cycle in progress is a read or a

write cycle. This pin should be connected directly to

the Intel386 DX CPU W/RÝpin. HIGH indicates a

write cycle; LOW, a read cycle. This input is ignored

if any of the signals STEN, NPS1Ý, or NPS2 is inac-

tive. Setup and hold times are referenced to

CPUCLK2.

3.1.10 ADDRESS STROBE (ADSÝ)

This input, in conjunction with the READYÝinput

indicates when the MCP bus-control logic may sam-

ple W/RÝand the chip-select signals. Setup and

hold times are referenced to CPUCLK2. This pin

should be connected to the Intel386 DX CPU ADSÝ

pin.

Intel387TM DX MATH COPROCESSOR

3.1.11 BUS READY INPUT (READYÝ)

This input indicates to the MCP when a Intel386 DX

CPU bus cycle is to be terminated. It is used by the

bus-control logic to trace bus activities. Bus cycles

can be extended indefinitely until terminated by

READYÝ. This input should be connected to the

same signal that drives the Intel386 DX CPU

READYÝinput. Setup and hold times are refer-

enced to CPUCLK2.

3.1.12 READY OUTPUT (READYOÝ)

This pin is activated at such a time that write cycles

are terminated after two clocks (except FLDENV

and FRSTOR) and read cycles after three clocks. In

configurations where no extra wait states are re-

quired, this pin must directly or indirectly drive the

Intel386 DX CPU READYÝinput. Refer to section

3.4 ‘‘Bus Operation’’ for details. This pin is activated

only during bus cycles that select the MCP. This sig-

nal is referenced to CPUCLK2.

3.1.13 STATUS ENABLE (STEN)

This pin serves as a chip select for the MCP. When

inactive, this pin forces BUSYÝ, PEREQ, ERRORÝ,

and READYOÝoutputs into floating state. D31–D0

are normally floating and leave floating state only if

STEN is active and additional conditions are met.

STEN also causes the chip to recognize its other

chip-select inputs. STEN makes it easier to do on-

board testing (using the overdrive method) of other

chips in systems containing the MCP. STEN should

be pulled up with a resistor so that it can be pulled

down when testing. In boards that do not use on-

board testing, STEN should be connected to VCC.

Setup and hold times are relative to CPUCLK2. Note

that STEN must maintain the same setup and hold

times as NPS1Ý, NPS2, and CMD0Ý(i.e. if STEN

changes state during a Intel387 DX MCP bus cycle,

it should change state during the same CLK period

as the NPS1Ý, NPS2, and CMD0Ýsignals).

3.1.14 MCP Select Ý1 (NPS1Ý)

When active (along with STEN and NPS2) in the first

period of a Intel386 DX CPU bus cycle, this signal

indicates that the purpose of the bus cycle is to com-

municate with the MCP. This pin should be connect-

ed directly to the Intel386 DX CPU M/IOÝpin, so

that the MCP is selected only when the Intel386 DX

CPU performs I/O cycles. Setup and hold times are

referenced to CPUCLK2.

3.1.15 MCP SELECT Ý2 (NPS2)

When active (along with STEN and NPS1Ý)inthe

first period of an Intel386 DX CPU bus cycle, this

signal indicates that the purpose of the bus cycle is

to communicate with the MCP. This pin should be

connected directly to the Intel386 DX CPU A31 pin,

so that the MCP is selected only when the Intel386

DX CPU uses one of the I/O addresses reserved for

the MCP (800000F8 or 800000FC). Setup and hold

times are referenced to CPUCLK2.

3.1.16 COMMAND (CMD0Ý)

During a write cycle, this signal indicates whether an

opcode (CMD0Ýactive) or data (CMD0Ýinactive)

is being sent to the MCP. During a read cycle, it

indicates whether the control or status register

(CMD0Ýactive) or a data register (CMD0Ýinactive)

is being read. CMD0Ýshould be connected directly

to the A2 output of the Intel386 DX Microprocessor.

Setup and hold times are referenced to CPUCLK2.

3.2 Processor Architecture

As shown by the block diagram on the front page,

the MCP is internally divided into three sections: the

bus control logic (BCL), the data interface and con-

trol unit, and the floating point unit (FPU). The FPU

(with the support of the control unit which contains

the sequencer and other support units) executes all

numerics instructions. The data interface and control

unit is responsible for the data flow to and from the

FPU and the control registers, for receiving the in-

structions, decoding them, and sequencing the mi-

croinstructions, and for handling some of the admin-

istrative instructions. The BCL is responsible for the

Intel386 DX CPU bus tracking and interface. The

BCL is the only unit in the Intel387 DX MCP that

must run synchronously with the Intel386 DX CPU;

the rest of the MCP can run asynchronously with

respect to the Intel386 DX Microprocessor.

Intel387TM DX MATH COPROCESSOR

3.2.1 BUS CONTROL LOGIC

The BCL communicates solely with the CPU using

I/O bus cycles. The BCL appears to the CPU as a

special peripheral device. It is special in two re-

spects: the CPU initiates I/O automatically when it

encounters ESC instructions, and the CPU uses re-

served I/O addresses to communicate with the BCL.

The BCL does not communicate directly with memo-

ry. The CPU performs all memory access, transfer-

ring input operands from memory to the MCP and

transferring outputs from the MCP to memory.

3.2.2 DATA INTERFACE AND CONTROL UNIT

The data interface and control unit latches the data

and, subject to BCL control, directs the data to the

FIFO or the instruction decoder. The instruction de-

coder decodes the ESC instructions sent to it by the

CPU and generates controls that direct the data flow

in the FIFO. It also triggers the microinstruction se-

quencer that controls execution of each instruction.

If the ESC instruction is FINIT, FCLEX, FSTSW,

FSTSW AX, or FSTCW, the control executes it inde-

pendently of the FPU and the sequencer. The data

interface and control unit is the one that generates

the BUSYÝ, PEREQ and ERRORÝsignals that syn-

chronize Intel387 DX MCP activities with the In-

tel386 DX CPU. It also supports the FPU in all opera-

tions that it cannot perform alone (e.g. exceptions

handling, transcendental operations, etc.).

3.2.3 FLOATING POINT UNIT

The FPU executes all instructions that involve the

dental, constant, and data transfer instructions. The

data path in the FPU is 84 bits wide (68 significant

bits, 15 exponent bits, and a sign bit) which allows

internal operand transfers to be performed at very

high speeds.

3.3 System Configuration

As an extension to the Intel386 DX Microprocessor,

the Intel387 DX Math Coprocessor can be connect-

ed to the CPU as shown by Figure 3.3. A dedicated

240448–8

Figure 3.3. Intel386TM DX Microprocessor and Intel387TM DX Math Coprocessor System Configuration

Intel387TM DX MATH COPROCESSOR

Table 3.4. Bus Cycles Definition

STEN NPS1ÝNPS2 CMD0ÝW/RÝBus Cycle Type

0 x x x x MCP not selected and all

outputs in floating state

1 1 x x x MCP not selected

1 x 0 x x MCP not selected

1 0 1 0 0 CW or SW read from MCP

1 0 1 0 1 Opcode write to MCP

1 0 1 1 0 Data read from MCP

1 0 1 1 1 Data write to MCP

communication protocol makes possible high-speed

transfer of opcodes and operands between the In-

tel386 DX CPU and Intel387 DX MCP. The Intel387

DX MCP is designed so that no additional compo-

nents are required for interface with the Intel386 DX

CPU. The Intel387 DX MCP shares the 32-bit wide

local bus of the Intel386 DX CPU and most control

pins of the Intel387 DX MCP are connected directly

to pins of the Intel386 DX Microprocessor.

3.3.1 BUS CYCLE TRACKING

The ADSÝand READYÝsignals allow the MCP to

track the beginning and end of the Intel386 DX CPU

bus cycles, respectively. When ADSÝis asserted at

the same time as the MCP chip-select inputs, the

bus cycle is intended for the MCP. To signal the end

of a bus cycle for the MCP, READYÝmay be assert-

ed directly or indirectly by the MCP or by other bus-

control logic. Refer to Table 3.4 for definition of the

types of MCP bus cycles.

3.3.2 MCP ADDRESSING

The NPS1Ý, NPS2 and STEN signals allow the

MCP to identify which bus cycles are intended for

the MCP. The MCP responds only to I/O cycles

when bit 31 of the I/O address is set. In other words,

the MCP acts as an I/O device in a reserved I/O

address space.

Because A31 is used to select the MCP for data

transfers, it is not possible for a program running on

the Intel386 DX CPU to address the MCP with an I/

O instruction. Only ESC instructions cause the In-

tel386 DX Microprocessor to communicate with the

MCP. The Intel386 DX CPU BS16Ýinput must be

inactive during I/O cycles when A31 is active.

3.3.3 FUNCTION SELECT

The CMD0Ýand W/RÝsignals identify the four

kinds of bus cycle: control or status register read,

data read, opcode write, data write.

3.3.4 CPU/MCP Synchronization

The pin pairs BUSYÝ, PEREQ, and ERRORÝare

used for various aspects of synchronization between

the CPU and the MCP.

BUSYÝis used to synchronize instruction transfer

from the Intel386 DX CPU to the MCP. When the

MCP recognizes an ESC instruction, it asserts

BUSYÝ. For most ESC instructions, the Intel386 DX

CPU waits for the MCP to deassert BUSYÝbefore

sending the new opcode.

The MCP uses the PEREQ pin of the Intel386 DX

CPU to signal that the MCP is ready for data transfer

to or from its data FIFO. The MCP does not directly

access memory; rather, the Intel386 DX Microproc-

essor provides memory access services for the

MCP. Thus, memory access on behalf of the MCP

always obeys the rules applicable to the mode of the

Intel386 DX CPU, whether the Intel386 DX CPU be

in real-address mode or protected mode.

Once the Intel386 DX CPU initiates an MCP instruc-

tion that has operands, the Intel386 DX CPU waits

for PEREQ signals that indicate when the MCP is

ready for operand transfer. Once all operands have

been transferred (or if the instruction has no oper-

ands) the Intel386 DX CPU continues program exe-

cution while the MCP executes the ESC instruction.

In 8086/8087 systems, WAIT instructions may be

required to achieve synchronization of both com-

mands and operands. In 80286/80287, Intel386 DX

Microprocessor and Intel387 DX Math Coprocessor

systems, WAIT instructions are required only for op-

erand synchronization; namely, after MCP stores to

memory (except FSTSW and FSTCW) or loads from

memory. Used this way, WAIT ensures that the val-

ue has already been written or read by the MCP be-

fore the CPU reads or changes the value.

Intel387TM DX MATH COPROCESSOR

Once it has started to execute a numerics instruction

and has transferred the operands from the Intel386

DX CPU, the MCP can process the instruction in par-

allel with and independent of the host CPU. When

the MCP detects an exception, it asserts the ER-

RORÝsignal, which causes a Intel386 DX CPU in-

terrupt.

3.3.5 SYNCHRONOUS OR ASYNCHRONOUS

MODES

The internal logic of the Intel387 DX MCP (the FPU)

can either operate directly from the CPU clock (syn-

chronous mode) or from a separate clock (asynchro-

nous mode). The two configurations are distin-

guished by the CKM pin. In either case, the bus con-

trol logic (BCL) of the MCP is synchronized with the

CPU clock. Use of asynchronous mode allows the

Intel386 DX CPU and the FPU section of the MCP to

run at different speeds. In this case, the ratio of the

frequency of NUMCLK2 to the frequency of

CPUCLK2 must lie within the range 10:16 to 14:10.

Use of synchronous mode eliminates one clock gen-

erator from the board design.

3.3.6 AUTOMATIC BUS CYCLE TERMINATION

In configurations where no extra wait states are re-

quired, READYOÝcan be used to drive the Intel386

DX CPU READYÝinput. If this pin is used, it should

be connected to the logic that ORs all READY out-

puts from peripherals on the Intel386 DX CPU bus.

READYOÝis asserted by the MCP only during I/O

cycles that select the MCP. Refer to section 3.4

‘‘Bus Operation’’ for details.

3.4 Bus Operation

With respect to the bus interface, the Intel387 DX

MCP is fully synchronous with the Intel386 DX Mi-

croprocessor. Both operate at the same rate, be-

cause each generates its internal CLK signal by di-

viding CPUCLK2 by two.

The Intel386 DX CPU initiates a new bus cycle by

activating ADSÝ. The MCP recognizes a bus cycle,

if, during the cycle in which ADSÝis activated,

STEN, NPS1Ý, and NPS2 are all activated. Proper

operation is achieved if NPS1Ýis connected to the

M/IOÝoutput of the Intel386 DX CPU, and NPS2 to

the A31 output. The Intel386 DX CPU’s A31 output

is guaranteed to be inactive in all bus cycles that do

not address the MCP (i.e. I/O cycles to other devic-

es, interrupt acknowledge, and reserved types of

bus cycles). System logic must not signal a 16-bit

bus cycle via the Intel386 DX CPU BS16Ýinput dur-

ing I/O cycles when A31 is active.

During the CLK period in which ADSÝis activated,

the MCP also examines the W/RÝinput signal to

determine whether the cycle is a read or a write cy-

cle and examines the CMD0Ýinput to determine

whether an opcode, operand, or control/status reg-

ister transfer is to occur.

The Intel387 DX MCP supports both pipelined and

nonpipelined bus cycles. A nonpipelined cycle is one

for which the Intel386 DX CPU asserts ADSÝwhen

no other MCP bus cycle is in progress. A pipelined

bus cycle is one for which the Intel386 DX CPU as-

serts ADSÝand provides valid next-address and

control signals as soon as in the second CLK period

after the ADSÝassertion for the previous Intel386

DX CPU bus cycle. Pipelining increases the availabil-

ity of the bus by at least one CLK period. The MCP

supports pipelined bus cycles in order to optimize

address pipelining by the Intel386 DX CPU for mem-

ory cycles.

Bus operation is described in terms of an abstract

state machine

. Figure 3.4 illustrates the states and

state transitions for MCP bus cycles:

#TIis the idle state. This is the state of the bus

logic after RESET, the state to which bus logic

returns after evey nonpipelined bus cycle, and

the state to which bus logic returns after a series

of pipelined cycles.

#TRS is the READYÝsensitive state. Different

types of bus cycle may require a minimum of one

or two successive TRS states. The bus logic re-

mains in TRS state until READYÝis sensed, at

which point the bus cycle terminates. Any number

of wait states may be implemented by delaying

READYÝ, thereby causing additional successive

TRS states.

#TPis the first state for every pipelined bus cycle.

240448–9

Figure 3.4. Bus State Diagram

Intel387TM DX MATH COPROCESSOR

The READYOÝoutput of the Intel387 DX MCP indi-

cates when a bus cycle for the MCP may be termi-

nated if no extra wait states are required. For all

write cycles (except those for the instructions

FLDENV and FRSTOR), READYOÝis always as-

serted in the first TRS state, regardless of the num-

ber of wait states. For all read cycles and write cy-

cles for FLDENV and FRSTOR, READYOÝis al-

ways asserted in the second TRS state, regardless

of the number of wait states. These rules apply to

both pipelined and nonpipelined cycles. Systems de-

signers must use READYOÝin one of the following

ways:

1. Connect it (directly or through logic that ORs

READY signals from other devices) to the

READYÝinputs of the Intel386 DX CPU and In-

tel387 DX MCP.

2. Use it as one input to a wait-state generator.

The following sections illustrate different types of

MCP bus cycles.

Because different instructions have different

amounts of overhead before, between, and after op-

erand transfer cycles, it is not possible to represent

in a few diagrams all of the combinations of succes-

sive operand transfer cycles. The following bus-cy-

cle diagrams show memory cycles between MCP

operand-transfer cycles. Note however that, during

the instructions FLDENV, FSTENV, FSAVE, and

FRSTOR, some consecutive accesses to the MCP

do not have intervening memory accesses. For the

timing relationship between operand transfer cycles

and opcode write or other overhead activities, see

Figure 3.8.

3.4.1 NONPIPELINED BUS CYCLES

Figure 3.5 illustrates bus activity for consecutive

nonpipelined bus cycles.

3.4.1.1 Write Cycle

At the second clock of the bus cycle, the Intel387

DX MCP enters the TRS (READYÝ-sensitive) state.

During this state, the Intel387 DX MCP samples the

READYÝinput and stays in this state as long as

READYÝis inactive.

In write cycles, the MCP drives the READYOÝsig-

nal for one CLK period beginning with the second

CLK of the bus cycle; therefore, the fastest write

cycle takes two CLK cycles (see cycle 2 of Figure

3.5). For the instructions FLDENV and FRSTOR,

however, the MCP forces a wait state by delaying

the activation of READYOÝto the second TRS cy-

cle (not shown in Figure 3.5).

When READYÝis asserted the MCP returns to the

idle state, in which ADSÝcould be asserted again

by the Intel386 DX Microprocessor for the next cy-

cle.

3.4.1.2 Read Cycle

At the second clock of the bus cycle, the MCP en-

ters the TRS state. See Figure 3.5. In this state, the

MCP samples the READYÝinput and stays in this

state as long as READYÝis inactive.

At the rising edge of CLK in the second clock period

of the cycle, the MCP starts to drive the D31–D0

outputs and continues to drive them as long as it

stays in TRS state.

In read cycles that address the MCP, at least one

wait state must be inserted to insure that the In-

tel386 DX CPU latches the correct data. Since the

MCP starts driving the system data bus only at the

rising edge of CLK in the second clock period of the

bus cycle, not enough time is left for the data signals

to propagate and be latched by the Intel386 DX CPU

at the falling edge of the same clock period. The

MCP drives the READYOÝsignal for one CLK peri-

od in the third CLK of the bus cycle. Therefore, if the

READYOÝoutput is used to drive the Intel386 DX

CPU READYÝinput, one wait state is inserted auto-

matically.

Because one wait state is required for MCP reads,

the minimum is three CLK cycles per read, as cycle

3 of Figure 3.5 shows.

When READYÝis asserted the MCP returns to the

idle state, in which ADSÝcould be asserted again

by the Intel386 DX CPU for the next cycle. The tran-

sition from TRS state to idle state causes the MCP to

put the tristate D31–D0 outputs into the floating

state, allowing another device to drive the system

data bus.

Intel387TM DX MATH COPROCESSOR

240448–10

Cycles1&2represent part of the operand transfer cycle for instructions involving either 4-byte or 8-byte operand loads.

Cycles3&4represent part of the operand transfer cycle for a store operation.

*Cycles1&2could repeat here or TIstates for various non-operand transfer cycles and overhead.

Figure 3.5. Nonpipelined Read and Write Cycles

3.4.2 PIPELINED BUS CYCLES

Because all the activities of the Intel387 DX MCP

bus interface occur either during the TRS state or

during the transitions to or from that state, the only

difference between a pipelined and a nonpipelined

cycle is the manner of changing from one state to

another. The exact activities in each state are de-

tailed in the previous section ‘‘Nonpipelined Bus Cy-

cles’’.

When the Intel386 DX CPU asserts ADSÝbefore

the end of a bus cycle, both ADSÝand READYÝ

are active during a TRS state. This condition causes

the MCP to change to a different state named TP.

The MCP activities in the transition from a TRS state

to a TPstate are exactly the same as those in the

transition from a TRS state to a TIstate in nonpipe-

lined cycles.

TPstate is metastable; therefore, one clock period

later the MCP returns to TRS state. In consecutive

pipelined cycles, the MCP bus logic uses only TRS

and TPstates.

Figure 3.6 shows the fastest transition into and out

of the pipelined bus cycles. Cycle 1 in this figure

represents a nonpipelined cycle. (Nonpipelined write

cycles with only one TRS state (i.e. no wait states)

are always followed by another nonpipelined cycle,

because READYÝis asserted before the earliest

possible assertion of ADSÝfor the next cycle.)

Figure 3.7 shows the pipelined write and read cycles

with one additional TRS states beyond the minimum

required. To delay the assertion of READYÝre-

quires external logic.

Intel387TM DX MATH COPROCESSOR

3.4.3 BUS CYCLES OF MIXED TYPE

When the Intel387 DX MCP bus logic is in the TRS

state, it distinguishes between nonpipelined and

pipelined cycles according to the behavior of ADSÝ

and READYÝ. In a nonpipelined cycle, only

READYÝis activated, and the transition is from TRS

to idle state. In a pipelined cycle, both READYÝand

ADSÝare active and the transition is first from TRS

state to TPstate then, after one clock period, back

to TRS state.

3.4.4 BUSYÝAND PEREQ TIMING

RELATIONSHIP

Figure 3.8 shows the activation of BUSYÝat the

beginning of instruction execution and its deactiva-

tion after execution of the instruction is complete.

When possible, the Intel387 DX MCP may deacti-

vate BUSYÝprior to the completion of the current

instruction allowing the CPU to transfer the next in-

struction’s opcode and operands. PEREQ is activat-

ed in this interval. If ERRORÝ(not shown in the

diagram) is ever asserted, it would occur at least six

CPUCLK2 periods after the deactivation of PEREQ

and at least six CPUCLK2 periods before the deacti-

vation of BUSYÝ. Figure 3.8 shows also that STEN

is activated at the beginning of a bus cycle.

240448–11

Cycle 1– Cycle 4 represent the operand transfer cycle for an instruction involving a transfer of two 32-bit loads in total.

The opcode write cycles and other overhead are not shown.

Note that the next cycle will be a pipelined cycle if both READYÝand ADSÝare sampled active at the end of a TRS

state of the current cycle.

Figure 3.6. Fastest Transitions to and from Pipelined Cycles

Intel387TM DX MATH COPROCESSOR

240448–12

NOTE:

1. Cycles between operand write to the MCP and storing result.

Figure 3.7. Pipelined Cycles with Wait States

240448–13

NOTES:

1. Instruction dependent.

2. PEREQ is an asynchronous input to the Intel386TM DX Microprocessor; it may not be asserted (instruction depen-

dent).

3. More operand transfers.

4. Memory read (operand) cycle is not shown.

Figure 3.8. STEN, BUSYÝand PEREQ Timing Relationship

Intel387TM DX MATH COPROCESSOR

4.0 ELECTRICAL DATA

4.1 Absolute Maximum Ratings*

Case Temperature TC

Under Bias ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀb65§Ctoa

110§C

Storage Temperature ÀÀÀÀÀÀÀÀÀÀb65§Ctoa

150§C

Voltage on Any Pin with

Respect to Ground ÀÀÀÀÀÀÀÀÀb0.5 to VCC a0.5V

Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W

NOTICE: This is a production data sheet. The specifi-

cations are subject to change without notice.

WARNING: Stressing the device beyond the ‘‘Absolute

Maximum Ratings’’ may cause permanent damage.

These are stress ratings only. Operation beyond the

‘‘Operating Conditions’’ is not recommended and ex-

tended exposure beyond the ‘‘Operating Conditions’’

may affect device reliability.

4.2 DC Characteristics

Table 4.1. DC Specifications TCe0§to 85§C, VCC e5V g5%

Symbol Parameter Min Max Units Test Conditions

VIL Input LO Voltage b0.3 a0.8 V (Note 1)

VIH Input HI Voltage 2.0 VCC a0.3 V (Note 1)

VCL CPUCLK2 Input LO Voltage b0.3 a0.8 V

VCH CPUCLK2 Input HI Voltage 3.7 VCC a0.3 V

VOL Output LO Voltage 0.45 V (Note 2)

VOH Output HI Voltage 2.4 V (Note 3)

ICC Supply Current

NUMCLK2 e32 MHz(4) 160 mA ICC typ. e95 mA

NUMCLK2 e40 MHz(4) 180 mA ICC typ. e105 mA

NUMCLK2 e50 MHz(4) 210 mA ICC typ. e125 mA

NUMCLK2 e66.6 MHz(4) 250 mA ICC typ. e150 mA

ILI Input Leakage Current g15 mA0V

IN sVCC

ILO I/O Leakage Current g15 mA 0.45V sVOsVCC

CIN Input Capacitance 10 pF fc e1 MHz

COI/O or Output Capacitance 12 pF fc e1 MHz

CCLK Clock Capacitance 15 pF fc e1 MHz

NOTES:

1. This parameter is for all inputs, including NUMCLK2 but excluding CPUCLK2.

2. This parameter is measured at IOL as follows:

data e4.0 mA

READYOÝe2.5 mA

ERRORÝ, BUSYÝ, PEREQ e2.5 mA

3. This parameter is measured at IOH as follows:

data e1.0 mA

READYOÝe0.6 mA

ERRORÝ, BUSYÝ, PEREQ e0.6 mA

4. ICC is measured at steady state, maximum capacitive loading on the outputs, CPUCLK2 at the same frequency as

NUMCLK2.

Intel387TM DX MATH COPROCESSOR

4.3 AC Characteristics

Table 4.2a. i387 DX/i386 DX Interface and Execution Frequencies

Frequency (MHz)

i386 DX System i387 DX 16-33

Execution Frequency (MHz)

Min Max

16 MHz 10.0 MHz 22.4 MHz

20 MHz 12.5 MHz 28.0 MHz

25 MHz 15.6 MHz 33.0 MHz

33 MHz 20.6 MHz 33.0 MHz

NOTE:

The external clock frequencies for the i387 DX and i386 DX are

equal to twice the interface and execution frequencies show

above.

Table 4.2b. Timing Requirements of the Execution Unit

TCe0§Ctoa

85§C, VCC e5V g5%

Pin Symbol Parameter 16 MHz –33 MHz

Conditions

Test

Reference

Figure

Min (ns) Max (ns)

NUMCLK2 t1 Period 15 125 2.0V 4.1

NUMCLK2 t2a High Time 6.25 2.0V

NUMCLK2 t2b High Time 4.5 3.7V

NUMCLK2 t3a Low Time 6.25 2.0V

NUMCLK2 t3b Low Time 4.5 0.8V

NUMCLK2 t4 Fall Time 6 3.7V to 0.8V

NUMCLK2 t5 Rise Time 6 0.8V to 2.7V

Table 4.2c. Timing Requirements of the Bus Interface Unit

TCe0§Ctoa

85§C, VCC e5V g5%

(All measurements made at 1.5V and 50 pF unless otherwise specified)

Pin Symbol Parameter 16 MHz–33 MHz

Conditions

Test

Reference

Figure

Min (ns) Max (ns)

CPUCLK2 t1 Period 15 125 2.0V 4.1

CPUCLK2 t2a High Time 6.25 2.0V

CPUCLK2 t2b High Time 4.5 3.7V

CPUCLK2 t3a Low Time 6.25 2.0V

CPUCLK2 t3b Low Time 4.5 0.8V

CPUCLK2 t4 Fall Time 6 3.7V to 0.8V

CPUCLK2 t5 Rise Time 6 0.8V to 3.7V

NUMCLK2/ Ratio 10/16 14/10

CPUCLK2

READYOÝt7 Out Delay 4 17 4.2

READYOÝ(1) t7 Out Delay 4 15 CLe25 pF

PEREQ t7 Out Delay 4 25

BUSYÝt7 Out Delay 4 21

BUSYÝ(1) t7 Out Delay 4 19 CLe25 pF

ERRORÝt7 Out Delay 4 25

D31–D0 t8 Out Delay 0 37 4.3

D31–D0 t10 Setup Time 8

D31–D0 t11 Hold Time 8

D31–D0(2) t12 Float Time 3 19

Intel387TM DX MATH COPROCESSOR

Table 4.2c. Timing Requirements of the Bus Interface Unit (Continued)

TCe0§Ctoa

85§C, VCC e5V g5%

(All measurements made at 1.5V and 50 pF unless otherwise specified)

Pin Symbol Parameter 16 MHz–33 MHz

Conditions

Test

Reference

Figure

Min (ns) Max (ns)

PEREQ(2) t13 Float Time 1 30 4.5

BUSYÝ(2) t13 Float Time 1 30

ERRORÝ(2) t13 Float Time 1 30

READYOÝ(2) t13 Float Time 1 30

ADSÝt14 Setup Time 13 4.3

ADSÝt15 Hold Time 4

W/RÝt14 Setup Time 13

W/RÝt15 Hold Time 4

READYÝt16 Setup Time 7

READYÝt17 Hold Time 4

CMDOÝt16 Setup Time 13

CMDOÝt17 Hold Time 2

NPS1Ýt16 Setup Time 13

NPS2

NPS1Ýt17 Hold Time 2

NPS2

STEN t16 Setup Time 13

STEN t17 Hold Time 2

RESETIN t18 Setup Time 5 4.4

RESETIN t19 Hold Time 3

NOTES:

1. Not tested at 25 pF.

2. Float delay is not tested. Float condition occurs when maximum output current becomes less than ILO in magnitude.

*nom - nominal value 240448–14

NOTE:

This graph will not be linear outside of the CLrange

shown.

Figure 4.0a. Typical Output Valid Delay vs Load

Capacitance at Max Operating Temperature

240448–15

NOTE:

This graph will not be linear outside of the CLrange

shown.

Figure 4.0b. Typical Output Rise Time vs Load

Capacitance at Max Operating Temperature

Intel387TM DX MATH COPROCESSOR

240448–16

Figure 4.1. CPUCLK2/NUMCLK2 Waveform and Measurement Points for

Input/Output A.C. Specifications

240448–17

Figure 4.2. Output Signals

Intel387TM DX MATH COPROCESSOR

240448–18

Figure 4.3. Input and I/O Signals

NOTE: 240448–19

The second internal processor phase following RESET high to low transition is PH2.

Figure 4.4. RESET Signal

240448–20

Figure 4.5. Float from STEN

Intel387TM DX MATH COPROCESSOR

Table 4.3. Other Parameters

Pin Symbol Parameter Min Max Units

RESETIN t30 Duration 40 NUMCLK2

RESETIN t31 RESETIN Inactive to 1st Opcode Write 50 NUMCLK2

BUSYÝt32 Duration 6 CPUCLK2

BUSYÝ, ERRORÝt33 ERRORÝ(In) Active to BUSYÝInactive 6 CPUCLK2

PEREQ, ERRORÝt34 PEREQ Inactive to ERRORÝActive 6 CPUCLK2

READYÝ, BUSYÝt35 READYÝActive to BUSYÝActive 4 4 CPUCLK2

READYÝt36 Minimum Time from Opcode Write to 6 CPUCLK2

Opcode/Operand Write

READYÝt37 Minimum Time from Operand Write to 8 CPUCLK2

Operand Write

240448–21

*In NUMCLK2’s

** or last operand

NOTE:

1. Memory read (operand) cycle is not shown.

Figure 4.6. Other Parameters

Intel387TM DX MATH COPROCESSOR

Instruction Optional

First Byte Second Byte Fields

1 11011 OPA 1 MOD 1 OPB R/M SIB DISP

2 11011 MF OPA MOD OPB R/M SIB DISP

3 11011 d P OPA 1 1 OPB ST(i)

4 11011 0 0 1 1 1 1 OP

5 11011 0 1 1 1 1 1 OP

15–11 10 9 8 7 6 5 43210

5.0 Intel387TM DX MCP EXTENSIONS

TO THE Intel386TM DX CPU

INSTRUCTION SET

Instructions for the Intel387 DX MCP assume one of

the five forms shown in the following table. In all

cases, instructions are at least two bytes long and

begin with the bit pattern 11011B, which identifies

the ESCAPE class of instruction. Instructions that

refer to memory operands specify addresses using

the Intel386 DX CPU addressing modes.

OP eInstruction opcode, possible split into two

fields OPA and OPB

MF eMemory Format

00Ð32-bit real

01Ð32-bit integer

10Ð64-bit real

11Ð16-bit integer

PePop

0ÐDo not pop stack

1ÐPop stack after operation

ESC e11011

deDestination

0ÐDestination is ST(0)

1ÐDestination is ST(i)

R XOR d e0ÐDestination (op) Source

R XOR d e1ÐSource (op) Destination

ST(i) eRegister stack element

000 eStack top

001 eSecond stack element

111 eEighth stack element

MOD (Mode field) and R/M (Register/Memory spec-

ifier) have the same interpretation as the corre-

sponding fields of the Intel386 DX Microprocessor

instructions (refer to

Intel386

DX Microprocessor

Programmer’s Reference Manual

SIB (Scale Index Base) byte and DISP (displace-

ment) are optionally present in instructions that have

MOD and R/M fields. Their presence depends on

the values of MOD and R/M, as for Intel386 DX Mi-

croprocessor instructions.

The instruction summaries that follow assume that

the instruction has been prefetched, decoded, and is

ready for execution; that bus cycles do not require

wait states; that there are no local bus HOLD re-

quest delaying processor access to the bus; and

that no exceptions are detected during instruction

execution. If the instruction has MOD and R/M fields

that call for both base and index registers, add one

clock.

Intel387TM DX MATH COPROCESSOR

Intel387TM DX MCP Extensions to the Intel386TM DX CPU Instruction Set

Encoding Clock Count Range

Instruction Byte Byte Optional 32-Bit 32-Bit 64-Bit 16-Bit

0 1 Bytes 2–6 Real Integer Real Integer

DATA TRANSFER

FLD eLoada

Integer/real memory to ST(0) ESC MF 1 MOD 000 R/M SIB/DISP 9– 18 26– 42 16–23 42– 53

Long integer memory to ST(0) ESC 111 MOD 101 R/M SIB/DISP 26– 54

Extended real memory to ST(0) ESC 011 MOD 101 R/M SIB/DISP 12–43

BCD memory to ST(0) ESC 111 MOD 100 R/M SIB/DISP 45– 97

ST(i) to ST(0) ESC 001 11000 ST(i) 7–12

FST eStore

ST(0) to integer/real memory ESC MF 1 MOD 010 R/M SIB/DISP 25–43 57– 76 32– 44 58–76

ST(0) to ST(i) ESC 101 11010 ST(i) 7–11

FSTP eStore and Pop

ST(0) to integer/real memory ESC MF 1 MOD 011 R/M SIB/DISP 25–43 57– 76 32– 44 58–76

ST(0) to long integer memory ESC 111 MOD 111 R/M SIB/DISP 60– 82

ST(0) to extended real ESC 011 MOD 111 R/M SIB/DISP 46 –52

ST(0) to BCD memory ESC 111 MOD 110 R/M SIB/DISP 112–190

ST(0) to ST(i) ESC 101 11011 ST (i) 7–11

FXCH eExchange

ST(i) and ST(0) ESC 001 11001 ST(i) 10–17

COMPARISON

FCOM eCompare

Integer/real memory to ST(0) ESC MF 0 MOD 010 R/M SIB/DISP 13–25 34 –52 14 – 27 39– 62

ST(i) to ST(0) ESC 000 11010 ST(i) 13–21

FCOMP eCompare and pop

Integer/real memory to ST ESC MF 0 MOD 011 R/M SIB/DISP 13–25 34 –52 14– 27 39– 62

ST(i) to ST(0) ESC 000 11011 ST(i) 13–21

FCOMPP eCompare and pop twice

ST(1) to ST(0) ESC 110 1101 1001 13– 21

FTST eTest ST(0) ESC 001 1110 0100 17–25

FUCOM eUnordered compare ESC 101 11100 ST(i) 13–21

FUCOMP eUnordered compare

and pop ESC 101 11101 ST(i) 13–21

FUCOMPP eUnordered compare

and pop twice ESC 010 1110 1001 13–21

FXAM eExamine ST(0) ESC 001 11100101 24–37

CONSTANTS

FLDZ eLoad a0.0 into ST(0) ESC 001 1110 1110 10– 17

FLD1 eLoad a1.0 into ST(0) ESC 001 1110 1000 15– 22

FLDPI eLoad pi into ST(0) ESC 001 1110 1011 26– 36

FLDL2T eLoad log2(10) into ST(0) ESC 001 1110 1001 26–36

Shaded areas indicate instructions not available in 8087/80287.

NOTE:

a. When loading single- or double-precision zero from memory, add 5 clocks.

Intel387TM DX MATH COPROCESSOR

Intel387TM DX MCP Extensions to the Intel386TM DX CPU Instruction Set (Continued)

Encoding Clock Count Range

Instruction Byte Byte Optional 32-Bit 32-Bit 64-Bit 16-Bit

0 1 Bytes 2–6 Real Integer Real Integer

CONSTANTS (Continued)

FLDL2E eLoad log2(e) into ST(0) ESC 001 1110 1010 26–36

FLDLG2 eLoad log10(2) into ST(0) ESC 001 1110 1100 25–35

FLDLN2 eLoad loge(2) into ST(0) ESC 001 1110 1101 26 –38

ARITHMETIC

FADD eAdd

Integer/real memory with ST(0) ESC MF 0 MOD 000 R/M SIB/DISP 12–29 34 – 56 15– 34 38– 64

ST(i) and ST(0) ESCdP0 11000 ST(i) 12–26b

FSUB eSubtract

Integer/real memory with ST(0) ESC MF 0 MOD 10 R R/M SIB/DISP 12–29 34– 56 15–34 38–64c

ST(i) and ST(0) ESCdP0 1110 R R/M 12–26d

FMUL eMultiply

Integer/real memory with ST(0) ESC MF 0 MOD 001 R/M SIB/DISP 19–32 43 – 71 23– 53 46– 74

ST(i) and ST(0) ESCdP0 1100 1 R/M 17–50e

FDIV eDivide

Integer/real memory with ST(0) ESC MF 0 MOD 11 R R/M SIB/DISP 77-85 101 – 114f81–91 105– 124g

ST(i) and ST(0) ESCdP0 1111 R R/M 77-80h

FSQRTieSquare root ESC 001 1111 1010 97 –111

FSCALE eScale ST(0) by ST(1) ESC 001 1111 1101 44–82

FPREM ePartial remainder ESC 001 1111 1000 56 –140

FPREM1 ePartial remainder

(IEEE) ESC 001 1111 0101 81–168

FRNDINT eRound ST(0) ESC 001 1111 1100 41– 62

to integer

FXTRACT eExtract components

of ST(0) ESC 001 1111 0100 42 –63

FABS eAbsolute value of ST(0) ESC 001 1110 0001 14 –21

FCHS eChange sign of ST(0) ESC 001 1110 0000 17 –24

Shaded areas indicate instructions not available in 8087/80287.

NOTES:

b. Add 3 clocks to the range when d e1.

c. Add 1 clock to each range when R e1.

d. Add 3 clocks to the range when d e0.

e. typical e52 (When d e0, 46 –54, typical e49).

f. Add 1 clock to the range when R e1.

g. 135– 141 when R e1.

h. Add 3 clocks to the range when d e1.

i. b0sST(0) sa%.

Intel387TM DX MATH COPROCESSOR

Intel387TM DX MCP Extensions to the Intel386TM DX CPU Instruction Set (Continued)

Encoding

Instruction Byte Byte Optional Clock Count Range

0 1 Bytes 2– 6

TRANSCENDENTAL

FCOSkeCosine of ST(0) ESC 001 1111 1111 122–680

FPTANkePartial tangent of ST(0) ESC 001 1111 0010 162–430j

FPATAN ePartial arctangent ESC 001 1111 0011 250 –420

FSINkeSine of ST(0) ESC 001 1111 1110 121–680

FSINCOSkeSine and cosine of ST(0) ESC 001 1111 1011 150 –650

F2XM1le2ST(0) b1 ESC 001 1111 0000 167–410

FYL2XmeST(1) *log2(ST(0)) ESC 001 1111 0001 99–436

FYL2XP1neST(1) *log2(ST(0) a1.0) ESC 001 1111 1001 210–447

PROCESSOR CONTROL

FINIT eInitialize MCP ESC 011 1110 0011 33

FSTSW AX eStore status word ESC 111 1110 0000 13

FLDCW eLoad control word ESC 001 MOD 101 R/M SIB/DISP 19

FSTCW eStore control word ESC 101 MOD 111 R/M SIB/DISP 15

FSTSW eStore status word ESC 101 MOD 111 R/M SIB/DISP 15

FCLEX eClear exceptions ESC 011 1110 0010 11

FSTENV eStore environment ESC 001 MOD 110 R/M SIB/DISP 103–104

FLDENV eLoad environment ESC 001 MOD 100 R/M SIB/DISP 71

FSAVE eSave state ESC 101 MOD 110 R/M SIB/DISP 375– 376

FRSTOR eRestore state ESC 101 MOD 100 R/M SIB/DISP 308

FINCSTP eIncrement stack pointer ESC 001 1111 0111 21

FDECSTP eDecrement stack pointer ESC 001 1111 0110 22

FFREE eFree ST(i) ESC 101 1100 0 ST(i) 18

FNOP eNo operations ESC 001 1101 0000 12

Shaded areas indicate instructions not available in 8087/80287.

NOTES:

j. These timings hold for operands in the range

kq/4. For operands not in this range, up to 76 additional clocks may be

needed to reduce the operand.

k. 0 s

ST(0)

k263.

l. b1.0 sST(0) s1.0.

m. 0 sST(0) k%,b%kST(1) ka%.

n. 0 s

ST(0)

k(2 bSQRT(2))/2, b%kST(1) ka%.

Intel387TM DX MATH COPROCESSOR

APPENDIX A

COMPATIBILITY BETWEEN

THE 80287 AND THE 8087

The 80286/80287 operating in Real-Address mode

will execute 8086/8087 programs without major

modification. However, because of differences in the

handling of numeric exceptions by the 80287 MCP

and the 8087 MCP, exception-handling routines

may

need to be changed.

This appendix summarizes the differences between

the 80287 MCP and the 8087 MCP, and provides

details showing how 8086/8087 programs can be

ported to the 80286/80287.

1. The MCP signals exceptions through a dedicated

ERRORÝline to the 80286. The MCP error signal

does not pass through an interrupt controller (the

8087 INT signal does). Therefore, any interrupt-

controller-oriented instructions in numeric excep-

tion handlers for the 8086/8087 should be delet-

ed.

2. The 8087 instructions FENI/FNENI and FDISI/

FNDISI perform no useful function in the 80287. If

the 80287 encounters one of these opcodes in its

instruction stream, the instruction will effectively

be ignoredÐnone of the 80287 internal states will

be updated. While 8086/8087 containing these

instructions may be executed on the

80286/80287, it is unlikely that the exception-

handling routines containing these instructions

will be completely portable to the 80287.

3. Interrupt vector 16 must point to the numeric ex-

ception handling routine.

4. The ESC instruction address saved in the 80287

includes any leading prefixes before the ESC op-

code. The corresponding address saved in the

8087 does not include leading prefixes.

5. In Protected-Address mode, the format of the

80287’s saved instruction and address pointers is

different than for the 8087. The instruction op-

code is not saved in Protected modeÐexception

handlers will have to retrieve the opcode from

memory if needed.

6. Interrupt 7 will occur in the 80286 when executing

ESC instructions with either TS (task switched) or

EM (emulation) of the 80286 MSW set (TS e1or

EM e1). If TS is set, then a WAIT instruction will

also cause interrupt 7. An exception handler

should be included in 80286/80287 code to han-

dle these situations.

7. Interrupt 9 will occur if the second or subsequent

words of a floating-point operand fall outside a

segment’s size. Interrupt 13 will occur if the start-

ing address of a numeric operand falls outside a

segment’s size. An exception handler should be

included in 80286/80287 code to report these

programming errors.

8. Except for the processor control instructions, all

of the 80287 numeric instructions are automati-

cally synchronized by the 80286 CPUÐthe 80286

automatically tests the BUSYÝline from the

80287 to ensure that the 80287 has completed its

previous instruction before executing the next

ESC instruction. No explicit WAIT instructions are

required to assure this synchronization. For the

8087 used with 8086 and 8088 processors, ex-

plicit WAITs are required before each numeric in-

struction to ensure synchronization. Although

8086/8087 programs having explicit WAIT in-

structions will execute perfectly on the

80286/80287 without reassembly, these WAIT in-

structions are unnecessary.

9. Since the 80287 does not require WAIT instruc-

tions before each numeric instruction, the

ASM286 assembler does not automatically gener-

ate these WAIT instructions. The ASM86 assem-

bler, however, automatically precedes every ESC

instruction with a WAIT instruction. Although nu-

meric routines generated using the ASM86 as-

sembler will generally execute correctly on the

80286/80287, reassembly using ASM286 may re-

sult in a more compact code image.

The processor control instructions for the 80287

may be coded using either a WAIT or No-WAIT

form of mnemonic. The WAIT forms of these in-

structions cause ASM286 to precede the ESC in-

struction with a CPU WAIT instruction, in the iden-

tical manner as does ASM86.

DATA SHEET REVISION REVIEW

The following list represents the key differences be-

tween this and the -003 versions of the Intel387TM

Math Coprocessor Data Sheet. Please review this

summary carefully.

1. Corrected typographical errors.

2. Corrected clock ratio ‘‘PIN’’ name on Table 4.2c

to NUMCLK/CPUCLK.

A-1