74LVC1G08GM - Philips Semiconductors / NXP Semiconductors

DATA SH EET

Product speciﬁcation

Supersedes data of 2002 Oct 02 2004 Sep 15

INTEGRATED CIRCUITS

74LVC1G08

Single 2-input AND gate

2004 Sep 15 2

Philips Semiconductors Product speciﬁcation

Single 2-input AND gate 74LVC1G08

FEATURES

•Wide supply voltage range from 1.65 V to 5.5 V

•High noise immunity

•Complies with JEDEC standard:

– JESD8-7 (1.65 V to 1.95 V)

– JESD8-5 (2.3 V to 2.7 V)

– JESD8B/JESD36 (2.7 V to 3.6 V).

•±24 mA output drive (VCC = 3.0 V)

•CMOS low power consumption

•Latch-up performance ≤250 mA

•Direct interface with TTL levels

•Inputs accept voltages up to 5 V

•ESD protection:

HBM EIA/JESD22-A114-B exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V.

•Multiple package options

•Specified from −40 °C to +85 °C and −40 °C to +125 °C.

DESCRIPTION

The 74LVC1G08 is a high-performance, low-power,

low-voltage, Si-gate CMOS device, superior to most

advanced CMOS compatible TTL families.

Input can be driven from either 3.3 V or 5 V devices.

These features allow the use of these devices in a mixed

3.3 V and 5 V environment.

Schmitttriggeractionatallinputsmakesthecircuittolerant

for slower input rise and fall time.

This device is fully specified for partial power-down

applications using Ioff. The Ioff circuitry disables the output,

preventing the damaging backflow current through the

device when it is powered down.

The 74LVC1G08 provides the single 2-input AND function.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25°C; tr=t

f≤2.5 ns.

Notes

1. CPD is used to determine the dynamic power dissipation (PDin µW).

PD=C

PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:

fi= input frequency in MHz;

fo= output frequency in MHz;

CL= output load capacitance in pF;

VCC = supply voltage in Volts;

N = total load switching outputs;

Σ(CL×VCC2×fo) = sum of the outputs.

2. The condition is VI= GND to VCC.

SYMBOL PARAMETER CONDITIONS TYPICAL UNIT

tPHL/tPLH propagation delay

inputs A, B to output Y VCC = 1.8 V; CL= 30 pF; RL=1kΩ3.4 ns

VCC = 2.5 V; CL= 30 pF; RL= 500 Ω2.2 ns

VCC = 2.7 V; CL= 50 pF; RL= 500 Ω2.5 ns

VCC = 3.3 V; CL= 50 pF; RL= 500 Ω2.1 ns

VCC = 5.0 V; CL= 50 pF; RL= 500 Ω1.7 ns

CIinput capacitance 5 pF

CPD power dissipation capacitance VCC = 3.3 V; notes 1 and 2 16 pF

2004 Sep 15 3

Philips Semiconductors Product speciﬁcation

Single 2-input AND gate 74LVC1G08

FUNCTION TABLE

See note 1.

Note

1. H = HIGH voltage level;

L = LOW voltage level.

ORDERING INFORMATION

PINNING

INPUT OUTPUT

ABY

LLL

LHL

HLL

HHH

TYPE NUMBER PACKAGE

TEMPERATURE

RANGE PINS PACKAGE MATERIAL CODE MARKING

74LVC1G08GW −40 °C to +125 °C 5 SC-88A plastic SOT353 VE

74LVC1G08GV −40 °C to +125 °C 5 SC-74A plastic SOT753 V08

74LVC1G08GM −40 °C to +125 °C 6 XSON6 plastic SOT886 VE

PIN (TSSOP5 AND VSSOP5) PIN (XSON6) SYMBOL DESCRIPTION

1 1 B data input B

2 2 A data input A

3 3 GND ground (0 V)

4 4 Y data output Y

- 5 n.c. not connected

56V

CC supply voltage

2004 Sep 15 4

Philips Semiconductors Product speciﬁcation

Single 2-input AND gate 74LVC1G08

GND Y

001aab638

Fig.1 Pin configuration SC-88A and SC-74A.

001aab639

GND

n.c.

VCC

Transparent top view

Fig.2 Pin configuration XSON6.

handbook, halfpage

MNA113

Fig.3 Logic symbol.

handbook, halfpage

MNA114

Fig.4 IEE/IEC logic symbol.

mna221

Fig.5 Logic diagram.

2004 Sep 15 5

Philips Semiconductors Product speciﬁcation

Single 2-input AND gate 74LVC1G08

RECOMMENDED OPERATING CONDITIONS

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).

Notes

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VCC supply voltage 1.65 5.5 V

VIinput voltage 0 5.5 V

VOoutput voltage active mode 0 VCC V

VCC = 0 V; Power-down mode 0 5.5 V

Tamb operating ambient temperature −40 +125 °C

tr, tfinput rise and fall times VCC = 1.65 V to 2.7 V 0 20 ns/V

VCC = 2.7 V to 5.5 V 0 10 ns/V

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VCC supply voltage −0.5 +6.5 V

IIK input diode current VI<0V −−50 mA

VIinput voltage note 1 −0.5 +6.5 V

IOK output diode current VO>V

CC or VO<0V −±50 mA

VOoutput voltage active mode; notes 1 and 2 −0.5 VCC + 0.5 V

Power-down mode; notes 1 and 2 −0.5 +6.5 V

IOoutput source or sink current VO=0VtoV

CC −±50 mA

ICC, IGND VCC or GND current −±100 mA

Tstg storage temperature −65 +150 °C

Ptot power dissipation Tamb =−40 °C to +125 °C−250 mW

2004 Sep 15 6

Philips Semiconductors Product speciﬁcation

Single 2-input AND gate 74LVC1G08

DC CHARACTERISTICS

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNIT

OTHER VCC (V)

Tamb = −40 °C to +85 °C

VIH HIGH-level input

voltage 1.65 to 1.95 0.65 ×VCC −−V

2.3 to 2.7 1.7 −−V

2.7 to 3.6 2.0 −−V

4.5 to 5.5 0.7 ×VCC −−V

VIL LOW-level input

voltage 1.65 to 1.95 −−0.35 ×VCC V

2.3 to 2.7 −−0.7 V

2.7 to 3.6 −−0.8 V

4.5 to 5.5 −−0.3 ×VCC V

VOL LOW-level output

voltage VI=V

IH or VIL

IO= 100 µA 1.65 to 5.5 −−0.1 V

IO= 4 mA 1.65 −−0.45 V

IO= 8 mA 2.3 −−0.3 V

IO= 12 mA 2.7 −−0.4 V

IO= 24 mA 3.0 −−0.55 V

IO= 32 mA 4.5 −−0.55 V

VOH HIGH-level output

voltage VI=V

IH or VIL

IO=−100 µA 1.65 to 5.5 VCC −0.1 −−V

IO=−4 mA 1.65 1.2 −−V

IO=−8 mA 2.3 1.9 −−V

IO=−12 mA 2.7 2.2 −−V

IO=−24 mA 3.0 2.3 −−V

IO=−32 mA 4.5 3.8 −−V

ILI input leakage

current VI= 5.5 Vor GND 5.5 −±0.1 ±5µA

Ioff powerOFFleakage

current VIor VO= 5.5 V 0 −±0.1 ±10 µA

ICC quiescent supply

current VI=V

CC or GND;

IO=0 A 5.5 −0.1 10 µA

∆ICC additionalquiescent

supply current per

VI=V

CC −0.6 V;

IO=0 A 2.3 to 5.5 −5 500 µA

2004 Sep 15 7

Philips Semiconductors Product speciﬁcation

Single 2-input AND gate 74LVC1G08

Note

1. All typical values are measured at VCC = 3.3 V and Tamb =25°C.

Tamb = −40 °C to +125 °C

VIH HIGH-level input

voltage 1.65 to 1.95 0.65 ×VCC −−V

2.3 to 2.7 1.7 −−V

2.7 to 3.6 2.0 −−V

4.5 to 5.5 0.7 ×VCC −−V

VIL LOW-level input

voltage 1.65 to 1.95 −−0.35 ×VCC V

2.3 to 2.7 −−0.7 V

2.7 to 3.6 −−0.8 V

4.5 to 5.5 −−0.3 ×VCC V

VOL LOW-level output

voltage VI=V

IH or VIL

IO= 100 µA 1.65 to 5.5 −−0.1 V

IO= 4 mA 1.65 −−0.70 V

IO= 8 mA 2.3 −−0.45 V

IO= 12 mA 2.7 −−0.60 V

IO= 24 mA 3.0 −−0.80 V

IO= 32 mA 4.5 −−0.80 V

VOH HIGH-level output

voltage VI=V

IH or VIL

IO=−100 µA 1.65 to 5.5 VCC −0.1 −−V

IO=−4 mA 1.65 0.95 −−V

IO=−8 mA 2.3 1.7 −−V

IO=−12 mA 2.7 1.9 −−V

IO=−24 mA 3.0 2.0 −−V

IO=−32 mA 4.5 3.4 −−V

ILI input leakage

current VI= 5.5 Vor GND 5.5 −−±100 µA

Ioff powerOFFleakage

current VIor VO= 5.5 V 0 −−±200 µA

ICC quiescent supply

current VI=V

CC or GND;

IO=0 A 5.5 −−200 µA

∆ICC additionalquiescent

supply current per

VI=V

CC −0.6 V;

IO=0 A 2.3 to 5.5 −−5000 µA

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNIT

OTHER VCC (V)

2004 Sep 15 8

Philips Semiconductors Product speciﬁcation

Single 2-input AND gate 74LVC1G08

AC CHARACTERISTICS

GND = 0 V; tr=t

f≤2.0 ns.

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT

WAVEFORMS VCC (V)

Tamb = −40 °C to +85 °C

tPHL/tPLH propagation delay

A, B to Y see Figs 6 and 7 1.65 to 1.95 1.0 3.4 8.0 ns

2.3 to 2.7 0.5 2.2 5.5 ns

2.7 0.5 2.5 5.5 ns

3.0 to 3.6 0.5 2.1 4.5 ns

4.5 to 5.5 0.5 1.7 4.0 ns

Tamb = −40 °C to +125 °C

tPHL/tPLH propagation delay

A, B to Y see Figs 6 and 7 1.65 to 1.95 1.0 −10.5 ns

2.3 to 2.7 0.5 −7.0 ns

2.7 0.5 −7.0 ns

3.0 to 3.6 0.5 −6.0 ns

4.5 to 5.5 0.5 −5.5 ns

2004 Sep 15 9

Philips Semiconductors Product speciﬁcation

Single 2-input AND gate 74LVC1G08

AC WAVEFORMS

handbook, halfpage

MNA614

tPHL tPLH

A, B input

Y output

GND

VOH

VOL

Fig.6 Input A, B to output Y propagation delay times.

VCC VMINPUT

VItr=t

1.65 V to 1.95 V 0.5 ×VCC VCC ≤2.0 ns

2.3 V to 2.7 V 0.5 ×VCC VCC ≤2.0 ns

2.7 V 1.5 V 2.7 V ≤2.5 ns

3.0 V to 3.6 V 1.5 V 2.7 V ≤2.5 ns

4.5 V to 5.5 V 0.5 ×VCC VCC ≤2.5 ns

VOL and VOH are typical output voltage drop that occur with the output load.

2004 Sep 15 10

Philips Semiconductors Product speciﬁcation

Single 2-input AND gate 74LVC1G08

handbook, full pagewidth

VEXT

VCC

VIVO

MNA616

D.U.T.

PULSE

GENERATOR

Fig.7 Load circuitry for switching times.

VCC VICLRLVEXT

tPLH/tPHL tPZH/tPHZ tPZL/tPLZ

1.65 V to 1.95 V VCC 30 pF 1 kΩopen GND 2 ×VCC

2.3 V to 2.7 V VCC 30 pF 500 Ωopen GND 2 ×VCC

2.7 V 2.7 V 50 pF 500 Ωopen GND 6 V

3.0 V to 3.6 V 2.7 V 50 pF 500 Ωopen GND 6 V

4.5 V to 5.5 V VCC 50 pF 500 Ωopen GND 2 ×VCC

Definitions for test circuit:

RL= Load resistor.

CL= Load capacitance including jig and probe capacitance.

RT= Termination resistance should be equal to the output impedance Zo of the pulse generator.

2004 Sep 15 11

Philips Semiconductors Product speciﬁcation

Single 2-input AND gate 74LVC1G08

PACKAGE OUTLINES

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC EIAJ

SOT353

detail X

0 1 2 mm

scale

132

Plastic surface mounted package; 5 leads SOT353

UNIT A1

max bpcD

(2)

HELpQywv

mm 0.1 0.30

0.20 2.2

1.8

0.25

0.10 1.35

1.15 0.65

1.3 2.2

2.0 0.2 0.10.2

DIMENSIONS (mm are the original dimensions)

0.45

0.15 0.25

0.15

1.1

0.8

97-02-28SC-88A

2004 Sep 15 12

Philips Semiconductors Product speciﬁcation

Single 2-input AND gate 74LVC1G08

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT753 SC-74A

detail X

0 1 2 mm

scale

132

Plastic surface mounted package; 5 leads SOT753

UNIT A1bpcDEHELpQywv

mm 0.100

0.013 0.40

0.25 3.1

2.7

0.26

0.10 1.7

1.3

0.95 3.0

2.5 0.2 0.10.2

DIMENSIONS (mm are the original dimensions)

0.6

0.2 0.33

0.23

1.1

0.9

02-04-16

2004 Sep 15 13

Philips Semiconductors Product speciﬁcation

Single 2-input AND gate 74LVC1G08

terminal 1

index area

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT886 MO-252

SOT886

04-07-15

04-07-22

DIMENSIONS (mm are the original dimensions)

XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm

0 1 2 mm

scale

Notes

1. Including plating thickness.

2. Can be visible in some manufacturing processes.

UNIT

mm 0.25

0.17 1.5

1.4 0.35

0.27

max b E

1.05

0.95

Dee

0.40

0.32

0.50.6

A(1)

max

0.5 0.04

6×

(2)

4×

(2)

2004 Sep 15 14

Philips Semiconductors Product speciﬁcation

Single 2-input AND gate 74LVC1G08

DATA SHEET STATUS

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

LEVEL DATA SHEET

STATUS(1) PRODUCT

STATUS(2)(3) DEFINITION

I Objective data Development This data sheet contains data from the objective speciﬁcation for product

development. Philips Semiconductors reserves the right to change the

speciﬁcation in any manner without notice.

II Preliminary data Qualiﬁcation This data sheet contains data from the preliminary speciﬁcation.

Supplementary data will be published at a later date. Philips

Semiconductors reserves the right to change the speciﬁcation without

notice, in order to improve the design and supply the best possible

product.

III Product data Production This data sheet contains data from the product speciﬁcation. Philips

Semiconductors reserves the right to make changes at any time in order

to improve the design, manufacturing and supply. Relevant changes will

be communicated via a Customer Product/Process Change Notiﬁcation

(CPCN).

DEFINITIONS

Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the

same type number and title. For detailed information see

the relevant data sheet or data handbook.

Limiting values definition Limiting values given are in

accordance with the Absolute Maximum Rating System

(IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device.

These are stress ratings only and operation of the device

attheseor atanyother conditionsabovethose giveninthe

Characteristics sections of the specification is not implied.

Exposure to limiting values for extended periods may

affect device reliability.

Application information  Applications that are

described herein for any of these products are for

illustrative purposes only. Philips Semiconductors make

norepresentationorwarrantythatsuchapplicationswillbe

suitable for the specified use without further testing or

modification.

DISCLAIMERS

Life support applications  These products are not

designed for use in life support appliances, devices, or

systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips

Semiconductorscustomersusingorsellingtheseproducts

for use in such applications do so at their own risk and

agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Right to make changes  Philips Semiconductors

reserves the right to make changes in the products -

including circuits, standard cells, and/or software -

described or contained herein in order to improve design

and/or performance. When the product is in full production

(status ‘Production’), relevant changes will be

communicated via a Customer Product/Process Change

Notification (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these

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makes no representations or warranties that these

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right infringement, unless otherwise specified.

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Printed in The Netherlands R20/05/pp15 Date of release: 2004 Sep 15 Document order number: 9397 750 13757