Hybrid System XEMS HS 9403 16-Channel, 12-Bit Acquisition System DESCRIPTION The HS9403-8 and 9403-16 provide complete 12-bit data acquisition functionality in a single, 62-pin package. The 9403 includes 8- or 16-channel multiplexing, a pro- grammable gain instrumentation amplifier, sample-hold circuit, 10V buffered reference, 12-bit 10 u sec A/D and three-state output buffers. The 9403 is flexible enough to accept full scale input ranges from +10 mV to + 10V. Three-state output buf- fers allow output data to be accessed in any combination of three 4-bit bytes. Expansion to 32 single-ended or 16 differential inputs can be achieved with the addition of only 2 ICs. The 9403 is packaged in a 62-pin, hermetically-sealed, ceramic package. Temperature ranges available are 0C to 70C for commercial versions and - 55C to 125C with MIL-STD-883 Rev. C screening for military grades. ax ee aes : ante 1 Bhai HERAT EM o f oF a an i pee tt sare yay rh ary ey NT o 8) ae fH) coreg a BIT @ he wor ay {hee ==) GE: OAT 12 AB eee C28) fered) sos OF BE: eaten EADY 8 AON REF OU? fej naghavone (yah ES as My Se oe aa a ine Sa Se A WES TA: MLD ADS qapoaes 1. Multiplexer, Instrumentation Amp, S/H, A/D and 1. Save Board Real Estate Control Logic in a 62-Pin Package 2. Three State Output Buffer 2. Easy Interface with a Microprocessor Bus 3. Instrumentation Amp with Selectable Gain Ranging 3. Permits Use with Low Level Signal Inputs: 1 to 1000 +10 mV to +10V 4, Single-Ended (- 16) and Differential ( 8) Inputs 4. Flexibility to Handle More Input Channels 5. 50 kHz Minimum Throughput 5. For Use in High Speed Systems AMP GAIN EXTERNAL MUX (INPUT SETTING HOLD S/H BIPOLAR ENABLE +O RESISTOR CAPACITOR OUT INPUT {5) (49) (50) (48) (47) (45) (46) (39) OFFSET ADJUST GAIN ADJUST CHO( + )/CHO chat Ven saws + 3-STATE CH3( + )/CH3 BIT3 eral vor is onannen oe ara : ENABLE CH6( + )/CHE SINGLE CHIT VCH? OR (BITS 1-4) CHO( - )/CH8 8 CHANNEL CH1(-)/CHO DIFFERENTIAL 12-BIT BIT 5 CH2( )/CH10 MUX A/D 3-STATE BIT6 CH3( -)/CH11 CONVERTER BUFFER BIT? CH4( - )/CH12 BIT 8 CH5( - )/CH13 ENABLE CH6( ~ )/CH14 (BITS 5-8) CH7( - )/CH15 BIT 9 3-STATE BIT 10 MUX A SUFFER BIT 11 ADDRESS BIT 12 (LSB) outputs} 44 ENABLE Ag (BITS 9-12) MUX ADORESS TIMING ANDO Foe REGISTER CONTROL LOGIC + 10V REF + 10V REF OUT (19) (16) (15) (14) (13) (20) (8) 6) at) (42) 1) (18) (44) (43) TOAD RA1RA2RA4RAs CLEAR STROBE RDELAY ANG ANG DIG +5VDC -15VDC +15 VDC MUX ADDRESS signe pone GND 275SPECIFICATIONS (Typical @ + 25C and nominal power supplies unless otherwise specified) ANALOG INPUTS HS 9403 Number of Input Channels HS 9403-8 8 Differential HS 9403-16 16 Single-Ended Input Voltage Range! Unipolar Oto +10V Bipolar +10V Common Mode Voltage Range +11V min CMRR G=1 (10 kHz) 74 dB G = 1000 (60 Hz) 110 dB Input Bias Current +50 pA max Bias Current Drift Input Offset Current Offset Current Drift Input Offset Voltage Offset Voltage Drift Voltage Noise (RTI)? G=1 G=1000 Input Resistance Input Capacitance OFF Channel ON Channei 9403-8 9403-16 DIGITAL INPUTS Doubles every 10C +25 pA typ, + 100 pA max Doubles every 10C +2mvV (20 + 7G) pV/C 150 y V (RMS) 1.6 wv (RMS) 10129 10 pF 50 pF 100 pF Logic Levels Logic 1 Logic 0 Logic Loading Logic 1 Logic 0 STATIC PERFORMANCE +2V min, +5.5V max OV min, +0.8V max 40 A -0.8 mA No Missing Codes Integral Linearity Error Differential Linearity Error Unipolar Offset Error Bipolar Zero Errors Gain Error +10V REFERENCE Guaranteed over operating temperature range + V4 LSB typ, + 2 LSB max + V4 LSB typ, + Y2 LSB max +0.025% FSR typ, +0.1% FSR& max +0.025% FSR typ, + 0.1% FSR& max +0.025% typ, + 0.2% max Output Current (55C to + 125C) Output Voltage Output Voltage Drift DYNAMIC PERFORMANCE +15 mA max +10.000V +5 mV (with 5K& load) +3 ppm/C typ, +8 ppm/C max Throughput Rate S/H Acquisition Time? A/D Conversion Time Aperture Delay Sample-Hold Droop Feedthrough (@ 1 kHz) MUX Crosstalk (@ 1 kHz) Strobe Command Pulse Width Setup Time Digital Inputs to Strobe Hold Time Digital inputs from Strobe? DRIFT CHARACTERISTICS" 50 kHz min 9 sec typ, 10 uw sec max 10 psec max 100 nsec max 1 V/psec +0.01% max 80 dB min 40 nsec min 50 nsec min 50 nsec max Integral Linearity Differential Linearity Unipolar Offset Bipolar Zero Gain +1 ppm/C typ, +2 ppm/C max +1 ppm/C typ, +2 ppm/C max +3 ppm/C typ, +7 ppm/C max +3 ppm/C typ, + 10 ppm/C max +8 ppm/C typ, +30 ppm/C max 276 PRELIMINARY TECHNICAL DATA DIGITAL OUTPUTS HS9403 Logic Levels Logic 1" 2.4V min Logic O"' 0.4V max Logic Coding Unipolar Ranges Straight binary Bipolar Ranges Offset binary Fanout 5 TTL Loads POWER SUPPLIES Power Supply Range + 16V +5V +14.5V to + 15.5V +4.5V to +5.5V Current Drains Power Dissipation P.S.R.R. for 3 supplies P.S.R.R. (+ 10V ref) + 15V 37 mA typ, 49 mA max 16V 35 mA typ, 47 mA max + 5V 87 mA typ, 115 mA max 1.5W typ, 2.0W max 0.005%/% max 0.01%/% max TEMPERATURE RANGE Operating C-Option Operating B-Option Storage 0C to + 70C ~ 55C to + 125C - 65C to + 150C ABSOLUTE MAXIMUM RATINGS +Vcoc ~0.5V to + 18V -Voc +0.5V to 18V Yop -0.5to +7V Analog Input Channels +35V Digital Inputs -0.5to +7.0V NOTES: 1. For unity gain. 2. Referred to input. 3. Measured at output of S/H. 4. Specifications refer to entire system from MUX input to A/D output with instrumentation amplitier G= 1. 5. Initial offset and gain errors are adjustable to zero with optional external potentiometers 6. FSR = full scale range. Unipolar FSR = 10V, Bipolar FSR = 20V. For a 12-bit system, x 8. . Includes MUX address, MUX enable, clear and load inputs. 10. o 1 LSB = 0.024% FSR. Includes MUX switching and settling time, instrumentation amp unity gain settling time and S/H acquisition time. Specified for 10V step settling to 0.01% FSR. Measured at S/H output with S/H in hold mode. Unipolar 10V FSR is the basis for parts per million specifications PACKAGE OUTLINE inch (mm) DIMENSIONS 1 (35.6) 0.240 (6.1) 0.200 . : (5.1) 20 SPACES 0.150 AT 0.100 (2.5) EACH (3.810) 0.150% 52 eee ewe e eens ow | (3.810) : : 0.250 : . | (6.350) : - |9 SPACES : + [AT 0.100 : BOTTOM VIEW > EACH soo : + las) 62+ - {ob DOT ON TOP presses ses e es esccc ey 1.250 REFERENCES PIN 1 PIN SPACING IS 0.100 MAXIMUM PIN DIMENSIONS INCHES + 0.005 NON- CUMULATIVE (2.5mm) ARE 0.012 x 0.022 INCHES (0.3 x 0.5mm)PIN ASSIGNMENTS DIGITAL PIN FUNCTIONS FUNCTION PINNO.| STATE | DESCRIPTION PIN FUNCTION FUNCTION NO. HS 9403-16 HS 9403-8 1 CH3 iN CH3(+)IN 2 CH2 IN CH2(+)IN 3 CH1 IN CH1(+)IN 4 CHO IN CHO(+)IN 5 MUX ENABLE 6 R DELAY 7 EOC 8 STROBE 9 A8& 10 A4 4 AQ MUX ADDRESS OUT 12 Ai 13 RA8 14 RA4 15 RAD MUX ADDRESS IN 16 RA1 17 DIGITAL GROUND 18 +5V 19 LOAD ENABLE 20 CLEAR ENABLE 21 ENABLE (BITS 9-12) 22 BIT 12 OUT (LSB) 23 BIT 11 OUT 24 BIT 10 OUT 25 BIT 9 OUT 26 ENABLE (BITS 5-8) 27 BIT 8 OUT 28 BIT 7 OUT 29 BIT 6 OUT 30 BIT 5 OUT 31 ENABLE (BITS 1-4) 32 BIT 4 OUT 33 BIT 3 OUT 34 BIT 2 OUT 35 BIT 1 OUT (MSB) 36 GAIN ADJ 37 OFFSET ADJ 38 BIPOLAR INPUT 39 SAMPLE/HOLD OUT 40 +10V REFERENCE OUT 41 ANALOG SIGNAL GROUND 42 ANALOG POWER GROUND 43 +15V 44 15V 45 EXTERNAL HOLD CAP HIGH 46 EXTERNAL HOLD CAP LOW 47 R GAIN LOW 48 R GAIN HIGH 49 INSTRU. AMP (+) INPUT 50 INSTRU. AMP () INPUT 51 CH15 IN CH7(-)IN 52 CH14 IN CH6(-)IN 53 CH13 IN CHS(-)IN 54 CH12 IN CH4(-)IN 55 CH11 IN CH3(}IN 56 CH10 IN CH2(-)IN 57 CH9 IN CH1()IN 58 CH8 IN CHO(-)IN 59 CH7 IN CH7(+)IN 60 CH6 IN CH6(+)IN 61 CHS IN CH5(+)IN 62 CH4 IN CH4(+)IN MUX ENABLE EOC STROBE OUT LOAD CLEAR ENABLE (BITS 9-12) ENABLE (BITS 5-8) ENABLE (BITS 1-4) 5 7 MUX ADDRESS 9-12 MUX ADDRESS| 13-16 IN 19 20 al 26 31 LOGIC Q" Disables internal MUX qe Enables internal MUX QO Signal acquisition cycle in progress oq" A/D conversion in progress 1" ta 0 | Conversion complete 1 to "0" | Initiates acquisition and conversion of analog signal Output of MUX address register. Straight binary coding Selects MUX for random address mode. Straight binary coding Q Random address mode initiated on falling edge of STROBE yn Sequential address mode oO Forces MUX address to CHO _on next falling edge of STROBE regardless of LOAD and MUX address inputs Q Enables three-state outputs bits 9-12 4 Disables three-state out- puts bits 9-12 Q Enables three-state outputs bits 5-8 mq? Disables three-state out- puts bits 5-8 Q Enables three-state outputs outputs bits 1-4 wy" Disables three-state out- puts bits 1-4 ANALOG PIN FUNCTIONS S/H OUTPUT +10V REF OUT EXTERNAL HOLD CAPACITOR R GAIN INSTRUMENTATION AMP INPUTS FUNCTION PIN NO. | DESCRIPTION R DELAY 6 Connect external resistor to lengthen S/H acquisition time when instrumentation AMP is set for high gain (for normal operation, R DELAY tied to + 5V). GAIN ADJUST 36 External gain adjust (optional) OFFSET ADJUST 37 External offset adjust (optional) BIPOLAR INPUT 38 For unipolar operation (0 to + 10V), connect to pin 39 (S/H OUT). For Bipolar operation (+ 10V), connect to pin 40 (+ 10V REF OUT) 39 Sample-Hold output 40 Buffered + 10V reference output 45, 46 Add external polypropylene, polystyrene or teflon hold capacitor to improve S/H droop rate (optional) 47, 48 Optional gain selection point. a: 20k/(G 1). Leave open for =] 49, 50 Use when adding additional external multiplexers for ex- panded single-ended or differ- ential operation (see Appli- cations information). Connect pin 50 to analog common for HS 9403-16 277APPLICATIONS INFORMATION NOTES: 1. Input channels are protected to 20V beyond power supplies. 2. To improve sample-hold droop rate, an external hold capacitor may be connected between external hold cap pins 45 and 46. Polypropylene or teflon capaci- tors are recommended for best results. Acquisition time must be increased accordingly. 3. RGAIN (Q) = 20:000_ (GAIN 1) 4. To increase acquisition time allotment, connect a resistor from R DELAY (pin 6) to +5V (pin 18). R DELAY (q) = AMP settling ime _ 9 (see Table 1) (40.1% typical) RANDOM ADDRESS Set LOAD (pin 19) to LOGIC '0. The next falling edge of STROBE will load the MUX channel address present on pin 13 to pin 16. Address inputs must be stable 50 nsec before and after falling edge of STROBE pulse. TRIGGERED SEQUENTIAL ADDRESS Set LOAD (pin 19) and CLEAR (pin 20) to LOGIC '1. Applying a falling edge trigger pulse to STROBE (pin 8). This negative transition causes the contents of the address counter to increment by one followed by an A/D conversion. Changing digital data appearing at the address inputs will not affect the HS 9403 when it is in the sequential address mode. FREE-RUNNING SEQUENTIAL ADDRESS 109 Set LOAD (pin 19) and CLEAR (pin 20) to LOGIC *1. Connect EOC (pin 7) and STROBE (pin 8) together. AMP The falling edge of EOC will increment channel INPUT RGAIN | SETTLING SYSTEM address. When the EOC goes low, the digital output RANGE | GAIN} (R) TIME | R DELAY! THROUGHPUT | ACCURACY data is valid for the previous channel for approximately ov + | None ousec | None 55.5 kHe 0.009% 10p sec while the multiplexer is switching channels and the S/H is acquiring the new signal. +5V 2 } 20.0k 9 sec None 55.5 KHz 0,009% VALID OUTPUT +2.6V 4) 6.667 | QHsec | None 59.5 kHz 0.009% During the conversion (EOC high), the output of the tv 10 | 2020k | oysec | None 56.5 kHz 0.009% A/D is changing during the successive approximation sequence. If the outputs are connected to a Data Bus, +200mv] 50| 408.2 | 16 usec 7K 40.0 kHz 0.010% the enable inputs (pins 21, 26 and 31) must be held high to prevent invalid data from reaching the bus. If 400 mV 100 | 202.0 | 30 usec | 2IK 26.6 kHz 0.019% data is to be read immediately after conversion is com- + 50mvV| 200 | 100.5 60 psec 51K 44.5 kHz 0.016% pleted, connect EOC t EOC to ENABLE (bits 1-4), ENABLE (bits 5-8) and ENABLE (bits 9-12), pins 21, 26 and 31. + 20mv| 500] 40.08 | 144 usec | 135K 6.5 kHz 0.035% This will tri-state the outputs during conversion and enable them during the acquisition period. + 10mV] 1000 f 20.02 288 sec 279K 3.3 kHz 0.069% Table 1. Input Range Parameters ADDRESS INPUTS MUX CHANNEL A8 | A4 | A2 | A1| ENABLE | SELECTED X X X X 0 None ofolojo 1 QO MUX CHANNEL ADDRESSING ololo |. 1 1 The HS 9403-8 and HS 9403-16 are capable of having o7,oO {1 |] 0 1 2 their input multiplexer channels either randomly or 5 ; , ; : sequentially addressed. ofa tol 1 5 of] 1 1 | 0 1 6 o 11 1 1 1 7 HS 9403-8 ADDRESS MUX ADDRESS | ADDRESS j 0 0 0 1 8 MODE ENABLE | LOAD ] CLEAR INPUTS OUTPUTS | STROBE 1]/o0}f0 | 14 1 ) Random 1 0 1 Next channel | On channel | ''1" to 0" 1 0 1 0 1 10 1/o0]41 1 1 11 Sequential 1 1 1 Don't care }| On channel | 1 to O 4 1 0 0 1 12 1 1})o]14 1 13 Free-Running 1 1 1 Don't care | Onchannel } 1" to '0' 1 1 1 0 1 14 Sequential 4 1 1 4 1 15 HS 9403-16 Table 2. Table 3. MUX Channel Addressing 278TIMING DIAGRAM STROBE > }x40 nsec MIN iY J | NN Pe) } >| j}--40 nsec MIN EXTERNAL STROBE PULSE Eoc : 9usec TYP 9 psec TYP CHG cri DATA VALID y DATA VALID | ACQUISITION | CONVERSION | ACQUISITION | CONVERSION | ACQUISITION | CONVERSION | CHO CHO CH1 CH1 CH12 CH12 t LOAD ' = rs] i { t CLEAR " 2 t1, t2 2 50 nsec i ~*. XN 4 | oo > 50 nsec RAB \ | RA4 t \_ ! RA2 ( l t ' 1 RAI ( | ' cHi2 4 \ A8 _ SELECTED _! [4-40 nsec TYP i A4 1 | D A2 r | I Al nsec TYP | t 1 | CHO ADDRESSED \ ADDRESS MODE | CLEAR >|<__ SEQUENTIAL (EOC TIED TO STROBE) RANDOM OFFSET AND GAIN ADJUST CONNECTIONS The HS 9403 offset and gain adjustments may be made by connecting two 20K trim potentiometers as shown below: +15 VDC GAIN ADJUST (36) > 20K HS 9403 OFFSET ADJUST (37) = mS 20k a - 15 VDC Figure 1. Offset and Gain Adjust Connections Offset Adjustment Connect the OFFSET poten- tiometer as shown above and apply an analog input voltage equivalent to + Y2 LSB if operating in a uni- polar mode or FS + LSB if operating in a bipolar mode. While performing repeated conversions, adjust the offset potentiometer down until all output bits are 0. Then adjust up until the LSB just turns to a 1. Gain Adjust Connect the gain potentiometer as shown and apply an analog input voltage equivalent to +FS 12 LSB. While performing repeated conver- sions, adjust the gain potentiometer up until all the out- put bits are 1. Then adjust down until the LSB just turns to 0. NOTE: Since the offset adjustment effects the gain of the system, offset voltage must be adjusted first. CH1 ADDRESSED | CH12 ADDRESSED CODE MAY CHANGE DON'T CARE + Xv | CH2 ADDRESSED DIGITAL OUTPUT CODING UNIPOLAR STRAIGHT BINARY Q0to +10V Oto +5V +FS -1L5B + 9.9976 +4,9988 4111 1111 1111 +2FS + 5.0000 + 2.5000 1000 0000 0000 +1LSB + 0:0024 +0.0012 o000)=6a00d0)=s-:E0.:001 ZERO 0.0000 0.0000 0000.) =600c00)=s:O000 BIPOLAR OFFSET BINARY +10V +5V +FS 1L58 + 9.9951 +4.9976 1411 1141 4444 +2FS + 5.0000 + 2.5000 4100 000d 0000 +1LSB + 0.0049 + 0.0024 1000 0000 0001 ZERO 0.0000 0.0000 1000 0000 0000 -FS +1LSB ~ 9.9951 4.9976 0000 =690000 =60001 -FS ~ 10.000 - 5.0000 0000 =9000 =0000 GROUNDING CONSIDERATIONS The HS 9403 brings out separate pins for analog power ground, analog signal grounds, and digital ground. All three should be connected together as close to the unit as possible and connected to system analog ground. If the ground pins cannot be con- nected directly at the package, wide low resistive ground lines should be used and a non-polarized capacitor (0.1 to 1 F) should be connected between analog and digital ground directly at the package. Internal 0.01 wF ceramic decoupling capacitors are used in the device. However, it is advisable to add a 1 F or 10 wF tantalum capacitor to each power sup- ply pin from the central ground point to minimize power supply noise problems. 279APPLICATIONS INFORMATION (continued) INPUT EXPANSION Ho . . CHO O+ MSB The HS 9403 can be easily expanded to 32 single- Ws 9403-16 ended channels or 16 differential channels. When ex- \ . tending channel capacity, the multiplexer settling time CHIBSO 1 no Ags AgAg Az Ay O LSB must be extended through the use of R DELAY (pin 6). A J a] | =e Tt o/218 3 = ANALOG A20- eilz2 SIG COM Aso "Jala & CHO(+) O- MSB Ag = = x 2 | HS 9403-16 = t ( CH15{+) O4 At Ag Ag Ag Ag Ag Az A1 LSB A160 D a A20-_ |= ERED ADDRESS aao___| lb] $ STROBEO+Ick FLIP FLOP Ago____! | STROBE O___ INSTRU. AMP (-) CHo(-)o] 40% OUT INPUT cuts ENABLE | pe + 5V ! OA16 Ag 2 AB Ag A 1 \ lie cH 8 O AB Aa rom MUX ess MUX A4 OAs RDORESS CH15(- ! a2 2 OUTPUTS i A2 Ag OUTPUTS (-}O_4 AY OM CH310+J Ay OM Figure 2. 16-Channel Differential Input Expansion Figure 3. 32-Channel Single-Ended Input Expansion ORDERING INFORMATION CAUTION: ESD (Electro-Static Discharge) sensitive device. Permanent damage may occur when uncon- MODEL TEMPERATURE Pet ee eee ae subjected to high energy clecirostalic foam or shunts. Protective foam should be discharged to HS 9403C-8 | 0C to + 70C 8 differential input, 12-bit, data the destination socket before devices are removed. acquisition system (DAS) HS 9403C-16 ] OC to + 70C 16 single-ended input, 12-bit, DAS HS 9403B-8 | 55C to +125C | 8 differential input, 12-bit, DAS. MIL-STD-883 Rev. C, Level B HS 9403B-16 | -55C to +125C | 16 single-ended input, 12-bit, DAS. MIL-STD-883 Rev. C, Level B 280 Devices should be handled at static safe workstations only. Unused digital inputs must be grounded or tied to the logic supply voltage. Unless otherwise noted, the voltage at any digital input should never exceed the sup- ply voltage by more than 0.5 volts or go below volts. If this condition cannot be maintained, limit input current on digital inputs by using series resistors or contact Hybrid Systems for technical assistance.