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FEATURES
DDesigned for Analog and Digital Wireless
Handsets, Voice-Enabled Terminals, and
Telecommunications Applications
D2.7-V to 3.3-V Operation
DSelectable 13-Bit Linear or 8-Bit µ-Law
Companded Conversion
DDifferential Microphone Input With External
Gain Setting
DDifferential Earphone Output Capable of
Driving a 32-Ω to 8-Ω Load
DProgrammable Volume Control in Linear Mode
DMicrophone (MIC) and Earphone (EAR) Mute
Functions
DTypical Power Dissipation of 0.03 mW in
Power-Down Mode
D2.048-MHz Master Clock Rate
D300-Hz to 3.4-kHz Passband
DLow Profile 20-Terminal TSSOP Packaging
APPLICATIONS
DDigital Handset
DDigital Headset
DCordless Phones
DDigital PABX
DDigital Voice Recording
DESCRIPTION
The TLV320AIC1106 PCM codec is designed to
perform transmit encoding analog-to-digital (A/D)
conversion, receive decoding digital-to-analog (D/A)
conversion, and transmit and receive filtering for
voice-band communications systems. The
TLV320AIC1106 device operates in either the 13-bit
linear or 8-bit companded (µ-law) mode. The PCM
codec generates its own internal clocks from a
2.048-MHz master clock input.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
MICMUTE
RESET
VSS
EARVSS
EAROUT+
EARVDD
EAROUT−
EARVSS
MICGAIN+
MICIN−
EARMUTE
MCLK
PCMSYNC
PCMO
PCMI
DVSS
DVDD
LINSEL
MICGAIN−
MICIN+
PW PACKAGE
(TOP VIEW)
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for
Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
       !"# $%
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Copyright 2001, Texas Instruments Incorporated
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functional block diagram
Analog
Modulator
TX
Filter PCM
Interface
RX
Filter
Digital
Modulator
and Filter
RX
Volume
Control
PLL
Power
and
Reset
PCMO
PCMI
PCMSYNC
(5) EAROUT+
RESET
EARMUTE (20)
+
−
MICGAIN −
(10)
MICIN +
MICGAIN +
(12)
MICIN −
(11)
(9)
(17)
MCLK
LINSEL
EARVDD
EARVSS
VSS
DVSS
DVDD
EAROUT−
(7)
(19)
(18)
(16)
(2)
(13)
(6)
(8)
(3)
(15)
(14)
(4)
MIC Amp 1
MICMUTE (1)
MIC
Amp 2 EAR
AMP
RX = Receive
TX = Transmit
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detailed description
power up/reset
An external reset must be applied to the active-low RESET terminal while MCLK is active to ensure reset at
power up.
reference
A precision band-gap reference voltage is generated internally and supplies all required references to operate
the transmit and receive channels.
phase-locked loop
The phase-locked loop generates the internal clock frequency required for internal digital filters and modulators
by phase-locking to 2.048-MHz master clock input.
PCM interface
The PCM interface transmits and receives data at the PCMO and PCMI terminals, respectively. The data is
transmitted or received at the MCLK speed once on each PCMSYN cycle. The PCMSYN can be driven by an
external source that is derived from the master clock and used as an interrupt to the host controller.
microphone input
The microphone input circuit consists of two differential input/differential output amplifiers (MIC Amp 1 and
MIC Amp 2). MIC Amp 1 is a low-noise differential amplifier capable of an externally set gain. MIC Amp 2 is a
differential amplifier with a fixed gain of 6 dB.
analog modulator
The transmit channel modulator is a third-order sigma-delta design.
transmit filter
The transmit filter is a digital filter designed to meet Consultive Committee on International Telegraphy and
Telephony (CCITT) G.714 requirements. The TLV320AIC1106 device operates in either the 13-bit linear or 8-bit
companded µ-law mode.
receive filter
The receive (RX) filter is a digital filter that meets CCITT G.714 requirements. The TLV320AIC1106 device
operates in either the 13-bit linear or 8-bit µ-law companded mode, which is selected at the LINSEL input.
receive volume control
In linear mode, the three least significant bits of the 16-bit PCMI data sample is used to control volume. The
volume range is −18 dB to 3 dB in 3-dB steps.
digital modulator and filter
The second-order digital modulator and filter convert the received digital PCM data to the analog output required
by the earphone interface.
earphone amplifiers
EAROUT is recommended for use as a differential output; however, it can be connected in single-ended
topology as well. Clicks and pops are suppressed from the differential output.
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Terminal Functions
TERMINAL
I/O
DESCRIPTION
TERMINAL NO.
I/O
DESCRIPTION
EARVSS 4 I Analog ground for EAROUT+
DVDD 14 I Digital positive power supply
DVSS 15 I Digital negative power supply
EARMUTE 20 I Earphone mute
EAROUT− 7 O Earphone amplifier negative output
EAROUT+ 5 O Earphone amplifier positive output
EARVDD 6 I Analog positive power supply for the earphone amplifiers
EARVSS 8 I Analog ground for EAROUT−
LINSEL 13 I Companding enable
MCLK 19 I Master system clock input (2.048 MHz) (digital)
MICGAIN+ 9 I Microphone gain positive feedback
MICGAIN− 12 I Microphone gain negative feedback
MICMUTE 1 I Microphone mute
MICIN− 10 I Microphone negative input (−)
MICIN+ 11 IMicrophone positive input (+)
PCMI 16 I Receive PCM input
PCMO 17 O Transmit PCM output
PCMSYNC 18 I PCM frame synchronization
RESET 2 I Active-low reset
VSS 3 I Ground return for band-gap internal reference
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, DVDD, EARVDD −0.5 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO−0.5 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI−0.5 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free air temperature range, TA−40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE TA ≤25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 85°C
POWER RATING
PW 680 W 6.8 W/°C270 W
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recommended operating conditions (see Note 2)
MIN NOM MAX UNIT
Supply voltage, DVDD, EARVDD 2.7 3.3 V
High-level input voltage, VIH 0.7xVDD V
Low-level input voltage, VIL 0.3xVDD V
Load impedance between EAROUT+ and EAROUT−, RL8 to 32 Ω
Input voltage, MICIN 0.9xVDD V
Operating free-air temperature, TA−40 85 _C
NOTES: 1. To avoid possible damage and resulting reliability problems to these CMOS devices, follow the power-on initialization paragraph,
described in the Principles of Operations.
2. Voltages are with respect to DVSS, and EARVSS.
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
supply current
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IDD
Supply current from VDD
Operating 5 7 mA
IDD Supply current from VDD Power down, MCLK not present 10 30 µA
tpu Power-up time from power down 10 ms
digital interface
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage, PCMO IOH = −3.2 mA, VDD = 3 V DVDD−0.25 V
VOL Low-level output voltage, PCMO IOL = 3.2 mA, VDD = 3 V 0.2 V
IIH High-level input current, any digital input VI = 2.2 V to VDD 10 µA
IIL Low-level input current, any digital input VI = 0 to 0.8 V 10 µA
CIInput capacitance 10 pF
CoOutput capacitance 20 pF
microphone interface
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIO Input offset voltage See Note 3 −5 5 mV
IIB Input bias current −250 250 nA
CiInput capacitance 5 pF
VnMicrophone input referred noise, psophometric weighted MIC Amp 1 gain = 23.5 dB,
See Note 4 2.9 4 µVrms
MICMUTE −80 dB
NOTES: 3. Measured while MICIN+ and MICIN− are connected together. Less than a 0.5-mV offset results in 0 value code on PCMOUT.
4. Configured as shown in Figure 3.
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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (continued)
speaker interface
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD = 2.7 V, fully differential, 8-Ω load,
3-dBm0 output, volume control = −3 dB,
PCMI data input to −4 dB level 161 200
Earphone AMP output power (see Note 5) VDD = 2.7 V, fully differential, 16-Ω load,
3-dBm0 output, volume control = −3 dB,
PCMI data input to −2 dB level 128 160 mW
VDD = 2.7 V, fully differential, 32-Ω load,
3-dBm0 output, volume control = −3 dB,
PCMI data input to −1 dB level 81 100
3-dBm0 input, 8-Ω load 141 178
I
O
max Maximum output current for EAROUT (rms) 3-dBm0 input, 16-Ω load 90 112 mA
IOmax
Maximum output current for EAROUT (rms)
3-dBm0 input, 32-Ω load 50 63
mA
EARMUTE −80 dB
NOTE 5: Maximum power is with a load impedance of −20%, at 25°C.
transmit gain and dynamic range, companded mode (µ-law) or linear mode selected (see Notes 6 and 7)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Transmit reference-signal level (0dB) Differential, MIC Amp 1 configured for 23.5 dB gain 88 mVpp
Overload-signal level (3 dBm0) Differential, MIC Amp 1 configured for 23.5 dB gain 124 mVpp
Absolute gain error 0 dBm0 input signal, 2.7 V ≤ VDD ≤ 3.3 V −1 1 dB
Gain error with input level relative to gain at
MICIN−, MICIN+ to PCMO at 3 dBm0 to −30 dBm0 −0.5 0.5
Gain error with input level relative to gain at
−10 dBm0 MICIN, MICIN+ to PCMO
MICIN−, MICIN+ to PCMO at −31 dBm0 to −45 dBm0 −1 1 dB
−10 dBm0 MICIN, MICIN+ to PCMO
MICIN−, MICIN+ to PCMO at −46 dBm0 to −55 dBm0 −1.2 1.2
dB
NOTES: 6. Unless otherwise noted, the analog input is 0 dB, 1020-Hz sine wave, where 0 dB is defined as the zero-reference point of the channel
under test.
7. The reference signal level, which is input to the transmit channel, is defined as a value 3 dB below the full-scale value of 124-mVpp.
transmit filter transfer, companded mode (µ-law) or linear mode selected
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fMIC < 100 Hz −0.5 0.5
fMIC = 200 Hz −0.5 0.5
fMIC = 300 Hz to 3 kHz −0.5 0.5
Gain relative to input signal gain at 1.02 kHz fMIC = 3.4 kHz −1.5 0 dB
Gain relative to input signal gain at 1.02 kHz
fMIC = 4 kHz −14
dB
fMIC = 4.6 kHz −35
fMIC = 8 kHz −47
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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (continued)
transmit idle channel noise and distortion, companded mode (µ-law) selected
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Transmit idle channel noise, psophometrically weighted MIC Amp 1 configured for 23.5-dB gain
(see Note 8) −80 −70 dBm0p
MICIN−, MICIN+ to PCMO at 3 dBm0 27
MICIN−, MICIN+ to PCMO at 0 dBm0 30
MICIN−, MICIN+ to PCMO at −5 dBm0 33
MICIN−, MICIN+ to PCMO at −10 dBm0 36
dBm0
input MICIN−, MICIN+ to PCMO at −20 dBm0 35 dBm0
MICIN−, MICIN+ to PCMO at −30 dBm0 26
MICIN−, MICIN+ to PCMO at −40 dBm0 24
MICIN−, MICIN+ to PCMO at −45 dBm0 19
CCITT G.712 (7.1), R2 49
dB
power level, −13 dBm0 CCITT G.712 (7.2), R2 51 dB
NOTE 8: With recommended impedances and resistor tolerance of 1%
transmit idle channel noise and distortion, linear mode selected
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Transmit idle channel noise, psophometrically weighted MIC Amp 1 configured for 23.5-dB gain
(see Note 8) −80 −74 dBm0p
MICIN−, MICIN+ to PCMO at 3 dBm0 40 55
MICIN−, MICIN+ to PCMO at 0 dBm0 50 61
MICIN−, MICIN+ to PCMO at −5 dBm0 52 62
MICIN−, MICIN+ to PCMO at −10 dBm0 56 66
dB
sine-wave input MICIN−, MICIN+ to PCMO at −20 dBm0 52 68 dB
MICIN−, MICIN+ to PCMO at −30 dBm0 51 61
MICIN−, MICIN+ to PCMO at −40 dBm0 43 59
MICIN−, MICIN+ to PCMO at −45 dBm0 38 55
NOTE 8: With recommended impedances and resistor tolerance of 1%
receive gain and dynamic range, linear or companded (µ-law) mode selected (see Note 9)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Load = 8 Ω, volume control = −3 dB, PCMI data input to −4 dB level 3.2
Overload-signal level (3 dB) Load = 16 Ω, volume control = −3 dB, PCMI data input to −2 dB level 4.05 V
pp
Overload-signal level (3 dB)
Load = 32 Ω, volume control = −3 dB, PCMI data input to −1 dB level 4.54
Vpp
Absolute gain error 0 dBm0 input signal, 2.7 V ≤ VDD ≤ 3.3 V −1 1 dB
Gain error with output level
PCMI to EAROUT−, EAROUT+ at 3 dBm0 to −40 dBm0 −0.5 0.5
Gain error with output level
relative to gain at −10 dBm0
PCMI to EAROUT−, EAROUT+ at −41 dBm0 to −50 dBm0 −1 1 dB
relative to gain at −10 dBm0
PCMI to EAROUT−, EAROUT+ at −51 dBm0 to −55 dBm0 −1.2 1.2
dB
NOTE 9: 1020-Hz input signal at PCMI, output measured differentially between EAROUT− and EAROUT+
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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (continued)
receive filter transfer, companded mode (µ-law) or linear mode selected (MCLK = 2.048 MHz) (see Note 10)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fEAROUT < 100 Hz −15
fEAROUT = 200 Hz −5
fEAROUT = 300 Hz to 3 kHz −0.5 0.5
Gain relative to input signal gain at 1.02-kHz fEAROUT = 3.4 kHz −1.5 0 dB
Gain relative to input signal gain at 1.02-kHz
fEAROUT = 4 kHz −14
dB
fEAROUT = 4.6 kHz −35
fEAROUT = 8 kHz −47
NOTE 10: Volume control = −3 dB, PCMI data input to −1 dB level (32-Ω load)
receive idle channel noise and distortion, companded mode (µ-law) selected (see Note 10)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Receive noise, C-message weighted PCMI = 11111111 (µ-law) −90 −88 dBm0
PCMI to EAROUT−, EAROUT+ at 3 dBm0 21
PCMI to EAROUT−, EAROUT+ at 0 dBm0 25
PCMI to EAROUT−, EAROUT+ at −5 dBm0 36
Receive signal-to-distortion ratio with 1.02-kHz
PCMI to EAROUT−, EAROUT+ at −10 dBm0 43
dB
Receive signal-to-distortion ratio with 1.02-kHz
sine-wave input PCMI to EAROUT−, EAROUT+ at −20 dBm0 40 dB
sine-wave input
PCMI to EAROUT−, EAROUT+ at −30 dBm0 38
PCMI to EAROUT−, EAROUT+ at −40 dBm0 28
PCMI to EAROUT−, EAROUT+ at −45 dBm0 23
NOTE 10: Volume control = −3 dB, PCMI data input to −1 dB level (32-Ω load)
receive idle channel noise and distortion, linear mode selected (see Note 10)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Receive noise, (20-Hz to 20-kHz brickwall window) PCMI = 0000000000000 −83 −78 dBm0
PCMI to EAROUT−, EAROUT+ at 3 dBm0 48 52
PCMI to EAROUT−, EAROUT+ at 0 dBm0 51 56
PCMI to EAROUT−, EAROUT+ at −5 dBm0 57 59
Receive signal-to-distortion ratio with 1.02-kHz
PCMI to EAROUT−, EAROUT+ at −10 dBm0 55 62
dB
Receive signal-to-distortion ratio with 1.02-kHz
sine-wave input (0−4 kHz) PCMI to EAROUT−, EAROUT+ at −20 dBm0 51 53 dB
sine-wave input (0−4 kHz)
PCMI to EAROUT−, EAROUT+ at −30 dBm0 45 47
PCMI to EAROUT−, EAROUT+ at −40 dBm0 42 47
PCMI to EAROUT−, EAROUT+ at −45 dBm0 35 45
Intermodulation distortion, 2-tone CCITT method,
CCITT G.712 (7.1), R2 50
dB
Intermodulation distortion, 2-tone CCITT method,
composite power level, −13 dBm0 CCITT G.712 (7.2), R2 54 dB
NOTE 10: Volume control = −3 dB, PCMI data input to −1 dB level (32-Ω load)
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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (continued)
power supply rejection
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Supply voltage rejection, transmit channel MICIN−, MICIN+ = 0 V, VDD = 2.7 V + 100 mVpp,
f = 1 kHz, Resistor tolerance of 1% −74 −50 dB
Supply voltage rejection, receive channel
(differential) PCM code = positive zero, VDD = 2.7 V + 100 mVpp,
f = 1 kHz, Resistor tolerance of 1% −80 −65 dB
crosstalk attenuation, linear mode selected
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Crosstalk attenuation, transmit-to-receive
(differential) MICIN−, MICIN+ = 0 dB, f = 300 Hz to 3400 Hz measured
differentially between EAROUT− and EAROUT+ 70 dB
Crosstalk attenuation, receive-to-transmit PCMI = 0 dBm0, f = 300 Hz to 3400 Hz measured at PCMO 70 dB
timing requirements
clock
MIN NOM MAX UNIT
ttTransition time, MCLK 10 ns
fmclk MCLK frequency 2.048 MHz
MCLK jitter 37%
MCLK clock cycles per PCMSYN frame 256 256 cycles
transmit (see Figure 1)
MIN MAX UNIT
tsu(PCMSYN) Setup time, PCMSYN high before MCLK ↓20 tc(MCLK)−20 ns
th(PCMSYN) Hold time, PCMSYN high after MCLK ↓20 tc(MCLK)−20
receive (see Figure 2)
MIN MAX UNIT
tsu(PCSYN) Setup time, PCMSYN high before MCLK ↓20 tc(MCLK)−20 ns
th(PCSYN) Hold time, PCMSYN high after MCLK ↓20 tc(MCLK)−20 ns
tsu(PCMI) Setup time, PCMI high or low before MCLK ↓20 ns
th(PCMI) Hold time, PCMI high or low after MCLK ↓20 ns
switching characteristics over recommended operating conditions, CLmax = 10 pF (see Figure 1)
MIN MAX UNIT
tpd1 Propagation delay time, MCLK bit 1 high to PCMO bit 1 valid 35 ns
tpd2 Propagation delay time, MCLK high to PCMO valid, bits 2 to n 35 ns
tpd3 Propagation delay time, MCLK bit n low to PCMO bit n Hi-Z 30 ns
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PARAMETER MEASUREMENT INFORMATION
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
0 1 2 3 4 N−2 N−1 N N+1
Transmit Time Slot
1 2 3 4 N−2 N−1 N
80%
20%
tsu(PCMSYN) th(PCMSYN)
See Note A
See Note C
See Note B
tpd2
tpd1 See Note D tsu(PCMO)
tpd3
80%
20%
MCLK
PCMSYN
PCMO
NOTES: A. This window is allowed for PCMSYN high.
B. This window is allowed for PCMSYN low (th(PCMSYN) max determined by data collision considerations).
C. Transitions are measured at 50%.
D. Bit 1 = Most significant bit (MSB), Bit N = Least significant bit (LSB)
Figure 1. Transmit Timing Diagram
80%
20%
See Note C
PCMI
PCMSYN
MCLK
0 1 2 3 4 N −2 N −1 N N +1
20% 80%
ÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
1 2 3 4 N −2 N −1 N
See Note D
th(PCMSYN)
tsu(PCMSYN)
See Note A
tsu(PCMI)
th(PCMI)
See Note B
Receive Time Slot
NOTES: A. This window is allowed for PCMSYN high.
B. This window is allowed for PCMSYN low.
C. Transitions are measured at 50%.
D. Bit 1 = Most significant bit (MSB), Bit N = Least significant bit (LSB)
Figure 2. Receive Timing Diagram
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PRINCIPLES OF OPERATION
power-up initialization
An external reset with a minimum pulse width of 500 ns must be applied to the active-low RESET terminal with
MCLK active to ensure reset upon power up.
Table 1. Power-Up and Power-Down Power Consumption
(VDD = 2.7 V, Earphone Amplifier Loaded)
DEVICE STATUS MAXIMUM POWER CONSUMPTION
Power up 16.2 mW
Power down 81 µW
The loss of MCLK (no transition detected) automatically enters the device into a power-down state with PCMO
in the high-impedance state. If an asynchronous power down occurs during a pulse code modulation (PCM)
data transmit cycle, the PCM interface remains powered up until the PCM data is completely transferred.
conversion laws
The device can be programmed either for a 13-bit linear or 8-bit (µ-law) companding mode. The companding
operation approximates the CCITT G.711 recommendation. The linear mode operation uses a 13-bit twos
complement format. Linear mode is selected with LINSEL low. LINSEL is high for companding.
transmit operation
microphone input
The microphone input stage is a low-noise differential amplifier. The microphone must be capacitively coupled
to the MICIN− and MICIN+ terminals. Preamplifier (MIC Amp 1) gain is determined by selection of external
resistors R2 and R3. To achieve the recommended gain setting of 23.5 dB for MIC Amp 1, resistor values of
R2 = 34 kΩ and R3 = 510 kΩ are suggested. A 1% tolerance is recommended for all resistors to meet the
specification. The recommended range for R2 is 34−100 kΩ. For values above 100 kΩ, the noise performance
of the channel is degraded.
_
+
R3
R3
R2
R2
C1
C1
+V
R1
R1
MICGAIN−
MICGAIN+
MICIN+
MICIN−
MIC Amp 1
R1 = 2 kΩ
C1 = 0.22 µF
MIC Amp 1 Gain in dB +20 log ǒR3
R2Ǔ
Figure 3. Typical Microphone Interface

SLAS357 − DECEMBER 2001
12 www.ti.com
PRINCIPLES OF OPERATION
microphone mute function
Transmit channel muting can be selected by setting MICMUTE high. Muting provides 80-dB attenuation of the
input microphone signal.
receive operation
earphone amplifier
The analog signal is routed to the earphone amplifier differential output (EAROUT− or EAROUT+), which is
capable of driving a load as low as 8 Ω. EAROUT is recommended for use as a differential output.
earphone mute function
Receive channel muting can be selected by setting the EARMUTE terminal to high.
receive PCM data format
DCompanded mode: 8 bits are received, the MSB first
DLinear mode: 13 bits are received, the MSB first
Table 2. Receive Data Bit Definitions
BIT NO. COMPANDED
MODE LINEAR
MODE
1 CD7 LD12
2 CD6 LD11
3 CD5 LD10
4 CD4 LD9
5 CD3 LD8
6 CD2 LD7
7 CD1 LD6
8 CD0 LD5
9 − LD4
10 − LD3
11 − LD2
12 − LD1
13 − LD0
14 − RXVOL2
15 − RXVOL1
16 − RXVOL0

SLAS357 − DECEMBER 2001
13
www.ti.com
PRINCIPLES OF OPERATION
receive volume control
In linear mode, RXVOL [2:0] PCM data bits are used for volume control according to Table 3. Volume control
bits must be sent on PCMI for each 13-bit receive word. In companded mode, volume control is fixed at 0 dB.
Table 3. Volume Control Bit Definition in Linear Mode
RXVOL [2:0] GAIN SETTING
000 3 dB
001 0 dB
010 −3 dB
011 −6 dB
100 −9 dB
101 −12 dB
110 −15 dB
111 −18 dB
support section
The clock generator and control circuit uses the master clock input (MCLK) to generate internal clocks to drive
internal counters, filters, and converters.
clock frequencies and sample rates
A fixed PCMSYN rate of 8 kHz determines the sampling rate. The PCMSYN signal must be derived from the
master clock. The divide ratio must be set to 256 for the device to work properly.

SLAS357 − DECEMBER 2001
14 www.ti.com
TYPICAL CHARACTERISTICS
Figure 4
−40
−60
−100
−120 012345 6
Relative Gain − dB
−20
0
f − Frequency − kHz
RELATIVE GAIN
vs
FREQUENCY
20
−80
See Note A
Figure 5
−20
−30
−50
−60 0123456
Relative Gain − dB
−10
0
f − Frequency − kHz
RELATIVE GAIN
vs
FREQUENCY
10
−40
See Note B
NOTES: A. Transmit channel frequency response shown relative to the gain at a 1.02-kHz input signal in linear mode.
B. Receive channel frequency response shown relative to the gain at a 1.02-kHz input signal in linear mode.
Figure 6
−40
−60
−100
−120 012345 6
Relative Gain − dB
−20
0
f − Frequency − kHz
RELATIVE GAIN
vs
FREQUENCY
20
−80
See Note A
Figure 7
−20
−30
−50
−60 012345 6
Relative Gain − dB
−10
0
f − Frequency − kHz
RELATIVE GAIN
vs
FREQUENCY
10
−40
See Note B
NOTES: A. Transmit channel frequency response shown relative to the gain at a 1.02-kHz input signal in µ-Law mode.
B. Receive channel frequency response shown relative to the gain at a 1.02-kHz input signal in µ-Law mode.

SLAS357 − DECEMBER 2001
15
www.ti.com
TYPICAL CHARACTERISTICS
Figure 8
02.5 3 3.5
Supply Current − mA
4
Supply Voltage − V
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
10
6
8
2
See Note A
Figure 9
02.5 3 3.5
8
12
Supply Voltage − V
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
20
Supply Current − Aµ
See Note B
16
4
NOTES: A. Supply current as a function of supply voltage in power-up mode.
B. Supply current as a function of supply voltage in power-down mode.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLV320AIC1106PW ACTIVE TSSOP PW 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV320AIC1106PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV320AIC1106PWR ACTIVE TSSOP PW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV320AIC1106PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 27-Feb-2006
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV320AIC1106PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV320AIC1106PWR TSSOP PW 20 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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