IRF840 Data Sheet July 1999 8A, 500V, 0.850 Ohm, N-Channel Power MOSFET Ordering Information PART NUMBER IRF840 NOTE: PACKAGE TO-220AB 2312.3 Features * 8A, 500V This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA17425. File Number * rDS(ON) = 0.850 * Single Pulse Avalanche Energy Rated * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" Symbol BRAND D IRF840 When ordering, include the entire part number. G S Packaging JEDEC TO-220AB TOP VIEW SOURCE DRAIN GATE DRAIN (FLANGE) 4-257 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 IRF840 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ , TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg IRF840 500 500 8.0 5.1 32 20 125 1.0 510 -55 to 150 UNITS V V A A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified MIN TYP MAX UNITS Drain to Source Breakdown Voltage PARAMETER BVDSS VGS = 0V, ID = 250A (Figure 10) 500 - - V Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = 250A 2.0 - 4.0 V - - 25 A - - 250 A 8.0 - - A Zero-Gate Voltage Drain Current SYMBOL IDSS TEST CONDITIONS VDS = Rated BVDSS , VGS = 0V VDS = 0.8 x Rated BVDSS , VGS = 0V, TJ = 125oC On-State Drain Current (Note 2) Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time ID(ON) IGSS rDS(ON) gfs tD(ON) Rise Time tr Turn-Off Delay Time VDS > ID(ON) x rDS(ON)MAX , VGS = 10V VGS = 20V - - 100 nA VGS = 10V, ID = 4.4A (Figures 8, 9) - 0.8 0.85 4.9 7.4 - S - 15 21 ns - 21 35 ns - 50 74 ns VDS 50V, ID = 4.4A (Figure 12) VDD = 250V, ID 8A, RG = 9.1, RL = 30 MOSFET Switching Times are Essentially Independent of Operating Temperature. tD(OFF) Fall Time tf Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge Qg(TOT) Qgs VGS = 10V, ID = 8A, VDS = 0.8 x Rated BVDSS Ig(REF) = 1.5mA (Figure 14) Gate Charge is Essentially Independent of Operating Temperature - 20 30 ns - 42 63 nC - 7.0 - nC - 22 - nC - 1225 - pF Gate to Drain "Miller" Charge Qgd Input Capacitance CISS Output Capacitance COSS - 200 - pF Reverse-Transfer Capacitance CRSS - 85 - pF Modified MOSFET Symbol Showing the Internal Devices Measured from the Drain Inductances D Lead, 6mm (0.25in) from Package to Center of Die LD - 3.5 - nH - 4.5 - nH Measured from the Source Lead, 6mm (0.25in) from Header to Source Bonding Pad - 7.5 - nH - - 1.0 oC/W - - 62.5 oC/W Internal Drain Inductance LD Internal Source Inductance LS VGS = 0V, VDS = 25V, f = 1.0MHz (Figure 11) Measured from the Contact Screw on Tab to Center of Die G LS S Thermal Resistance Junction to Case RJC Thermal Resistance Junction to Ambient RJA 4-258 Free Air Operation IRF840 Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current ISD Pulse Source to Drain Current (Note 3) ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode MIN TYP MAX UNITS - - 8.0 A - - 32 A - - 2.0 V 210 475 970 ns 2.0 4.6 8.2 C D G S Source to Drain Diode Voltage (Note 2) VSD Reverse Recovery Time trr Reverse Recovered Charge QRR TJ = 25oC, ISD = 8.0A, VGS = 100A/s (Figure 13) TJ = 25oC, ISD = 8.0A, dISD/dt = 100A/s TJ = 25oC, ISD = 8.0A, dISD/dt = 100A/s NOTES: 2. Pulse Test: Pulse width 300s, duty cycle 2%. 3. Repetitive Rating: Pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 50V, starting TJ = 25oC, L = 14mH, RG = 25, peak IAS = 8A. Typical Performance Curves Unless Otherwise Specified 10 ID , DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 0.2 0 8 6 4 2 0 0 50 100 150 25 50 TC , CASE TEMPERATURE (oC) 75 100 150 125 TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 1 0.5 THERMAL IMPEDANCE ZJC , NORMALIZED TRANSIENT POWER DISSIPATION MULTIPLIER 1.2 0.2 0.1 0.1 0.05 0.02 0.01 10-2 10-3 -5 10 PDM SINGLE PULSE t1 t2 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-4 10-3 10-2 0.1 t1 , RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 4-259 1 10 IRF840 Typical Performance Curves Unless Otherwise Specified (Continued) 15 102 VGS = 10V 10 100s 1ms OPERATION IN THIS REGION IS LIMITED BY rDS(ON) 1 10ms TC = 25oC TJ = MAX RATED SINGLE PULSE 0.1 1 ID , DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 10s 12 VGS = 6.0V 9 VGS = 5.5V 6 VGS = 5.0V 3 DC 102 10 103 0 0 50 100 ISD(ON), DRAIN TO SOURCE CURRENT (A) VGS = 6.0V VGS = 5.5V 6 VGS = 5.0V 3 VGS = 4.0V 200 250 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDS 50V VGS = 10V 12 9 150 FIGURE 5. OUTPUT CHARACTERISTICS 15 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 100 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA ID , DRAIN CURRENT (A) VGS = 4.0V VGS = 4.5V VDS , DRAIN TO SOURCE VOLTAGE (V) 10 1 TJ = 150oC TJ = 25oC 0.1 VGS = 4.5V 0 0.01 0 3 6 9 12 VDS , DRAIN TO SOURCE VOLTAGE (V) 15 0 FIGURE 6. SATURATION CHARACTERISTICS 10 3.0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 8 6 VGS = 10V 4 2 VGS = 20V 0 0 8 32 16 24 TC , CASE TEMPERATURE (oC) FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs VOLTAGE AND DRAIN CURRENT 4-260 2 4 6 8 VSD , GATE TO SOURCE VOLTAGE (V) 10 FIGURE 7. TRANSFER CHARACTERISTICS NORMALIZED DRAIN TO SOURCE ON RESISTANCE VOLTAGE rDS(ON) , DRAIN TO SOURCE ON RESISTANCE () PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 40 2.4 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX ID = 4.4A, VGS = 10V 1.8 1.2 0.6 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 TJ , JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE IRF840 Typical Performance Curves (Continued) 3000 ID = 250A 1.15 1.05 0.95 1800 CISS 1200 COSS 0.85 0.75 -60 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD 2400 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.25 Unless Otherwise Specified CRSS 600 -40 -20 0 20 40 60 80 0 100 120 140 160 1 2 TJ , JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 100 ISD, SOURCE TO DRAIN CURRENT (A) 12 TJ = 25oC 9 TJ = 150oC 6 3 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 10 TJ = 150oC 3 6 9 ID , DRAIN CURRENT (A) 12 TJ = 25oC 1.0 0.1 0 0 15 FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT 1.2 0.3 0.6 0.9 VSD , SOURCE TO DRAIN VOLTAGE (V) 0 FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE 20 ID = 8A 16 VDS = 100V 12 VDS = 250V VDS = 400V 8 4 0 0 12 24 36 48 60 Qg, GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 4-261 102 FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDS 50V VGS , GATE TO SOURCE VOLTAGE (V) gfs, TRANSCONDUCTANCE (S) 15 5 10 2 5 VDS , DRAIN TO SOURCE VOLTAGE (V) 1.5 IRF840 Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN + RG REQUIRED PEAK IAS - VGS VDS IAS VDD VDD DUT tP 0V IAS 0 0.01 tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) tf tr RL VDS 90% 90% + RG - VDD 10% 10% 0 DUT 90% VGS VGS 0 FIGURE 17. SWITCHING TIME TEST CIRCUIT 0.2F 50% PULSE WIDTH 10% FIGURE 18. RESISTIVE SWITCHING WAVEFORMS VDS (ISOLATED SUPPLY) CURRENT REGULATOR 12V BATTERY 50% VDD Qg(TOT) SAME TYPE AS DUT 50k Qgd 0.3F VGS Qgs D VDS DUT G 0 Ig(REF) S 0 IG CURRENT SAMPLING RESISTOR VDS ID CURRENT SAMPLING RESISTOR FIGURE 19. GATE CHARGE TEST CIRCUIT 4-262 Ig(REF) 0 FIGURE 20. GATE CHARGE WAVEFORMS IRF840 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. 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