4-257
File Number
2312.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
http://www.intersil.com or 407-727-9207 |Copyright © Intersil Corporation 1999
IRF840
8A, 500V, 0.850 Ohm, N-Channel Power
MOSFET
This N-Channel enhancement mode silicon gate power field
effect transistor is an advanced power MOSFET designed,
tested, and guaranteed to withstand a specified level of
energy in the breakdown avalanche mode of operation. All of
these power MOSFETs are designed for applications such
as switching regulators, switching converters, motor drivers,
relay drivers, and drivers for high power bipolar switching
transistors requiring high speed and low gate drive power.
These types can be operated directly from integrated
circuits.
Formerly developmental type TA17425.
Features
8A, 500V
•r
DS(ON) = 0.850
Single Pulse Avalanche Energy Rated
SOA is Power Dissipation Limited
Nanosecond Switching Speeds
Linear Transfer Characteristics
High Input Impedance
Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Packaging
JEDEC TO-220AB
TOP VIEW
Ordering Information
PART NUMBER PACKAGE BRAND
IRF840 TO-220AB IRF840
NOTE: When ordering, include the entire part number. G
D
S
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
Data Sheet July 1999
4-258
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified
IRF840 UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS 500 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 500 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID8.0 A
TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID5.1 A
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 32 A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS ±20 V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD125 W
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 W/oC
Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS 510 mJ
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ,T
STG -55 to 150 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
pkg 300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 125oC.
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS VGS = 0V, ID = 250µA (Figure 10) 500 - - V
Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 2.0 - 4.0 V
Zero-Gate Voltage Drain Current IDSS VDS = Rated BVDSS, VGS = 0V - - 25 µA
VDS = 0.8 x Rated BVDSS,V
GS = 0V, TJ= 125oC - - 250 µA
On-State Drain Current (Note 2) ID(ON) VDS > ID(ON) x rDS(ON)MAX, VGS = 10V 8.0 - - A
Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA
Drain to Source On Resistance (Note 2) rDS(ON) VGS = 10V, ID = 4.4A (Figures 8, 9) - 0.8 0.85
Forward Transconductance (Note 2) gfs VDS 50V, ID = 4.4A (Figure 12) 4.9 7.4 - S
Turn-On Delay Time tD(ON) VDD = 250V, ID 8A, RG = 9.1, RL = 30
MOSFET Switching Times are Essentially
Independent of Operating Temperature.
-1521ns
Rise Time tr-2135ns
Turn-Off Delay Time tD(OFF) -5074ns
Fall Time tf-2030ns
Total Gate Charge
(Gate to Source + Gate to Drain) Qg(TOT) VGS = 10V, ID = 8A, VDS = 0.8 x Rated BVDSS
Ig(REF) = 1.5mA (Figure 14) Gate Charge is
Essentially Independent of Operating
Temperature
-4263nC
Gate to Source Charge Qgs - 7.0 - nC
Gate to Drain “Miller” Charge Qgd -22-nC
Input Capacitance CISS VGS = 0V, VDS = 25V, f = 1.0MHz (Figure 11) - 1225 - pF
Output Capacitance COSS - 200 - pF
Reverse-Transfer Capacitance CRSS -85-pF
Internal Drain Inductance LDMeasured from the
Contact Screw on Tab
to Center of Die
Modified MOSFET
Symbol Showing the
Internal Devices
Inductances
- 3.5 - nH
Measuredfromthe Drain
Lead, 6mm (0.25in) from
P ac kage to Center of Die
- 4.5 - nH
Internal Source Inductance LSMeasured from the
Source Lead, 6mm
(0.25in) from Header to
Source Bonding Pad
- 7.5 - nH
Thermal Resistance Junction to Case RθJC - - 1.0 oC/W
Thermal Resistance Junction to Ambient RθJA Free Air Operation - - 62.5 oC/W
LS
LD
G
D
S
IRF840
4-259
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Continuous Source to Drain Current ISD Modified MOSFET
Symbol Showing the
Integral Reverse P-N
Junction Diode
- - 8.0 A
Pulse Source to Drain Current (Note 3) ISDM - - 32 A
Source to Drain Diode Voltage (Note 2) VSD TJ = 25oC, ISD = 8.0A, VGS = 100A/µs (Figure 13) - - 2.0 V
Reverse Recovery Time trr TJ = 25oC, ISD = 8.0A, dISD/dt = 100A/µs 210 475 970 ns
Reverse Recovered Charge QRR TJ = 25oC, ISD = 8.0A, dISD/dt = 100A/µs 2.0 4.6 8.2 µC
NOTES:
2. Pulse Test: Pulse width 300µs, duty cycle 2%.
3. Repetitive Rating: Pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. VDD = 50V, starting TJ = 25oC, L = 14mH, RG = 25, peak IAS = 8A.
Typical Performance Curves
Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
G
D
S
0 50 100 150
0
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
0.2
0.4
0.6
0.8
1.0
1.2
TC, CASE TEMPERATURE (oC)
50 75 10025 150
10
8
6
0
4
ID, DRAIN CURRENT (A)
2
125
ZθJC, NORMALIZED TRANSIENT
1
10-2
10-5 10-4 10-3 0.1 1 10
t1, RECTANGULAR PULSE DURATION (s)
10-3
0.1
10-2
DUTY FACTOR: D = t1/t2
NOTES:
PEAK TJ= PDM x ZθJC x RθJC + TC
t2
PDM
t1t2
SINGLE PULSE
0.02
0.01
0.1
0.2
0.5
0.05
THERMAL IMPEDANCE
IRF840
4-260
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS
FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs
VOLTAGE AND DRAIN CURRENT FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
Typical Performance Curves
Unless Otherwise Specified (Continued)
10
110
102
0.1
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V) 103
102
1
1ms
10ms
DC
100µs
10µs
OPERATION IN THIS
REGION IS LIMITED
BY rDS(ON)
TJ = MAX RATED
SINGLE PULSE
TC = 25oC
VDS, DRAIN TO SOURCE VOLTAGE (V)
50 100 150 2000
15
12
9
0
6
ID, DRAIN CURRENT (A)
PULSE DURATION = 80µs
3
250
VGS = 5.0V
VGS = 6.0V
VGS = 10V
VGS = 4.0V
VGS = 4.5V
VGS = 5.5V
DUTY CYCLE = 0.5% MAX
VDS, DRAIN TO SOURCE VOLTAGE (V)
36912015
15
12
9
0
6
ID, DRAIN CURRENT (A)
3
VGS = 10V
VGS = 4.0V
VGS = 6.0V
VGS = 5.5V
VGS = 4.5V
VGS = 5.0V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
ISD(ON), DRAIN TO SOURCE
VSD, GATE TO SOURCE VOLTAGE (V)
100
10
0.1
0246810
TJ = 150oCTJ = 25oC
1
0.01
CURRENT (A)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDS 50V
TC, CASE TEMPERATURE (oC)
81624040
10
8
6
0
4
2
32
VGS = 20V
VGS = 10V
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE ()
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
20
3.0
1.8
0.6
100
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
2.4
1.2
0140
ON RESISTANCE VOLTAGE
-40 60 16012080400-60 -20
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
ID = 4.4A, VGS = 10V
IRF840
4-261
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
Typical Performance Curves
Unless Otherwise Specified (Continued)
20
1.25
1.05
0.85
100
TJ, JUNCTION TEMPERATURE (oC)
1.15
0.95
0.75 140
-40 60 16012080400-60 -20
ID = 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1
C, CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
3000
2400
1800
1200
600
025 102
10
CISS
52
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS CDS + CGD
COSS
CRSS
ID, DRAIN CURRENT (A)
36912015
15
12
9
0
6
gfs, TRANSCONDUCTANCE (S)
3
TJ = 25oC
TJ = 150oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDS 50V
ISD, SOURCE TO DRAIN CURRENT (A)
VSD, SOURCE TO DRAIN VOLTAGE (V)
10
0 0.3 0.6 0.9 1.5
1.0
TJ = 150oC
1.2
0.1
100
TJ = 25oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
Qg, GATE CHARGE (nC)
12 24 36 48060
20
8
VGS, GATE TO SOURCE VOLTAGE (V)
16
12
0
ID = 8A
4
VDS = 250V
VDS = 100V
VDS = 400V
IRF840
4-262
Test Circuits and Waveforms
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS
tP
VGS
0.01
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
VGS
RL
RG
DUT
+
-VDD
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
0.3µF
12V
BATTERY 50k
VDS
S
DUT
D
G
Ig(REF)
0
(ISOLATED
VDS
0.2µF
CURRENT
REGULATOR
ID CURRENT
SAMPLING
IG CURRENT
SAMPLING
SUPPLY)
RESISTOR RESISTOR
SAME TYPE
AS DUT Qg(TOT)
Qgd
Qgs
VDS
0
VGS
VDD
Ig(REF)
0
IRF840
4-263
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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IRF840