This is information on a product in full production.
January 2016 DocID024244 Rev 9 1/233
STM32F437xx
STM32F439xx
ARM Cortex-M4 32b MCU+FPU, 225DMIPS, up to 2MB Flash/256+4KB RAM, crypto,
USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 20 comm. interfaces, camera&LCD-TFT
Datasheet - production data
Features
•Core: ARM® 32-bit Cortex®-M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait state execution
from Flash memory, frequency up to 180 MHz,
MPU, 225 DMIPS/1.25 DMIPS/MHz
(Dhrystone 2.1), and DSP instructions
•Memories
– Up to 2 MB of Flash memory organized into
two banks allowing read-while-write
– Up to 256+4 KB of SRAM including 64-KB
of CCM (core coupled memory) data RAM
– Flexible external memory controller with up
to 32-bit data bus:
SRAM,PSRAM,SDRAM/LPSDR SDRAM ,
Compact Flash/NOR/NAND memories
•LCD parallel interface, 8080/6800 modes
•LCD-TFT controller up to XGA resolution with
dedicated Chrom-ART Accelerator™ for
enhanced graphic content creation (DMA2D)
•Clock, reset and supply management
– 1.7 V to 3.6 V application supply and I/Os
– POR, PDR, PVD and BOR
– 4-to-26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC (1%
accuracy)
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
•Low power
– Sleep, Stop and Standby modes
–V
BAT supply for RTC, 20×32 bit backup
registers + optional 4 KB backup SRAM
•3×12-bit, 2.4 MSPS ADC: up to 24 channels
and 7.2 MSPS in triple interleaved mode
•2×12-bit D/A converters
•General-purpose DMA: 16-stream DMA
controller with FIFOs and burst support
•Up to 17 timers: up to twelve 16-bit and two 32-
bit timers up to 180 MHz, each with up to 4
IC/OC/PWM or pulse counter and quadrature
(incremental) encoder input
•Debug mode
– SWD & JTAG interfaces
– Cortex-M4 Trace Macrocell™
•Up to 168 I/O ports with interrupt capability
– Up to 164 fast I/Os up to 90 MHz
– Up to 166 5 V-tolerant I/Os
•Up to 21 communication interfaces
– Up to 3 × I2C interfaces (SMBus/PMBus)
– Up to 4 USARTs/4 UARTs (11.25 Mbit/s,
ISO7816 interface, LIN, IrDA, modem
control)
– Up to 6 SPIs (45 Mbits/s), 2 with muxed
full-duplex I2S for audio class accuracy via
internal audio PLL or external clock
– 1 x SAI (serial audio interface)
– 2 × CAN (2.0B Active) and SDIO interface
•Advanced connectivity
– USB 2.0 full-speed device/host/OTG
controller with on-chip PHY
– USB 2.0 high-speed/full-speed
device/host/OTG controller with dedicated
DMA, on-chip full-speed PHY and ULPI
– 10/100 Ethernet MAC with dedicated DMA:
supports IEEE 1588v2 hardware, MII/RMII
•8- to 14-bit parallel camera interface up to
54 Mbytes/s
•Cryptographic acceleration: hardware
acceleration for AES 128, 192, 256, Triple
DES, HASH (MD5, SHA-1, SHA-2), and HMAC
•True random number generator
•CRC calculation unit
•RTC: subsecond accuracy, hardware calendar
•96-bit unique ID
Table 1. Device summary
Reference Part number
STM32F437xx
STM32F437VG, STM32F437ZG, STM32F437IG,
STM32F437VI, STM32F437ZI, STM32F437II,
STM32F437AI
STM32F439xx
STM32F439VI, STM32F439VG, STM32F439ZG,
STM32F439ZI, STM32F439IG, STM32F439II,
STM32F439BG, STM32F439BI, STM32F439NI,
STM32F439AI, STM32F439NG
LQFP100 (14 × 14 mm)
LQFP144 (20 × 20 mm) UFBGA169 (7 × 7 mm)
LQFP176 (24 × 24 mm)
LQFP208 (28 x 28 mm) UFBGA176 (10 x 10 mm)
&"'!
WLCSP143
TFBGA216 (13 x 13 mm)
www.st.com
Contents STM32F437xx and STM32F439xx
2/233 DocID024244 Rev 9
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1 ARM® Cortex®-M4 with FPU and embedded Flash and SRAM . . . . . . . 19
3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 19
3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 20
3.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.8 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.9 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.10 LCD-TFT controller (available only on STM32F439xx) . . . . . . . . . . . . . . 22
3.11 Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 23
3.13 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.15 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.16 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.18 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.18.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.18.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.18.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 30
3.19 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 30
3.20 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.21 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DocID024244 Rev 9 3/233
STM32F437xx and STM32F439xx Contents
5
3.22 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.22.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.22.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.22.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.22.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.22.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.22.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.23 Inter-integrated circuit interface ( I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.24 Universal synchronous/asynchronous receiver transmitters (USART) . . 35
3.25 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.26 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.27 Serial Audio interface (SAI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.28 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.29 Audio and LCD PLL(PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.30 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 38
3.31 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 38
3.32 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.33 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 39
3.34 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 39
3.35 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.36 Cryptographic acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.37 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.38 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.39 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.40 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.41 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.42 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.43 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Contents STM32F437xx and STM32F439xx
4/233 DocID024244 Rev 9
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 96
6.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 96
6.3.5 reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . 97
6.3.6 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.3.8 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.3.12 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 125
6.3.13 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.3.14 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.3.15 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 131
6.3.16 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.3.17 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6.3.18 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.3.19 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
6.3.20 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
6.3.21 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
6.3.22 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
6.3.23 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
6.3.24 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
6.3.25 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
6.3.26 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
6.3.27 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 189
6.3.28 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 190
DocID024244 Rev 9 5/233
STM32F437xx and STM32F439xx Contents
5
6.3.29 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 192
6.3.30 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
7.1 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
7.2 WLCSP143 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
7.3 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
7.4 LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
7.5 LQFP208 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
7.6 UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
7.7 UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
7.8 TFBGA216 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
7.9 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 222
A.1 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Appendix B Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
B.1 USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 223
B.2 USB OTG high speed (HS) interface solutions . . . . . . . . . . . . . . . . . . . . 225
B.3 Ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
List of tables STM32F437xx and STM32F439xx
6/233 DocID024244 Rev 9
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. STM32F437xx and STM32F439xx features and peripheral counts . . . . . . . . . . . . . . . . . . 14
Table 3. Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 27
Table 4. Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 5. Voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 6. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 7. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 8. USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 9. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 10. STM32F437xx and STM32F439xx pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 11. FMC pin definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 12. STM32F437xx and STM32F439xx alternate function mapping . . . . . . . . . . . . . . . . . . . . . 73
Table 13. STM32F437xx and STM32F439xx register boundary addresses. . . . . . . . . . . . . . . . . . . . 85
Table 14. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 15. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 16. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 17. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 18. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 95
Table 19. VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 20. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 96
Table 21. Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 96
Table 22. reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 23. Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 24. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator enabled except prefetch) or RAM. . . . . . 100
Table 25. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 26. Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . 102
Table 27. Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . 103
Table 28. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . 103
Table 29. Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . 104
Table 30. Typical current consumption in Run mode, code with data processing running from
Flash memory or RAM, regulator ON (ART accelerator enabled except prefetch),
VDD=1.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 31. Typical current consumption in Run mode, code with data processing running
from Flash memory, regulator OFF (ART accelerator enabled except prefetch). . . . . . . 107
Table 32. Typical current consumption in Sleep mode, regulator ON, VDD=1.7 V . . . . . . . . . . . . . 108
Table 33. Tyical current consumption in Sleep mode, regulator OFF. . . . . . . . . . . . . . . . . . . . . . . . 109
Table 34. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 35. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 36. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 37. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 38. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 39. HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 40. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 41. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 42. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 43. Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
DocID024244 Rev 9 7/233
STM32F437xx and STM32F439xx List of tables
8
Table 44. PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 45. PLLISAI (audio and LCD-TFT PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 46. SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 47. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 48. Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 49. Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 50. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 51. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 52. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 53. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 54. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 55. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 56. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 57. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 58. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 59. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 60. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 61. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 62. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 63. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 64. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 65. USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 66. USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 67. USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 68. USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 69. USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 70. Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 71. Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 72. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 73. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 74. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 75. ADC static accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 76. ADC static accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 77. ADC static accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 78. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 156
Table 79. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 156
Table 80. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 81. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 82. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 83. internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 84. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 85. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 86. Asynchronous non-multiplexed SRAM/PSRAM/NOR -
read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 87. Asynchronous non-multiplexed SRAM/PSRAM/NOR read -
NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 88. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 167
Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR write -
NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 90. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 91. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 169
Table 92. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 170
List of tables STM32F437xx and STM32F439xx
8/233 DocID024244 Rev 9
Table 93. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 171
Table 94. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 95. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 96. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 97. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 98. Switching characteristics for PC Card/CF read and write cycles
in attribute/common space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 99. Switching characteristics for PC Card/CF read and write cycles
in I/O space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 100. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 101. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 102. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 103. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 104. SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 105. LPSDR SDRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 106. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 107. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 108. Dynamic characteristics: SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 109. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 110. LQPF100 100-pin, 14 x 14 mm low-profile quad flat package mechanical data. . . . . . . . 195
Table 111. WLCSP143 - 143-pin, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 112. WLCSP143 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . 199
Table 113. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 114. LQFP176 - 176-pin, 24 x 24 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 115. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 116. UFBGA169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 117. UFBGA169 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 213
Table 118. UFBGA176+25 - 201-ball 10 x 10 mm, 0.65 mm pitch ultra thin fine pitch
ball grid array mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 119. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 216
Table 120. TFBGA216 - 216 ball 13 × 13 mm 0.8 mm pitch thin fine pitch ball grid array
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 121. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 122. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 123. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 222
Table 124. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
DocID024244 Rev 9 9/233
STM32F437xx and STM32F439xx List of figures
11
List of figures
Figure 1. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx
for LQFP100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 2. Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx
for LQFP144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 3. Compatible board design between STM32F2xx and STM32F4xx
for LQFP176 and UFBGA176 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 4. STM32F437xx and STM32F439xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 5. STM32F437xx and STM32F439xx Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 6. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 25
Figure 7. PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 8. Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 9. Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 10. Startup in regulator OFF mode: fast VDD slope
- power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 29
Figure 11. STM32F43x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 12. STM32F43x WLCSP143 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 13. STM32F43x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 14. STM32F43x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 15. STM32F43x LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 16. STM32F43x UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 17. STM32F43x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 18. STM32F43x TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 19. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 20. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 21. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 22. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 23. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 24. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 25. Typical VBAT current consumption (LSE and RTC ON/backup RAM OFF) . . . . . . . . . . . 104
Figure 26. Typical VBAT current consumption (LSE and RTC ON/backup RAM ON) . . . . . . . . . . . . 105
Figure 27. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 28. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 29. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 30. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 31. HSI deviation vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 32. ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 33. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 34. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 35. FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 36. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 37. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 38. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 39. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 40. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 41. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 42. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 43. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
List of figures STM32F437xx and STM32F439xx
10/233 DocID024244 Rev 9
Figure 44. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 45. USB OTG full speed timings: definition of data signal rise and fall time. . . . . . . . . . . . . . 148
Figure 46. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 47. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 48. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 49. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 50. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 51. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 52. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 159
Figure 53. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 160
Figure 54. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 165
Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 167
Figure 57. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 59. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 60. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 62. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 63. PC Card/CompactFlash controller waveforms for common memory read access . . . . . . 178
Figure 64. PC Card/CompactFlash controller waveforms for common memory write access . . . . . . 178
Figure 65. PC Card/CompactFlash controller waveforms for attribute memory
read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 66. PC Card/CompactFlash controller waveforms for attribute memory
write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 67. PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . 180
Figure 68. PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . 181
Figure 69. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 70. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 71. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 184
Figure 72. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 184
Figure 73. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 74. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 75. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 76. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 77. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 78. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 79. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 80. LQFP100 -100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . . 194
Figure 81. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 82. LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 83. WLCSP143 - 143-pin, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale
package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 84. WLCSP143 - 143-pin, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 85. WLCSP143 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 86. LQFP144-144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . . 200
Figure 87. LQPF144- 144-pin,20 x 20 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 88. LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 89. LQFP176 - 176-pin, 24 x 24 mm low-profile quad flat package outline . . . . . . . . . . . . . . 204
DocID024244 Rev 9 11/233
STM32F437xx and STM32F439xx List of figures
11
Figure 90. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat recommended footprint. . . . . . . . . 206
Figure 91. LQFP176 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Figure 92. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package outline . . . . . . . . . . . . . . 208
Figure 93. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 94. LQFP208 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Figure 95. UFBGA169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Figure 96. UFBGA169 - 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch
ball grid array recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 97. UFBGA169 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Figure 98. UFBGA176+25 - 201-ball 10 x 10 mm, 0.65 mm pitch ultra thin fine pitch
ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 99. UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch
ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 100. UFBGA176+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 101. TFBGA216 - 216 ball 13 × 13 mm 0.8 mm pitch thin fine pitch ball grid array
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Figure 102. TFBGA176 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Figure 103. USB controller configured as peripheral-only and used
in Full speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 104. USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 223
Figure 105. USB controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 224
Figure 106. USB controller configured as peripheral, host, or dual-mode
and used in high speed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 107. MII mode using a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 108. RMII with a 50 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 109. RMII with a 25 MHz crystal and PHY with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Introduction STM32F437xx and STM32F439xx
12/233 DocID024244 Rev 9
1 Introduction
This datasheet provides the description of the STM32F437xx and STM32F439xx line of
microcontrollers. For more details on the whole STMicroelectronics STM32 family, please
refer to Section 2.1: Full compatibility throughout the family.
The STM32F437xx and STM32F439xx datasheet should be read in conjunction with the
STM32F4xx reference manual.
For information on the Cortex®-M4 core, please refer to the Cortex®-M4 programming
manual (PM0214), available from www.st.com.
DocID024244 Rev 9 13/233
STM32F437xx and STM32F439xx Description
42
2 Description
The STM32F437xx and STM32F439xx devices are based on the high-performance ARM®
Cortex®-M4 32-bit RISC core operating at a frequency of up to 180 MHz. The Cortex-M4
core features a Floating point unit (FPU) single precision which supports all ARM® single-
precision data-processing instructions and data types. It also implements a full set of DSP
instructions and a memory protection unit (MPU) which enhances application security.
The STM32F437xx and STM32F439xx devices incorporate high-speed embedded
memories (Flash memory up to 2 Mbyte, up to 256 kbytes of SRAM), up to 4 Kbytes of
backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two
APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.
All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose
16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers,
a true random number generator (RNG) and a cryptographic acceleration cell. They also
feature standard and advanced communication interfaces.
•Up to three I2Cs
•Six SPIs, two I2Ss full duplex. To achieve audio class accuracy, the I2S peripherals can
be clocked via a dedicated internal audio PLL or via an external clock to allow
synchronization.
•Four USARTs plus four UARTs
•An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the
ULPI),
•Two CANs
•One SAI serial audio interface
•An SDIO/MMC interface
•Ethernet and camera interface
•LCD-TFT display controller
•Chrom-ART Accelerator™.
Advanced peripherals include an SDIO, a flexible memory control (FMC) interface, a
camera interface for CMOS sensors and a cryptographic acceleration cell. Refer to Table 2:
STM32F437xx and STM32F439xx features and peripheral counts for the list of peripherals
available on each part number.
The STM32F437xx and STM32F439xx devices operates in the –40 to +105 °C temperature
range from a 1.7 to 3.6 V power supply.
The supply voltage can drop to 1.7 V with the use of an external power supply supervisor
(refer to Section 3.17.2: Internal reset OFF). A comprehensive set of power-saving mode
allows the design of low-power applications.
The STM32F437xx and STM32F439xx devices offer devices in 8 packages ranging from
100 pins to 216 pins. The set of included peripherals changes with the device chosen.
Description STM32F437xx and STM32F439xx
14/233 DocID024244 Rev 9
These features make the STM32F437xx and STM32F439xx microcontrollers suitable for a wide range of applications:
•Motor drive and application control
•Medical equipment
•Industrial applications: PLC, inverters, circuit breakers
•Printers, and scanners
•Alarm systems, video intercom, and HVAC
•Home audio appliances
Figure 4 shows the general block diagram of the device family.
Table 2. STM32F437xx and STM32F439xx features and peripheral counts
Peripherals STM32F437
Vx
STM32F439
Vx STM32F437Zx STM32F437AI STM32F439AI STM32F439Zx STM32F437Ix STM32F439Ix STM32F439Bx STM32F439Nx
Flash memory in Kbytes 1024 2048 1024 2048 1024 2048 2048 2048 1024 2048 1024 2048 1024 2048 1024 2048 1024 2048
SRAM in
Kbytes
System 256(112+16+64+64)
Backup 4
FMC memory controller Yes(1)
Ethernet Yes
Timers
General-
purpose 10
Advance
d-control 2
Basic 2
Random number
generator Yes
STM32F437xx and STM32F439xx Description
DocID024244 Rev 9 15/233
Communication
interfaces
SPI / I2S 4/2 (full duplex)(2) 6/2 (full duplex)(2)
I2C 3
USART/
UART 4/4
USB
OTG FS Yes
USB
OTG HS Yes
CAN 2
SAI 1
SDIO Yes
Camera interface Yes
LCD-TFT No Yes No Yes Yes No Yes
Chrom-ART Accelerator™
(DMA2D) Yes
Cryptography Yes
GPIOs 82 114 140 168 168
12-bit ADC
Number of channels
3
16 24
12-bit DAC
Number of channels
Yes
2
Maximum CPU frequency 180 MHz
Operating voltage 1.7 to 3.6 V(3)
Operating temperatures
Ambient temperatures: –40 to +85 °C /–40 to +105 °C
Junction temperature: –40 to + 125 °C
Package LQFP100 WLCSP143
LQFP144 UFBGA169 WLCSP143
LQFP144
UFBGA176
LQFP176 LQFP208 TFBGA216
1. For the LQFP100 package, only FMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit
NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package.
2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.
3. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.17.2: Internal reset OFF).
Table 2. STM32F437xx and STM32F439xx features and peripheral counts (continued)
Peripherals STM32F437
Vx
STM32F439
Vx STM32F437Zx STM32F437AI STM32F439AI STM32F439Zx STM32F437Ix STM32F439Ix STM32F439Bx STM32F439Nx
Description STM32F437xx and STM32F439xx
16/233 DocID024244 Rev 9
2.1 Full compatibility throughout the family
The STM32F437xx and STM32F439xx devices are part of the STM32F4 family. They are
fully pin-to-pin, software and feature compatible with the STM32F2xx devices, allowing the
user to try different memory densities, peripherals, and performances (FPU, higher
frequency) for a greater degree of freedom during the development cycle.
The STM32F437xx and STM32F439xx devices maintain a close compatibility with the
whole STM32F10xx family. All functional pins are pin-to-pin compatible. The STM32F437xx
and STM32F439xx, however, are not drop-in replacements for the STM32F10xx devices:
the two families do not have the same power scheme, and so their power pins are different.
Nonetheless, transition from the STM32F10xx to the STM32F43x family remains simple as
only a few pins are impacted.
Figure 1, Figure 2, and Figure 3, give compatible board designs between the STM32F4xx,
STM32F2xx, and STM32F10xx families.
Figure 1. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx
for LQFP100 package
633
633
6$$
633
633
633
:RESISTORORSOLDERINGBRIDGEª
PRESENTFORTHE34-&XXX
CONFIGURATIONNOTPRESENTINTHE
34-&XXCONFIGURATION
AIC
633
633
6$$
4WO :RESISTORSCONNECTEDTO
633FORTHE34-&XX
633FORTHE34-&XX
633FOR34-&XX
6$$FOR34-&XX
6336$$OR.#FORTHE34-&XX
DocID024244 Rev 9 17/233
STM32F437xx and STM32F439xx Description
42
Figure 2. Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx
for LQFP144 package
Figure 3. Compatible board design between STM32F2xx and STM32F4xx
for LQFP176 and UFBGA176 packages
DLG
966
UHVLVWRURUVROGHULQJEULGJH
SUHVHQWIRUWKH670)[[
FRQILJXUDWLRQQRWSUHVHQWLQWKH
670)[[FRQILJXUDWLRQ
966
7ZRUHVLVWRUVFRQQHFWHGWR
966IRUWKH670)[[
9669''RU1&IRUWKH670)[[
9''RUVLJQDOIURPH[WHUQDOSRZHUVXSSO\VXSHUYLVRUIRUWKH670)[[
966
9''
966
966
3'5B21
966
9''
966IRU670)[[
9''IRU670)[[
6LJQDOIURP
H[WHUQDOSRZHU
VXSSO\
VXSHUYLVRU
1RWSRSXODWHGZKHQ
UHVLVWRURUVROGHULQJ
EULGJHSUHVHQW
1RWSRSXODWHGIRU670)[[
069
7ZRUHVLVWRUVFRQQHFWHGWR
9669''RU1&IRUWKH670)[[
9''RUVLJQDOIURPH[WHUQDOSRZHUVXSSO\VXSHUYLVRUIRUWKH670)[[
3'5B21
966
9''
6LJQDOIURPH[WHUQDO
SRZHUVXSSO\
VXSHUYLVRU
*1'IRU670)[[
%<3$66B5(*IRU670)[[
Description STM32F437xx and STM32F439xx
18/233 DocID024244 Rev 9
Figure 4. STM32F437xx and STM32F439xx block diagram
1. The timers connected to APB2 are clocked from TIMxCLK up to 180 MHz, while the timers connected to APB1 are clocked
from TIMxCLK either up to 90 MHz or 180 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register.
2. The LCD-TFT is available only on STM32F439xx devices.
'0)/0/24!
!("!0"
%84)47+50
!&
0!;=
4)-07-
COMPLCHAN4)-?#(;=.
CHAN4)-?#(;=%42
"+).AS!&
53!24
2848#+
#43243AS!&
30)
-/3)-)3/
3#+.33AS!&
!0"-(Z
!0"-(Z
ANALOGINPUTSCOMMON
TOTHE!$#S
6$$2%&?!$#
5!24
-/3)3$-)3/3$?EXT3#+#+
.3373-#+AS!&
30)3
4828
BX#!.
$!#?/54
AS!&
)4&
77$'
+""+032!-
/3#?).
/3#?/54
6$$!633!
.234
SMCARD
IR$!
B
3$)/--#
$;=
#-$#+AS!&
6"!4TO6
$-!
3#,3$!3-"!AS!&
)#3-"53
*4!'37
!2-#ORTEX-
-(Z
.6)#
%4-
-05
42!#%#,+
42!#%$;=
%THERNET-!#
$-!
&)&/
-))OR2-))AS!&
-$)/AS!&
53"
/4'(3
$0$-
5,0)#+$;=$)2340.84
)$6"533/&
$-!
3TREAMS
&)&/
!24!##%,
#!#(%
32!-+"
#,+.%;=!;=
$;=./%..7%.
.",;=3$#,+%;=3$.%;=
3$.7%.,
.7!)4.)/2$.2%'#$
).42
2.'
#AMERA
INTERFACE
(39.#639.#
05)8#,+$;=
0(9
53"
/4'&3
$0
$-
)$6"533/&
&)&/
!("-(Z
0(9
&)&/
53!24-"PS
4EMPERATURESENSOR
!$#
!$#
!$#
)&
)&
6$$!
6$$!
0/20$2
"/2
3UPPLY
SUPERVISION
6$$!
06$
)NT
0/2
RESET
84!,K(Z
-!.!'4
24#
2#(3
2#,3
3TANDBY
INTERFACE
)7$'
6"!4
6$$!
6$$
!75
2ESET
CLOCK
CONTROL
0,,
0#,+X
6$$TO6
633
6#!06#!0
6OLTAGE
REGULATOR
TO6
6$$ 0OWERMANAGMT
6$$
"ACKUPREGISTER
!("BUSMATRIX3-
!0"-(Z
,3
4)-
4)-
CHANNELSAS!&
$!#
$!#
-"&LASH
%XTERNALMEMORYCONTROLLER&-#
32!-3$2!-032!-
./2&LASH0##ARD
.!.$&LASH
4)-
4)-
4)-
4)-
4)-
4)-
4)-
$"53
-36
&)&/
&05
!0"-(ZMAX
32!-+"
##-DATA2!-+"
!("
!("-(Z
.*4234*4$)
*4#+37#,+
*4$/37$*4$/
)"53
3"53
$-!
&)&/
$-!
3TREAMS
&)&/
0";=
0#;=
0$;=
0%;=
0&;=
0';=
0(;=
0);=
'0)/0/24"
'0)/0/24#
'0)/0/24$
'0)/0/24%
'0)/0/24&
'0)/0/24'
'0)/0/24(
'0)/0/24)
4)-07-
B
B
4)-
B
4)-
B
SMCARD
IR$!
53!24
COMPLCHAN4)-?#(;=.
CHAN4)-?#(;=%42
"+).AS!&
CHANNELAS!&
CHANNELAS!&
2848#+
#43243AS!&
ANALOGINPUTSCOMMON
TOTHE!$#
ANALOGINPUTSFOR!$#
$!#?/54
AS!&
B
B
BX#!.
)#3-"53
)#3-"53
3#,3$!3-"!AS!&
3#,3$!3-"!AS!&
30)3
-/3)3$-)3/3$?EXT3#+#+
.3373-#+AS!&
4828
2848AS!&
2848AS!&
2848AS!&
#43243AS!&
2848AS!&
#43243AS!&
CHANNELAS!&
5!24
53!24
53!24
SMCARD
IR$!
SMCARD
IR$!
B
B
B
CHANNELAS!&
4)-
CHANNELSAS!&
B
B
B
B
CHANNELS
CHANNELS%42AS!&
CHANNELS%42AS!&
CHANNELS%42AS!&
$-!
!("!0"
,3
/3#?).
/3#?/54
(#,+X
84!,/3#
-(Z
&)&/
30)
3#+.33AS!&
30)
3#+.33AS!&
-/3)-)3/
-/3)-)3/
30)
3#+.33AS!&
-/3)-)3/
2848AS!&
5!24
2848AS!&
5!24
32!-+"
-"&LASH
&)&/
,#$4&4
&)&/
#(2/-!24
$-!$
0*;=
'0)/0/24*
0+;=
'0)/0/24+
3!)
3$3#+&3-#,+AS!&
&)&/
$IGITALFILTER
.2!3.#!3.!$6
4$%3!%3
(!3(
&)&/
&)&/
,#$?2;=,#$?';=,#$?";=
,#$?(39.#,#$?639.#,#$?$%
,#$?#,+
24#?!&
24#?!&
24#?(:
DocID024244 Rev 9 19/233
STM32F437xx and STM32F439xx Functional overview
42
3 Functional overview
3.1 ARM® Cortex®-M4 with FPU and embedded Flash and SRAM
The ARM® Cortex®-M4 with FPU processor is the latest generation of ARM processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The ARM® Cortex®-M4 with FPU core is a 32-bit RISC processor that features exceptional
code-efficiency, delivering the high-performance expected from an ARM core in the memory
size usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
Its single precision FPU (floating point unit) speeds up software development by using
metalanguage development tools, while avoiding saturation.
The STM32F43x family is compatible with all ARM tools and software.
Figure 4 shows the general block diagram of the STM32F43x family.
Note: Cortex-M4 with FPU core is binary compatible with the Cortex-M3 core.
3.2 Adaptive real-time memory accelerator (ART Accelerator™)
The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-
standard ARM® Cortex®-M4 with FPU processors. It balances the inherent performance
advantage of the ARM® Cortex®-M4 with FPU over Flash memory technologies, which
normally requires the processor to wait for the Flash memory at higher frequencies.
To release the processor full 225 DMIPS performance at this frequency, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 180 MHz.
3.3 Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4
gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
Functional overview STM32F437xx and STM32F439xx
20/233 DocID024244 Rev 9
3.4 Embedded Flash memory
The devices embed a Flash memory of up to 2 Mbytes available for storing programs and
data.
3.5 CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a software
signature during runtime, to be compared with a reference signature generated at link-time
and stored at a given memory location.
3.6 Embedded SRAM
All devices embed:
•Up to 256Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory)
data RAM
RAM memory is accessed (read/write) at CPU clock speed with 0 wait states.
•4 Kbytes of backup SRAM
This area is accessible only from the CPU. Its content is protected against possible
unwanted write accesses, and is retained in Standby or VBAT mode.
3.7 Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB
HS, LCD-TFT, and DMA2D) and the slaves (Flash memory, RAM, FMC, AHB and APB
peripherals) and ensures a seamless and efficient operation even when several high-speed
peripherals work simultaneously.
DocID024244 Rev 9 21/233
STM32F437xx and STM32F439xx Functional overview
42
Figure 5. STM32F437xx and STM32F439xx Multi-AHB matrix
3.8 DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.
$50
&RUWH[0
*3
'0$
*3
'0$
0$&
(WKHUQHW
86%27*
+6
%XVPDWUL[6
,&2'(
'&2'(
$&&(/
)ODVK
PHPRU\
65$0
.E\WH
65$0
.E\WH
$+%
SHULSKHUDOV
$+%
SHULSKHUDOV
)0&H[WHUQDO
0HP&WO
,EXV
'EXV
6EXV
'0$B3,
'0$B0(0
'0$B0(0
'0$B3
(7+(51(7B0
86%B+6B0
-36
&&0GDWD5$0
.E\WH
$3%
$3%
65$0
.E\WH
/&'7)7 &KURP$57$FFHOHUDWRU
'0$'
/&'7)7B0
'0$'
Functional overview STM32F437xx and STM32F439xx
22/233 DocID024244 Rev 9
The DMA can be used with the main peripherals:
•SPI and I2S
•I2C
•USART
•General-purpose, basic and advanced-control timers TIMx
•DAC
•SDIO
•Cryptographic acceleration
•Camera interface (DCMI)
•ADC
•SAI1.
3.9 Flexible memory controller (FMC)
All devices embed an FMC. It has four Chip Select outputs supporting the following modes:
PCCard/Compact Flash, SDRAM/LPSDR SDRAM, SRAM, PSRAM, NOR Flash and NAND
Flash.
Functionality overview:
•8-,16-, 32-bit data bus width
•Read FIFO for SDRAM controller
•Write FIFO
•Maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is 90 MHz.
LCD parallel interface
The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
3.10 LCD-TFT controller (available only on STM32F439xx)
The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)
and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
XGA (1024x768) resolution with the following features:
•2 displays layers with dedicated FIFO (64x32-bit)
•Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
•Up to 8 Input color formats selectable per layer
•Flexible blending between two layers using alpha value (per pixel or constant)
•Flexible programmable parameters for each layer
•Color keying (transparency color)
•Up to 4 programmable interrupt events.
DocID024244 Rev 9 23/233
STM32F437xx and STM32F439xx Functional overview
42
3.11 Chrom-ART Accelerator™ (DMA2D)
The Chrom-Art Accelerator™ (DMA2D) is a graphic accelerator which offers advanced bit
blitting, row data copy and pixel format conversion. It supports the following functions:
•Rectangle filling with a fixed color
•Rectangle copy
•Rectangle copy with pixel format conversion
•Rectangle composition with blending and pixel format conversion.
Various image format coding are supported, from indirect 4bpp color mode up to 32bpp
direct color. It embeds dedicated memory to store color lookup tables.
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automatized and are running independently from the CPU or the
DMAs.
3.12 Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 91 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-
M4 with FPU core.
•Closely coupled NVIC gives low-latency interrupt processing
•Interrupt entry vector table address passed directly to the core
•Allows early processing of interrupts
•Processing of late arriving, higher-priority interrupts
•Support tail chaining
•Processor state automatically saved
•Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
3.13 External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 23 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 168 GPIOs can be connected
to the 16 external interrupt lines.
3.14 Clocks and startup
On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full
temperature range. The application can then select as system clock either the RC oscillator
or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is
Functional overview STM32F437xx and STM32F439xx
24/233 DocID024244 Rev 9
detected, the system automatically switches back to the internal RC oscillator and a
software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing
to increase the frequency up to 180 MHz. Similarly, full interrupt management of the PLL
clock entry is available when necessary (for example if an indirectly used external oscillator
fails).
Several prescalers allow the configuration of the two AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB
buses is 180 MHz while the maximum frequency of the high-speed APB domains is
90 MHz. The maximum allowed frequency of the low-speed APB domain is 45 MHz.
The devices embed a dedicated PLL (PLLI2S) and PLLSAI which allows to achieve audio
class performance. In this case, the I2S master clock can generate all standard sampling
frequencies from 8 kHz to 192 kHz.
3.15 Boot modes
At startup, boot pins are used to select one out of three boot options:
•Boot from user Flash
•Boot from system memory
•Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory
through a serial interface. Refer to application note AN2606 for details.
3.16 Power supply schemes
•VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when
enabled), provided externally through VDD pins.
•VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset
blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
•VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
Note: VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply
supervisor (refer to Section 3.17.2: Internal reset OFF). Refer to Table 3: Voltage regulator
configuration mode versus device operating mode to identify the packages supporting this
option.
3.17 Power supply supervisor
3.17.1 Internal reset ON
On packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On the other package, the power supply supervisor is always
enabled.
The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
DocID024244 Rev 9 25/233
STM32F437xx and STM32F439xx Functional overview
42
reached, the option byte loading process starts, either to confirm or modify default BOR
thresholds, or to disable BOR permanently. Three BOR thresholds are available through
option bytes. The device remains in reset mode when VDD is below a specified threshold,
VPOR/PDR or VBOR, without the need for an external reset circuit.
The device also features an embedded programmable voltage detector (PVD) that monitors
the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
3.17.2 Internal reset OFF
This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.
An external power supply supervisor should monitor VDD and should maintain the device in
reset mode as long as VDD is below a specified threshold. PDR_ON should be connected to
this external power supply supervisor. Refer to Figure 6: Power supply supervisor
interconnection with internal reset OFF.
Figure 6. Power supply supervisor interconnection with internal reset OFF
The VDD specified threshold, below which the device must be maintained under reset, is
1.7 V (see Figure 7).
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no more supported:
•The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
•The brownout reset (BOR) circuitry must be disabled
•The embedded programmable voltage detector (PVD) is disabled
•VBAT functionality is no more available and VBAT pin should be connected to VDD.
All packages, except for the LQFP100, allow to disable the internal reset through the
PDR_ON signal.
069
1567
9''
3'5B21
([WHUQDO9''SRZHUVXSSO\VXSHUYLVRU
([WUHVHWFRQWUROOHUDFWLYHZKHQ
9''9
9''
$SSOLFDWLRQUHVHW
VLJQDORSWLRQDO
Functional overview STM32F437xx and STM32F439xx
26/233 DocID024244 Rev 9
Figure 7. PDR_ON control with internal reset OFF
3.18 Voltage regulator
The regulator has four operating modes:
•Regulator ON
– Main regulator mode (MR)
– Low power regulator (LPR)
– Power-down
•Regulator OFF
3.18.1 Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
There are three power modes configured by software when the regulator is ON:
•MR mode used in Run/sleep modes or in Stop modes
– In Run/Sleep mode
The MR mode is used either in the normal mode (default mode) or the over-drive
mode (enabled by software). Different voltages scaling are provided to reach the
best compromise between maximum frequency and dynamic power consumption.
069
9''
WLPH
3'5 9
WLPH
1567
3'5B21 3'5B21
5HVHWE\RWKHUVRXUFHWKDQ
SRZHUVXSSO\VXSHUYLVRU
DocID024244 Rev 9 27/233
STM32F437xx and STM32F439xx Functional overview
42
The over-drive mode allows operating at a higher frequency than the normal mode
for a given voltage scaling.
– In Stop modes
The MR can be configured in two ways during stop mode:
MR operates in normal mode (default mode of MR in stop mode)
MR operates in under-drive mode (reduced leakage mode).
•LPR is used in the Stop modes:
The LP regulator mode is configured by software when entering Stop mode.
Like the MR mode, the LPR can be configured in two ways during stop mode:
– LPR operates in normal mode (default mode when LPR is ON)
– LPR operates in under-drive mode (reduced leakage mode).
•Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost.
Refer to Table 3 for a summary of voltage regulator modes versus device operating modes.
Two external ceramic capacitors should be connected on VCAP_1 and VCAP_2 pin. Refer to
Figure 22: Power supply scheme and Table 19: VCAP1/VCAP2 operating conditions.
All packages have the regulator ON feature.
3.18.2 Regulator OFF
This feature is available only on packages featuring the BYPASS_REG pin. The regulator is
disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply
externally a V12 voltage source through VCAP_1 and VCAP_2 pins.
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency. Refer to Table 17: General operating
conditions.The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling
capacitors. Refer to Figure 22: Power supply scheme.
When the regulator is OFF, there is no more internal monitoring on V12. An external power
supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin
should be used for this purpose, and act as power-on reset on V12 power domain.
Table 3. Voltage regulator configuration mode versus device operating mode(1)
1. ‘-’ means that the corresponding configuration is not available.
Voltage regulator
configuration Run mode Sleep mode Stop mode Standby mode
Normal mode MR MR MR or LPR -
Over-drive
mode(2)
2. The over-drive mode is not available when VDD = 1.7 to 2.1 V.
MR MR - -
Under-drive mode - - MR or LPR -
Power-down
mode ---Yes