bq24171
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SLUSAF2A –FEBRUARY 2011–REVISED MAY 2011
JEITA Compliant Stand-Alone Switch-Mode Li-Ion and Li-Polymer
Battery Charger with Integrated MOSFETs and Power Path Selector
Check for Samples: bq24171
1FEATURES APPLICATIONS
•JEITA Compatible Battery Temperature •Tablet PC
Sensing •Netbook and Ultra-Mobile Computers
•1.6MHz Synchronous Switch-Mode Charger •Portable Data Capture Terminals
with 4A Integrated N-MOSFETs •Portable Printers
•Up to 94% Efficiency •Medical Diagnostics Equipment
•30V Input Rating with Adjustable Over-Voltage •Battery Bay Chargers
Protection •Battery Back-Up Systems
–4.5V to 17V Input Operating Voltage
•Battery Charge Voltage DESCRIPTION
–1, 2, or 3-Cell with 4.2V/Cell The bq24171 is highly integrated stand-alone Li-ion
and Li-polymer switch-mode battery charger with two
•High Integration integrated N-channel power MOSFETs. It offers a
–Automatic Power Path Selector Between constant-frequency synchronous PWM controller with
Adapter and Battery high accuracy regulation of input current, charge
–Dynamic Power Management current, and voltage. It closely monitors the battery
pack temperature and allows charge only in a JEITA
–Integrated 20-V Switching MOSFETs profile compatible window with lower charge rate at
–Integrated Bootstrap Diode low temperature and lower charge voltage at high
–Internal Loop Compensation temperature. It also provides battery detection,
pre-conditioning, charge termination, and charge
–Internal Digital Soft Start status monitoring. The thermal regulation loop
•Safety reduces charge current to maintain the junction
–Thermal Regulation Loop Throttles Back temperature of 120°C during operation.
Current to Limit Tj= 120°CThe bq24171 charges the battery in three phases:
–Thermal Shutdown preconditioning, constant current, and constant
–Battery Thermistor Sense Hot/Cold Charge voltage. It is adjustable for up to three series Li+
Suspend &Battery Detect cells.
–Input Over-Voltage Protection with Charge is terminated when the current reaches 10%
Programmable Threshold of the fast charge rate. A programmable charge timer
offers a safety back up. The bq24171 automatically
–Cycle-by-Cycle Current Limit restarts the charge cycle if the battery voltage falls
•Accuracy below an internal threshold, and enters a
– ±0.5% Charge Voltage Regulation low-quiescent current sleep mode when the input
voltage falls below the battery voltage.
– ±4% Charge Current Regulation
– ±4% Input Current Regulation The bq24171 features Dynamic Power Management
(DPM) to reduce the charge current when the input
•Less than 15μA Battery Current with Adapter power limit is reached to avoid over-loading the
Removed adapter. A highly-accurate current-sense amplifier
•Less than 1.5mA Input Current with Adapter enables precise measurement of input current from
Present and Charge Disabled adapter to monitor overall system power.
•Small QFN Package
–3.5mm ×5.5mm QFN-24 Pin
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright ©2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
PVCC
PVCC
AVCC
ACN
ACP
CMSRC
ACDRV
STAT
TS
TTC
PGND
PGND
BTST
REGN
BATDRV
OVPSET
ACSET
SRP
SRN
FB
1
SW
SW
VREF
ISET
24
AGND
2
3
4
5
6
7
8
9
10
11
23
22
21
20
19
18
17
16
15
14
12 13
bq24171
SLUSAF2A –FEBRUARY 2011–REVISED MAY 2011
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The bq24171 provides power path selector gate driver ACDRV/CMSRC on input NMOS pair ACFET (Q1) and
RBFET (Q2), and BATDRV on a battery PMOS device (Q3). When the qualified adapter is present, the system is
directly connected to the adapter. Otherwise, the system is connected to the battery. In addition, the power path
prevents battery from boosting back to the input.
The bq24171 charges battery from DC source as high as 17V, including car battery. The input over-voltage limit
is adjustable through OVPSET pin. The AVCC, ACP and ACN pins are 30V rating. When a high-voltage DC
source is inserted, Q1/Q2 remain off to avoid high-voltage damage to the system.
For 1 cell applications, if the battery is not removable, the system can be directly connected to the battery to
simplify the power path design and lower the cost. With this configuration, the battery can automatically
supplement the system load if the adapter is overloaded.
The bq24171 is available in a 24-pin, 3.5mmx5.5 mm thin QFN package.
RGY PACKAGE
(TOP VIEW)
PIN FUNCTIONS
PIN TYPE DESCRIPTION
NO. NAME
1,24 SW P Switching node, charge current output inductor connection. Connect the 0.047-µF bootstrap capacitor
from SW to BTST.
2,3 PVCC P Charger input voltage. Connect at least 10-µF ceramic capacitor from PVCC to PGND and place it as
close as possible to IC.
4 AVCC P IC power positive supply. Place a 1-µF ceramic capacitor from AVCC to AGND and place it as close as
possible to IC. Place a 10-Ωresistor from input side to AVCC pin to filter the noise. For 5V input, a 5-Ω
resistor is recommended.
5 ACN I Adapter current sense resistor negative input. A 0.1-µF ceramic capacitor is placed from ACN to ACP to
provide differential-mode filtering. An optional 0.1-µF ceramic capacitor is placed from ACN pin to AGND
for common-mode filtering.
6 ACP P/I Adapter current sense resistor positive input. A 0.1-µF ceramic capacitor is placed from ACN to ACP to
provide differential-mode filtering. A 0.1-µF ceramic capacitor is placed from ACP pin to AGND for
common-mode filtering.
7 CMSRC O Connect to common source of N-channel ACFET and reverse blocking MOSFET (RBFET). Place 4-kΩ
resistor from CMSRC pin to the common source of ACFET and RBFET to control the turn-on speed. The
resistance between ACDRV and CMSRC should be 500-kΩor bigger.
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ISET
CHG
SR
V
I = 20 R´
ACSET
DPM
AC
V
I = 20 R´
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SLUSAF2A –FEBRUARY 2011–REVISED MAY 2011
PIN FUNCTIONS (continued)
PIN TYPE DESCRIPTION
NO. NAME
8 ACDRV O AC adapter to system switch driver output. Connect to 4-kΩresistor then to the gate of the ACFET
N-channel power MOSFET and the reverse conduction blocking N-channel power MOSFET. Connect
both FETs as common-source. The internal gate drive is asymmetrical, allowing a quick turn-off and
slower turn-on in addition to the internal break-before-make logic with respect to the BATDRV.
9 STAT O Open-drain charge status pin with 10-kΩpull up to power rail. The STAT pin can be used to drive LED or
communicate with the host processor. It indicates various charger operations: LOW when charge in
progress. HIGH when charge is complete or in SLEEP mode. Blinking at 0.5Hz when fault occurs,
including charge suspend, input over-voltage, timer fault and battery absent.
10 TS I Temperature qualification voltage input. Connect a negative temperature coefficient thermistor. Program
the hot and cold temperature window with a resistor divider from VREF to TS to AGND. The 103AT
thermistor is recommended.
11 TTC I Safety Timer and termination control. Connect a capacitor from this node to AGND to set the fast charge
safety timer(5.6min/nF). Pre-charge timer is internally fixed to 30 minutes. Pull the TTC to LOW to disable
the charge termination and safety timer. Pull the TTC to HIGH to disable the safety timer but allow the
charge termination.
12 VREF P 3.3V reference voltage output. Place a 1-μF ceramic capacitor from VREF to AGND pin close to the IC.
This voltage could be used for programming ISET and ACSET and TS pins.
13 ISET I Fast charge current set point. Use a voltage divider from VREF to ISET to AGND to set the fast charge
current:
The pre-charge and termination current is internally as one tenth of the charge current. The charger is
disabled when ISET pin voltage is below 40mV and enabled when ISET pin voltage is above 120mV.
14 FB I Charge voltage analog feedback adjustment. Connect the output of a resistor divider powered from the
battery terminals to FB to AGND. Output voltage is regulated to 2.1V on FB pin during constant-voltage
mode.
15 SRN I Charge current sense resistor negative input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to
provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from SRN pin to AGND for
common-mode filtering.
16 SRP I/P Charge current sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to
provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from SRP pin to AGND for
common-mode filtering.
17 ACSET I Input current set point. Use a voltage divider from VREF to ACSET to AGND to set this value:
18 OVPSET I Valid input voltage set point. Use a voltage divider from input to OVPSET to AGND to set this voltage.
The voltage above internal 1.6V reference indicates input over-voltage, and the voltage below internal
0.5V reference indicates input under-voltage. In either condition, charge terminates, and input NMOS pair
ACFET/RBFET turn off. LED driven by STAT pin keeps blinking, reporting fault condition.
19 BATDRV O Battery discharge MOSFET gate driver output. Connect to 1kohm resistor to the gate of the BATFET
P-channel power MOSFET. Connect the source of the BATFET to the system load voltage node. Connect
the drain of the BATFET to the battery pack positive node. The internal gate drive is asymmetrical to
allow a quick turn-off and slower turn-on, in addition to the internal break-before-make logic with respect
to ACDRV.
20 REGN P PWM low side driver positive 6V supply output. Connect a 1-μF ceramic capacitor from REGN to PGND
pin, close to the IC. Generate high-side driver bootstrap voltage by integrated diode from REGN to BTST.
21 BTST P PWM high side driver positive supply. Connect the 0.047-µF bootstrap capacitor from SW to BTST.
22,23 PGND P Power ground. Ground connection for high-current power converter node. On PCB layout, connect
directly to ground connection of input and output capacitors of the charger. Only connect to AGND
through the Thermal Pad underneath the IC.
Thermal AGND P Exposed pad beneath the IC. Always solder Thermal Pad to the board, and have vias on the Thermal
Pad Pad plane star-connecting to AGND and ground plane for high-current power converter. It dissipates the
heat from the IC.
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 3
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L: 3.3?H
12V Adapter
C9, C10
10?
VBAT
SW
BTST
REGN
PGND
C5
0.047?
ACP
CIN
2.2?
ISET
VREF
CMSRC
TTC SRN
OVPSET
TS
SRP
THERMAL
PAD
C3: 0.1?
STAT
PVCC
ACN
VREF
FB
RIN
2
BATDRV
C7
0.1?
C11: 0.1µ
C12: 0.1µ
C4: 10µ
C2: 1µ
C1
1µ
C6
1?
VREF
R11
4.02k
R12
4.02k
ACDRV
Q1 Q2
Q3
R14
1k
C8
0.1?
RT
103AT
R2
232k
R3
32.4k
R1
10
R6
1000k
R7
100k R8
2.2k
R9
6.8k
R10
1.5k
AVCC
ACSET
R4
100k
R5
22.1k
VREF
D1
D3
D2
VBAT
VREF
bq24171
L: 3.3?H
C9, C10
10?
VBAT
SW
BTST
REGN
PGND
C5
0.047?
ACP
CIN
2.2?
ISET
VREF
CMSRC
TTC SRN
OVPSET
TS
SRP
THERMAL
PAD
C3: 0.1?
STAT
PVCC
ACN
VREF
RIN
2
R : 10m
AC
BATDRVBATDRV
C7
0.1?
C11: 0.1µ
C12: 0.1µ
C4: 10µ
C2: 1µ
C1
1µ
C6
1?
VREF
R11
4.02k
R12
4.02k
ACDRV R :10m
SR
Q1 Q2
Q3
R14
1k
C8
0.1?
RT
103AT
R2
232k
R3
32.4k
R1
10
R6
1000k
R7
100k R8
R9 R10
1.5k
AVCC
ACSET
R4
100k
R5
22.1k
VREF
D1
D3
D2
VBAT
VREF
10?10?
System
R2
299 kW
R2
100 kW
bq24171
SLUSAF2A –FEBRUARY 2011–REVISED MAY 2011
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TYPICAL APPLICATIONS
Figure 1. Typical Application Schematic (12V input, 2 cell battery 8.4V, 2A charge current, 0.2A
pre-charge/termination current, 3A DPM current, 18V input OVP)
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3.3?H
USB
10?
VBAT
SW
BTST
REGN
PGND
0.047?
ACP
ISET
VREF
CMSRC
TTC SRN
OVPSET
TS
SRP
THERMAL
PAD
STAT
PVCC
ACN
VREF
FB
BATDRV
0.1?
4.7µ
1µ
C1
1µ
1?
VREF
ACDRV
0.1?
RT
103AT
R11
5
AVCC
ACSET
VREF
D3
ILIM_500mA
Selectable
current limit
R6
400k
R7
100k R8
R9
6.8k
R10
1.5k
R4
100k
R5A
12.1k
R5B
12.1k
VREF
bq24171
R2
100k
R1
100k
3.3?H
10?
SW
BTST
REGN
PGND
0.047?
ACP
ISET
VREF
CMSRC
TTC SRN
OVPSET
TS
SRP
THERMAL
PAD
STAT
PVCC
ACN
VREF
FB
BATDRVBATDRV
0.1?
4.7µ
1µ
C1
1µ
1?
VREF
ACDRV R : 20m
SR
0.1?
RT
103AT
AVCC
ACSET
VREF
D3
ILIM_500mA
System
Selectable
current limit
R6
400k
R7
100k
2.2k
R10
1.5k
R4
100k
R5A
12.1k
R5B
12.1k
VREF
R2
100k
R1
100k
10?10?
D1
Optional
bq24171
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SLUSAF2A –FEBRUARY 2011–REVISED MAY 2011
Figure 2. Typical Application Schematic with Single Cell Unremovable Battery (USB with input OVP 8V,
selectable charge current limit of 900mA or 500mA, system connected after sense resistor)
ORDERING INFORMATION(1)
PART NUMBER PART MARKING PACKAGE ORDERING NUMBER QUANTITY
bq24171RGYR 3000
bq24171 bq24171 24-Pin 3.5mm×5.5mm QFN bq24171RGYT 250
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
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SLUSAF2A –FEBRUARY 2011–REVISED MAY 2011
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)(2)
VALUE UNIT
AVCC, ACP, ACN, ACDRV, CMSRC, STAT –0.3 to 30
PVCC –0.3 to 20
BATDRV, SRP, SRN –0.3 to 20
SW –2 to 20
Voltage range (with respect to AGND) V
FB –0.3 to 16
OVPSET, REGN, TS, TTC –0.3 to 7
VREF, ISET, ACSET –0.3 to 3.6
PGND –0.3 to 0.3
Maximum difference voltage SRP–SRN, ACP-ACN –0.5 to 0.5 V
Junction temperature range, TJ–40 to 155 °C
Storage temperature range, Tstg –55 to 155 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging
Section of the data book for thermal limitations and considerations of packages.
THERMAL INFORMATION bq24171
THERMAL METRIC(1) RGY UNITS
24 PINS
θJA Junction-to-ambient thermal resistance(2) 35.7
ψJT Junction-to-top characterization parameter(3) 0.4 °C/W
ψJB Junction-to-board characterization parameter(4) 31.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(4) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT
Input voltage VIN 4.5 17 V
Output voltage VOUT 13.5 V
Output current (RSR 10mΩ) IOUT 0.6 4 A
ACP - ACN –200 200 mV
Maximum difference voltage SRP–SRN –200 200 mV
Operation free-air temperature range, TA–40 85 °C
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SLUSAF2A –FEBRUARY 2011–REVISED MAY 2011
ELECTRICAL CHARACTERISTICS
4.5V ≤V(PVCC, AVCC) ≤17V, –40°C<TJ+ 125°C, typical values are at TA= 25°C, with respect to AGND (unless otherwise
noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
OPERATING CONDITIONS
AVCC input voltage operating range during
VAVCC_OP 4.5 17 V
charging
QUIESCENT CURRENTS
VAVCC >VUVLO, VSRN >VAVCC (SLEEP), 15
TJ= 0°C to 85°C
BTST, SW, SRP, SRN, VAVCC >VUVLO, VAVCC >
Battery discharge current (sum of currents
IBAT µA
VSRN, ISET <40mV, VBAT=12.6V, Charge 25
into AVCC, PVCC, ACP, ACN) disabled
BTST, SW, SRP, SRN, VAVCC >VUVLO, VAVCC >25
VSRN, ISET >120mV, VBAT=12.6V, Charge done
VAVCC >VUVLO, VAVCC >VSRN, ISET <40mV, 1.2 1.5
VBAT=12.6V, Charge disabled
Adapter supply current (sum of current into VAVCC >VUVLO, VAVCC >VSRN, ISET >120mV,
IAC 2.5 5 mA
AVCC,ACP, ACN) Charge enabled, no switching
VAVCC >VUVLO, VAVCC >VSRN, ISET >120mV, 15(1)
Charge enabled, switching
CHARGE VOLTAGE REGULATION
VT3 <VTS <VT1 2.1
VFB_REG Feedback Regulation Voltage VT4 <VTS <VT3 2.05 V
VT5 <VTS <VT4 2.025
TJ= 0 to 85°C–0.5% –0.5%
Charge Voltage Regulation Accuracy TJ=–40 to 125°C–0.7% –0.7%
IVFB Leakage Current into FB pin VFB = 2.1V, 2.05V, 2.025V 100 nA
CURRENT REGULATION –FAST CHARGE
VISET ISET Voltage Range RSENSE = 10mΩ0.12 0.8 V
Charge Current Set Factor (Amps of Charge
KISET RSENSE = 10mΩ5 A/V
Current per Volt on ISET pin)
VSRP-SRN = 40 mV –4% 4%
Charge Current Regulation Accuracy VSRP-SRN = 20 mV –7% 7%
(with Schottky diode on SW) VSRP-SRN = 5 mV –25% 25%
VISET_CD Charge Disable Threshold ISET falling 40 50 mV
VISET_CE Charge Enable Threshold ISET rising 100 120 mV
IISET Leakage Current into ISET VISET = 2V 100 nA
INPUT CURRENT REGULATION
Input DPM Current Set Factor (Amps of
KDPM RSENSE = 10mΩ5 A/V
Input Current per Volt on ACSET)
VACP-ACN = 80 mV -4% 4%
VACP-ACN = 40 mV -9% 9%
Input DPM Current Regulation Accuracy VACP-ACN = 20 mV –15% 15%
(with Schottky diode on SW) VACP-ACN = 5 mV –20% 20%
VACP-ACN = 2.5 mV -40% 40%
IACSET Leakage Current into ACSET pin VACSET = 2V 100 nA
CURRENT REGULATION –PRE-CHARGE
KIPRECHG Precharge current set factor Percentage of fast charge current 10%(2)
VSRP-SRN = 4 mV –25% 25%
Precharge current regulation accuracy VSRP-SRN = 2 mV –40% 40%
(1) Specified by design
(2) The minimum current is 120 mA on 10mΩsense resistor.
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ELECTRICAL CHARACTERISTICS (continued)
4.5V ≤V(PVCC, AVCC) ≤17V, –40°C<TJ+ 125°C, typical values are at TA= 25°C, with respect to AGND (unless otherwise
noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
CHARGE TERMINATION
KTERM Termination current set factor Percentage of fast charge current 10%(3)
VSRP-SRN = 4 mV –25% 25%
Termination current regulation accuracy VSRP-SRN = 2 mV –40% 40%
tTERM_DEG Deglitch time for termination (both edges) 100 ms
tQUAL Termination qualification time VSRN >VRECH and ICHG <ITERM 250 ms
IQUAL Termination qualification current Discharge current once termination is detected 2 mA
INPUT UNDER-VOLTAGE LOCK-OUT COMPARATOR (UVLO)
VUVLO AC under-voltage rising threshold Measure on AVCC 3.4 3.6 3.8 V
VUVLO_HYS AC under-voltage hysteresis, falling Measure on AVCC 300 mV
SLEEP COMPARATOR (REVERSE DISCHARGING PROTECTION)
VSLEEP SLEEP mode threshold VAVCC –VSRN falling 50 90 150 mV
VSLEEP_HYS SLEEP mode hysteresis VAVCC –VSRN rising 200 mV
tSLEEP_FALL_CD SLEEP deglitch to disable charge VAVCC –VSRN falling 1 ms
tSLEEP_FALL_FETOFF SLEEP deglitch to turn off input FETs VAVCC –VSRN falling 5 ms
Deglitch to enter SLEEP mode, disable
tSLEEP_FALL VAVCC –VSRN falling 100 ms
VREF and enter low quiescent mode
Deglitch to exit SLEEP mode, and enable
tSLEEP_PWRUP VAVCC –VSRN rising 30 ms
VREF
ACN-SRN COMPARATOR
VACN-SRN Threshold to turn on BATFET VACN-SRN falling 150 220 300 mV
VACN-SRN_HYS Hysteresis to turn off BATFET VACN-SRN rising 100 mV
tBATFETOFF_DEG Deglitch to turn on BATFET VACN-SRN falling 2 ms
tBATFETON_DEG Deglitch to turn off BATFET VACN-SRN rising 50 µs
BAT LOWV COMPARATOR
VLOWV Precharge to fast charge transition Measure on FB 1.43 1.45 1.47 V
VLOWV_HYS Fast charge to precharge hysteresis Measure on FB 100 mV
tpre2fas VLOWV rising deglitch Delay to start fast charge current 25 ms
tfast2pre VLOWV falling deglitch Delay to start precharge current 25 ms
RECHARGE COMPARATOR
Recharge Threshold, below regulation
VRECHG Measure on FB 35 50 65 mV
voltage limit, VFB_REG-VFB
tRECH_RISE_DEG VRECHG rising deglitch VFB decreasing below VRECHG 10 ms
tRECH_FALL_DEG VRECHG falling deglitch VFB increasing above VRECHG 10 ms
BAT OVER-VOLTAGE COMPARATOR
VOV_RISE Over-voltage rising threshold As percentage of VFB_REG 104%
VOV_FALL Over-voltage falling threshold As percentage of VFB_REG 102%
(3) The minimum current is 120 mA on 10mΩsense resistor.
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SLUSAF2A –FEBRUARY 2011–REVISED MAY 2011
ELECTRICAL CHARACTERISTICS (continued)
4.5V ≤V(PVCC, AVCC) ≤17V, –40°C<TJ+ 125°C, typical values are at TA= 25°C, with respect to AGND (unless otherwise
noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
INPUT OVER-VOLTAGE COMPARATOR (ACOV)
AC Over-Voltage Rising Threshold to turn
VACOV OVPSET rising 1.57 1.6 1.63 V
off ACFET
VACOV_HYS AC over-voltage falling hysteresis OVPSET falling 50 mV
AC Over-Voltage Rising Deglitch to turn off
tACOV_RISE_DEG OVPSET rising 1 µs
ACFET and Disable Charge
AC Over-Voltage Falling Deglitch to Turn on
tACOV_FALL_DEG OVPSET falling 30 ms
ACFET
INPUT UNDER-VOLTAGE COMPARATOR (ACUV)
AC Under-Voltage Falling Threshold to turn
VACUV OVPSET falling 0.487 0.497 0.507 V
off ACFET
VACUV_HYS AC Under-Voltage Rising Hysteresis OVPSET rising 100 mV
AC Under-Voltage Falling Deglitch to turn
tACOV_FALL_DEG OVPSET falling 1 µs
off ACFET and Disable Charge
AC Under-Voltage Rising Deglitch to turn on
tACOV_RISE_DEG OVPSET rising 30 ms
ACFET
THERMAL REGULATION
TJ_REG Junction Temperature Regulation Accuracy ISET >120mV, Charging 120 °C
THERMAL SHUTDOWN COMPARATOR
TSHUT Thermal shutdown rising temperature Temperature rising 150 °C
TSHUT_HYS Thermal shutdown hysteresis Temperature falling 20 °C
tSHUT_RISE_DEG Thermal shutdown rising deglitch Temperature rising 100 µs
tSHUT_FALL_DEG Thermal shutdown falling deglitch Temperature falling 10 ms
THERMISTOR COMPARATOR
T1 (0 °C) threshold, Charge suspended
VT1 VTS rising, As Percentage to VVREF 70.2% 70.8% 71.4%
below this temperature.
Charge back to ICHARGE/2 and VFB=2.1 V
VT1-HYS Hysteresis, VTS falling 0.6%
above this temperature.
T2 (10 °C) threshold, Charge back to
VT2 ICHARGE/2 and VFB=2.1 V below this VTS rising, As Percentage to VVREF 68.0% 68.6% 69.2%
temperature.
Charge back to ICHARGE and VFB=2.1 V
VT2-HYS Hysteresis, VTS falling 0.8%
above this temperature.
T3 (45 °C) threshold, Charge back to
VT3 ICHARGE and VFB=2.05 V above this VTS falling, As Percentage to VVREF 55.5% 56.1% 56.7%
temperature.
Charge back to ICHARGE and VFB=2.1 V
VT3-HYS Hysteresis, VTS rising 0.8%
below this temperature.
T4 (50 °C) threshold, Charge back to
VT4 ICHARGE and VFB=2.025 V above this VTS falling, As Percentage to VVREF 53.2% 53.7% 54.2%
temperature.
Charge back to ICHARGE and VFB=2.05 V
VT4-HYS Hysteresis, VTS rising 0.8%
below this temperature.
T5 (60 °C) threshold, Charge suspended
VT5 VTS falling, As Percentage to VVREF 47.6% 48.1% 48.6%
above this temperature.
Charge back to ICHARGE and VFB=2.025 V
VT5-HYS Hysteresis, VTS rising 1.2%
below this temperature.
Deglitch time for Temperature Out of Valid VTS <VT5 or VTS >VT1 400 ms
Charge Range Detection
Deglitch time for Temperature In Valid VTS >VT5 + VT5_HYS or VTS <VT1 - VT1_HYS 20
Range Detection
Deglitch time for Temperature Detection 25 ms
above/below T2, T3, T4 threshold
Charge Current when VTS between VT1 and ICHARGE/
VT2 range 2
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ELECTRICAL CHARACTERISTICS (continued)
4.5V ≤V(PVCC, AVCC) ≤17V, –40°C<TJ+ 125°C, typical values are at TA= 25°C, with respect to AGND (unless otherwise
noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
CHARGE OVER-CURRENT COMPARATOR (CYCLE-BY-CYCLE)
Charge Over-Current Rising Threshold,
VOCP_CHRG Current as percentage of fast charge current 160%
VSRP>2.2V
VOCP_MIN Charge Over-Current Limit Min, VSRP<2.2V Measure VSRP-SRN 45 mV
VOCP_MAX Charge Over-Current Limit Max, VSRP>2.2V Measure VSRP-SRN 75 mV
HSFET OVER-CURRENT COMPARATOR (CYCLE-BY-CYCLE)
IOCP_HSFET Current limit on HSFET Measure on HSFET 8 11.5 A
CHARGE UNDER-CURRENT COMPARATOR (CYCLE-BY-CYCLE)
VUCP Charge under-current falling threshold Measure on V(SRP-SRN) 1 5 9 mV
BAT SHORT COMPARATOR
VBATSHT Battery short falling threshold Measure on SRN 2 V
VBATSHT_HYS Battery short rising hysteresis Measure on SRN 200 mV
tBATSHT_DEG Deglitch on both edges 1 µs
VBATSHT Charge Current during BATSHORT Percentage of fast charge current 10%(4)
VREF REGULATOR
VVREF_REG VREF regulator voltage VAVCC >VUVLO, No load 3.267 3.3 3.333 V
IVREF_LIM VREF current limit VVREF = 0 V, VAVCC >VUVLO 35 90 mA
REGN REGULATOR
VREGN_REG REGN regulator voltage VAVCC >10 V, ISET >120 mV 5.7 6.0 6.3 V
IREGN_LIM REGN current limit VREGN = 0 V, VAVCC >10 v, ISET >120 mV 40 120 mA
TTC INPUT
tprechrg Precharge Safety Timer Precharge time before fault occurs 1620 1800 1980 Sec
tfastchrg Fast Charge Timer Range Tchg=CTTC*KTTC 1 10 hr
Fast Charge Timer Accuracy -10% 10%
KTTC Timer Multiplier 5.6 min/nF
VTTC_LOW TTC Low Threshold TTC falling 0.4 V
ITTC TTC Source/Sink Current 45 50 55 µA
VTTC_OSC_HI TTC oscillator high threshold 1.5 V
VTTC_OSC_LO TTC oscillator low threshold 1 V
BATTERY SWITCH (BATFET) DRIVER
RDS_BAT_OFF BATFET Turn-off Resistance VAVCC >5V 100 Ω
RDS_BAT_ON BATFET Turn-on Resistance VAVCC >5V 20 kΩ
VBATDRV_REG =VACN - VBATDRV when VAVCC >5V
VBATDRV_REG BATFET Drive Voltage 4.2 7 V
and BATFET is on
BATFET Power-up Delay to turn off
tBATFET_DEG 30 ms
BATFET after adapter is detected
AC SWITCH (ACFET) DRIVER
IACFET ACDRV Charge Pump Current Limit VACDRV - VCMSRC = 5V 60 µA
VACDRV_REG Gate Drive Voltage on ACFET VACDRV - VCMSRC when VAVCC >VUVLO 4.2 6 V
Maximum load between ACDRV and
RACDRV_LOAD 500 kΩ
CMSRC
AC/BAT SWITCH DRIVER TIMING
Dead Time when switching between ACFET and
tDRV_DEAD Driver Dead Time 10 µs
BATFET
(4) The minimum current is 120 mA on 10mΩsense resistor.
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ELECTRICAL CHARACTERISTICS (continued)
4.5V ≤V(PVCC, AVCC) ≤17V, –40°C<TJ+ 125°C, typical values are at TA= 25°C, with respect to AGND (unless otherwise
noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
BATTERY DETECTION
tWAKE Wake timer Max time charge is enabled 500 ms
IWAKE Wake current RSENSE = 10 mΩ50 125 200 mA
tDISCHARGE Discharge timer Max time discharge current is applied 1 sec
IDISCHARGE Discharge current 8 mA
IFAULT Fault current after a timeout fault 2 mA
Wake threshold with respect to VREG To
VWAKE Measure on FB 50 mV
detect battery absent during WAKE
Discharge Threshold to detect battery
VDISCH Measure on FB 1.45 V
absent during discharge
INTERNAL PWM
fsw PWM Switching Frequency 1360 1600 1840 kHz
Dead time when switching between LSFET and
tSW_DEAD Driver Dead Time(5) 30 ns
HSFET no load
RDS_HI High Side MOSFET On Resistance VBTST –VSW = 4.5 V 25 45 mΩ
RDS_LO Low Side MOSFET On Resistance 60 110 mΩ
VBTST –VSW when low side refresh pulse is 3
requested, VAVCC=4.5V
Bootstrap Refresh Comparator Threshold
VBTST_REFRESH V
Voltage VBTST –VSW when low side refresh pulse is 4
requested, VAVCC>6V
INTERNAL SOFT START (8 steps to regulation current ICHG)
SS_STEP Soft start steps 8 step
TSS_STEP Soft start step time 1.6 3 ms
CHARGER SECTION POWER-UP SEQUENCING
Delay from ISET above 120mV to start
tCE_DELAY 1.5 s
charging battery
INTEGRATED BTST DIODE
VFForward Bias Voltage IF=120mA at 25°C 0.85 V
VRReverse breakdown voltage IR=2uA at 25°C 20 V
LOGIC IO PIN CHARACTERISTICS
VOUT_LO STAT Output Low Saturation Voltage Sink Current = 5 mA 0.5 V
(5) Specified by design
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20 ms/div
AVCC
10V/div
VREF
2V/div
ACDRV
5V/div
STAT
10V/div
400 ms/div
ISET
500mV/div
REGN
5V/div
STAT
10V/div
IL
1A/div
4 ms/div
PH
5V/div
IOUT
1A/div
2 s/divm
ISET
500mV/div
PH
5V/div
IL
2A/div
bq24171
SLUSAF2A –FEBRUARY 2011–REVISED MAY 2011
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TYPICAL CHARACTERISTICS
Table 1. Table of Graphs(1)
FIGURE DESCRIPTION
Figure 3 AVCC, VREF, ACDRV and STAT Power Up (ISET=0)
Figure 4 Charge Enable by ISET
Figure 5 Current Soft Start
Figure 6 Charge Disable by ISET
Figure 7 Continuous Conduction Mode Switching
Figure 8 Discontinuous Conduction Mode Switching
Figure 9 BATFET to ACFET Transition during Power Up
Figure 10 System Load Transient (Input Current DPM)
Figure 11 Battery Insertion and Removal
Figure 12 Battery to Ground Short Protection
Figure 13 Battery to Ground Short Transition
Figure 14 Efficiency vs Output Current (VIN=15V)
Figure 15 Efficiency vs Output Current (VOUT=3.8V)
(1) All waveforms and data are measured on HPA610 and HPA706 EVMs.
Figure 3. Power Up (ISET = 0) Figure 4. Charge Enable by ISET
Figure 5. Current Soft Start Figure 6. Charge Disable by ISET
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200 ns/div
PH
5V/div
IL
1A/div
200 ns/div
PH
5V/div
IL
1A/div
10 ms/div
AVCC
10V/div
ACDRV
10V/div
VSYS
10V/div
BATDRV
10V/div
200 s/divm
IIN
1A/div
ISYS
2A/div
IOUT
1A/div
2 ms/div
SRN
5V/div
PH
10V/div
IL
1A/div
400 ms/div
SRN
5V/div
PH
10V/div
IL
1A/div
bq24171
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SLUSAF2A –FEBRUARY 2011–REVISED MAY 2011
Figure 7. Continuous Conduction Mode Switching Figure 8. Discontinuous Conduction Mode Switching
Figure 9. BATFET to ACFET Transition During Powerup Figure 10. System Load Transient (Input current DPM)
Figure 11. Battery Insertion and Removal Figure 12. Battery to Ground Short Protection
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4 s/divm
SRN
5V/div
PH
10V/div
IL
1A/div
80
82
88
90
96
0 0.5 2.0 3.0 3.5
Charge Current - A
Efficiency - %
84
86
92
1.0 1.5 2.5 4.0
94
VIN 15V 3 cell
VIN 15V 2 cell
80
82
88
90
94
0 0.5 2.0 3.0 3.5
Charge Current - A
Efficiency - %
84
86
92
1.0 1.5 2.5 4.0
VIN 5V BAT 3.8V
VIN 9V BAT 3.8V
bq24171
SLUSAF2A –FEBRUARY 2011–REVISED MAY 2011
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Figure 13. Battery to Ground Short Transition
Figure 14. Efficiency vs Output Current (VIN = 15V) Figure 15. Efficiency vs Output Current (VOUT = 3.8V)
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FUNCTIONAL BLOCK DIAGRAM
Figure 16. Functional Block Diagram
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VLOWV
VRECH
10% ICHRG
Precharge
Current
Regulation
Phase
Fastcharge Current
Regulation Phase
Fastcharge Voltage
Regulation Phase Termination
Charge
Voltage
Charge
Current
Regulation Voltage
ICHRG
Fast Charge Safety Timer
Precharge
Timer
R2
V = 2.1 V 1+
BAT R1
é ù
´ê ú
ë û
ISET
CHARGE
SR
V
I = 20 R´
bq24171
SLUSAF2A –FEBRUARY 2011–REVISED MAY 2011
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DETAILED DESCRIPTION
Figure 17. Typical Charging Profile
BATTERY VOLTAGE REGULATION
The bq24171 offers a high accuracy voltage regulator on for the charging voltage.
The bq24171 uses external resistor divider for voltage feedback and regulate to internal 2.1V voltage reference
on FB pin. Use the following equation for the regulation voltage for bq24171:
(1)
where R2 is connected from FB to the battery and R1 is connected from FB to GND.
BATTERY CURRENT REGULATION
The ISET input sets the maximum charging current. Battery current is sensed by current sensing resistor RSR
connected between SRP and SRN. The full-scale differential voltage between SRP and SRN is 40mV max. The
equation for charge current is:
(2)
The valid input voltage range of ISET is up to 0.8V. With 10mΩsense resistor, the maximum output current is
4A. With 20mΩsense resistor, the maximum output current is 2A.
The charger is disabled when ISET pin voltage is below 40mV and is enabled when ISET pin voltage is above
120mV. For 10mΩcurrent sensing resistor, the minimum fast charge current must be higher than 600mA.
Under high ambient temperature, the charge current will fold back to keep IC temperature not exceeding 120°C.
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ISET
PRECHARGE
SR
V
I = 200 R´
ACSET
DPM
AC
V
I = 20 R´
ISET
TERM
SR
V
I = 200 R´
TTC TTC TTC
t = C K´
bq24171
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SLUSAF2A –FEBRUARY 2011–REVISED MAY 2011
BATTERY PRECHARGE CURRENT REGULATION
On Power-up, if the battery voltage is below the VLOWV threshold, the bq24171 applies the pre-charge current to
the battery. This pre-charge feature is intended to revive deeply discharged cells. If the VLOWV threshold is not
reached within 30 minutes of initiating pre-charge, the charger turns off and a FAULT is indicated on the status
pins.
For bq24171, the pre-charge current is set as 10% of the fast charge rate set by ISET voltage.
(3)
INPUT CURRENT REGULATION
The total input current from an AC adapter or other DC sources is a function of the system supply current and
the battery charging current. System current normally fluctuated as portions of the systems are powered up or
down. Without Dynamic Power Management (DPM), the source must be able to supply the maximum system
current and the maximum available charger input current simultaneously. By using DPM, the input current
regulator reduces the charging current when the summation of system power and charge power exceeds the
maximum input power. Therefore, the current capability of the AC adapter can be lowered, reducing system cost.
Input current is set by the voltage on ACSET pin using the following equation:
(4)
The ACP and ACN pins are used to sense across RAC with default value of 10mΩ. However, resistors of other
values can also be used. A larger sense resistor will give a larger sense voltage and higher regulation accuracy,
at the expense of higher conduction loss.
CHARGE TERMINATION, RECHARGE, AND SAFETY TIMERS
The charger monitors the charging current during the voltage regulation phase. Termination is detected when the
FB voltage is higher than recharge threshold and the charge current is less than the termination current
threshold, as calculated below:
(5)
where VISET is the voltage on the ISET pin and RSR is the sense resistor. There is a 25ms deglitch time during
transition between fast-charge and pre-charge.
As a safety backup, the charger also provides an internal fixed 30 minutes pre-charge safety timer and a
programmable fast charge timer. The fast charge time is programmed by the capacitor connected between the
TTC pin and AGND, and is given by the formula:
(6)
Where CTTC is the capacitor connected to TTC and KTTC is the constant multiplier.
A new charge cycle is initiated when one of the following conditions occurs:
•The battery voltage falls below the recharge threshold
•A power-on-reset (POR) event occurs
•ISET pin toggled below 40mV (disable charge) and above 120mV (enable charge)
Pull TTC pin to AGND to disable both termination and fast charge safety timer (reset timer). Pull TTC pin to
VREF to disable the safety timer, but allow charge termination.
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POWER UP
The charge uses a SLEEP comparator to determine the source of power on the AVCC pin, since AVCC can be
supplied either from the battery or the adapter. With the adapter source present, if the AVCC voltage is greater
than the SRN voltage, the charger exits SLEEP mode. If all conditions are met for charging, the charger then
starts charge the battery (see the Enabling and Disabling Charging section). If SRN voltage is greater than
AVCC, the charger enters low quiescent current SLEEP mode to minimize current drain from the battery. During
SLEEP mode, the VREF output turns off and the STAT pin goes to high impedance.
If AVCC is below the UVLO threshold, the device is disabled.
INPUT UNDER-VOLTAGE LOCK-OUT (UVLO)
The system must have a minimum AVCC voltage to allow proper operation. This AVCC voltage could come from
either input adapter or battery, since a conduction path exists from the battery to AVCC through the high side
NMOS body diode. When AVCC is below the UVLO threshold, all circuits on the IC are disabled.
INPUT OVER-VOLTAGE/UNDER-VOLTAGE PROTECTION
ACOV provides protection to prevent system damage due to high input voltage. In bq24171, once the voltage on
OVPSET is above the 1.6V ACOV threshold or below the 0.5V ACUV threshold, charge is disabled and input
MOSFETs turn off. The bq24171 provides flexibility to set the input qualification threshold.
ENABLE AND DISABLE CHARGING
The following conditions have to be valid before charging is enabled:
•ISET pin above 120mV
•Device is not in Under-Voltage-Lock-Out (UVLO) mode (i.e. VAVCC >VUVLO)
•Device is not in SLEEP mode (i.e. VAVCC >VSRN)
•OVPSET voltage is between 0.5V and 1.6V to qualify the adapter
•1.5s delay is complete after initial power-up
•REGN LDO and VREF LDO voltages are at correct levels
•Thermal Shut down (TSHUT) is not valid
•TS fault is not detected
•ACFET turns on (See System Power Selector for details)
One of the following conditions stops on-going charging:
•ISET pin voltage is below 40mV
•Device is in UVLO mode
•Adapter is removed, causing the device to enter SLEEP mode
•OVPSET voltage indicates the adapter is not valid
•REGN or VREF LDO voltage is overloaded
•TSHUT temperature threshold is reached
•TS voltage goes out of range indicating the battery temperature is too hot or too cold
•ACFET turns off
•TTC timer expires or pre-charge timer expires
SYSTEM POWER SELECTOR
The IC automatically switches adapter or battery power to the system load. The battery is connected to the
system by default during power up or during SLEEP mode. When the adapter plugs in and the voltage is above
the battery voltage, the IC exits SLEEP mode. The battery is disconnected from the system and the adapter is
connected to the system after exiting SLEEP. An automatic break-before-make logic prevents shoot-through
currents when the selectors switch.
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The ACDRV is used to drive a pair of back-to-back n-channel power MOSFETs between adapter and ACP with
sources connected together to CMSRC. The n-channel FET with the drain connected to the ACP (Q2, RBFET)
provides reverse battery discharge protection, and minimizes system power dissipation with its low-RDSON. The
other n-channel FET with drain connected to adapter input (Q1, ACFET) separates battery from adapter, and
provides a limited dI/dt when connecting the adapter to the system by controlling the FET turn-on time. The
/BATDRV controls a p-channel power MOSFET (Q3, BATFET) placed between battery and system with drain
connected to battery.
Before the adapter is detected, the ACDRV is pulled to CMSRC to keep ACFET off, disconnecting the adapter
from system. /BATDRV stays at ACN-6V (clamp to ground) to connect battery to system if all the following
conditions are valid:
•VAVCC >VUVLO (battery supplies AVCC)
•VACN <VSRN + 200 mV
After the device comes out of SLEEP mode, the system begins to switch from battery to adapter. The AVCC
voltage has to be 300mV above SRN to enable the transition. The break-before-make logic keeps both ACFET
and BATFET off for 10us before ACFET turns on. This prevents shoot-through current or any large discharging
current from going into the battery. The /BATDRV is pulled up to ACN and the ACDRV pin is set to CMSRC + 6V
by an internal charge pump to turn on n-channel ACFET, connecting the adapter to the system if all the following
conditions are valid:
•VACUV <VOVPSET <VACOV
•VAVCC >VSRN + 300 mV
When the adapter is removed, the IC turns off ACFET and enters SLEEP mode.
BATFET keeps off until the system drops close to SRN. The BATDRV pin is driven to ACN - 6V by an internal
regulator to turn on p-channel BATFET, connecting the battery to the system.
Asymmetrical gate drive provides fast turn-off and slow turn-on of the ACFET and BATFET to help the
break-before-make logic and to allow a soft-start at turn–on of both MOSFETs. The delay time can be further
increased, by putting a capacitor from gate to source of the power MOSFETs.
CONVERTER OPERATION
The bq24171 employs a 1.6MHz constant-frequency step-down switching regulator. The fixed frequency
oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage,
charge current, and temperature, simplifying output filter design and keeping it out of the audible noise region.
A type III compensation network allows using ceramic capacitors at the output of the converter. An internal
saw-tooth ramp is compared to the internal error control signal to vary the duty-cycle of the converter. The ramp
height is proportional to the AVCC voltage to cancel out any loop gain variation due to a change in input voltage,
and simplifies the loop compensation. Internal gate drive logic allows achieving 97% duty-cycle before pulse
skipping starts.
AUTOMATIC INTERNAL SOFT-START CHARGER CURRENT
The charger automatically soft-starts the charger regulation current every time the charger goes into fast-charge
to ensure there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists
of stepping-up the charge regulation current into 8 evenly divided steps up to the programmed charge current.
Each step lasts around 1.6ms, for a typical rise time of 12.8ms. No external components are needed for this
function.
CHARGE OVER-CURRENT PROTECTION
The charger monitors top side MOSFET current by high side sense FET. When peak current exceeds MOSFET
limit, it will turn off the top side MOSFET and keep it off until the next cycle. The charger has a secondary
cycle-to-cycle over-current protection. It monitors the charge current, and prevents the current from exceeding
160% of the programmed charge current. The high-side gate drive turns off when either over-current condition is
detected, and automatically resumes when the current falls below the over-current threshold.
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POR or RECHARGE
Enable 125mA charge
current, start 0.5s timer
VFB > VRECH No
Battery Present,
Begin Charge
0.5s timer
expired
Yes
No
Yes
Disable 125mA
charge current
Apply 8mA discharge
current, start 1s timer
VFB < VBATOWV No
Battery Present,
Begin Charge
1s timer
expired
Yes
No
Yes
Disable 8mA
discharge current
Battery Absent
bq24171
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CHARGE UNDER-CURRENT PROTECTION
After the recharge, if the SRP-SRN voltage decreases below 5mV, the low side FET will be turned off for the rest
of the switching cycle. During discontinuous conduction mode (DCM), the low side FET will only turn on for a
short period of time when the bootstrap capacitor voltage drops below 4V to provide refresh charge for the
capacitor. This is important to prevent negative inductor current from causing any boost effect in which the input
voltage increases as power is transferred from the battery to the input capacitors. This can lead to an
over-voltage on the AVCC node and potentially cause damage to the system.
BATTERY DETECTION
For applications with removable battery packs, IC provides a battery absent detection scheme to reliably detect
insertion or removal of battery packs. The battery detection routine runs on power up, or if battery voltage falls
below recharge threshold voltage due to removing a battery or discharging a battery.
Figure 18. Battery Detection Flowchart
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VBAT_RE
Battery
Absent
VRECH
VLOW
Battery
Absent
Battery
Present
DISCH DISCH
MAX
2
1
I t
C = R
(2.05 V - 1.45 V) 1+ R
´
é ù
´ê ú
ë û
MAX
8 mA 1 sec
C = = 2.2 mF
500 k
0.6 V 1+
100 k
´
W
é ù
´ê ú
W
ë û
bq24171
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SLUSAF2A –FEBRUARY 2011–REVISED MAY 2011
Once the device has powered up, a 8-mA discharge current is applied to the SRN terminal. If the battery voltage
falls below the LOWV threshold within 1 second, the discharge source is turned off, and the charger is turned on
at low charge current (125mA). If the battery voltage gets up above the recharge threshold within 500ms, there is
no battery present and the cycle restarts. If either the 500ms or 1 second timer time out before the respective
thresholds are hit, a battery is detected and a charge cycle is initiated.
Figure 19. Battery Detect Timing Diagram
Care must be taken that the total output capacitance at the battery node is not so large that the discharge current
source cannot pull the voltage below the LOWV threshold during the 1 second discharge time. The maximum
output capacitances can be calculated according to the following equation:
(7)
Where CMAX is the maximum output capacitance, IDISCH is the discharge current, tDISCH is the discharge time, and
R2and R1are the voltage feedback resistors from the battery to the FB pin.
Example
For a 3-cell Li+ charger, with R2= 500kΩ, R1= 100kΩ(giving 12.6V for voltage regulation), IDISCH = 8mA, tDISCH
= 1 second.
(8)
Based on these calculations, no more than 2200 µF should be allowed on the battery node for proper operation
of the battery detection circuit.
BATTERY SHORT PROTECTION
When SRN pin voltage is lower than 2V it is considered as battery short condition during charging period. The
charger will shut down immediately for 1ms, then soft start back to the charging current the same as precharge
current. This prevents high current may build in output inductor and cause inductor saturation when battery
terminal is shorted during charging. The converter works in non-synchronous mode during battery short.
BATTERY OVER-VOLTAGE PROTECTION
The converter will not allow the high-side FET to turn-on until the battery voltage goes below 102% of the
regulation voltage. This allows one-cycle response to an over-voltage condition –such as occurs when the load
is removed or the battery is disconnected. A total 6mA current sink from SRP/SRN to AGND allows discharging
the stored output inductor energy that is transferred to the output capacitors. If battery over-voltage condition
lasts for more than 30ms, charge is disabled.
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0°C
(T1)
10 °C
(T2)
45 °C
(T3)
50°C
(T4)
60 °C
(T5)
Charge
Suspended
ICharge/2
ICharge
Charge
Suspended
Charge Current
Temperature
VFB=2.05 V
VFB=2.025 V
Charge Voltage
VFB=2.1 V
Temperature
VREF COLD HOT
VREF VREF
HOT COLD
1 1
V RTH RTH
VT1 VT5
RT2 =
V V
RTH 1 RTH 1
VT5 VT1
æ ö
´ ´ ´ -
ç ÷
è ø
æ ö æ ö
´ - - ´ -
ç ÷ ç ÷
è ø è ø
VREF
COLD
V1
VT1
RT1 = 1 1
+
RT2 RTH
-
bq24171
SLUSAF2A –FEBRUARY 2011–REVISED MAY 2011
www.ti.com
TEMPERATURE QUALIFICATION AND JEITA GUIDELINE
The controller continuously monitors battery temperature by measuring the voltage between the TS pin and
GND. A negative temperature coefficient thermistor (NTC) and an external voltage divider typically develop this
voltage. The controller compares this voltage against its internal thresholds to determine if charging is allowed.
To initiate a charge cycle, the voltage on TS pin must be within the VT1 to VT5 thresholds. If VTS is outside of this
range, the controller suspends charge and waits until the battery temperature is within the VT1 to VT5 range.
During the charge cycle the battery temperature must be within the VT1 to VT5 thresholds. If battery temperature
is outside of this range, the controller suspends charge and waits until the battery temperature is within the VT1 to
VT5 range. The controller suspends charge by turning off the PWM charge FETs. If VTS is within the range of VT1
and VT2, charge voltage regulation on FB pin is 2.1 V and the charge current is reduced to ICHARGE/2 (To avoid
early termination during VT1 and VT2 range, fast charge current need to be bigger than 2 times of termination
current); if VTS is within the range of VT2 and VT3, the charge voltage regulation on FB pin is 2.1 V; if VTS is within
VT3 and VT4, the charge voltage regulation on FB pin is reduced back to 2.05 V; and if VTS is within VT4 and VT5,
the charge voltage regulation on FB pin is further reduced to 2.025 V. Figure 20 below summarizes the
operation. See the Li-ion battery-charger solutions for JEITA compliance, SLYT365
Figure 20. TS Pin, Thermistor Sense Thresholds
Assuming a 103AT NTC thermistor on the battery pack as shown in Figure 21, the values of RT1 and RT2 can
be determined by using Equation 9 and Equation 10:
(9)
(10)
22 Submit Documentation Feedback Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s): bq24171
VREF
TS
RT2
RT1
RTH
103AT
bq24171
o
1
=
2 LCp
f
bq24171
www.ti.com
SLUSAF2A –FEBRUARY 2011–REVISED MAY 2011
Figure 21. TS Resistor Network
For example, 103AT NTC thermistors are used to monitor the battery pack temperature. Select T1 = 0ºC for
COLD and T5 = 60ºC for HOT, then we get RT2 = 6.8kΩand RT1 = 2.2kΩas in the design tool. A small RC filter
is suggested to use for system-level ESD protection.
MOSFET SHORT CIRCUIT AND INDUCTOR SHORT CIRCUIT PROTECTION
The IC has a short circuit protection feature. Its cycle-by-cycle current monitoring feature is achieved through
monitoring the voltage drop across Rdson of the MOSFETs. The charger will be latched off, but the ACFET keep
on to power the system. The only way to reset the charger from latch-off status is remove adapter then plug
adapter in again. Meanwhile, STAT is blinking to report the fault condition.
THERMAL REGULATION AND SHUTDOWN PROTECTION
The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the
ambient, to keep junctions temperatures low. The internal thermal regulation loop will fold back the charge
current to keep the junction temperature from exceeding 120°C. As added level of protection, the charger
converter turns off and self-protects whenever the junction temperature exceeds the TSHUT threshold of 150°C.
The charger stays off until the junction temperature falls below 130°C.
TIMER FAULT RECOVERY
The IC provides a recovery method to deal with timer fault conditions. The following summarizes this method:
Condition 1: The battery voltage is above the recharge threshold and a timeout fault occurs.
Recovery Method: The timer fault will clear when the battery voltage falls below the recharge threshold, and
battery detection will begin. A POR or taking ISET below 40mV will also clear the fault.
Condition 2: The battery voltage is below the recharge threshold and a timeout fault occurs.
Recovery Method: Under this scenario, the IC applies the fault current to the battery. This small current is used
to detect a battery removal condition and remains on as long as the battery voltage stays below the recharge
threshold. If the battery voltage goes above the recharge threshold, the IC disabled the fault current and
executes the recovery method described in Condition 1. A POR or taking ISET below 40mV will also clear the
fault.
INDUCTOR, CAPACITOR, AND SENSE RESISTOR SELECTION GUIDELINES
The IC provides internal loop compensation. With this scheme, the best stability occurs when the LC resonant
frequency, fo, is approximately 15kHz –25kHz for the IC.
(11)
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): bq24171
bq24171
SLUSAF2A –FEBRUARY 2011–REVISED MAY 2011
www.ti.com
Table 2 provides a summary of typical LC components for various charge currents.
Table 2. Typical Values as a Function of Charge Current
CHARGE CURRENT 1A 2A 3A 4A
Output inductor L 6.8 µH 3.3 µH 3.3 µH 2.2 µH
Output capacitor C 10 µF 20 µF 20 µF 30 µF
CHARGE STATUS OUTPUTS
The open-drain STAT outputs indicate various charger operations as listed in Table 3. These status pins can be
used to drive LEDs or communicate with the host processor. Note that OFF indicates that the open-drain
transistor is turned off.
Table 3. STAT Pin Definition
CHARGE STATE STAT
Charge in progress (including recharging) ON
Charge complete, Sleep mode, Charge disabled OFF
Charge suspend, Input over-voltage, Battery over-voltage, timer fault, , battery absent BLINK
24 Submit Documentation Feedback Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s): bq24171
SAT CHG RIPPLE
I I +(1/2)I³
IN
RIPPLE
V D (1 D)
I = fs × L
´ ´ -
CIN CHG
I I D (1 D)= ´ ´ -
RIPPLE
COUT RIPPLE
I
I 0.29 I
2 3
= » ´
´
OUT OUT
O2IN
V V
V 1 V
8LCfs
æ ö
D = -
ç ÷
ç ÷
è ø
bq24171
www.ti.com
SLUSAF2A –FEBRUARY 2011–REVISED MAY 2011
APPLICATION INFORMATION
INDUCTOR SELECTION
The bq24171 has a 1600-kHz switching frequency to allow the use of small inductor and capacitor values.
Inductor saturation current should be higher than the charging current (ICHG) plus half the ripple current (IRIPPLE):
(12)
Inductor ripple current depends on input voltage (VIN), duty cycle (D = VOUT/VIN), switching frequency (fs), and
inductance (L):
(13)
The maximum inductor ripple current happens with D = 0.5 or close to 0.5. Usually inductor ripple is designed in
the range of 20% to 40% of the maximum charging current as a trade-off between inductor size and efficiency for
a practical design.
INPUT CAPACITOR
The input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst
case RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate
at 50% duty cycle, then the worst case capacitor RMS current ICIN occurs where the duty cycle is closest to 50%
and can be estimated by the following equation:
(14)
A low ESR ceramic capacitor such as X7R or X5R is preferred for the input decoupling capacitor and should be
placed as close as possible to the drain of the high-side MOSFET and source of the low-side MOSFET. The
voltage rating of the capacitor must be higher than the normal input voltage level. A 25V rating or higher
capacitor is preferred for a 15V input voltage. A 20μF capacitance is suggested for a typical 3A to 4A charging
current.
OUTPUT CAPACITOR
The output capacitor also should have enough ripple current rating to absorb output switching ripple current. The
output capacitor RMS current ICOUT is given as:
(15)
The output capacitor voltage ripple can be calculated as follows:
(16)
At certain input/output voltages and switching frequencies, the voltage ripple can be reduced by increasing the
output filter LC.
The bq24171 has an internal loop compensator. To achieve good loop stability, the resonant frequency of the
output inductor and output capacitor should be designed between 15 kHz and 25 kHz. The preferred ceramic
capacitor has a 25V or higher rating, X7R or X5R.
INPUT FILTER DESIGN
During adapter hot plug-in, the parasitic inductance and the input capacitor from the adapter cable form a second
order system. The voltage spike at the AVCC pin may be beyond the IC maximum voltage rating and damage
the IC. The input filter must be carefully designed and tested to prevent an over-voltage event on the AVCC pin.
There are several methods to damping or limiting the over-voltage spike during adapter hot plug-in. An
electrolytic capacitor with high ESR as an input capacitor can damp the over-voltage spike well below the IC
maximum pin voltage rating. A high current capability TVS Zener diode can also limit the over-voltage level to an
IC safe level. However, these two solutions may not be lowest cost or smallest size.
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): bq24171
R1(2010)
2W
C1
2.2 Fm
D1
C2
0.1 - 1 Fm
R2(1206)
4.7 - 30 W
Adapter
Connector AVCC pin
CIN
2. ?
CMSRC
RIN
2
R11
4.02k
R12
4.02k
ACDRV
Q1 Q2
ADAPTER
CIN
2.2
?
RIN
2
Q1 Q2
CGS
CGD
SYS
40?
C
PVCC
SYS
RSNS
RGS
499k
C4 1m
bq24171
SLUSAF2A –FEBRUARY 2011–REVISED MAY 2011
www.ti.com
A cost effective and small size solution is shown in Figure 22. R1 and C1 are composed of a damping RC
network to damp the hot plug-in oscillation. As a result, the over-voltage spike is limited to a safe level. D1 is
used for reverse voltage protection for the AVCC pin. C2 is the AVCC pin decoupling capacitor and it should be
placed as close as possible to the AVCC pin. R2 and C2 form a damping RC network to further protect the IC
from high dv/dt and high voltage spikes. The C2 value should be less than the C1 value so R1 can dominant the
equivalent ESR value to provide enough damping effect for hot plug-in. R1 and R2 must be sized to handle
in-rush current power loss according to the resistor manufacturer’s datasheet. Verify the filter component values
with a real application and make any minor adjustments needed to fit in the real application circuit.
If the input is 5V (USB host or USB adapter), diode D1 can be omitted. R2 must be 5Ωor higher to limit the
current if the input is reversely inserted.
Figure 22. Input Filter
INPUT ACFET AND RBFET SELECTION
N-type MOSFETs are used as input ACFET(Q1) and RBFET(Q2) for better cost effective and small size solution,
as shown in Figure 22. Normally, there are around 50uF capacitor totally connected at PVCC node --- 10µF
capacitor for buck converter of bq24171 and 40µF capacitor for system side. There is a surge current during Q1
turn-on period when a valid adapter is inserted. Decreasing the turn-on speed of Q1 can limit this surge current
in desirable range by selecting a MOSFET with relative bigger CGD and/or CGS. At the case Q1 turn on too fast,
we need add external CGD and/or CGS. For example, 4.7nF CGD and 47nF CGS are adopted on EVM while using
NexFET CSD17313 as Q1.
Figure 23. Input ACFET and RBFET
PCB LAYOUT
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize the high frequency current path loop (see Figure 24) is important to prevent electrical
and magnetic field radiation and high frequency resonant problems. The following is a PCB layout priority list for
proper layout. Layout of the PCB according to this specific order is essential.
1. Place input capacitor as close as possible to the PVCC supply and ground connections and use the shortest
copper trace connection. These parts should be placed on the same layer of the PCB instead of on different
layers and using vias to make this connection.
2. Place the inductor input terminal as close as possible to the SW terminal. Minimize the copper area of this
trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging
current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance from this
area to any other trace or plane.
26 Submit Documentation Feedback Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s): bq24171
High
Frequency
Current
Path
L1 R1
C3
C1 C2
PGND
SW VBAT
BAT
VIN
Current Direction
To SRP and SRN pin
RSNS
Current Sensing Direction
bq24171
www.ti.com
SLUSAF2A –FEBRUARY 2011–REVISED MAY 2011
3. The charging current sensing resistor should be placed right next to the inductor output. Route the sense
leads connected across the sensing resistor back to the IC in the same layer, close to each other (minimize
loop area) and do not route the sense leads through a high-current path (see Figure 25 for Kelvin connection
for best current accuracy). Place decoupling capacitor on these traces next to the IC.
4. Place output capacitor next to the sensing resistor output and ground.
5. Output capacitor ground connections need to be tied to the same copper that connects to the input capacitor
ground before connecting to system ground.
6. Route analog ground separately from power ground and use a single ground connection to tie charger power
ground to charger analog ground. Just beneath the IC use analog ground copper pour but avoid power pins
to reduce inductive and capacitive noise coupling. Use the thermal pad as a single ground connection point
to connect analog ground and power ground together, or use a 0-Ωresistor to tie analog ground to power
ground. A star-connection under the thermal pad is highly recommended.
7. It is critical that the exposed thermal pad on the backside of the IC package be soldered to the PCB ground.
Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the
other layers.
8. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible.
9. The number and physical size of the vias should be enough for a given current path.
Figure 24. High Frequency Current Path
Figure 25. Sensing Resistor PCB Layout
Copyright ©2011, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): bq24171
bq24171
SLUSAF2A –FEBRUARY 2011–REVISED MAY 2011
www.ti.com
REVISION HISTORY
Note: Page numbers of current version may differ from previous versions.
Changes from Original (February 2011) to Revision A Page
•Changed publication to Rev A, May 2011 ............................................................................................................................ 1
•Changed the 4th FEATURES bullet from "4.5V to 17V Input Operating Voltage"to "30V Input Rating with Adjustable
Over-Voltage Protection"and sub-bullet "4.5V to 17V Input Operating Voltage"................................................................. 1
•Added esds note to top of second page; added "DESCRIPTION (Continued)"title on second page; and new
paragraph on page 2 (beginning "The bq24171 charges battery from DC source as high as 17V.") .................................. 2
•Added connection between CMSRC and ACP in Figure 2 Typical Application schematic. ................................................. 5
•Changed ABS MAX table first-row descriptors from "PVCC, AVCC, ACN, CMSRC, STAT"to "AVCC, ACP, ACN,
ACDRV, CMSRC, STAT"and second-row descriptor from "ACDRV, BTST"to "PVCC"; changed PVCC max voltage
from 30V to 20V .................................................................................................................................................................... 6
•Changed hyperlink to point to Design Tool sluc244a ......................................................................................................... 23
•Added new paragraph under INPUT FILTER DESIGN section (beginning..."If the input is 5V....") ................................... 26
28 Submit Documentation Feedback Copyright ©2011, Texas Instruments Incorporated
Product Folder Link(s): bq24171
PACKAGE OPTION ADDENDUM
www.ti.com 19-Apr-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
BQ24171RGYR ACTIVE VQFN RGY 24 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
BQ24171RGYT ACTIVE VQFN RGY 24 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
BQ24171RGYR VQFN RGY 24 3000 330.0 12.4 3.8 5.8 1.2 8.0 12.0 Q1
BQ24171RGYT VQFN RGY 24 250 180.0 12.4 3.8 5.8 1.2 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ24171RGYR VQFN RGY 24 3000 367.0 367.0 35.0
BQ24171RGYT VQFN RGY 24 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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