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IS66WVE4M16ALL
Rev.A | May 2011 www.issi.com -SRAM@issi.com
Overview
The IS66WVE4M16ALL is an integrated memory device containi ng 64Mbit Pseudo Static Random Acce ss
Memory using a self-refresh DRAM array orga nized as 4M words by 16 bits. The device includes several
power saving modes : Partial Array Refresh mode where data is retained in a portion of the array and
Deep Power Down mode. Both these modes reduce standby current drain. The die has separate power
rails, VDDQ and VSSQ for the I/O to be run from a separate power supply from the device core.
Asynchronous and page mode interface
Dual voltage rails for optional performance
VDD 1.8V, VDDQ 1.8V
Page mode read access
Interpage Read access : 70ns
Intrapage Read access : 20ns
Low Power Consumption
Asynchronous Operation < 30 mA
Intrapage Read < 18mA
Standby < 180 uA (max.)
Deep power-down (DPD) < 3uA (Typ)
Low Power F eatu re
Temperature Controlled Refresh
Partial Array Refresh
Deep power-down (DPD) mode
Operating temperature Range
Industrial -40°C~85°C
Package:
48-ball TFBGA, 48-pin TSOP-I
1.8V Core Async/Page PSRAM
Features
Copyright © 2011 Integrated S i l i con Solution, Inc. All rights reserved. ISS I reserves the right t o make changes to this specific ation and it s
products at any tim e without noti ce. ISSI assum es no liability arising out of the application or use of any i nformat i on, products or services
described herein. Custom ers are advised to obtain the latest version of this device specif ic ation before relying on any publi shed inf orm ati on
and before pl acing orders f or produc ts.
Integrated Sili con Solution, Inc. does not recommend the use of any of its products in l i f e support applic at i ons where the f ailure or
malfunction of the product can reasonably be expected to cause failure of the life support syst em or to signifi cantly affect its safety or
effectiveness. Products are not authorized for use i n such applicat i ons unless I ntegrated S i l i con Solution, I nc. receives written assurance t o
its satisfactio n, that:
a.) the risk of injury or damage has been minimized;
b.) the user ass ume all such risk s; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Notes :
1. The 48-pin TSOP -I package option is not yet available. Please contact SRAM marketing at sram@issi.com for
additional information.