FEATURES FUNCTIONAL BLOCK DIAGRAMS 16-bit resolution 11.8 nV/Hz noise spectral density 1 s settling time 1.1 nV-sec glitch energy 0.05 ppm/C temperature drift 5 kV HBM ESD classification 0.375 mW power consumption at 3 V 2.7 V to 5.5 V single-supply operation Hardware CS and LDAC functions 50 MHz SPI-/QSPI-/MICROWIRE-/DSP-compatible interface Power-on reset clears DAC output to zero scale Available in 3 mm x 3 mm, 8-/10-lead LFCSP and 10-lead MSOP VDD AD5541A 16-BIT DAC REF VOUT AGND VLOGIC 16-BIT DAC LATCH CS CONTROL LOGIC DIN SERIAL INPUT REGISTER SCLK 08516-001 LDAC DGND Figure 1. AD5541A APPLICATIONS VDD Automatic test equipment Precision source-measure instruments Data acquisition systems Medical instrumentation Aerospace instrumentation Communications infrastructure equipment Industrial control AD5541A-1 16-BIT DAC REF 16-BIT DAC LATCH CS DIN VOUT CONTROL LOGIC SCLK SERIAL INPUT REGISITER CLR GND 08516-002 Data Sheet 2.7 V to 5.5 V, Serial-Input, Voltage Output, Unbuffered 16-Bit DAC AD5541A Figure 2. AD5541A-1 GENERAL DESCRIPTION The AD5541A is a single, 16-bit, serial input, unbuffered voltage output digital-to-analog converter (DAC) that operates from a single 2.7 V to 5.5 V supply. The DAC output range extends from 0 V to VREF and is guaranteed monotonic, providing 1 LSB INL accuracy at 16 bits without adjustment over the full specified temperature range of -40C to +125C. The AD5541A is available in a 3 mm x 3 mm, 10-lead LFCSP and 10-lead MSOP. The AD5541A-1 is available in a 3 mm x 3 mm, 8-lead LFCSP. Offering unbuffered outputs, the AD5541A achieves a 1 s settling time with low power consumption and low offset errors. Providing low noise performance of 11.8 nV/Hz and low glitch, the AD5541A is suitable for deployment across multiple end systems. Rev. B The AD5541A uses a versatile 3-wire interface that is compatible with 50 MHz SPI, QSPITM, MICROWIRETM, and DSP interface standards. Table 1. Related Devices Part No. AD5040/AD5060 AD5541/AD5542 AD5781/AD5791 AD5024/AD5064 AD5061 AD5542A Description 2.7 V to 5.5 V 14-/16-bit buffed output DACs 2.7 V to 5.5 V 16-bit voltage output DACs 18-/20-bit voltage output DACs 4.5 V to 5.5 V, 12-/16-bit quad channel DACs Single, 16-bit nanoDAC, 4 LSB INL, SOT-23 16-bit, bipolar, voltage output DAC PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 16-bit performance without adjustment. 2.7 V to 5.5 V single operation. Low 11.8 nV/Hz noise spectral density. Low 0.05 ppm/C temperature drift. 3 mm x 3 mm LFCSP and MSOP packaging. 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Technical Support www.analog.com AD5541A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Serial Interface ............................................................................ 14 Applications ....................................................................................... 1 Unipolar Output Operation ...................................................... 15 Functional Block Diagrams ............................................................. 1 Output Amplifier Selection ....................................................... 15 General Description ......................................................................... 1 Force Sense Amplifier Selection ............................................... 16 Product Highlights ........................................................................... 1 Reference and Ground ............................................................... 16 Revision History ............................................................................... 2 Power-On Reset .......................................................................... 16 Specifications..................................................................................... 3 Power Supply and Reference Bypassing .................................. 16 AC Characteristics ........................................................................ 4 Applications Information .............................................................. 17 Timing Characteristics ................................................................ 5 Microprocessor Interfacing ....................................................... 17 Absolute Maximum Ratings ............................................................ 6 AD5541A to ADSP-BF531 Interface ....................................... 17 ESD Caution .................................................................................. 6 AD5541A to SPORT Interface .................................................. 17 Pin Configurations and Function Descriptions ........................... 7 Layout Guidelines....................................................................... 17 Typical Performance Characteristics ............................................. 9 Galvanically Isolated Interface ................................................. 17 Terminology .................................................................................... 13 Decoding Multiple DACs .......................................................... 18 Theory of Operation ...................................................................... 14 Outline Dimensions ....................................................................... 19 Digital-to-Analog Section ......................................................... 14 Ordering Guide .......................................................................... 20 REVISION HISTORY 4/2018--Rev. A to Rev. B Change to Output Noise Parameter, Table 3 ................................. 4 Changes to Figure 25 ...................................................................... 12 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 20 3/2011--Rev. 0 to Rev. A Added 10-Lead LFCSP and 8-Lead LFCSP ..................... Universal Changes to Features, General Description, and Product Highlights Sections and Table 1 ..................................................... 1 Added Figure 2; Renumbered Sequentially .................................. 1 Changes to Logic Inputs Parameter, Table 1 ................................. 3 Changes to Figure 3 ...........................................................................5 Changes to Table 5.............................................................................6 Changes to Table 6.............................................................................7 Added Figure 5 and Figure 6............................................................8 Added Table 7; Renumbered Sequentially .....................................8 Changes to Figure 15...................................................................... 10 Changed VREF to VREF - 1 LSB in Unipolar Output Operation Section .............................................................................................. 15 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 18 7/2010--Revision 0: Initial Version Rev. B | Page 2 of 20 Data Sheet AD5541A SPECIFICATIONS VDD = 2.7 V to 5.5 V, 2.5 V VREF VDD, AGND = DGND = 0 V, -40C < TA < +125C, 1 unless otherwise noted. Table 2. Parameter STATIC PERFORMANCE Resolution Relative Accuracy (INL) Typ Max Unit Test Condition Differential Nonlinearity (DNL) 0.5 0.5 0.5 1.0 2.0 1.0 Bits LSB LSB LSB B grade A grade Guaranteed monotonic Gain Error 0.5 2 3 4 Gain Error Temperature Coefficient Zero-Code Error 0.1 0.3 Zero-Code Temperature Coefficient DC Power Supply Rejection Ratio OUTPUT CHARACTERISTICS 2 Output Voltage Range DAC Output Impedance DAC REFERENCE INPUT 3 Reference Input Range Reference Input Resistance Reference Input Capacitance Min 16 Input Capacitance2 Hysteresis Voltage2 POWER REQUIREMENTS VDD IDD VLOGIC ILOGIC Power Dissipation TA = 25C -40C < TA < +85C -40C < TA < +125C VREF - 1 LSB V k Unipolar operation Tolerance typically 20% VDD V k pF pF Unipolar operation Code 0x0000 Code 0xFFFF 0.7 1.5 3 0.05 1 0 6.25 2.0 9 26 26 LOGIC INPUTS Input Current Input Low Voltage, VINL Input High Voltage, VINH LSB LSB LSB ppm/C LSB LSB LSB ppm/C LSB 1 0.4 0.8 2.4 1.8 1.3 10 0.15 2.7 125 1.8 15 0.625 5.5 150 5.5 24 0.825 For 2.7 V VLOGIC 5.5 V: -40C < TA < +125C. For 1.8 V VLOGIC 2.7 V: -40C < TA < +105C. Guaranteed by design, but not subject to production test. 3 Reference input resistance is code-dependent, minimum at 0x8555. 1 2 Rev. B | Page 3 of 20 A V V V V V pF V V A V A mW TA = 25C -40C < TA < +85C -40C < TA < +125C VDD 10% VLOGIC = 1.8 V to 5.5 V VLOGIC = 2.7 V to 5.5 V VLOGIC = 4.5 V to 5.5 V VLOGIC = 2.7 V to 3.6 V VLOGIC = 1.8 V to 2.7 V All digital inputs at 0 V, VLOGIC, or VDD VIH = VLOGIC or VDD and VIL = GND All digital inputs at 0 V, VLOGIC, or VDD AD5541A Data Sheet AC CHARACTERISTICS VDD = 2.7 V to 5.5 V, 2.5 V VREF VDD, AGND = DGND = 0 V, -40C < TA < +125C, unless otherwise noted. Table 3. Parameter Output Voltage Settling Time Slew Rate Digital-to-Analog Glitch Impulse Reference -3 dB Bandwidth Reference Feedthrough Digital Feedthrough Signal-to-Noise Ratio Spurious Free Dynamic Range Total Harmonic Distortion Output Noise Spectral Density Output Noise Min Typ 1 17 1.1 2.2 1 0.2 92 80 74 Max 11.8 1.25 Unit s V/s nV-sec MHz mV p-p nV-sec dB dB dB nV/Hz V p-p Rev. B | Page 4 of 20 Test Condition To 1/2 LSB of full scale, CL = 10 pF CL = 10 pF, measured from 0% to 63% 1 LSB change around major carry All 1s loaded All 0s loaded, VREF = 1 V p-p at 100 kHz Digitally generated sine wave at 1 kHz DAC code = 0xFFFF, frequency 10 kHz, VREF = 2.5 V 1 V p-p DAC code = 0x0000, frequency = 1 kHz 0.1 Hz to 10 Hz Data Sheet AD5541A TIMING CHARACTERISTICS VDD = 5 V, 2.5 V VREF VDD, VINH = 90% of VLOGIC, VINL = 10% of VLOGIC, AGND = DGND = 0 V, -40C < TA < +105C, unless otherwise noted. Table 4. Parameter 1,2 fSCLK t1 t2 t3 t4 t5 t6 t7 t8 t9 t9 t10 t11 t12 2 Limit at 2.7 V VLOGIC 5.5 V 50 20 10 10 5 5 5 5 10 4 5 20 10 15 Unit MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min Description SCLK cycle frequency SCLK cycle time SCLK high time SCLK low time CS low to SCLK high setup CS high to SCLK high setup SCLK high to CS low hold time SCLK high to CS high hold time Data setup time Data hold time (VINH = 90% of VDD, VINL = 10% of VDD) Data hold time (VINH = 3 V, VINL = 0 V) LDAC pulse width CS high to LDAC low setup CS high time between active periods Guaranteed by design and characterization. Not production tested. All input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VINL + VINH)/2. t1 SCLK t2 t6 t3 CS t5 t7 t4 t12 t8 t9 DIN DB15 t11 t10 LDAC Figure 3. Timing Diagram Rev. B | Page 5 of 20 08516-003 1 Limit at 1.8 VLOGIC 2.7 V 14 70 35 35 5 5 5 10 35 5 5 20 10 15 AD5541A Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 5. Parameter VDD to AGND VLOGIC to DGND Digital Input Voltage to DGND VOUT to AGND AGND to DGND Input Current to Any Pin Except Supplies Operating Temperature Range Industrial (A, B Versions) Storage Temperature Range Maximum Junction Temperature (TJ max) Package Power Dissipation Thermal Impedance, JA LFCSP (CP-10-9) LFCSP (CP-8-11) MSOP (RM-10) Lead Temperature, Soldering Peak Temperature1 ESD2 1 2 Rating -0.3 V to +6 V -0.3 V to +6 V -0.3 V to VDD/VLOGIC + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to +0.3 V 10 mA Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION -40C to +125C -65C to +150C 150C (TJ max - TA)/JA 50C/W 62C/W 135C/W 260C 5 kV As per JEDEC Standard 20. Human body model (HBM) classification. Rev. B | Page 6 of 20 Data Sheet AD5541A PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS AD5541A 9 DGND AGND 3 TOP VIEW (Not to Scale) 8 LDAC REF 4 CS 5 7 DIN 6 SCLK 08516-031 10 VLOGIC VDD 1 VOUT 2 Figure 4. AD5541A 10-Lead MSOP Pin Configuration Table 6. AD5541A Pin Function Descriptions 1 2 3 4 Pin No. Mnemonic VDD VOUT AGND REF 5 6 CS SCLK 7 DIN 8 LDAC 9 10 DGND VLOGIC Description Analog Supply Voltage. Analog Output Voltage from the DAC. Ground Reference Point for Analog Circuitry. Voltage Reference Input for the DAC. Connect to an external 2.5 V reference. The reference can range from 2 V to VDD. Logic Input Signal. The chip select signal is used to frame the serial data input. Clock Input. Data is clocked into the serial input register on the rising edge of SCLK. The duty cycle must be between 40% and 60%. Serial Data Input. This device accepts 16-bit words. Data is clocked into the serial input register on the rising edge of SCLK. LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the serial register data. Digital Ground. Ground reference for digital circuitry. Logic Power Supply. Rev. B | Page 7 of 20 AD5541A Data Sheet SCLK 3 AD5541A AGND 3 TOP VIEW (Not to Scale) 7 VDD TOP VIEW (Not to Scale) 6 VOUT REF 4 5 CLR CS 5 DIN 4 NOTES 1. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SUBSTRATE, GND. 10 VLOGIC VOUT 2 AD5541A-1 9 DGND 8 LDAC 7 DIN 6 SCLK NOTES 1. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SUBSTRATE, GND. 08516-004 CS 2 VDD 1 8 GND Figure 5. AD5541A-1 8-Lead LFCSP Pin Configuration 08516-005 REF 1 Figure 6. AD5541A 10-Lead LFCSP Pin Configuration Table 7. AD5541A-1 and AD5541A Pin Function Descriptions Pin No. 8-Lead LFCSP 10-Lead LFCSP 1 4 Mnemonic REF 2 3 5 6 CS SCLK 4 7 DIN 5 N/A1 CLR 6 N/A1 7 8 N/A1 N/A1 N/A1 2 9 1 N/A1 3 10 8 VOUT DGND VDD GND AGND VLOGIC LDAC EPAD 1 Description Voltage Reference Input for the DAC. Connect to an external 2.5 V reference. The reference can range from 2 V to VDD. Logic Input Signal. The chip select signal is used to frame the serial data input. Clock Input. Data is clocked into the serial input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%. Serial Data Input. This device accepts 16-bit words. Data is clocked into the serial input register on the rising edge of SCLK. Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored. When CLR is activated, the serial input register and the DAC register are cleared to zero scale. Analog Output Voltage from the DAC. Digital Ground. Ground reference for digital circuitry. Analog Supply Voltage. Ground Reference Point for Both Analog and Digital Circuitry. Ground Reference Point for Analog Circuitry. Logic Power Supply. LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the serial input register. Exposed Pad. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, GND. N/A means not applicable. Rev. B | Page 8 of 20 Data Sheet AD5541A TYPICAL PERFORMANCE CHARACTERISTICS 0.50 0.50 DIFFERENTIAL NONLINEARITY (LSB) 0 -0.25 -0.50 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 CODE 0 -0.25 -0.50 08516-006 -0.75 0.25 0 8192 Figure 7. Integral Nonlinearity vs. Code 0.75 0 -0.25 -0.50 -0.75 -40 -20 0 20 40 60 80 TEMPERATURE (C) 100 120 140 0.50 0.25 0 -0.25 -0.50 -60 08516-007 -1.00 -60 VDD = 5V VREF = 2.5V Figure 8. Integral Nonlinearity vs. Temperature -40 -20 0 20 40 60 80 TEMPERATURE (C) 100 120 140 08516-010 DIFFERENTIAL NONLINEARITY (LSB) VDD = 5V VREF = 2.5V INTEGRAL NONLINEARITY (LSB) 16,384 24,576 32,768 40,960 49,152 57,344 65,536 CODE Figure 10. Differential Nonlinearity vs. Code 0.25 Figure 11. Differential Nonlinearity vs. Temperature 0.50 0.75 VDD = 5V TA = 25C VREF = 2.5V TA = 25C 0.25 0.50 LINEARITY ERROR (LSB) DNL 0 -0.25 -0.50 DNL 0.25 0 INL -0.25 INL -0.75 2 3 4 5 SUPPLY VOLTAGE (V) 6 7 -0.50 08516-008 LINEARITY ERROR (LSB) 08516-009 0.25 VDD = 5V VREF = 2.5V 0 Figure 9. Linearity Error vs. Supply Voltage 1 2 3 4 REFERENCE VOLTAGE (V) 5 Figure 12. Linearity Error vs. Reference Voltage Rev. B | Page 9 of 20 6 08516-011 INTEGRAL NONLINEARITY (LSB) VDD = 5V VREF = 2.5V AD5541A Data Sheet 1.5 3 VDD = 5V VREF = 2.5V TA = 25C 1.0 ZERO-CODE ERROR (LSB) 1 0 -1 0.5 0 -0.5 -1.0 -2 -50 0 50 TEMPERATURE (C) 100 150 -1.5 -55 08516-012 -3 -100 Figure 13. Gain Error vs. Temperature 45 TEMPERATURE (C) 95 Figure 16. Zero-Code Error vs. Temperature 200 160 TA = 25C VDD = 5V VREF = 2.5V TA = 25C 140 120 SUPPLY CURRENT (A) SUPPLY CURRENT (A) -5 08516-015 GAIN ERROR (LSB) 2 VDD = 5V VREF = 2.5V TA = 25C 100 80 60 40 150 REFERENCE VOLTAGE VDD = 5V 100 SUPPLY VOLTAGE VREF = 2.5V 50 -5 45 TEMPERATURE (C) 0 08516-013 0 -55 95 0 2 1 3 4 Figure 14. Supply Current vs. Temperature 6 Figure 17. Supply Current vs. Reference Voltage or Supply Voltage 200 200 VDD = 5V VREF = 2.5V TA = 25C 180 REFERENCE CURRENT (A) 160 140 120 100 80 60 40 150 100 50 0 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 DIGITAL INPUT VOLTAGE (V) 1.9 2.0 0 0 Figure 15. Supply Current vs. Digital Input Voltage 10,000 20,000 30,000 40,000 CODE (Decimal) 50,000 60,000 Figure 18. Reference Current vs. Code Rev. B | Page 10 of 20 70,000 08516-017 20 08516-014 SUPPLY CURRENT (A) 5 VOLTAGE (V) 08516-016 20 Data Sheet AD5541A VREF = 2.5V VDD = 5V TA = 25C VREF = 2.5V VDD = 5V TA = 25C 100 * * * * 100 DIN (5V/DIV) * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * VOUT (1V/DIV) 90 VOUT (50mV/DIV) GAIN = -216 1LSB = 8.2mV VOUT (50mV/DIV) 10 10 0% * * * * * * * * * * * * * * * * * * * * * * * * 08516-018 0% 2s/DIV * * * * * * * * * * * * * * * * 08516-021 90 0.5s/DIV Figure 19. Digital Feedthrough Figure 22. Small Signal Settling Time 5 1.236 CS 5 +125C +25C -55C 0 1.234 4 -5 3 -10 HITS VOLTAGE (V) 1.232 1.230 -15 2 1.228 VOUT -20 1 1.226 0 0.5 1.0 0 -30 2.0 1.5 90 08516-032 1.224 -0.5 TIME (ns) Figure 20. Digital-to-Analog Glitch Impulse 100 110 IDD SUPPLY (A) 120 Figure 23. Analog Supply Current Histogram 6 VREF = 2.5V VDD = 5V TA = 25C 2s/DIV 100 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 08516-038 -25 +125C +25C -55C 5 CS (5V/DIV) 4 90 HITS 10pF 50pF 3 100pF 2 200pF 1 10 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * VOUT (0.5V/DIV) Figure 21. Large Signal Settling Time 0 15 16 17 18 ILOGIC AT RAILS (A) 19 Figure 24. Digital Supply Current Histogram Rev. B | Page 11 of 20 08516-039 * * * * 08516-020 0% * * * * OUTPUT NOISE (V rms) AD5541A Data Sheet 1.5 40 1.0 20 0 VOUT (dBm) 0.5 0 -20 -40 -0.5 -60 -1.0 0 20 40 60 TIME (Seconds) 80 100 -100 08516-033 -1.5 0 40 10 35 0 30 30,000 40,000 50,000 FREQUENCY (Hz) 60,000 70,000 VOUT/VREF (dBm) -10 25 20 15 -20 -30 -40 10 700 800 900 1000 1100 FREQUENCY (Hz) 1200 1300 1400 -60 1k Figure 26. Noise Spectral Density vs. Frequency,1 kHz 12 10 8 6 4 9800 9900 10,000 10,100 10,200 10,300 10,400 FREQUENCY (Hz) 08516-035 2 9700 100k 1M FREQUENCY (Hz) 10M Figure 29. Multiplying Bandwidth 14 0 9600 10k Figure 27. Noise Spectral Density vs. Frequency, 10 kHz Rev. B | Page 12 of 20 100M 08516-037 -50 5 0 600 NOISE SPECTRAL DENSITY (nV rms/ Hz) 20,000 Figure 28. Total Harmonic Distortion 08516-034 NOISE SPECTRAL DENSITY (nV rms/ Hz) Figure 25. 0.1 Hz to 10 Hz Output Noise 10,000 08516-036 -80 Data Sheet AD5541A TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or INL is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot is shown in Figure 7. Differential Nonlinearity (DNL) DNL is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. A typical DNL vs. code plot is shown in Figure 10. Gain Error Gain error is the difference between the actual and ideal analog output range, expressed as a percent of the full-scale range. It is the deviation in slope of the DAC transfer characteristic from ideal. Gain Error Temperature Coefficient Gain error temperature coefficient is a measure of the change in gain error with changes in temperature. It is expressed in ppm/C. Zero-Code Error Zero-code error is a measure of the output error when zero code is loaded to the DAC register. Zero-Code Temperature Coefficient This is a measure of the change in zero-code error with a change in temperature. It is expressed in mV/C. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition. A digital-to-analog glitch impulse plot is shown in Figure 20. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but it is measured when the DAC output is not updated. CS is held high while the SCLK and DIN signals are toggled. It is specified in nV-sec and is measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. A typical digital feedthrough plot is shown in Figure 19. Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the power supply voltage. The power supply rejection ratio is expressed in terms of percent change in output per percent change in VDD for full-scale output of the DAC. VDD is varied by 10%. Reference Feedthrough Reference feedthrough is a measure of the feedthrough from the VREF input to the DAC output when the DAC is loaded with all 0s. A 100 kHz, 1 V p-p is applied to VREF. Reference feedthrough is expressed in mV p-p. Rev. B | Page 13 of 20 AD5541A Data Sheet THEORY OF OPERATION The AD5541A is a single, 16-bit, serial input, voltage output DAC. It operates from a single supply ranging from 2.7 V to 5 V and consumes typically 125 A with a supply of 5 V. Data is written to these devices in a 16-bit word format, via a 3- or 4-wire serial interface. To ensure a known power-up state, this part is designed with a power-on reset function. The output is reset to 0 V. DIGITAL-TO-ANALOG SECTION The DAC architecture consists of two matched DAC sections. A simplified circuit diagram is shown in Figure 30. The DAC architecture of the AD5541A is segmented. The four MSBs of the 16-bit data-word are decoded to drive 15 switches, E1 to E15. Each switch connects one of 15 matched resistors to either AGND or VREF. The remaining 12 bits of the data-word drive the S0 to S11 switches of a 12-bit voltage mode R-2R ladder network. R 2R R VOUT 2R 2R . . . . . 2R 2R 2R . . . . . 2R S0 S1 . . . . . S11 E1 E2 . . . . . E15 12-BIT R-2R LADDER FOUR MSBs DECODED INTO 15 EQUAL SEGMENTS The AD5541A is controlled by a versatile 3- or 4-wire serial interface that operates at clock rates of up to 50 MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards. The timing diagram is shown in Figure 3. The AD5541A has a separate serial input register from the 16-bit DAC register that allows preloading of a new data value into the serial input register without disturbing the present DAC output voltage. Input data is framed by the chip select input, CS. After a highto-low transition on CS, data is shifted synchronously and latched into the serial input register on the rising edge of the serial clock, SCLK. After 16 data bits have been loaded into the serial input register, a low-to-high transition on CS transfers the contents of the shift register to the DAC register if LDAC is held low. If LDAC is high at this point, a low-to-high transition on CS transfers the contents into the serial input register only. After a new value is fully loaded in the serial input register, it can be asynchronously transferred to the DAC register by strobing the LDAC pin. Data is loaded MSB first in 16-bit words. Data can be loaded to the part only while CS is low. 08516-022 VREF SERIAL INTERFACE Figure 30. DAC Architecture With this type of DAC configuration, the output impedance is independent of code, whereas the input impedance seen by the reference is heavily code dependent. The output voltage is dependent on the reference voltage, as shown in the following equation: VOUT = VREF x D 2N where: D is the decimal data-word loaded to the DAC register. N is the resolution of the DAC. For a reference of 2.5 V, the equation simplifies to the following: VOUT = 2. 5 x D 65,536 This gives a VOUT of 1.25 V with midscale loaded and 2.5 V with full scale loaded to the DAC. The LSB size is VREF/65,536. Rev. B | Page 14 of 20 Data Sheet AD5541A UNIPOLAR OUTPUT OPERATION OUTPUT AMPLIFIER SELECTION This DAC is capable of driving unbuffered loads of 60 k. Unbuffered operation results in low supply current, typically 300 A, and a low offset error. The AD5541A provides a unipolar output swing ranging from 0 V to VREF - 1 LSB. Figure 31 shows a typical unipolar output voltage circuit. The code table for this mode of operation is shown in Table 8. The example includes the ADR421 2.5 V reference and the AD8628 low offset and zero-drift reference buffer. For bipolar mode, a precision amplifier should be used and supplied from a dual power supply. This provides the VREF output. In a single-supply application, selection of a suitable op amp may be more difficult because the output swing of the amplifier does not usually include the negative rail, in this case, AGND. This can result in some degradation of the specified performance unless the application does not use codes near zero. The selected op amp must have a very low offset voltage (the DAC LSB is 38 V with a 2.5 V reference) to eliminate the need for output offset trims. Input bias current should also be very low because the bias current, multiplied by the DAC output impedance (approximately 6 k), adds to the zero-code error. Rail-to-rail input and output performance is required. For fast settling, the slew rate of the op amp should not impede the settling time of the DAC. Output impedance of the DAC is constant and code independent, but to minimize gain errors, the input impedance of the output amplifier should be as high as possible. The amplifier should also have a 3 dB bandwidth of 1 MHz or greater. The amplifier adds another time constant to the system, thus increasing the settling time of the output. A higher 3 dB amplifier bandwidth results in a shorter effective settling time of the combined DAC and amplifier. Table 8. Unipolar Code Table DAC Latch Contents MSB LSB 1111 1111 1111 1111 1000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 Analog Output VREF x (65,535/65,536) VREF x (32,768/65,536) = 1/2 VREF VREF x (1/65,536) 0V Assuming a perfect reference, the unipolar worst-case output voltage can be calculated from the following equation: D x (VREF + VGE ) + V ZSE + INL 216 where: VOUT-UNI is the unipolar mode worst-case output. D is the code loaded to DAC. VREF is the reference voltage applied to the part. VGE is the gain error in volts. VZSE is the zero-scale error in volts. INL is the integral nonlinearity in volts. 5V 0.1F AD8628 2 VIN 10F + 1F VOUT 6 5V ADR421 0.1F 0.1F 4 SERIAL INTERFACE VDD REF AD820/ OP196 CS DIN AD5541A SCLK DGND AGND Figure 31. Unipolar Output Rev. B | Page 15 of 20 VOUT EXTERNAL OP AMP UNIPOLAR OUTPUT 08516-023 VOUT -UNI = AD5541A Data Sheet FORCE SENSE AMPLIFIER SELECTION POWER-ON RESET Use single-supply, low noise amplifiers. A low output impedance at high frequencies is preferred because the amplifiers must be able to handle dynamic currents of up to 20 mA. The AD5541A has a power-on reset function to ensure that the output is at a known state on power-up. On power-up, the DAC register contains all 0s until the data is loaded from the serial register. However, the serial register is not cleared on power-up; therefore, its contents are undefined. When loading data initially to the DAC, 16 bits or more should be loaded to prevent erroneous data appearing on the output. If more than 16 bits are loaded, the last 16 are kept, and if less than 16 bits are loaded, bits remain from the previous word. If the AD5541A must be interfaced with data shorter than 16 bits, pad the data with 0s at the LSBs. REFERENCE AND GROUND Because the input impedance is code dependent, drive the reference pin from a low impedance source. The AD5541A operates with a voltage reference ranging from 2 V to VDD. References below 2 V result in reduced accuracy. The full-scale output voltage of the DAC is determined by the reference. Table 8 outlines the analog output voltage or particular digital codes. If the application does not require separate force and sense lines, tie the lines close to the package to minimize voltage drops between the package leads and the internal die. POWER SUPPLY AND REFERENCE BYPASSING For accurate high resolution performance, it is recommended that the reference and supply pins be bypassed with a 10 F tantalum capacitor in parallel with a 0.1 F ceramic capacitor. Rev. B | Page 16 of 20 Data Sheet AD5541A APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING LAYOUT GUIDELINES Microprocessor interfacing to the AD5541A is via a serial bus that uses standard protocol that is compatible with DSP processors and microcontrollers. The communications channel requires a 3- or 4-wire interface consisting of a clock signal, a data signal, and a synchronization signal. The AD5541A requires a 16-bit data-word with data valid on the rising edge of SCLK. In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. Design the printed circuit board (PCB) on which the AD5541A is mounted so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5541A is in a system where multiple devices require an analog ground-to-digital ground connection, make the connection at one point only. Establish the star ground point as close as possible to the device. AD5541A TO ADSP-BF531 INTERFACE The SPI interface of the AD5541A is designed to be easily connected to industry-standard DSPs and microcontrollers. Figure 32 shows how the AD5541A can be connected to the Analog Devices, Inc., Blackfin(R) DSP. The Blackfin has an integrated SPI port that can be connected directly to the SPI pins of the AD5541A. The AD5541A should have ample supply bypassing of 10 F in parallel with 0.1 F on each supply located as close to the package as possible, ideally right up against the device. The 10 F capacitors are the tantalum bead type. The 0.1 F capacitor should have low effective series resistance (ESR) and low effective series inductance (ESI), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. AD5541A SPISELx SCK MOSI CS SCLK DIN GALVANICALLY ISOLATED INTERFACE LDAC Figure 32. AD5541A to ADSP-BF531 Interface AD5541A TO SPORT INTERFACE The Analog Devices ADSP-BF527 has one SPORT serial port. Figure 33 shows how one SPORT interface can be used to control the AD5541A. AD5541A SPORT_TFS SPORT_TSCK SPORT_DTO CS In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. iCoupler(R) products from Analog Devices provide voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5541A makes the part ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 34 shows a 4-channel isolated interface to the AD5541A using an ADuM1400. For further information, visit http://www.analog.com/icouplers. SCLK CONTROLLER DIN SERIAL CLOCK IN GPIO0 LDAC 08516-041 ADSP-BF527 SERIAL DATA OUT Figure 33. AD5541A to SPORT Interface ADuM14001 VIA VOA ENCODE DECODE ENCODE DECODE ENCODE DECODE ENCODE DECODE VIB VOB VIC SYNC OUT LOAD DAC OUT 1 VOC VID VOD ADDITIONAL PINS OMITTED FOR CLARITY. Figure 34. Isolated Interface Rev. B | Page 17 of 20 TO SCLK TO DIN TO CS TO LDAC 08516-042 PF9 08516-040 ADSP-BF531 AD5541A Data Sheet DECODING MULTIPLE DACS AD5541A SCLK The CS pin of the AD5541A can be used to select one of a number of DACs. All devices receive the same serial clock and serial data, but only one device receives the CS signal at any one time. The DAC addressed is determined by the decoder. There is some digital feedthrough from the digital input lines. Using a burst clock minimizes the effects of digital feedthrough on the analog signal channels. Figure 35 shows a typical circuit. CS DIN ENABLE CODED ADDRESS VOUT DIN VDD SCLK AD5541A EN CS DECODER VOUT DIN SCLK DGND AD5541A CS VOUT DIN SCLK AD5541A CS SCLK Figure 35. Addressing Multiple DACs Rev. B | Page 18 of 20 VOUT 08516-030 DIN Data Sheet AD5541A OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15 MAX 1.10 MAX 0.30 0.15 0.70 0.55 0.40 0.23 0.13 6 0 091709-A 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 36. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters DETAIL A (JEDEC 95) 2.48 2.38 2.23 3.10 3.00 SQ 2.90 0.50 BSC 10 6 1.74 1.64 1.49 EXPOSED PAD 0.50 0.40 0.30 1 5 BOTTOM VIE W TOP VIEW PKG-004362 0.80 0.75 0.70 SEATING PLANE SIDE VIEW 0.30 0.25 0.20 0.05 MAX 0.02 NOM COPLANARITY 0.08 PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.20 REF Figure 37. 10-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm x 3 mm Body and 0.75 mm Package Height (CP-10-9) Dimensions shown in millimeters Rev. B | Page 19 of 20 0.20 MIN 02-07-2017-C PIN 1 INDEX AREA AD5541A Data Sheet DETAIL A (JEDEC 95) 2.44 2.34 2.24 3.10 3.00 SQ 2.90 0.50 BSC 8 5 PIN 1 INDEX AREA TOP VIEW PKG-005136 SEATING PLANE SIDE VIEW 0.30 0.25 0.20 1 4 0.20 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET COMPLIANT TO JEDEC STANDARDS MO-229-W3030D-4 02-10-2017-C 0.50 0.40 0.30 0.80 0.75 0.70 1.70 1.60 1.50 EXPOSED PAD Figure 38. 8-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm x 3 mm Body and 0.75 mm Package Height (CP-8-11) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD5541ABRMZ AD5541ABRMZ-REEL7 AD5541AARMZ AD5541AARMZ-REEL7 AD5541AACPZ-REEL7 AD5541ABCPZ-REEL7 AD5541ABCPZ-500RL7 AD5541ABCPZ-1-RL7 EVAL-AD5541ASDZ 1 INL 1 LSB 1 LSB 2 LSB 2 LSB 2 LSB 1 LSB 1 LSB 1 LSB DNL 1 LSB 1 LSB 1 LSB 1 LSB 1 LSB 1 LSB 1 LSB 1 LSB Power-On Reset to Code Zero Scale Zero Scale Zero Scale Zero Scale Zero Scale Zero Scale Zero Scale Zero Scale Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Z = RoHS Compliant Part. (c)2010-2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08516-0-4/18(B) Rev. B | Page 20 of 20 Package Description 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead LFCSP 10-Lead LFCSP 10-Lead LFCSP 8-Lead LFCSP AD5541A Evaluation Board Package Option RM-10 RM-10 RM-10 RM-10 CP-10-9 CP-10-9 CP-10-9 CP-8-11 Marking Code DEQ DEQ DER DER DER DEQ DEQ DFG