186 54164,/74164 8-Parallel-Out Serial Shift Register Schottky TTL High-Speed TTL Low-Power Schottky TTL Standard TTL Low-Power TTL Device Type : clowns Device Type a nnnte Device Type colter Device Type coed Device Type Clare SN54L S16a J@ wo] SN54164 Ju wD[ SNSAl_ 164 Dane |r Tl. SNTALS 164 J@IND SN74164 Lane SN7AL 164 Jay[Na}tay FAIRCHILD - J reste rast [00 fio "| #0| Poratea Fosse or Ty MOTOROLA SNTAL S164 Pw MC 74164 PD TT NS.C. DMA Sea SIL [owas watt pam ae PHILIPS NTA 5164 N7a16a o SIGNETICS wags mat] Taare Poa SIEMENS FLJ441 gv FUJITSU TAL S164 Ma HITACHI , HD74L S164 Po HD74164 DIP: MITSUBISHI : M74LS 164 Pa MS53364 Pu NEC AMTALS co HPB2164 Day TOSHIBA TD3503A Pa i AMD Tt, AmT4L S164 t Electrical Characteristics SNS4LS164/SN74LS164 absolute maximum ratings over operating free-air temperature range Supply voltage, Voc iv Input voltage | WwW Operating free-air temperature range SSC to 125C ac to 70C SN54' SN78 | Storage temperature range | BC to 150C recommended operating conditions SN54LS164 SN74LS164 | UNIT MIN NOM MAX |MIN NOM MAX Suppiy voltaeg. Voc 45 5 5.5 | 4.75 5 5.25 Vv High-evel output current, IOH 400 = 400{ vA Low-level output current. IQL 4 a a Clock frequency. fgigck 9 25 0 25 | MHz Width of clock or clear wput pulse. tw 20 20 ns Data setup time, tsetup iS 1S ns Oata hold time. thoid 5 5 ns. Operating free-air temperature, T 4 55 125 a 70] C electrical characteristics over recommended cperating free-air temperature range PARAMETER ) TEST CONDITIONS + MIN TYP t MAX! UNIT Vik High-level input voltage 2 Vv Vit Low-level input voltage 0.8 v Vv Input clamp voltage Voo=MIN. i) 18mA - eT vy I Voc=MIN, Vis 2V, VOH = High-levet output voltage VIL =0.8V, gy = ~ 400A 27 35 v Voc=MIN, Viy= 2V. ~ Vou Low-level output voltage 035 05 v VIL =0.8V, Io, =8mA Input current maximum 4 VooMAX, Vy av a input voltage . UH High-ievel input current Voo MAX, Vi=2 ?v 20, uA Ti Low-level input current Voo=MAX, V)-0.4V 04] mA | los Short-circuit output current | VoG =MAX omnes om ms ve Veg =MAX, | 7 loc Supply current | Seo Noe 1 a mA r fmax Maximum ciock frequency { | MHz | wand VQ EBV, a CPHL rapagation delay time, hiah todow: Ta=25c, | 6 ns |____ lve! Qoutputs from elear neut tae = ats |. tet ye obagation delay time, lowsto-high Oy = 15pF + "7 ors level O outputs from clock input Propagaticn delay time. high -to-lo: t PHL level Q Outputs from clock input 7 | Pin Assignment Oo Positive logic: soc fiinctron tabl (Top View) je SERIAL weurs Vg { 164, typical Function Table 164,'LS164,L164 (see Note 2) INPUTS OUTPUTS CLE. AS |CLOCK|] A B i x x x L u L | L | X X [Qo OB Ano | | t HOH | H Onan Tan t | ul x | L QAn OGn ee a LS164, L164 clear, shift, and output guTeut oureuT OUTPUT ouTEUT Om 0B de Op % 8-BIT PARALLEL-OUT SHIFT REGISTER clear sequences outeut OF oureun OG cue AR a i SERIAL : INPUTS, puTeuTs: I clean NOTES: 1 ground, - then 2. H =high level X =urrelevant t = transition 4.5V, applied to clear (steady state), L= Lowlevel (steady state) (any input, including transitions) from low to high tevel Lear Gc #8 Measured with outputs open, serial inputs grounded. and a momentary Sao, 980, OHO =the level of Oa Og, or OH resnectively, before the indicated steady-state input conditions were established San, In = the clock: indi the tevel of Qa or OG pete icates a one-bit shift re the most-receat transition of tFor conditions shown at MINo: MAX. use the appriate velue specified under recommended operating conditions for the apphcable device type TA typical values are at Voc: SV. Ta 25C *Not more than two outputs shoud be shorted at a time