1
FEATURES
DESCRIPTION
APPLICATIONS
SIMPLIFIED APPLICATION DIAGRAM
VDG−03170
5
13
12
16
15
1
2
3
KFF
RT
LVBP
SGND
VDD
HDRV
SW
DBP
4 PGD
11
ILIM
TPS40070PWP
6 SS
7 FB
8 COMP
14BOOST
LDRV 10
PGND 9
Powergood
VOUT
VDD
VOUT
VDD
TPS40070
TPS40071
www.ti.com
.................................................................................................................................................. SLUS582J – DECEMBER 2003 – REVISED APRIL 2009
HIGH-EFFICIENCY MIDRANGE INPUT SYNCHRONOUSBUCK CONTROLLER WITH VOLTAGE FEED-FORWARD
2
•Operation Over 4.5-V to 28-V Input Range•Programmable Fixed-Frequency up to 1-MHz
The TPS4007x is a mid voltage, wide input (4.5 V to28 V), synchronous, step-down converter.Voltage-Mode Controller•Predictive Gate Drive™ With Anti-Cross
The TPS4007x offers design flexibility with a varietyConduction Circuitry
of user programmable functions, including; soft-start,UVLO, operating frequency, voltage feed-forward and•< 1% Internal 700-mV Reference
high-side FET sensed short circuit protection.•Internal Gate Drive Outputs for High-Side and
The TPS4007x incorporates MOSFET gate drivers forSynchronous N-Channel MOSFETs
external N-channel high-side and synchronous•16-Pin PowerPAD™ Package
rectifier (SR) MOSFETs. Gate drive logic incorporates•Thermal Shutdown Protection
predictive anti-cross conduction circuitry to preventsimultaneous high-side and synchronous rectifier•TPS40070: Source Only
conduction, while minimizing to eliminating current•TPS40071: Source/Sink
flow in the body diode of the SR FET. The TPS40071•Programmable High-Side Sense Short Circuit
allows the supply output to sink current at all times.Protection
The TPS40070 implements a source-only powersupply.
•Power Modules•Networking/Telecom
•PCI Express
•Industrial
•Servers
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Predictive Gate Drive, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003 – 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
DESCRIPTION (CONTINUED)
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
TPS40070
TPS40071
SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 ..................................................................................................................................................
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The TPS4007x uses voltage feed-forward control techniques to provide good line regulation over a wide-inputvoltage range, and fast response to input line transients with near constant gain with input variation to ease loopcompensation. The externally programmable short circuit protection provides fault current limiting, as well ashiccup mode operation for thermal protection in the presence of a shorted output.The TPS4007x is packaged in a16-pin PowerPAD package for better thermal performance at higher voltages and frequencies. See SLMA002 forinformation on board layout for the PowerPAD package. The pcb pad that the PowerPAD solders to should beconnected to GND. Due to the die attach method, the PowerPAD itself cannot be used as the device groundconnection. The two device grounds must be connected as well.
ORDERING INFORMATION
T
A
APPLICATION PACKAGE PART NUMBER
SOURCE ONLY
(1)
Plastic HTSSOP (PWP)
(
(2)
)
TPS40070PWP40 ° C to 85 ° C
SOURCE/SINK
(1)
Plastic HTSSOP (PWP)
(
(2)
)
TPS40071PWP
(1) See Application Information section and Table 1.(2) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS40070PWPR). See the applicationsection of the data sheet for PowerPAD drawing and layout information.
over operating free-air temperature range unless otherwise noted
(1)
TPS40070
UNITTPS40071
VDD, ILIM 30COMP, FB, KFF, PGD, LVBP – 0.3 to 6V
DD
Input voltage range
SW – 0.3 to 40SW, transient < 50 ns – 2.5
VCOMP, KFF, RT, SS – 0.3 to 6VBOOST 50V
OUT
Output voltage range
DBP 10.5LVBP 6I
OUT
Output current source LDRV, HDRV 1.5LDRV, HDRV 2.0 AI
OUT
Output current sink
KFF 10RT 1Output current mALVBP 1.5T
J
Operating junction temperature range – 40 to 125T
stg
Storage temperature – 55 to 150 ° CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260
(1) Stresses beyond those listed under " absolute maximum ratings " may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under " recommended operatingconditions " is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
MIN NOM MAX UNIT
V
DD
Input voltage 4.5 28 VT
A
Operating free-air temperature -40 85 ° C
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Product Folder Link(s): TPS40070 TPS40071
ELECTRICAL CHARACTERISTICS
TPS40070
TPS40071
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.................................................................................................................................................. SLUS582J – DECEMBER 2003 – REVISED APRIL 2009
T
A
= – 40 ° C to 85 ° C, V
IN
= 12 V
dc
, R
T
= 90.9 k Ω, I
KFF
= 300 A, f
SW
= 500 kHz, all parameters at zero power dissipation (unlessotherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY
V
DD
Input voltage range, VIN 4.5 28 V
OPERATING CURRENT
I
DD
Quiescent current Output drivers not switching 2.5 3.5 mA
LVBP
V
LVBP
Output voltage T
A
= T
J
= 25 ° C 3.9 4.2 4.5 V
OSCILLATOR/RAMP GENERATOR
(1)
f
OSC
Accuracy 450 500 550 kHzV
RAMP
PWM ramp voltage
(2)
V
PEAK
-V
VAL
2.0 VV
RT
RT voltage 2.23 2.40 2.58 Vt
ON
Minimum output pulse time
(2)
C
HDRV
= 0 nF 250 nsV
FB
= 0 V, 100 kHz ≤f
SW
≤500 kHz 84% 93%Maximum duty cycle
V
FB
= 0 V, f
SW
= 1 MHz 76% 93%V
KFF
Feed-forward voltage 0.35 0.40 0.45 VI
KFF
Feed-forward current operating range
(2)
20 1100 µA
SOFT START
I
SS
Charge current 7 12 17 µAt
DSCH
Discharge time C
SS
= 3.9 nF 25 75
µsC
SS
= 3.9 nF,t
SS
Soft-start time 210 290 500V
SS
rising from 0.7 V to 1.6 VCommand zero output voltage
(1)
300 mV
DBP
V
DD
> 10 V 7 8 9V
DBP
Output voltage VV
DD
= 4.5 V, I
OUT
= 25 mA 4.0 4.3
ERROR AMPLIFIER
T
A
= T
J
= 25 ° C 0.698 0.700 0.704V
FB
Feedback regulation voltage total variation 0 ° C ≤T
A
≤85 ° C 0.690 0.700 0.707
V40 ° C ≤T
A
≤85 ° C 0.690 0.700 0.715V
SS
Soft-start offset from VSS
(2)
Offset from V
SS
to error amplifier 1G
BW
Gain bandwidth
(2)
5 10 MHzA
VOL
Open loop gain 50 dBI
SRC
Output source current 2.5 4.5
mAI
SINK
Output sink current 2.5 6I
BIAS
Input bias current V
FB
= 0.7 V – 250 0 nA
(1) For zero output voltage only. Does not assure lack of activity on HDRV or LDRV.(2) Ensured by design. Not production tested.
Copyright © 2003 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TPS40070 TPS40071
TPS40070
TPS40071
SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 ..................................................................................................................................................
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ELECTRICAL CHARACTERISTICS (continued)T
A
= – 40 ° C to 85 ° C, V
IN
= 12 V
dc
, R
T
= 90.9 k Ω, I
KFF
= 300 A, f
SW
= 500 kHz, all parameters at zero power dissipation (unlessotherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SHORT CIRCUIT CURRENT PROTECTION
I
ILIM
Current sink into current limit 80 105 125 µAV
ILIM(ofst)
Current limit offset voltage V
ILIM
= 11.5 V, (V
SW
- V
ILIM
) V
DD
= 12 V – 75 – 50 – 30 mVt
HSC
Minimum HDRV pulse width During short circuit 135 225 nsPropagation delay to output
(3)
50 nst
BLANK
Blanking time
(3)
50 nst
OFF
Off time during a fault (SS cycle times) 7 cyclesV
SW
Switching level to end precondition
(3)
(V
DD
- V
SW
) 2 Vt
PC
Precondition time
(3)
100 nsV
ILIM
Current limit precondition voltage threshold
(3)
6.8 V
OUTPUT DRIVERS
t
HFALL
High-side driver fall time
(3)
36C
HDRV
= 2200 pF, (HDRV - SW) nst
HRISE
High-side driver rise time
(3)
48t
HFALL
High-side driver fall time
(3)
72C
HDRV
= 2200 pF, (HDRV - SW)
nsV
DD
= 4.5 V, 0.2 V ≤V
SS
≤4 Vt
HRISE
High-side driver rise time
(3)
96t
LFALL
Low-side driver fall time
(3)
24C
LDRV
= 2200 pF nst
LRISE
Low-side driver rise time
(3)
48t
LFALL
Low-side driver fall time
(3)
48C
LDRV
= 2200 pF, V
DD
= 4.5 V,
ns0.2 V ≤V
SS
≤4 Vt
LRISE
Low-side driver rise time
(3)
96I
HDRV
= -0.01 A, (V
BOOST
- V
HDRV
) 0.7 1.0V
OH
High-level output voltage, HDRV VI
HDRV
= -0.1 A, (V
BOOST
- V
HDRV
) 0.95 1.30(V
HDRV
- V
SW
), I
HDRV
= 0.01A 0.06 0.10V
OL
Low-level output voltage, HDRV V(V
HDRV
- V
SW
), I
HDRV
= 0.1 A 0.65 1.0(V
DBP
- V
LDRV
), I
LDRV
= -0.01A 0.65 1.00V
OH
High-level output voltage, LDRV V(V
DBP
- V
LDRV
), I
LDRV
= -0.1 A 0.875 1.200I
LDRV
= 0.01 A 0.03 0.05V
OL
Low-level output voltage, LDRV VI
LDRV
= 0.1 A 0.3 0.5
ZERO CURRENT DETECTION
I
ZERO
Zero current threshold, TPS40070 – 5 0 5 mV
BOOST REGULATOR
V
BOOST
Output voltage V
DD
= 12 V 15.2 17.0 V
UVLO
V
UVLO
Programmable UVLO threshold voltage R
KFF
= 90.9 k Ω, turn-on, V
DD
rising 6.2 7.2 8.2Programmable UVLO hysteresis R
KFF
= 90.9 k Ω1.10 1.55 2.00 VFixed UVLO threshold voltage Turn-on, V
DD
rising 4.15 4.30 4.45Fixed UVLO hysteresis 275 365 mV
POWER GOOD
V
PG
Powergood voltage I
PG
= 1 mA 370 500V
OH
High-level output voltage, FB 770 mVV
OL
Low-level output voltage, FB 630
THERMAL SHUTDOWN
Shutdown temperature threshold
(3)
165
° CHysteresis
(3)
15
(3) Ensured by design. Not production tested.
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Product Folder Link(s): TPS40070 TPS40071
THERMAL
PAD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
KFF
RT
LVBP
PGD
SGND
SS
FB
COMP
ILIM
VDD
BOOST
HDRV
SW
DBP
LDRV
PGND
PWP PACKAGE(1)(2)
(TOP VIEW)
TPS40070
TPS40071
www.ti.com
.................................................................................................................................................. SLUS582J – DECEMBER 2003 – REVISED APRIL 2009
(1) For more information on the PWP package, refer to TI Technical Brief (SLMA002).(2) PowerPAD™ heat slug must be connected to SGND (pin 5) or electrically isolated from all other pins.
Table 1. Terminal Functions
TERMINAL
I/O DESCRIPTIONNAME NO.
Gate drive voltage for the high-side N-channel MOSFET. The BOOST voltage is 8 V greater than the inputBOOST 14 I
voltage. A capacitor should be connected from this pin to the SW pin.Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to theCOMP 8 O
FB pin to compensate the overall loop. The comp pin is internally clamped to 3.4 V.8-V reference used for the gate drive of the N-channel synchronous rectifier. This pin should be bypassed toDBP 11 O
ground with a 1.0- µF ceramic capacitor.Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the internal referenceFB 7 I
voltage, 0.7 V.Floating gate drive for the high-side N-channel MOSFET. This pin switches from BOOST (MOSFET on) to SWHDRV 13 O
(MOSFET off).Short circuit protection programming pin. This pin is used to set the overcurrent threshold. An internal current sinkfrom this pin to ground sets a voltage drop across an external resistor connected from this pin to VDD. The voltageon this pin is compared to the voltage drop (V
VDD
-V
SW
) across the high side N-channel MOSFET duringILIM 16 I conduction. Just prior to the beginning of a switching cycle this pin is pulled to approximately VDD/2 and releasedwhen SW is within 2 V of V
DD
or after a timeout (the precondition time) - whichever occurs first. Placing acapacitor across the resistor from ILIM to VDD allows the ILIM threshold to decrease during the switch on time,effectively programming the ILIM blanking time. See applications information.A resistor is connected from this pin to VIN programs the amount of feed-forward voltage. The current fed into thisKFF 1 I pin is internally divided by 25 and used to control the slope of the PWM ramp and program undervoltage lockout.Nominal voltage at this pin is maintained at 400 mV.Gate drive for the N-channel synchronous rectifier. This pin switches from DBP (MOSFET on) to ground (MOSFETLDRV 10 O
off). For proper operation, the total gate charge of the MOSFET connected to LDRV should be less than 50nC.4.2-V reference used for internal device logic only. This pin should be bypassed by a 0.1- µF ceramic capacitor.LVBP 3 O
External loads less than 1 mA and electrically quiet may be applied.This is an open drain output that pulls to ground when soft start is active, or when the FB pin is outside a 10%PGD 4 O
band around VREF.Power ground reference for the device. There should be a low-impedance path from this pin to the source(s) of thePGND 9
lower MOSFET(s).RT 2 I A resistor is connected from this pin to ground to set the internal oscillator and switching frequency.SGND 5 Signal ground reference for the device.Soft-start programming pin. A capacitor connected from this pin to ground programs the soft-start time. Thecapacitor is charged with an internal current source of 10 µA. The resulting voltage ramp on the SS pin is used asa second non-inverting input to the error amplifier. The voltage at this error amplifier input is approximately 1 VSS 6 I less that that on the SS pin. Output voltage regulation is controlled by the SS voltage ramp until the voltage on theSS pin reaches the internal reference voltage of 1 V plus the internal reference voltage of 0.7 V. If SS is below the1-V offset voltage to the error amplifier. The resulting output voltage is zero. Also provides timing for fault recoveryattempts. Maximum recommended capacitor value is 22nF.This pin is connected to the switched node of the converter. It is used for short circuit sensing, gate drive timingSW 12 I information and is the return for the high side driver. A 1.5- Ωresistor is required in series with this pin forprotection against substrate current issues.VDD 15 I Supply voltage for the device.
Copyright © 2003 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TPS40070 TPS40071
VDG−03171
11
13
10
15
3
2
1
VDD
LVBP
RT
KFF
DBP
HDRV
LDRV
4
5
7
6
PGD
SGND
FB
SS
8COMP
Reference
Regulator
Predictive
Gate Drive
Control
Logic
UVLO
Controller
Oscillator
16 ILIM
Pulse
Control
SW
CLK
SS Active
HDRV
LDRV
12 SW
Overcurrent
Comparator
and Control
CLK
ILIM OC
9 PGND
14 BOOST
VDD
UVLO
Ramp
Generator
Power
Good
Logic
770 mV
FB
630 mV
SS Active
PWM
OC
CLK
UVLO
FAULT IZERO
DBP
+
+
700 mV
RAMP
IZERO
Comparator
and Control
(TPS40070 only)
IZERO
Soft Start
and
Fault Control
OC
CLK
SW
PGND
LVBP
TPS40070
TPS40071
SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 ..................................................................................................................................................
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FUNCTIONAL BLOCK DIAGRAM
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APPLICATION INFORMATION
MINIMUM PULSE WIDTH
SLEW RATE LIMIT ON VDD
15
9
16
13
12
10
ILIM
HDRV
SW
LDRV
VDD
PGND
TPS40070
C
R
VIN
UDG−05058
+
_
TPS40070
TPS40071
www.ti.com
.................................................................................................................................................. SLUS582J – DECEMBER 2003 – REVISED APRIL 2009
The TPS40070 family of parts allows the user to construct synchronous voltage-mode buck converters withinputs ranging from 4.5 V to 28 V and outputs as low as 700 mV. Predictive gate drive circuitry optimizesswitching delays for increased efficiency and improved converter output power capability. Voltage feed-forward isemployed to ease loop compensation and provide better line transient response.
A converter based on the TPS40070 operates as a single quadrant (source only) converter at all times. Whenthe rectifier FET is on and the controller senses that current is near zero in the inductor, the rectifier FET isturned off, preventing the buildup of negative or reverse current in the inductor. This feature prevents theconverter from pulling energy from its output and forcing that energy onto its input.
Converters based on the TPS40071 operates as a two quadrant converter all the time (source and sink current).This is the controller of choice for most applications.
The TPS4007x devices have limitations on the minimum pulse width that can be used to design a converter.Reliable operation is guaranteed for nominal pulse widths of 250 ns and above. This places some restrictions onthe conversion ratio that can be achieved at a given switching frequency. Figure 2 shows minimum outputvoltage for a given input voltage and frequency.
The regulator that supplies power for the drivers on the TPS40070/1 requires a limited rising slew rate on VDDfor proper operation if the input voltage is above 10 V. If the slew rate is too great, this regulator can over shootand damage to the part can occur. To ensure that the part operates properly, limit the slew rate to no more than0.12 V/ µs as the voltage at VDD crosses 8 V. If necessary, an R-C filter can be used on the VDD pin of thedevice. Connect the resistor from the VDD pin to the input supply of the converter. Connect the capacitor fromthe VDD pin to PGND. There should not be excessive (more than a 200-mV) voltage drop across the resistor innormal operation. This places some constraints on ↔the R-C values that can be used. Figure 1 is a schematicfragment that shows the connection of the R-C slew rate limit circuit. Equation 1 and Equation 2 give values for Rand C that limits the slew rate in the worst case condition.
Figure 1. Limiting the Slew Rate
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Product Folder Link(s): TPS40070 TPS40071
CuVIN *8 V
R SR
(1)
Rt0.2 V
fSW Qg(TOT) )IDD
(2)
SETTING THE SWITCHING FREQUENCY (PROGRAMMING THE CLOCK OSCILLATOR)
RT+ǒ1
fSW(kHz) 17.82 10*6*23ǓkW
(3)
100
1.5
0.5 1000200 300 400 500 600 700 800 900
1.0
3.0
2.0
2.5
4.5
3.5
4.0
5.0
MINIMUM OUTPUT VOLTAGE
vs
FREQUENCY
fOSC - Oscillator Frequency - kHz
VOUT - Output V oltage - V
VIN = 28 V
VIN = 24 V
VIN = 18 V
VIN = 15 V
VIN = 12 V
VIN = 10 V
VIN = 8 V
VIN = 5 V
PROGRAMMING THE RAMP GENERATOR CIRCUIT AND UVLO
TPS40070
TPS40071
SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 ..................................................................................................................................................
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where
•V
VIN
is the final value of the input voltage ramp•f
SW
is the switching frequency•Q
g(TOT)
is the combined total gate charge for both upper and lower MOSFETs (from MOSFET data sheet)•I
DD
is the TPS4007x input current (3.5 mA maximum)•SR is the maximum allowed slew rate [12 × 10
4
] (V/s)
The TPS4007x has independent clock oscillator and PWM ramp generator circuits. The clock oscillator serves asthe master clock to the ramp generator circuit. Connecting a single resistor from RT to ground sets the switchingfrequency of the clock oscillator. The clock frequency is related to R
T
by:
Figure 2. Figure 3.
The ramp generator circuit provides the actual ramp used by the PWM comparator. The ramp generator providesvoltage feed-forward control by varying the PWM ramp slope with line voltage, while maintaining a constant rampmagnitude. Varying the PWM ramp directly with line voltage provides excellent response to line variations sincethe PWM does not have to wait for loop delays before changing the duty cycle. (See Figure 9 ).
The PWM ramp must reach approximately 1 V in amplitude during a clock cycle, or the PWM is not allowed tostart. The PWM ramp time is programmed via a single resistor (R
KFF
) connected from KFF VDD. R
KFF
, V
STARTand R
T
are related by (approximately):
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RKFF +0.131 RT VUVLO(on) *1.61 10*3 VUVLO(on)2)1.886 VUVLO *1.363 *0.02 RT*4.87 10*5 R2
T
RKFF − Feedforward Impedance − kΩ
100 150 250 300 350 450200 400
4
2
8
6
10
14
12
18
16
20
VUVLO − Programmable UVLO Threshold − V
UVLOVON
fSW = 300 kHz
UVLOVOFF
VDD − Input Voltage − V
fOSC − Frequency − kHz
490
480
485
505
495
500
520
510
515
525
275 9 11 15 17 19 23 2513 21 29
TPS40070
TPS40071
www.ti.com
.................................................................................................................................................. SLUS582J – DECEMBER 2003 – REVISED APRIL 2009
(4)
where
•R
T
and R
KFF
are in k Ω
•V
UVLO(on)
is in V
This yields typical numbers for the programmed startup voltage. The minimum and maximum values may vary up15% from this number. Figure 5 through Figure 6 show the typical relationship of V
UVLO(on)
, V
UVLO(off)
and R
KFF
atthree common frequencies.
FREQUENCY UNDERVOLTAGE LOCKOUT THRESHOLDvs vsINPUT VOLTAGE FEEDFORWARD IMPEDANCE
Figure 4. Figure 5.
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60 90 150 180 210 270120 240
4
2
8
6
10
14
12
18
16
20
RKFF − Feedforward Impedance − kΩ
VUVLO − Programmable UVLO Threshold − V
UVLOVON
fSW = 500 kHz
UVLOVOFF
40 60 100 120 140 18080 160
4
2
8
6
10
14
12
18
16
20
RKFF − Feedforward Impedance − kΩ
VUVLO − Programmable UVLO Threshold − V
UVLOVON
fSW = 750 kHz
UVLOVOFF
TPS40070
TPS40071
SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 ..................................................................................................................................................
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UNDERVOLTAGE LOCKOUT THRESHOLD UNDERVOLTAGE LOCKOUT THRESHOLDvs vsFEEDFORWARD IMPEDANCE FEEDFORWARD IMPEDANCE
Figure 6. Figure 7.
The programmable UVLO circuit incorporates 20% hysteresis from the start voltage to the shutdown voltage. Forexample, if the startup voltage is programmed to be 10 V, the controller starts when V
DD
reaches 10 V and shutsdown when V
DD
falls below 8 V. The maximum duty cycle begins to decrease as the input voltage rises to twicethe startup voltage. Below this point, the maximum duty cycle is as specified in the electrical table. Note that withthis scheme, the theoretical maximum output voltage that the converter can produce is approximately two timesthe programmed startup voltage. For design, set the programmed startup voltage equal to or greater than thedesired output voltage divided by maximum duty cycle (85% for frequencies 500 kHz and below). For example, a5-V output converter should not have a programmed startup voltage below 5.9 V. Figure 8 shows the theoreticalmaximum duty cycle (typical) for various programmed startup voltages
At startup, LDRV may pulse high when V
DD
is in the range of 1 V to 1.25 V and V
DD
is rising extremely slowly. Tominimize these effects, the ramp rate of V
DD
at startup should be greater than 1 V/ms.
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Product Folder Link(s): TPS40070 TPS40071
8 16 20 24 28124
40
20
30
70
50
60
100
80
90
TYPICAL MAXIMUM DUTY CYCLE
vs
INPUT VOLTAGE
VIN - Input Voltage - V
Duty Cycle - %
UVLO(on) = 8 V
UVLO(on) = 15 V
UVLO(on) = 4.5 V
UVLO(on) = 12 V
VDG−03172
RAMP
COMP
SW
VIN
VIN
SW
COMP
RAMP
VPEAK
VVALLEY
T2
tON1 > tON2 and d1 > d2
tON2
tON1
d+tON
T
T1
TPS40070
TPS40071
www.ti.com
.................................................................................................................................................. SLUS582J – DECEMBER 2003 – REVISED APRIL 2009
Figure 8.
Figure 9. Voltage Feed-Forward and PWM Duty Cycle Waveforms
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PROGRAMMING SOFT START
tSTART w2p L COUT
Ǹ
(5)
tSTART vDMIN
fSW 10*7ms
(6)
CSS +12 10*6A
0.7 V tSTART (Farads)
(7)
PROGRAMMING SHORT CIRCUIT PROTECTION
ILIM Threshold
T2
T1 ILIM Threshold
T3
T1
ILIM
ILIM
SW
SW
VIN − 2V
VIN − 2V
UDG−03173
Overcurrent
(A)
(B)
TPS40070
TPS40071
SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 ..................................................................................................................................................
www.ti.com
TPS4007x uses a closed-loop approach to ensure a controlled ramp on the output during start-up. Soft-start isprogrammed by connecting an external capacitor (C
SS
) from the SS pin to GND. This capacitor is charged by afixed current, generating a ramp signal. The voltage on SS is level shifted down approximately 1 V and fed into aseparate non-inverting input to the error amplifier. The loop is closed on the lower of the level shifted SS voltageor the 700-mV internal reference voltage. Once the level shifted SS voltage rises above the internal referencevoltage, output voltage regulation is based on the internal reference. To ensure a controlled ramp-up of theoutput voltage the soft-start time should be greater than the L-C
OUT
time constant or:
To ensure correct start up of the converter, the soft-start time is limited and can be calculated using Equation 6 .
where
•D
MIN
is the minimum operating duty cycle•f
SW
is the converter switching frequency
Please note: There is a direct correlation between t
START
and the input current required during start-up. The lowert
START
is, the higher the input current required during start-up since the output capacitance must be chargedfaster. For a desired soft-start time, the soft-start capacitance, C
SS
, can be found from:
The TPS4007x uses a two-tier approach for short circuit protection. The first tier is a pulse-by-pulse protectionscheme. Short circuit protection is implemented on the high-side MOSFET by sensing the voltage drop acrossthe MOSFET when its gate is driven high. The MOSFET voltage is compared to the voltage dropped across aresistor (R
ILIM
) connected from V
DD
to the ILIM pin when driven by a constant current sink. If the voltage dropacross the MOSFET exceeds the voltage drop across the ILIM resistor the switching pulse is immediatelyterminated. The MOSFET remains off until the next switching cycle is initiated. This is illustrated in Figure 10 .
Figure 10. Switching and Current Limit Waveforms and Timing Relationship
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Product Folder Link(s): TPS40070 TPS40071
TPS40070
TPS40071
www.ti.com
.................................................................................................................................................. SLUS582J – DECEMBER 2003 – REVISED APRIL 2009
In addition, just prior to the high-side MOSFET turning on, the ILIM pin is pulled down to approximately half ofVDD. The ILIM pin is allowed to return to its nominal value after one of two events occur. If the SW node rises towithin approximately 2 V of V
DD
, the device allows ILIM to go back to its nominal value. This is illustrated inFigure 10 (A). T1 is the delay time from the internal PWM signal being asserted and the rise of SW. This includesa driver delay of 50 ns typical. T2 is the reaction time of the sensing circuit that allows ILIM to start to return to itsnominal value, typically 20ns. The second event that can cause ILIM to return to its nominal value is for aninternal timeout to expire. This is illustrated in Figure 10 (B) as T3. Here SW never rises to V
DD
-2 V, for whateverreason, and the internal timer times out, releasing the ILIM pin.
Prior to ILIM starting back to its nominal value, overcurrent sensing is not enabled. In normal operation, thisensures that the SW node is at a higher voltage than ILIM when overcurrent sensing starts, avoiding false tripswhile allowing for a quicker blanking delay than would ordinarily be possible. Placing a capacitor across R
ILIMsets an exponential approach to the normal voltage at the ILIM pin. This exponential decay of the overcurrentthreshold can be used to compensate for ringing on the SW node after its rising edge and to help compensatefor slower turn-on FETs. Choosing the proper capacitance requires care. If the capacitance is too large, thevoltage at ILIM does not approach the desired overcurrent level quickly enough, resulting in an apparent shift inovercurrent threshold as pulse width changes.
Also, the comparator that uses ILIM and SW to determine if an overcurrent condition exists has a clamp on itsSW input. This clamp makes the SW node never appear to fall more than 1.4 V (approximately, could be asmuch as 2 V at -40C) below V
DD
. When ILIM is more than 1.4 V below V
DD
, the overcurrent circuit is effectivelydisabled. As a general rule, it is best to make the time constant of the R-C at the ILIM pin 0.2 times or less of thenominal pulse width of the converter as shown in see Equation 13 .
The second tier protection incorporates a fault counter. The fault counter is incremented on each cycle with anovercurrent pulse and decremented on a clock cycle without an overcurrent pulse. When the counter reachesseven (7) a fault condition is declared by the controller. When this happens, the outputs are placed in a statedefined in Table 2 . Seven soft-start cycles are initiated (without activity on the HDRV and LDRV outputs) and thePWM is disabled during this period. The counter is decremented on each soft-start cycle. When the counter isdecremented to zero the PWM is re-enabled and the controller attempts to restart. If the fault has been removedthe output starts up normally. If the output is still present the counter counts seven overcurrent pulses andre-enter the second tier fault mode. Refer to Figure 11 for typical fault protection waveforms.
Copyright © 2003 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPS40070 TPS40071
ISCP(min) uǒCOUT VOUT
tSTART Ǔ)ILOAD )ǒIRIPPLE
2Ǔ
(8)
RILIM +100 ǒRDS(ON)max ISCP )VILIM(ofst)Ǔ)9 RVDD IRVDD )4.5 V
109 IILIM (W)
(9)
IRVDD +fSW Qg(TOT) )IDD (A)
(10)
ISCP(max) +1.09 IILIM(max) RILIM *0.09 RVDD IRVDD *0.045 V )75 mV
RDS(ON)min (A)
(11)
ISCP(min) +1.09 IILIM(min) RILIM *0.09 RVDD IRVDD *0.045 V )30 mV
RDS(ON)max (A)
(12)
CILIM(max) +VOUT 0.2
VIN RILIM fSW (Farads)
(13)
TPS40070
TPS40071
SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 ..................................................................................................................................................
www.ti.com
The minimum short circuit limit setpoint (I
SCP(min)
) depends on t
START
, C
OUT
, V
OUT
, ripple current in inductor(I
RIPPLE
) and the load current at turn-on (I
LOAD
).
The short circuit limit programming resistor (R
ILIM
) is calculated from:
where
•I
ILIM
is the current into the ILIM pin (110 µA typical)•V
ILIM(ofst)
is the offset voltage between SW and ILIM pins (-50 mV typical)•I
SCP
is the short-circuit protection current•R
DS(ON)max
is the drain-to-source resistance of the high-side MOSFET•R
VDD
is the slew rate limit resistor if used•I
RVDD
is the current through R
VDD
and can be calculated using Equation 10 .
where
•f
SW
is the switching frequency•Q
g(TOT)
is the combined total gate charge for both upper and lower MOSFETs (from MOSFET data sheet)•I
DD
is the TPS4007x input current (3.5 mA maximum)
To find the range of the overcurrent values use the following equations.
The TPS40070/1 provides short circuit protection only. As such, it is recommended that the minimum short circuitprotection level be placed at least 20% above the maximum output current required from the converter. Themaximum output of the converter should be the steady state maximum output plus any transient specificationthat may exist.
The ILIM capacitor maximum value can be found from:
Note that this is a recommended maximum value. If a smaller value can be used, it should be. For mostapplications, consider using half the maximum value above.
14 Submit Documentation Feedback Copyright © 2003 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS40070 TPS40071
VDG−03174
tBLANKING
7 Current-Limit Trips
(HDRV Cycle Terminated by Current-Limit Trip) 7
Soft-Start
Cycles
HDRV
Clock
VILIM
VVIN − VSW
SS
LOOP COMPENSATION
KPWM ^VUVLO (on)
(14)
TPS40070
TPS40071
www.ti.com
.................................................................................................................................................. SLUS582J – DECEMBER 2003 – REVISED APRIL 2009
Figure 11. Typical Fault Protection Waveforms
Voltage mode buck type converters are typically compensated using Type III networks. Since the TPS4007xuses voltage feedforward control, the gain of the voltage feedforward circuit must be included in the PWM gain.The gain of the voltage feedforward circuit combined with the PWM circuit and power stage for the TPS4007x is:
The remainder of the loop compensation is performed as in a normal buck converter. Note that the voltagefeedforward circuitry removes the input voltage term from the expression for PWM gain. PWM gain is strictly afunction of the programmed startup voltage.
Copyright © 2003 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS40070 TPS40071
BOOST AND DBP BYPASS CAPACITANCE
INTERNAL REGULATORS
255 10 2015 30
4.10
4.00
4.05
4.15
4.20
4.35
4.25
4.30
4.40
4.45
4.50
INPUT VOLTAGE
vs
LOW VOLTAGE BYPASS VOLTAGE
VDD - Input Voltage - V
VDBP - Low V oltage Bypass Voltage - V
TPS4007x POWER DISSIPATION
PD+Qg VDR fSW (Wattsńdriver)
(15)
TPS40070
TPS40071
SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 ..................................................................................................................................................
www.ti.com
The BOOST capacitance provides a local, low-impedance flying source for the high-side driver. The BOOSTcapacitor should be a good quality, high-frequency capacitor. A capacitor with a minimum value of 100-nF issuggested.
The DBP has to provide energy for both the synchronous MOSFET and the high-side MOSFET (via the BOOSTcapacitor). The suggested value for this capacitor is 1- µF ceramic, minimum.
The internal regulators are linear regulators that provide controlled voltages for the drivers and the internalcircuitry to operate from. The DBP pin is connected to a nominal 8-V regulator that provides power for the drivercircuits to operate from. This regulator has two modes of operation. At V
DD
voltages below 8.5 V ,the regulator isin a low dropout mode of operation and tries to provide as little impedance as possible from VDD to DBP. Above10 V at V
DD
, the regulator regulates DBP to 8 V. Between these two voltages, the regulator remains in the state itwas in when V
DD
entered this region (see Figure 12 ). Small amounts of current can be drawn from this pin forother circuit functions, as long as power dissipation in the controller device remains at acceptable levels andjunction temperature does not exceed 125C.
The LVBP pin is connected to another internal regulator that provides 4.2-V (nom) for the operation oflow-voltage circuitry in the controller. This pin can be used for other circuit purposes, but extreme care must betaken to ensure that no extra noise is coupled onto this pin, since controller performance suffers. Current draw isnot to exceed 1 mA. See Figure 13 for typical output voltage at this pin.
Figure 12. Figure 13.
The power dissipation in the TPS4007x is largely dependent on the MOSFET driver currents and the inputvoltage. The driver current is proportional to the total gate charge, Qg, of the external MOSFETs. Driver power(neglecting external gate resistance) can be calculated from:
where
•V
DR
is the driver output voltage
16 Submit Documentation Feedback Copyright © 2003 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS40070 TPS40071
PT+ǒ2 PD
VDR )IQǓ VIN (Watts)
(16)
PT+ǒ2 Qg fSW )IQǓ VIN (Watts)
(17)
qJA +36.51OCńW
(18)
PT+TJ*TA
qJA (Watts)
(19)
fSW +ǒƪǒTJ*TAǓ
ǒqJA VDDǓƫ*IQǓ
ǒ2 QgǓ(Hz)
(20)
BOOST DIODE
LOW VOLTAGE OPERATION
GROUNDING AND BOARD LAYOUT
TPS40070
TPS40071
www.ti.com
.................................................................................................................................................. SLUS582J – DECEMBER 2003 – REVISED APRIL 2009
And the total power dissipation in the TPS4007x, assuming the same MOSFET is selected for both the high-sideand synchronous rectifier is described in Equation 16 .
or
where:
•I
Q
is the quiescent operating current (neglecting drivers)
The maximum power capability of the TPS4007x PowerPAD package is dependent on the layout as well as airflow. The thermal impedance from junction to air assuming 2-oz. copper trace and thermal pad with solder andno air flow is see teh application report titled PowerPAD Thermally Enhanced Package (SLMA002) for detailedinformation on PowerPAD package mounting and usage.
The maximum allowable package power dissipation is related to ambient temperature by Equation 19 .
Substituting Equation 19 into Equation 18 and solving for f
SW
yields the maximum operating frequency for theTPS4007x. The result is described in Equation 20 .
The TPS4007x series has internal diodes to charge the boost capacitor connected from SW to BOOST. The dropacross this diode is rather large at 1.4-V nominal at room temperature. If this drop is too large for a particularapplication, an external diode may be connected from DBP (anode) to BOOST (cathode). This providessignificantly improved gate drive for the high side FET, especially at lower input voltages.
If the programmable UVLO is set to less than 6.5 V nominal, connect a 330-k Ωresistor across the soft-startcapacitor. This eliminates a race condition inside the device that can lead to an output voltage overshoot onpower down of the part. If operation is expected below -10 ° C ambient temperature and at less than 5-V input, itis recommended that a diode be connected from LVBP to DBP. (See Figure 16 ).
The TPS4007x provides separate signal ground (SGND) and power ground (PGND) pins. Care should be givento proper separation of the circuit grounds. Each ground should consist of a plane to minimize its impedance ifpossible. The high power noisy circuits such as the output, synchronous rectifier, MOSFET driver decouplingcapacitor (DBP), and the input capacitor should be connected to PGND plane.
Sensitive nodes such as the FB resistor divider and RT should be connected to the SGND plane. The SGNDplane should only make a single point connection to the PGND plane. It is suggested that the SGND pin be tiedto the copper area for the PowerPAD underneath the chip. Tie the PGND to the PowerPAD copper area as welland make the connection to the power circuit ground from the PGND pin. Reference the output voltage divider tothe SGND pin.
Copyright © 2003 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TPS40070 TPS40071
Output Ripple Consideration
TPS40070
TPS40071
SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 ..................................................................................................................................................
www.ti.com
Component placement should ensure that bypass capacitors (LVPB and DBP) are located as close as possibleto their respective power and ground pins. Also, sensitive circuits such as FB, RT and ILIM should not be locatednear high dv/dt nodes such as HDRV, LDRV, BOOST, and the switch node (SW). Failure to follow careful layoutpractices results in sub-optimal operation. More detailed information can be found in the TPS40071EVM User'sGuide (SLUU180).
In addition to the typical output ripple associated with switching converters, which can vary from 5 mV to150 mV, the TPS40070/1 exhibits a low-frequency ripple from 5 mV to 50 mV. The ripple, a consequence of thecharge pump in the driver supply regulator, is well bounded under changes in line, load, and temperature. Theripple frequency does vary with the converter switching frequency and can vary from 10 kHz to 60 kHz.
18 Submit Documentation Feedback Copyright © 2003 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS40070 TPS40071
SYNCHRONOUS RECTIFIER CONTROL
VDG−03175
VOUT
1.8 V
10 A
1
2
3
4
16
15
14
13
ILIM
VDD
BOOST
HDRV
KFF
RT
LVBP
PG
TPS40070PWP
TPS40071PWP
5
6
7
8
12
11
10
9
SW
DBP
LDRV
PGND
SGND
SS
VFB
COMP
+
C3
22 nF
C5
5.6 nF
12 V
+
−
PWP
C7
10 pF
Q2
Si7856DP
Q1
Si7840DP
+ +
C6
4.7 nF
C4 470 pF −
C12
22 µFC14
22 µF
L1
COEV
DXM1306−1R6
1.6 µH
C13
4.7 nF
C15
47 µFC16
470 µFC17
470 µFC18
0.1 µF
C8
0.1 µF
C9
1 µF
C10
0.1 µF
R6
165 kΩ
R2
165 kΩ
C2
0.1 µF
R5
10 kΩ
R3
5.49 kΩR8
226 Ω
VDD
R7 8.66 kΩ
R9
2 kΩ
1.5 Ω
TPS40070
TPS40071
www.ti.com
.................................................................................................................................................. SLUS582J – DECEMBER 2003 – REVISED APRIL 2009
Depending on which device is used the synchronous rectifier is controlled in slightly different ways. Table 2describes the differences. For proper operation, the total gate charge of the MOSFET connected to LDRV shouldbe less than 50 nC.
Table 2. Synchronous Rectifier MOSFET States
SYNCHRONOUS RECTIFIER OPERATION DURINGDEVICE
SOFT-START NORMAL FAULT OVERVOLTAGE
Turns OFF when I
ZERO
detected Turns Off when I
ZERO
detected or Turns OFF when I
ZERO
detected orTPS40070 OFFor start of next cycle start of next cycle start of next cycleTurns OFF only at start of next Turns OFF only at start of next cycle,TPS40071 Turns OFF only at start of next cycle ONcycle if duty cycle is > 0
Figure 14. 300 kHz, 12 V to 1.8 V
Copyright © 2003 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): TPS40070 TPS40071
1
2
3
4
16
15
14
13
ILIM
VDD
BOOST
HDRV
KFF
RT
LVPB
PG
TPS40070PWP
TPS40071PWP
5
6
7
8
12
11
10
9
SW
DBP
LDRV
PGND
SGND
SS
VFB
COMP
+
C3
22 nF
C5
5.6 nF
12 V
+
−
PWP
C7
10 pF
C13
4.7 nF
Q2
Si7856DP
Q1
Si7840DP
+ +
C6
4.7 nF
−
D1
BAT54
VDG−03176
C12
22 µFC14
22 µF
C15
47 µFC16
470 µFC17
470 µFC18
0.1 µF
C8
0.1 µF
C9 1 µF
C10
0.1 µF
R6
165 kΩ
R2
165 kΩ
C2
0.1 µF
R5
10 kΩ
R3
5.49 kΩR8
226 Ω
VDD
R7 8.66 kΩ
C4 470 pF
R9
2 kΩ
L1
COEV
DXM1306−1R6
1.6 µH
VOUT
1.8 V
10 A
1.5 Ω
TPS40070
TPS40071
SLUS582J – DECEMBER 2003 – REVISED APRIL 2009 ..................................................................................................................................................
www.ti.com
Figure 15. 300 kHz, 12 V to 1.8 V with Improved High-Side Gate Drive
See Application Information section Boost Diodes.
20 Submit Documentation Feedback Copyright © 2003 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS40070 TPS40071
VDG−03177
C12
22 µFC14
22 µF
C15
47 µFC16
470 µFC17
470 µFC18
0.1 µF
C8
0.1 µF
C9 1 µF
C10 0.1 µF
R6
47 kΩ
R2
90.1 kΩ
C2
0.1 µF
R5
10 kΩ
R3
12.1 kΩR8
226 Ω
VDD
R7 8.66 kΩ
R9
2 kΩ
R4 330 kΩ
L1
COEV
DXM1306−1R6
1.6 µHVOUT
1.2 V
10 A
1
2
3
4
16
15
14
13
ILIM
VDD
BOOST
HDRV
KFF
RT
PGD
TPS40070PWP
TPS40071PWP
5
6
7
8
12
11
10
9
SW
LDRV
PGND
SGND
SS
VFB
COMP
+
C3 22 nF
C5
5.6 nF
5 V
+
−
PWP
C7
10 pF
C13
4.7 nF
Q2
Si7860DP
Q1
Si7860DP
+ +
C6
4.7 nF
C4 470 pF −
LVBP
DBP
D1
BAT54
D2
BAT54
Note resistor across soft−start capacitor.
Diode D2 for operation below −10°C
1.5 Ω
TPS40070
TPS40071
www.ti.com
.................................................................................................................................................. SLUS582J – DECEMBER 2003 – REVISED APRIL 2009
Figure 16. 500 kHz, 5 V to 1.2 V with Improved High-Side Gate Drive
See Application Information section Boost Diodes.
Copyright © 2003 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): TPS40070 TPS40071
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS40070PWP NRND HTSSOP PWP 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS40070PWPG4 NRND HTSSOP PWP 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS40070PWPR NRND HTSSOP PWP 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS40070PWPRG4 NRND HTSSOP PWP 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS40071PWP NRND HTSSOP PWP 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS40071PWPG4 NRND HTSSOP PWP 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS40071PWPR NRND HTSSOP PWP 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS40071PWPRG4 NRND HTSSOP PWP 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 3-Jul-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS40070PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TPS40071PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS40070PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0
TPS40071PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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