INTEGRATED CIRCUITS DATA SEE | For a compiete data sheet, please also download: . ss The [O08 FAH C/HCT/NCU/NCMOS Logic Family Specifications | . os The (C08 74HOQVNCTYNCLYROMOS Logie Package Information | | The ICOS PANC/HOT/HCU/HCMOS Logic Package Outines | 74HC/HCT534 Octal D-type flip-flop; positive edge-trigger; 3-state; inverting Product specification 1998 Apr 10 Supersedes data of September 1993 File under Integrated Circuits, |CO6 Philips PHILIPS Semiconductors fsPhilips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state; inverting 74HC/HCT534 FEATURES * 3-state inverting outputs for bus oriented applications 8-bit positive, edge-triggered register Common 3-state output enable input Qutput capability: bus driver loco category: MSI. GENERAL DESCRIPTION The 74HC/HCT534 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V; Tamb = 25C; i; =4=-6ns The 74HC/HCT534 are octal D-type flip-flops featuring separate D-type inpuis for each flip-flop and inverting 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flaps. The & flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requiremenis on the LOW-io-HIGH CP transition. When OE is LOW, the contents of the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-staie. Operation of the OE input does not affect the state of the flip-flops. The 534 is functionally identical to the 374, but has inverted ouipuis. TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT teu! Ply propagation delay CP to Qn CL =15 pF; Vec=5V 112 13 ns imax maximum clock frequency 61 AO MHz C, input capacitance 3.5 3.5 pF Cpp power dissipation capacitance per flip-flop notes 1 and 2 19 19 pF Notes 1. Cpp is used to determine the dynamic power dissipation (Pp in pW): Pp = Cep x Vec x if + (CL x Veco? x fp) where: fi = input frequency in MHz. fo = output frequency in MHz. (CL x Vec? x fy) = sum of outputs. . = output load capacitance in pF. Voc = supply voltage in V. 2. Far HC the condition is V; = GND to Veg; for HCT the condition is V) = GND to Veg - 1.5 V. ORDERING INFORMATION TYPE PACK AGE NUMBER NAME DESCRIPTION VERSION 74HC534 sO20 plastic small outline package; 20 leads; body width 7.6 mm SOT163-1 74HC534 DIP20 | plastic dual in-line package; 20 leads (300 mil) SOT146-1 7AHCT534 5020 plastic small outline package; 20 leads; body width 7.6 mm SOT163-1 74HCT534 DBIP20 | plastic dual in-line package; 20 leads (300 mil) SOT146-1 1998 Apr 10Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; ar 74HC/HCT534 3-state; inverting PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1 OE 3-slate output enable input (active LOW) 2,5, 6,9, 12,15, 16,19 | Qo to Q7 3-slate outputs 3, 4, 7, 8, 13, 14, 17, 18 Dg to Dz data inputs 10 GND ground (0 V) 11 cP clock input (LOW-to-HIGH, edge-triggered) 20 Voc positive supply voliage oes U 20] Yoo 1 Qq [2 73] a | 11 11 cP Do [3] 18] 07 1, ay fo2 ; , 4 5 4b Qy o Dy [4] 17] Dg 7 1 1 6 4 5 af a] a _] P2 Q2 e | 534 +) dg Q3 jo 7 6 Q, [6] 15] Gs Bio, = ayo % 8 9 14 15 ,pD Qs }(o De [7] 14] Ds 17 | . a 16 13 12 d3 [8] 13] D4 18 | a, bo 2 14 15 Qs fe] fl ay e, 17 16 GND [ro] na] cp 1 MGM955 18 19 MGM956 MGM954 Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.8 IEC logic symbol. 1998 Apr 10 3Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger, ee gens 74HC/HCT534 3-state; inverting a 5 6 3-STATE 3 OUTPUTS 12 15 16 19 MGM957 Fig.4 Functional diagram. FUNCTION TABLE INPUTS OUTPUTS OPERATING MODES INTERNAL FLIP-FLOPS = = OE cP Dn Q) to Q; load and read register L tT | L H L tT h H L load register and disable outputs H tT | L Z H tT h H Z Note 1. Z = high impedance OFF-state; T = LOW-to-HIGH clock transition. 1998 Apr 10 H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level; | = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transitionPhilips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state; inverting 4 ah 4 ah 4 ah 4 ah 4 ah 4 ah 4 ah 4 Q cP cP cP cP cP cP cP cP FF FF FF FF FF FF FF FF 1 2 3 4 5 6 a 8 74HC/HCT534 Fig.6 Logic diagram. 1998 Apr 10 5Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; a 74HC/HCT534 3-state; inverting DC CHARACTERISTICS FOR 74HC For the DC characteristics see chapter 74HC/HCT/HCU/HCMOS Logic Family Specifications. Quiput capability: bus driver log category: MSI. AC CHARACTERISTICS FOR 74HC GND =0V;i,=% =6 ns; C, = 50 pF Tamb (C) TEST CONDITIONS 74HC SYMBOL |PARAMETER UNIT Voc WAVEFORMS +25 40 to +85 | -40 to +125 (VY) min. | typ. | max. | min. | max. | min. | max. tpHL/ tpl | propagation delay 41 165 205 250 |ns 2.0 | Fig.6 nP to nQ, 15 133 At 50 4.5 12 28 35 43 6.0 tpzH/ tpz_ | 3-state output enable 33 150 190 225 |ns 2.0 | Fig.7 time 12 | 30 38 45 45 OF to Qn 10 |26 33 38 6.0 tpHz/ tpiz | 3-state output disable 41 150 190 225 |ns 2.0 | Fig.7 time 15 |30 38 45 AS GE lo Gn 12 | 26 33 38 6.0 trot ttiy | output transition time 14 | 60 75 90 ns 2.0 | Fig.6 12 15 18 4.5 10 13 15 6.0 tw clock pulse width 80 19 100 120 ns 2.0 | Fig.6 HIGH or LOW 16 |7 20 24 45 14 6 17 20 6.0 tsu setup time 60 6 75 90 ns 2.0 | Fig.8 Dy te CP 12 12 15 18 4.5 10 2 13 15 6.0 th hald time 5 -3 5 5 ns 2.0 | Fig.8 Dn to GP 5 |-1 5 5 45 5 -1 5 5 6.0 imax maximum clock pulse 6.0 |18 4.8 4.0 MHz |2.0 | Fig.6 frequency 30 | 55 24 20 4.5 35 66 28 24 6.0 1998 Apr 10 6Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state; inverting 74HC/HCT534 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see chapter 74HC/HCT/HCU/HCMOS Logic Family Specifications. Quiput capability: bus driver log category: MSI. Note to HCT types The value of additional quiescent supply current (Alcc) for a unit load of 1 is given in the family specifications. To determine Algc per input, multiply this value by the unit load coefficient shown in the table below. UNIT LOAD COEFFICIENT 1.25 cP 0.90 Dn 0.35 AC CHARACTERISTICS FOR 74HCT GND =0V;i,=% =6 ns; C, = 50 pF Tamp (C) TEST CONDITIONS 74HCT SYMBOL |PARAMETER UNIT Voc WAVEFORMS +25 -40 to +85 | -40 to +125 () min. | typ. | max | min. | max. | min. | max. tpHi/ tpLH | propagation delay 16 |30 38 45 ns 4.5 Fig.6 CP io Q, tpzH/ tpz__ | 3-state output enable time 16 |30 38 45 ns 4.5 Fig.7 OE to Q, tpuz/ tpiz 3-state output disable 18 |30 38 A5 ns 4.5 Fig.7 time OE to Q, tTHL/ tTLH | output transition time 5 12 15 18 ns 4.5 Fig.6 tw clock pulse widih 23. | 14 29 35 ns A5 Fig.6 HIGH or LOW tsu set-up time 12 |4 15 18 ns A5 Fig.8 DB, te CP th hold time 5 -1 5 5 ns A5 Fig.8 Dn ta CP fmax maximum clock pulse 22 36 18 15 MHz |4.5 Fig.6 frequency 1998 Apr 10 7Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state; inverting 74HC/HCT534 AC WAVEFORMS GP INPUT _| Qp OUTPUT THL TTLH MeMase (1) HG: Vy = 50%; | = GND to Voc. HCT: Vy = 1.3 V; V)= GND to 3V. Fig.6 Waveforms showing the clock (CP) to output (Q,) propagation delays, the clock pulse width, output transition times and the maximum clock pulse frequency. OE INPUT Q, QUTPUT LOW-to-OFF OFF-to-LOW a, | 2, Q, OUTPUT 90% HIGH-10-OFF vu? OFF-to-HIGH outputs outputs _._ ouiputs enabled diaebled enabled MGMs61 (1) HG: Vy = 50%: V) = GND to Voc. HCT: Vy = 1.3 V; V = GND to 3 V. Fig.7 Waveforms showing the 3-state enable and disable times. 1998 Apr 10 8Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state; inverting 74HC/HCT534 GP INPUT Dy INPUT Q, OUTPUT Vall? MGM360 The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HG: Viy = 50%; V; = GND to Voc. HGT: Vy = 1.3 V; V| = GND to 3 V. Fig.8 Waveforms showing the data set-up and hold times tor D, input. 1998 Apr 10 9Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 74HC/HCT534 3-state; inverting PACKAGE OUTLINES DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1 a DB Me |- seating plane ~| b pe 20 | 11 _ M, #] Piro rire a fir Pin 1 index | -p-- _ _ _ _ | _ _ _ _ tt E | Le UU A UL a | 0 0 5 10mm (a scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A Ay Ag (4) (1) 20) UNIT max. min. max. b by c D E e 1 L Me Mu w max. 1.73 0.53 0.36 76.92 6.40 3.60 6.25 10.0 mm 42) 051 | 32 | 430 | 038 | 0.23 | 2654 | 622 | 254 | 762 | 305 | 790 | 33 | 0254) 20 . 0.068 0.021 0.014 1.060 0.25 0.14 0.32 0.39 inches | 0.17 | 0.920 | 0.13 | 9951 | 9.015 | 0.009 | 1.045 | o24 | 919 | 939 | gyo | o31 | 033 | 201 | 9.078 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE EUROPEAN ISSUE DATE VERSION IEC JEDEC EIAJ PROJECTION SOT146-1 $C603 i oe oon 1998 Apr 10 10Philips Semiconductors Octal D-type flip-flop; positive edge-trigger; 3-state; inverting Product specification 74HC/HCT534 $020: plastic small outline package; 20 leads; body width 7.5 mm $0T163-1 tt D a + +>_{A] | x LSJ Sa Cc y / | ad ly | He vie] v MO] Al ee 20 11 I t I | \ Q JA dt de Ag D | Ai m\ (A3) , pin 1 index i r= 0 a J ~~ Lp yw 1 10 detail X - [eo] ao few P 0 5 10mm L L ] L L L J scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT | vax. | AA Ad | As bp pM) | gM] He L La Q v w 74 | 6 0.30 | 2.45 049 | 0.32 | 13.0 | 7.6 10.65 14 11 0.9 mm | 265 | oto | 225 | 928 | 936 023) 126) 74 | 127 | tooo] 14 | o4 | to | 97) 975) Ot | ga | go o . 0.012 | 0.096 0.019 | 0.013) 0.51 | 0.30 0.419 0.043 | 0.043 0.035 | 9 inches | 9-19 | go94| 0089 | 9-21 | o1044/ 0.009/| 0.49 | 0.29 | 2-999 | g.394 | 9-995 | oco46 | o.03a | 997 | 9.01 | 9.004) 9 o1g Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION PROJECTION ISSUE DATE IEC JEDEC EIAJ SEAL SOT163-1 o75E04 MS-013AG =} } 97-05-22 1998 Apr 10 11Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state; inverting 74HC/HCT534 SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook 1026; integrated Circuit Packages (order code 9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tsig max). li the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. $0 REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding ageni) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. 1998 Apr 10 Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating methed. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. WAVE SOLDERING Wave soldering techniques can be used for all SO packages if the following conditions are observed: + A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. The longitudinal axis of the package footprint must be parallel to the solder flow. The package footprint mustincorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds ai up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 secands between 270 and 320 C.Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; ar 74HC/HCT534 3-state; inverting DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these producis can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1998 Apr 10 13