UPD67AMC-XXX-5A4-E2-A - Renesas Electronics - Datasheet.Directory

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2000

DATA SHEET

4-BIT SINGLE-CHIP MICROCONTROLLER

FOR INFRARED REMOTE CONTROL TRANSMISSION

DESCRIPTION

With their 2.0 V low-voltage operation, carrier generator for infrared remote control transmission, standby release

function through key input, and programmable timer, the

µ

PD67, 67A, 68, 68A, and 69 are ideal for infrared remote

control transmitters.

A one-time PROM product, the

µ

PD6P9, has also been provided for the

µ

PD67, 67A, 68, 68A, and 69 for program

evaluation or small-quantity production.

FEATURES

•Program memory (ROM)

•

µ

PD67, 67A: 1,002 × 10 bits

•

µ

PD68, 68A: 2,026 × 10 bits

•

µ

PD69: 4,074 × 10 bits

•Data memory (RAM)

•

µ

PD67, 67A, 68, 68A: 32 × 4 bits

•

µ

PD69: 128 × 4 bits

•On-chip carrier generator for infrared remote control: Each high-/low-level width can be set from 250 ns to 64

µ

s (@ fX = 4 MHz operation) via modulo registers

•9-bit programmable timer: 1 channel

•Instruction execution time: 16

µ

s (@ fX = 4 MHz operation: ceramic oscillation)

•Stack level: 1 level (Stack RAM is multiplexed with data memory RF.)

•I/O pins (KI/O): 8

•Input pins (KI): 4

•Sense input pins (S0, S2): 2

•S1/LED pin (I/O): 1 (when in output mode, this is the remote control transmission display pin)

•Power supply voltage: VDD = 2.0 to 3.6 V

•Operating ambient temperature: TA = –40 to +85°C

•Oscillator frequency: fX = 3.5 to 4.5 MHz

•On-chip POC circuit and RAM retention detector

•Capacitor for oscillator: 15 pF (mask option)

APPLICATIONS

Infrared remote control transmitters (for AV and household electric appliances)

MOS INTEGRATED CIRCUIT

µ

PD67, 67A, 68, 68A, 69

The mark shows major revised points.

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics

sales representative for availability and additional information.

Document No. U14935EJ2V1DS00 (2nd edition)

Date Published August 2005 N CP(K)

Printed in Japan

2

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

ORDERING INFORMATION

Part Number Package

µ

PD67MC-×××-5A4 20-pin plastic SSOP (7.62 mm (300))

µ

PD67AMC-×××-5A4 20-pin plastic SSOP (7.62 mm (300))

µ

PD68MC-×××-5A4 20-pin plastic SSOP (7.62 mm (300))

µ

PD68AMC-×××-5A4 20-pin plastic SSOP (7.62 mm (300))

µ

PD69MC-×××-5A4 20-pin plastic SSOP (7.62 mm (300))

µ

PD67MC-×××-5A4-A 20-pin plastic SSOP (7.62 mm (300))

µ

PD67AMC-×××-5A4-A 20-pin plastic SSOP (7.62 mm (300))

µ

PD68MC-×××-5A4-A 20-pin plastic SSOP (7.62 mm (300))

µ

PD68AMC-×××-5A4-A 20-pin plastic SSOP (7.62 mm (300))

µ

PD69MC-×××-5A4-A 20-pin plastic SSOP (7.62 mm (300))

Remarks 1. ××× indicates ROM code suffix.

2. Products that have the part numbers suffixed by “-A” are lead-free products.

PIN CONFIGURATION (TOP VIEW)

20-pin Plastic SSOP (7.62 mm (300))

Caution The pin numbers of KI and KI/O are in the reverse order of those in the

µ

PD6600A, and 6124A.

1

2

3

4

5

6

7

8

9

10

K

I/O6

K

I/O7

S

0

S

1

/LED

REM

V

DD

X

OUT

X

IN

GND

S

2

20

19

18

17

16

15

14

13

12

11

K

I/O5

K

I/O4

K

I/O3

K

I/O2

K

I/O1

K

I/O0

K

I3

K

I2

K

I1

K

I0

3

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

LIST OF FUNCTIONS

Item

µ

PD67, 67A

µ

PD68, 68A

µ

PD69

µ

PD6P9

ROM capacity 1,002 × 10 bits 2,026 × 10 bits 4,074 × 10 bits

Mask ROM One-time PROM

RAM capacity 32 × 4 bits 128 × 4 bits

Stack 1 level (multiplexed with RF of RAM)

I/O pins • Key input (KI): 4

•Key I/O (KI/O): 8

•Key extended input (S0, S1, S2): 3

•Remote control transmission display output (LED): 1 (multiplexed with S1 pin)

Number of keys • 32

•56 (when extended by key extension input)

Clock frequency Ceramic oscillation

•fX = 3.5 to 4.5 MHz

Instruction execution time 16

µ

s (@ fX = 4 MHz)

Carrier frequency Each high-/low-level width can be set from 250 ns to 64

µ

s (@ fX = 4 MHz operation)

via modulo registers

TimerNote 9-bit programmable timer: 1 channel, timer clock: fX/64

POC circuit On-chip

RAM retention detector On-chip

Capacitor for oscillation (15 pF) Mask option Set to be used/

not used in device

Supply voltage VDD = 2.0 to 3.6 V VDD = 2.2 to 3.6 V

Operating ambient temperature TA = –40 to +85°C

Package 20-pin plastic SSOP (7.62 mm (300))

BLOCK DIAGRAM

K

I0

to K

I3

K

I/O0

to K

I/O7

S

0

, S

1

/LED, S

2

Port K

I

Port K

I/O

Port S

4

8

3

4

8

3

ROM

RAM

System control

Carrier

generator

9-bit timer

CPU

core

X

IN

X

OUT

V

DD

GND

REM

S

1

/LED

Note The timer output time differs between the

µ

PD67, 68, and 69 and the

µ

PD67A and 68A. For details, refer

to 4 TIMER.

4

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

CONTENTS

1. PIN FUNCTIONS ............................................................................................................................ 6

1.1 List of Pin Functions ............................................................................................................ 6

1.2 Pin I/O Circuits ...................................................................................................................... 7

1.3 Connection of Unused Pins................................................................................................. 8

2. INTERNAL CPU FUNCTIONS ..................................................................................................... 9

2.1 Program Counter (PC) .......................................................................................................... 9

2.2 Stack Pointer (SP) ................................................................................................................. 9

2.3 Address Stack Register (ASR (RF)).................................................................................... 9

2.4 Program Memory (ROM)....................................................................................................... 10

2.5 Data Memory (RAM) .............................................................................................................. 11

2.6 Data Pointer (DP) .................................................................................................................. 12

2.7 Accumulator (A) .................................................................................................................... 12

2.8 Arithmetic and Logic Unit (ALU)......................................................................................... 12

2.9 Flags ....................................................................................................................................... 13

2.9.1 Status flag (F) .............................................................................................................................. 13

2.9.2 Carry flag (CY) ............................................................................................................................ 13

3. PORT REGISTERS (PX) .............................................................................................................. 14

3.1 KI/O Port (P0) .......................................................................................................................... 15

3.2 KI Port/Special Ports (P1)..................................................................................................... 15

3.2.1 KI port (P11: bits 4 to 7 of P1) ..................................................................................................... 15

3.2.2 S0 port (bit 2 of P1) ..................................................................................................................... 16

3.2.3 S1/LED (bit 3 of P1) ..................................................................................................................... 16

3.2.4 S2 port (bit 1 of P1) ..................................................................................................................... 16

3.3 Control Register 0 (P3) ......................................................................................................... 17

3.3.1 RAM retention flag (bit 3 of P3) .................................................................................................. 18

3.4 Control Register 1 (P4) ......................................................................................................... 19

4. TIMER .............................................................................................................................................. 20

4.1 Timer Configuration .............................................................................................................. 20

4.2 Timer Operation .................................................................................................................... 21

4.3 Carrier Output ........................................................................................................................ 23

4.3.1 Carrier output generator .............................................................................................................. 23

4.3.2 Carrier output control .................................................................................................................. 24

4.4 Software Control of Timer Output....................................................................................... 26

5. STANDBY FUNCTION ................................................................................................................... 27

5.1 Outline of Standby Function ............................................................................................... 27

5.2 Standby Mode Setting and Release ................................................................................... 28

5.3 Standby Mode Release Timing ............................................................................................ 30

6. RESET ............................................................................................................................................. 31

5

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

7. POC CIRCUIT................................................................................................................................. 32

7.1 Functions of POC Circuit ..................................................................................................... 33

7.2 Oscillation Check at Low Supply Voltage .......................................................................... 33

8. SYSTEM CLOCK OSCILLATOR.................................................................................................. 34

9. INSTRUCTION SET ....................................................................................................................... 35

9.1 Machine Language Output by Assembler ......................................................................... 35

9.2 Circuit Symbol Description ................................................................................................. 36

9.3 Mnemonic to/from Machine Language (Assembler Output) Contrast Table ................ 37

9.4 Accumulator Manipulation Instructions ............................................................................ 41

9.5 I/O Instructions ...................................................................................................................... 44

9.6 Data Transfer Instructions ................................................................................................... 45

9.7 Branch Instructions .............................................................................................................. 47

9.8 Subroutine Instructions ....................................................................................................... 48

9.9 Timer Operation Instructions .............................................................................................. 49

9.10 Others ..................................................................................................................................... 52

10. ASSEMBLER RESERVED WORDS ............................................................................................ 54

10.1 Mask Option Directives ........................................................................................................ 54

10.1.1 OPTION and ENDOP quasi-directives ....................................................................................... 54

10.1.2 Mask option definition quasi-directives ...................................................................................... 54

11. ELECTRICAL SPECIFICATIONS.................................................................................................. 55

12. CHARACTERISTIC CURVES (REFERENCE VALUES) ............................................................ 59

13. APPLICATION CIRCUIT EXAMPLE ............................................................................................ 60

14. PACKAGE DRAWINGS.................................................................................................................. 63

15. RECOMMENDED SOLDERING CONDITIONS ........................................................................... 64

APPENDIX A. DEVELOPMENT TOOLS ............................................................................................ 65

APPENDIX B. FUNCTIONAL COMPARISON BETWEEN

µ

PD67A, 68A, 69,

AND OTHER PRODUCTS......................................................................................... 66

APPENDIX C. EXAMPLE OF REMOTE-CONTROL TRANSMISSION FORMAT (in the case of

NEC transmission format in command one-shot transmission mode) .............. 67

6

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

1. PIN FUNCTIONS

1.1 List of Pin Functions

Pin No. Symbol Function Output Format After Reset

1KI/O0 to KI/O7 CMOS High-level output

2push-pullNote 1

15 to 20

3S0—High-impedance

(OFF mode)

4S1/LED CMOS push-pull High-level output

(LED)

5REM CMOS push-pull Low-level output

6VDD ——

7XOUT —Low level

8XIN (oscillation stopped)

9GND ——

10 S2—Input

(high-impedance,

STOP mode

release cannot be

used)

11 to 14

K

I0

to K

I3

Note 2

—Input (low-level)

Notes 1. Be careful about this because the drive capacity of the low-level output side is held low.

2. In order to prevent malfunction, be sure to input a low level to one or more of pins KI0 to KI3 when

POC is released by supply voltage rising (Can be left open. When open, leave the pull-down resistor

connected).

8-bit I/O port. Input/output can be specified in 8-bit units.

In input mode, the use of a pull-down resistor can be

specified.

In output mode, these pins can be used as key scan

outputs from a key matrix.

Input port.

Can also be used as a key return input from a key matrix.

In input mode, the use of a pull-down resistor for the S0

and S1 ports can be specified by software in 2-bit units.

If input mode is canceled by software, this pin is placed

in OFF mode and enters a high-impedance state.

I/O port.

In input mode (S1), this pin can also be used as a key

return input from a key matrix.

The use of a pull-down resistor for the S0 and S1 ports

can be specified by software in 2-bit units.

In output mode (LED), this pin becomes the remote

control transmission display output (active low). When

the remote control carrier is output from the REM output,

this pin outputs a low level from the LED output in

synchronization with the REM signal.

Infrared remote control transmission output.

This output is active high.

Each carrier high-/low-level width can be freely set in

a range of 250 ns to 64

µ

s (@ fX = 4 MHz) by

software.

Power supply

Pins for connecting ceramic resonators for the system

clock.

A capacitor (15 pF) for the oscillator can be specified by

a mask option.

GND

Input port.

The use of STOP mode release for the S2 port can be

specified by software. When used as a key input from

a key matrix, enable the use of STOP mode release (at

this time, a pull-down resistor is connected internally.)

When STOP mode release is disabled, this pin can be

used as an input port that does not release the STOP

mode even if the release condition is established

(at this time, a pull-down resistor is not connected internally.)

4-bit input port.

These pins can also be used as a key return inputs

from a key matrix. The use of a pull-down resistor

can be specified by software in 4-bit units.

7

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

1.2 Pin I/O Circuits

The I/O circuits of pins of the

µ

PD67, 67A, 68, 68A, and 69 are shown in partially simplified forms below.

(1) KI/O0 to KI/O7 (4) S0

(5) S1/LED

Note The drive capacity is held low.

(2) KI0 to KI3

(3) REM (6) S2

P-ch

N-chNote

N-ch

V

DD

Output

latch

Input buffer

Data

Output

disable

Selector

N-ch

Input buffer

Pull-down flag

Standby

release

P-ch

N-ch

VDD

Output

latch

Carrier

generator

Data

OFF mode

Pull-down flag N-ch

Standby

release

Input buffer

N-ch

Input buffer

STOP release

ON/OFF

Standby

release

P-ch

N-ch

N-ch

V

DD

REM

output latch

Input buffer

Output

disable

Pull-down flag

Standby

release

8

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

1.3 Connection of Unused Pins

The following connections are recommended for unused pins.

Table 1-1. Connection of Unused Pins

Pin Connection

Inside the Microcontroller Outside the Microcontroller

KI/O Input mode — Leave open.

Output mode High-level output

REM —

S1/LED Output mode (LED) setting

S0OFF mode setting Directly connect to GND.

S2—

K1—

Caution The I/O mode and the pin output level are recommended to be fixed by setting them

repeatedly in each loop of the program.

9

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

2. INTERNAL CPU FUNCTIONS

2.1 Program Counter (PC): 11 Bits (

µ

PD67, 67A, 68, 68A)

12 Bits (

µ

PD69)

The program counter (PC) is a binary counter that holds the address information of the program memory.

Figure 2-1. Program Counter Configuration

The PC contains the address of the instruction that should be executed next. Normally, the counter contents

are automatically incremented in accordance with the instruction length (byte count) each time an instruction is

executed.

However, when executing jump instructions (JMP, JC, JNC, JF, JNF), the PC contains the jump destination

address written in the operand.

When executing the subroutine call instruction (CALL), the call destination address written in the operand is

entered in the PC after the PC contents at the time are saved in the address stack register (ASR). If the return

instruction (RET) is executed after the CALL instruction is executed, the address saved in the ASR is restored to

the PC.

After reset, the value of the PC becomes “000H”.

2.2 Stack Pointer (SP): 1 Bit

This is a 1-bit register that holds the status of the address stack register.

The stack pointer contents are incremented when the call instruction (CALL) is executed and decremented when

the return instruction (RET) is executed.

When reset, the stack pointer contents are cleared to 0.

When the stack pointer overflows (stack level 2 or more) or underflows, the CPU is defined as hung up, a system

reset signal is generated, and the PC becomes 000H.

As no instruction is available to set a value directly for the stack pointer, it is not possible to operate the pointer

by means of a program.

2.3 Address Stack Register (ASR (RF)): 11 Bits (

µ

PD67, 67A, 68, 68A)

12 Bits (

µ

PD69)

The address stack register saves the return address of the program after a subroutine call instruction is executed.

The lower 8 bits are allocated in RF of the data memory as a alternate-function RAM. The register holds the

ASR value even after the RET instruction is executed.

After reset, it holds the previous data (undefined when turning on the power).

Caution If RF is accessed as the data memory, the higher 3 bits of the

µ

PD67, 67A, 68, and 68A, and

higher 4 bits of the

µ

PD69 become undefined.

Figure 2-2. Address Stack Register Configuration

PC9PC10 PC0PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1

PD67, 67A, 68, 68A

PC11

PD69

µ

µ

PC

ASR10 ASR9 ASR8 ASR7 ASR6 ASR5 ASR4 ASR3 ASR2 ASR1 ASR0ASR

RF

PD69

µ

µ

ASR11

PD67, 67A, 68, 68A

10

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

2.4 Program Memory (ROM): 1,002 Steps × 10 Bits (

µ

PD67, 67A)

2,026 Steps × 10 Bits (

µ

PD68, 68A)

4,074 Steps × 10 Bits (

µ

PD69)

The ROM consists of 10 bits per step, and is addressed by the program counter.

The program memory stores programs and table data, etc.

The 22 steps from 7EAH to 7FFH of the

µ

PD67, 67A, 68, and 68A, and FEAH to FFFH of the

µ

PD69 cannot

be used in the test program area.

Figure 2-3. Program Memory Map

Note The unmounted area and test program area are designed so that a program or data placed in either of

them by mistake is returned to the 000H address.

10 bits

Page 0

0

3

4

7

7

7

0

3

3

7

7

7

Unmounted areaNote

Test program areaNote Test program areaNote

Page 0

Page 1

10 bits

(a) PD67, 67A (b) PD68, 68A

µµ

0

7

8

F

F

F

Test program areaNote

Page 0

10 bits

(c) PD69

µ

3

4

B

C

Page 1

Page 2

Page 3

H

H

H

H

H

H

0

F

0

9

A

F

0

F

0

E

E

F

H

H

H

H

H

H

0

9

A

9

A

F

0

E

E

E

E

F

H

H

H

H

H

H

H

H

H

H

0

F

0

9

A

F

F

0

F

0

0

F

0

E

E

F

F

0

F

0

11

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

2.5 Data Memory (RAM): 32 × 4 Bits (

µ

PD67, 67A, 68, 68A)

128 × 4 Bits (

µ

PD69)

The data memory, which is a static RAM consisting of 32 × 4 bits, is used to retain processed data. The data

memory is sometimes processed in 8-bit units. R0 can be used as the ROM data pointer.

RF is also used as the ASR.

After reset, R0 is cleared to 00H and R1 to RF retain the previous data (undefined when turning on the power).

Figure 2-4. Data Memory Configuration

R0

R1

R2

R3

R4

R5

R6

R7

R8

R9

RA

RB

RC

RD

RE

RF

R

10

R

00

R

11

R

01

R

12

R

02

R

13

R

03

R

14

R

04

R

15

R

05

R

16

R

06

R

17

R

07

R

18

R

08

R

19

R

09

R

1A

R

0A

R

1B

R

0B

R

1C

R

0C

R

1D

R

0D

R

1E

R

0E

R

1F

R

0F

→DP (refer to 2.6 Data Pointer (DP))

→ASR (refer to 2.3 Address Stack Register (ASR (RF)))

R1n (higher 4 bits) R0n (lower 4 bits)

R0

R1

R2

R3

R4

R5

R6

R7

R8

R9

RA

RB

RC

RD

RE

RF

R

10

R

00

R

11

R

01

R

12

R

02

R

13

R

03

R

14

R

04

R

15

R

05

R

16

R

06

R

17

R

07

R

18

R

08

R

19

R

09

R

1A

R

0A

R

1B

R

0B

R

1C

R

0C

R

1D

R

0D

R

1E

R

0E

R

1F

R

0F

R1n (higher 4 bits) R0n (lower 4 bits)

Page 0Note

Pages 1 to 3Note

Note

µ

PD67, 67A, 68, 68A: Page 0

µ

PD69: Pages 0 to 3 (pages can be switched using bits 0 and 1 of control register 0)

12

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

2.6 Data Pointer (DP): 12 Bits

The ROM data table can be referenced by setting the ROM address in the data pointer to call the ROM contents.

The lower 8 bits of the ROM address are specified by R0 of the data memory; and the higher 4 bits by bits 4

to 7 of the P3 register (CR0).

After reset, the pointer contents become 000H.

Figure 2-5. Data Pointer Configuration

Note Set DP10 and DP11 to 0 in the case of the

µ

PD67 and 67A, and set DP10 to 0 in the case of the

µ

PD68

and 68A.

2.7 Accumulator (A): 4 Bits

The accumulator, which refers to a register consisting of 4 bits, plays a leading role in performing various

operations.

After reset, the accumulator contents are left undefined.

Figure 2-6. Accumulator Configuration

A3A2A1A0A

2.8 Arithmetic and Logic Unit (ALU): 4 Bits

The arithmetic and logic unit (ALU), which refers to an arithmetic circuit consisting of 4 bits, executes simple

(mainly logical) operations.

R

00

DP

9

DP

8

DP

7

DP

6

DP

5

DP

4

DP

3

DP

2

DP

1

DP

0

R

10

R0

b

4

b

5

P3

register

P

3

DP

10Note

b

6

DP

11Note

b

7

13

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

2.9 Flags

2.9.1 Status flag (F)

Pin and timer statuses can be checked by executing the STTS instruction to check the status flag.

The status flag is set (to 1) in the following cases.

•If the condition specified with the operand is met when the STTS instruction is executed

•When standby mode is released.

•When the release condition is met at the point of executing the HALT instruction. (In this case, the system

does not enter the standby mode.)

Conversely, the status flag is cleared (to 0) in the following cases:

•If the condition specified with the operand is not met when the STTS instruction is executed.

•When the status flag has been set (to 1), the HALT instruction executed, but the release condition is not met

at the point of executing the HALT instruction. (In this case, the system does not enter the standby mode.)

Table 2-1. Conditions for Status Flag (F) to Be Set by STTS Instruction

Operand Value of STTS Instruction Condition for Status Flag (F) to Be Set

b3b2b1b0

0000High level is input to at least one of KI pins.

011High level is input to at least one of KI pins.

110High level is input to at least one of KI pins.

101The down counter of the timer is 0.

1Either of the combinations [The following condition is added in addition to the above.]

of b2, b1, and b0 above. High level is input to at least one of S0Note 1, S1Note 1, or S2Note 2 pins.

Notes 1. The S0 and S1 pins must be set to input mode (bit 2 and bit 0 of the P4 register are set to 0 and 1,

respectively).

2. The use of STOP mode release for the S2 pin must be enabled (bit 3 of the P4 register is set to 1).

2.9.2 Carry flag (CY)

The carry flag is set (to 1) in the following cases:

•If the ANL instruction or the XRL instruction is executed when bit 3 of the accumulator is 1 and bit 3 of the

operand is 1.

•If the RL instruction or the RLZ instruction is executed when bit 3 of the accumulator is 1.

•If the INC instruction or the SCAF instruction is executed when the value of the accumulator is 0FH.

The carry flag is cleared (to 0) in the following cases:

•If the ANL instruction or the XRL instruction is executed when at least either bit 3 of the accumulator or bit

3 of the operand is 0.

•If the RL instruction or the RLZ instruction is executed when bit 3 of the accumulator is 0.

•If the INC instruction or the SCAF instruction is executed when the value of the accumulator is other than 0FH.

•If the ORL instruction is executed.

•When data is written to the accumulator by the MOV instruction or the IN instruction.

14

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

3. PORT REGISTERS (PX)

The KI/O port, the KI port, the special ports (S0, S1/LED, S2), and the control registers are treated as port registers.

After reset, the port register values are as shown below.

Figure 3-1. Port Register Configuration

Notes 1. ×: Refers to the value based on the KI and S2 pin state.

2. ×: Refers to the value based on decrease of power supply voltage (0 when VDD ≤ VID)

Remark VID: RAM retention detection voltage

Table 3-1. Relationship Between Ports and Reading/Writing

Port Name Input Mode Output Mode

Read Write Read Write

KI/O Pin state Output latch Output latch Output latch

KIPin state — — —

S0Pin state — Note —

S1/LED Pin state — Pin state —

S2Pin state — — —

Note When in OFF mode, “1” is always read.

Port register

P0

K

I/O7

P

00

After reset

FFH

K

I/O6

K

I/O5

K

I/O4

K

I/O3

K

I/O2

K

I/O1

K

I/O0

P

10

P1

K

I3

P

01

××××11×1B

Note 1

K

I2

K

I1

K

I0

S

1

/LED S

0

S

2

1

P

11

P3 (control register 0)

DP

11

P

03

0000×000B

Note 2

DP

10

DP

9

DP

8

RAM

retention

flag

–ID1ID0

P

13

P4 (control register 1)

0

P

04

26H

0K

I

Pull-down

S

0

/S

1

Pull-down

S

2

STOP release

S

1

/LED mode K

I/O

mode S

0

mode

P

14

15

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

3.1 KI/O Port (P0)

The KI/O port is an 8-bit I/O port for key scan output.

I/O mode is set by bit 1 of the P4 register.

If a read instruction is executed, the pin state can be read in input mode, whereas the output latch contents can

be read in output mode.

If a write instruction is executed, data can be written to the output latch regardless of input or output mode.

After reset, the port is placed in output mode and the value of the output latch (P0) becomes 1111 1111B.

The KI/O port incorporates a pull-down resistor, allowing pull-down in input mode only.

Caution When a key is double-pressed, a high-level output and a low-level output may conflict at the

KI/O port. To avoid this, the low-level output current of the KI/O port is held low. Therefore, be

careful when using the KI/O port for purposes other than key scan output.

The KI/O port is designed so that even when connected directly to VDD within the normal supply

voltage range (VDD = 2.0 to 3.6 V), no problem occurs.

Table 3-2. KI/O Port (P0)

Bit b7b6b5b4b3b2b1b0

Name KI/O7 KI/O6 KI/O5 KI/O4 KI/O3 KI/O2 KI/O1 KI/O0

b0 to b7:When reading: In input mode, the KI/O pin’s state is read.

In output mode, the KI/O pin’s output latch contents are read.

When writing: Data is written to the KI/O pin’s output latch regardless of input or output mode.

3.2 KI Port/Special Ports (P1)

3.2.1 KI port (P11: bits 4 to 7 of P1)

The KI port is a 4-bit input port for key input. The pin state can be read.

The use of a pull-down resistor for the KI port can be specified in 4-bit units by software using bit 5 of the P4

register. After reset, a pull-down resistor is connected.

Table 3-3. KI/Special Port Register (P1)

Bit b7b6b5b4b3b2b1b0

Name KI3 KI2 KI1 KI0 S1/LED S0S2Fixed to “1”

b1:The state of the S2 pin is read (read only).

b2:In input mode, state of the S0 pin is read (read only).

In OFF mode, this bit is fixed to 1.

b3:The state of the S1/LED pin is read regardless of input/output mode (read only).

b4 to b7:The state of the KI pin is read (read only).

Caution In order to prevent malfunction, be sure to input a low level to one or more of pins KI0 to KI3

when POC is released by supply voltage rising (Can be left open. When open, leave the pull-

down resistor connected).

16

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

3.2.2 S0 port (bit 2 of P1)

The S0 port is an input/OFF mode port.

The pin state can be read by setting this port to input mode using bit 0 of the P4 register.

In input mode, the use of a pull-down resistor for the S0 and S1/LED port can be specified in 2-bit units by software

using bit 4 of the P4 register.

If input mode is released (thus set to OFF mode), the pin becomes high-impedance but is configured so that

through current does not flow internally. In OFF mode, 1 can be read regardless of the pin state.

After reset, S0 is set to OFF mode, thus becoming high-impedance.

3.2.3 S1/LED port (bit 3 of P1)

The S1/LED port is an I/O port.

Input or output mode can be set using bit 2 of the P4 resister. The pin state can be read in both input mode

and output mode.

When in input mode, the use of a pull-down resistor for the S0 and S1/LED ports can be specified in 2-bit units

by software using bit 4 of the P4 register.

When in output mode, the pull-down resistor is automatically disconnected and this pin becomes the remote

control transmission display pin (refer to 4 TIMER).

After reset, S1/LED is placed in output mode, and a high level is output.

3.2.4 S2 port (bit 1 of P1)

The S2 port is an input port.

Use of STOP mode release for the S2 port can be specified by bit 3 of the P4 register.

When using the pin as a key input from a key matrix, enable (bit 3 of the P4 register is set to 1) the use of STOP

mode release (at this time, a pull-down resistor is connected internally.) When STOP mode release is disabled

(bit 3 of the P4 register is set to 0), it can be used as an input port that does not release the STOP mode even if

the release condition is met (at this time, a pull-down resistor is not connected internally.)

The state of the pin can be read in both cases.

After reset, S2 is set to input mode where the STOP mode release is disabled, and enters a high-impedance

state.

17

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

3.3 Control Register 0 (P3)

Control register 0 consists of 8 bits. The contents that can be controlled are as shown below.

After reset, the register becomes 0000 ×000BNote.

Note ×: Refers to the value based on a decrease of power supply voltage (0 when VDD ≤ VID)

Remark VID: RAM retention detection voltage

Table 3-4. Control Register 0 (P3)

(1)

µ

PD67, 67A, 68, 68A

Bit b7Note b6Note b5b4b3b2b1b0

Name DP (Data Pointer) — ID0

DP11 DP10 DP9DP8

Setting 0 0 0 0 0

Not retainable

Fixed to 0

11 111

Retainable

After reset 0 0 0 0 ×000

(2)

µ

PD69

Bit b7b6b5b4b3b2b1b0

Name DP (Data Pointer) — ID1 ID0

DP11 DP10 DP9DP8

Setting 0 0 0 0 0

Not retainable

Fixed to 0

Specification of

11 111

Retainable

PAGE0 to PAGE3

After reset 0 0 0 0 ×000

b0, b1:Specify RAM pages 0 to 3 (

µ

PD69 only). Fixed to 0 in the

µ

PD67, 67A, 68, and 68A.

ID1 ID0 RAM

00Page 0

01Page 1

10Page 2

11Page 3

b3:RAM retention flag. For function details, refer to 3.3.1 RAM retention flag (bit 3 of P3).

b4 to b7:Specify the higher bits of the ROM data pointer (DP8 to DP11).

Note Set b7 and b6 to 0 in the case of the

µ

PD67 and 67A, and set b7 to 0 in the case of the

µ

PD68 and 68A.

RAM

retention

flag

RAM

retention

flag

18

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

3.3.1 RAM retention flag (bit 3 of P3)

The RAM retention flag indicates whether the supply voltage has fallen below the level at which the contents

of the RAM are lost while the battery is being exchanged or when the battery voltage has dropped.

This flag is at bit 3 of control register 0 (P3).

It is cleared to 0 if the supply voltage drops below the RAM retention detection voltage (approx. 1.4 V TYP.).

If this flag is 0, it can be judged that the RAM contents have been lost or that power has just been applied. This

flag can be used to initialize the RAM via software. After initializing the RAM and writing the necessary data to it,

set this RAM retention flag to 1 by software. At this time, 1 means that data has been set to the RAM.

Figure 3-2. Supply Voltage Transition and Detection Voltage

(1) If the supply voltage rises after the battery has been set, and exceeds VPOC (POC detection voltage),

reset is cleared. Because the supply voltage rises from 0 V, which is lower than VID (RAM retention

detection voltage), the RAM retention flag remains in the initial status 0.

(2) The supply voltage has now risen to the level at which the device can operate. Write the necessary data

to the RAM and set the RAM retention flag to 1.

(3) The device is reset if the supply voltage drops below VPOC. At point (A) in the above figure, the RAM

retention flag remains 1 because the supply voltage is higher than VID at this point.

(4) If the RAM retention flag is checked by software after reset has been cleared, it is 1. This means that

the contents of the RAM have not been lost. It is therefore not necessary to initialize the RAM by software.

(5) The device is reset if the supply voltage drops below VPOC. At point (B) in the figure, the voltage is lower

than VID. Consequently, the RAM retention flag is cleared to 0.

(6) If the RAM retention flag is checked by software after reset has been cleared, it is 0. This means that

the contents of the RAM may have been lost. If this case, initialize the RAM by software.

V

DD

V

POC

V

ID

0 V

RAM retention flag

(A)

(B)

(6)(5)(4)(3)(2)

Set to 1 Flag contents

are read

Flag contents

are read

(1)

t

POC detection voltage

(Refer to 7. POC CIRCUIT)

V

POC

= 1.85 V (TYP.)

RAM retention detection voltage

V

ID

= 1.4 V (TYP.)

19

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

3.4 Control Register 1 (P4)

Control register 1 consists of 8 bits. The contents that can be controlled are as shown below.

After reset, the register becomes 0010 0110B.

Table 3-5. Control Register 1 (P4)

Bit b7b6b5b4b3b2b1b0

Name — — KIS0/S1S2S1/LED KI/O S0

Pull-down Pull-down

STOP release

mode mode mode

Setting 0 Fixed Fixed OFF OFF Disable S1IN OFF

1to 0 to 0 ON ON Enable LED OUT IN

After reset 00100110

b0:Specifies the input mode of the S0 port. 0 = OFF mode (high impedance); 1 = IN (input mode).

b1:Specifies the I/O mode of the KI/O port.

0 = IN (input mode); 1 = OUT (output mode).

b2:Specifies the I/O mode of the S1/LED port. 0 = S1 (input mode); 1 = LED (output mode).

b3:Specified the use of STOP mode release by S2 port (with/without pull-down resistor). 0 = disable (without

pull-down); 1 = enable (with pull-down).

b4:Specifies the use of a pull-down resistor in S0/S1 port input mode. 0 = OFF (not used);

1 = ON (used)

b5:Specifies the use of a pull-down resistor for the KI port. 0 = OFF (not used);

1 = ON (used).

Remark In output mode or in OFF mode, all the pull-down resistors are automatically disconnected.

20

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

4. TIMER

4.1 Timer Configuration

The timer is the block used for creating a remote control transmission pattern. As shown in Figure 4-1, it consists

of a 9-bit down counter (t8 to t0), a flag (t9) permitting the 1-bit timer output, and a zero detector.

Figure 4-1. Timer Configuration

S1/LED

REM

Carrier

synchronous

circuit

Carrier signal

Zero detector

9-bit down counter

t9t8t7t6t5t4t3t2t1t0

T

T1

fX/64

Timer operation end signal

(HALT # ×101B release

signal)

Count

clock

T0

21

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

4.2 Timer Operation

The timer starts (counting down) when a value other than 0 is set for the down counter with a timer manipulation

instruction. The timer manipulation instructions for making the timer start operation are shown below:

MOV T0, A

MOV T1, A

MOV T, #data10

MOV T, @R0

The down counter is decremented (–1) in the cycle of 64/fX. If the value of the down counter becomes 0, the

zero detector generates the timer operation end signal to stop the timer operation. At this time, if the timer is in

HALT mode (HALT #×101B) waiting for the timer to stop its operation, the HALT mode is released and the instruction

following the HALT instruction is executed. The output of the timer operation end signal is continued while the down

counter is 0 and the timer is stopped. The following relational expression applies between the timer’s output time

and the down counter’s set value.

(a)

µ

PD67, 68, and 69

Timer output time = (Set value + 1) × 64/fX

(b)

µ

PD67A and 68A

Timer output time = (Set value + 1) × 64/fX – 4/fX

In addition, when the timer is set successively, in the

µ

PD67A and 68A, the timer output time is also 4/fX shorter

than the total time. An example is shown below.

Example When fX = 4 MHz

MOV T, #3FFH

STTS #05H

HALT #05H

MOV T, #232H

STTS #05H

HALT #05H

In the case above, the timer output time is as follows.

(a)

µ

PD67, 68, and 69

(Set value + 1) × 64/fX + (Set value + 1) × 64/fX

= (511 + 1) × 64/4 + (50 + 1) × 64/4

= 9.008 ms

(b)

µ

PD67A and 68A

(Set value + 1) × 64/fX + (Set value + 1) × 64/fX – 4/fX

= (511 +1) × 64/4 + (50 +1) × 64/4 – 4/4

= 9.007 ms

22

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

By setting the flag (t9) that enables the timer output to 1, the timer can output its operation status from the S1/

LED pin and the REM pin. The REM pin can also output the carrier while the timer is in operation.

Table 4-1. Timer Output (at t9 = 1)

S1/LED Pin REM Pin

Timer operating Low level High level (or carrier outputNote)

Timer halting High level Low level

Note The carrier output results if bit 9 (CARY) of the high-level period setting modulo register (MOD1) is cleared

(to 0).

Figure 4-2. Timer Output (When Carrier Is Not Output)

(a)

µ

PD67, 68, and 69

(b)

µ

PD67A and 68A

Timer output time:

(Set value + 1) × 64/fX

LED

REM

Timer output time:

(Set value + 1) × 64/fX – 4/fX

LED

REM

4/fX

23

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

4.3 Carrier Output

4.3.1 Carrier output generator

The carrier generator consists of a 9-bit counter and two modulo registers for setting the high- and low-level

periods (MOD1 and MOD0 respectively).

Figure 4-3. Configuration of Remote Controller Carrier Generator

Notes 1. Bit 9 of the modulo register for setting the low-level period (MOD0) is fixed to 0.

2. t9: Flag that enables timer output (timer block) (see Figure 4-1 Timer Configuration)

The carrier duty ratio and carrier frequency can be determined by setting the high- and low-level widths using

the respective modulo registers. Each of these widths can be set in a range of 250 ns to 64

µ

s (@ fX = 4 MHz).

The system clock multiplied by 2 is used for the 9-bit counter input (8 MHz when fX = 4 MHz). MOD0 and MOD1

are read and written using timer manipulation instructions.

MOV A, M00 MOV M00, A MOV M0, #data10

MOV A, M01 MOV M01, A MOV M1, #data10

MOV A, M10 MOV M10, A MOV M0, @R0

MOV A, M11 MOV M11, A MOV M1, @R0

The values of MOD0 and MOD1 can be calculated from the following expressions.

MOD0 = (2 × fX × (1 – D) × T) – 1

MOD1 = (2 × fX × D × T) – 1

Caution Be sure to input values in range of 001H to 1FFH to MOD0 and MOD1.

Remark D: Carrier duty ratio (0 < D < 1)

fX:Input clock (MHz)

T: Carrier cycle (

µ

s)

Carrier signal

F/F

Match

Clear

M11

t

9

CARY

Modulo register for setting the high-level period (MOD1)

Modulo register for setting the low-level period (MOD0)Note 1

t

8

t

7

t

6

t

5

t

4

t

3

t

2

t

1

t

0

t

8

0t

7

t

6

t

5

t

4

t

3

t

2

t

1

t

0

2f

X

f

X

f

X

t

9Note 2

M10

M1 M01

Selector

Comparator

9-bit counter

Multiplier

M00

M0

24

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

4.3.2 Carrier output control

Remote controller carrier can be output from the REM pin by clearing (0) bit 9 (CARY) of the modulo register

for setting the high-level period (MOD1).

When performing carrier output, be sure to set the timer operation after setting the MOD0 and MOD1 values.

Note that a malfunction may occur if the values of MOD0 and MOD1 are changed while carrier is being output from

the REM pin.

Executing the timer manipulation instruction starts the carrier output from the low level.

If the timer’s down counter reaches 0 during carrier output, carrier output is stopped and the REM pin becomes

low level. If the down counter reaches 0 while the carrier output is high level, carrier output will stop after first

becoming low level following the set period of high level.

Figure 4-4. Timer Output (When Carrier Is Output)

(a)

µ

PD67, 68, and 69

(b)

µ

PD67A and 68A

Notes 1. If the down counter reaches 0 while the carrier output is high level, carrier output will stop after

becoming low level.

2. As shown in figure (b) above, in the

µ

PD67A and 68A, because the timer output time is 4/fX shorter

(1

µ

s: fX = 4 MHz) than in the

µ

PD67, 68, and 69, the down counter reaches 0 while the carrier output

is low level, so the carrier may be one clock shorter than in the

µ

PD67, 68, and 69.

Timer output time: (Set value+1) × 64/fX

LED

REM

Note 1

tH

tL

Timer manipulation instruction

Timer output time: (Set value+1) × 64/fX – 4/fX

LED

REM

Note 2

tH

tL

Timer manipulation instruction

4/fX

25

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

tH (

µ

s)

0.25

1.0

2.5

5.0

8.25

8.25

8.75

8.75

8.75

9.0

9.125

13.25

15.0

25.0

32.0

MOD1

01H

07H

13H

27H

41H

41H

45H

45H

45H

47H

48H

69H

77H

C7H

FFH

MOD0

01H

0BH

13H

27H

41H

85H

89H

8BH

8CH

91H

94H

D5H

77H

C7H

FFH

tL (

µ

s)

0.25

1.5

2.5

5.0

8.25

16.75

17.25

17.5

17.625

18.25

18.625

26.75

15.0

25.0

32.0

T (

µ

s)

0.5

2.5

5.0

10

16.5

25

26.0

26.25

26.375

27.25

27.75

40.0

30.0

50.0

64.0

fC (kHz)

2,000

400

200

100

60.6

40

38.5

38.10

37.9

36.7

36.0

25

33.3

20

15.6

Duty

1/2

2/5

1/2

1/2

1/2

1/3

1/3

1/3

1/3

1/3

1/3

1/3

1/2

1/2

1/2

t

H

t

L

T

Carrier signal

Output from the REM pin is as follows, in accordance with the values set to bit 9 (CARY) of MOD1 and the timer

output enable flag (t9), and the value of the timer block’s 9-bit down counter (t0 to t8).

Table 4-2. REM Pin Output

MOD1 Bit 9 (CARY) Timer Output Enable Flag 9-Bit Down Counter REM Pin

(Timer Block t9)(Timer Block t0 to t8)

—— 0Low-level output

—0Other than 0

01 Carrier outputNote

1High-level output

Note Input values in the range of 001H to 1FFH to MOD0 and MOD1.

Caution MOD0 and MOD1 must be set while the REM pin is low level (t9 = 0 or t0 to t8 = 0).

Table 4-3. Example of Carrier Frequency Settings (fX = 4 MHz)

Setting Value

26

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

4.4 Software Control of Timer Output

The timer output can be controlled by software. As shown in Figure 4-5, a pulse with a minimum width of 1

instruction cycle (64/fX) can be output in the

µ

PD67, 68, and 69, and a pulse with a minimum width of 64/fX –

4/fX can be output in the

µ

PD67A and 68A.

Figure 4-5. Output of Pulse of 1-Instruction Cycle Width

MOV T, #0000000000B; low-level output from the REM pin

MOV T, #1000000000B; high-level output from the REM pin

MOV T, #0000000000B; low-level output from the REM pin

(a)

µ

PD67, 68, and 69

(b)

µ

PD67A and 68A

………

64/f

X

LED

REM

64/f

X

– 4/f

X

LED

REM

4/f

X

27

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

5. STANDBY FUNCTION

5.1 Outline of Standby Function

To save current consumption, two types of standby modes, i.e., HALT mode and STOP mode, have been provided

available.

In STOP mode, the system clock stops oscillation. At this time, the XIN and XOUT pins are fixed to a low level.

In HALT mode, CPU operation halts, while the system clock continues oscillation. When in HALT mode, the

timer (including REM output and LED output) operates.

In either STOP mode or HALT mode, the statuses of the data memory, accumulator, and port registers, etc.

immediately before the standby mode is set are retained. Therefore, make sure to set the port status for the system

so that the current consumption of the whole system is suppressed before the standby mode is set.

Table 5-1. Statuses During Standby Mode

STOP Mode HALT Mode

Setting instruction HALT instruction

Clock oscillator Oscillation stopped Oscillation continued

CPU • Operation halted

Data memory • Immediately preceding status retained

Operation Accumulator • Immediately preceding status retained

statuses Flag F • 0 (When 1, the flag is not placed in the standby mode.)

CY • Immediately preceding status retained

Port register • Immediately preceding status retained

Timer • Operation halted • Operable

(The count value is reset to “0”)

Cautions 1. Write the NOP instruction as the first instruction after STOP mode is released.

2. When standby mode is released, the status flag (F) is set (to 1).

3. If, at the point the standby mode has been set, its release condition is met, then the system

does not enter the standby mode. However, the status flag (F) is set (1).

28

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

5.2 Standby Mode Setting and Release

The standby mode is set with the HALT #b3b2b1b0B instruction for both STOP mode and HALT mode. For the

standby mode to be set, the status flag (F) is required to have been cleared (to 0).

The standby mode is released by the release condition specified with the reset (POC) or the operand of HALT

instruction. If the standby mode is released, the status flag (F) is set (to 1).

Even when the HALT instruction is executed in the state that the status flag (F) has been set (to 1), the standby

mode is not set. If the release condition is not met at this time, the status flag is cleared (to 0). If the release condition

is met, the status flag remains set (to 1).

Even in the case when the release condition has been already met at the point that the HALT instruction is

executed, the standby mode is not set. Here, also, the status flag (F) is set (to 1).

Caution Depending on the status of the status flag (F), the HALT instruction may not be executed. Be

careful about this. For example, when setting HALT mode after checking the key status with

the STTS instruction, the system does not enter HALT mode as long as the status flag (F)

remains set (to 1) and thus sometimes performs an unintended operation. In this case, the

intended operation can be realized by executing the STTS instruction immediately after setting

the timer to clear (to 0) the status flag.

Example STTS #03H ;To check the KI pin status.

MOV T, #0xxH ;To set the timer

STTS #05H ;To clear the status flag

(During this time, be sure not to execute an instruction that may set the status flag.)

HALT #05H ;To set HALT mode

Table 5-2. Addresses Executed After Standby Mode Release

Release Condition Address Executed After Release

Reset Address 0

Release condition shown in Table 5-3 The address following the HALT instruction

……

29

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

Table 5-3. Standby Mode Setup (HALT #b3b2b1b0B) and Release Conditions

Operand Value of

HALT Instruction Setting Mode Precondition for Setup Release Condition

b3b2b1b0

0000STOP All KI/O pins are high-level output. High level is input to at least one

of KI pins.

011STOP All KI/O pins are high-level output. High level is input to at least one

of KI pins.

110STOPNote 1 The KI/O0 pin is high-level output. High level is input to at least one

of KI pins.

1Any of the STOP [The following condition is added in addition to the above.]

combinations of — High level is input to at least one

b2b1b0 above of S0, S1 and S2 pinsNote 2.

0/1 101HALT — When the timer’s down counter is 0

Notes 1. When setting HALT #×110B, configure a key matrix by using the KI/O0 pin and the KI pin so that the

standby mode can be released.

2. At least one of the S0, S1 and S2 pins (the pin used for releasing the standby mode) must be specified

as follows:

S0, S1 pins: Input mode (specified by bits 0 and 2 of the P4 register)

S2 pin: Use of STOP mode release enabled (specified by bit 3 of the P4 register)

Cautions 1. The internal reset takes effect when the HALT instruction is executed with an operand value

other than that above or when the precondition has not been satisfied when executing the

HALT instruction.

2. If STOP mode is set when the timer’s down counter is not 0 (timer operating), the system

is placed in STOP mode only after all the 10 bits of the timer’s down counter and the timer

output permit flag are cleared to 0.

3. Write the NOP instruction as the first instruction after STOP mode is released.

30

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

5.3 Standby Mode Release Timing

(1) STOP mode release timing

Figure 5-1. STOP Mode Release by Release Condition

Caution When a release condition is met in the STOP mode, the device is released from the STOP mode,

and goes into a wait state. At this time, if the release condition is not held, the device goes

into STOP mode again after the wait time has elapsed. Therefore, when releasing the STOP

mode, it is necessary to hold the release condition longer than the wait time.

(2) HALT mode release timing

Figure 5-2. HALT Mode Release by Release Condition

Wait

(52/f

X

+

α)

HALT mode

Operation

mode

STOP mode

Oscillation

stopped Oscillation

Operation

mode

Oscillation

HALT instruction

(STOP mode)

Standby

release signal

Clock

α : Oscillation growth time

HALT mode Operation mode

Oscillation

Operation

mode

HALT instruction

(HALT mode)

Standby

release signal

Clock

31

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

6. RESET

A system reset is effected by the following causes:

• When the POC circuit has detected low power-supply voltage

• When the operand value is illegal or does not satisfy the precondition when the HALT instruction is executed

• When the accumulator is 0H when the RLZ instruction is executed

• When stack pointer overflows or underflows

Table 6-1. Hardware Statuses After Reset

Hardware •Reset by On-Chip POC Circuit During Operation • Reset by the On-Chip POC Circuit During

•Reset by Other FactorsNote 1 Standby Mode

PC

11 bits:

µ

PD67, 67A,

000H

68, 68A

12 bits:

µ

PD69

SP (1 bit) 0B

Data R0 = DP 000H

memory R1 to RF Undefined

Accumulator (A) Undefined

Status flag (F) 0B

Carry flag (CY) 0B

Timer (10 bits) 000H

Port register P0 FFH

P1 ×××× 11×1BNote 2

Control register P3 0000×000BNote 3

P4 26H

Notes 1. The following resets are available.

•Reset when executing the HALT instruction (when the operand value is illegal or does not satisfy

the precondition)

•Reset when executing the RLZ instruction (when A = 0)

•Reset by stack pointer’s overflow or underflow

2. ×:Refers to the value by the KI or S2 pin status.

In order to prevent malfunction, be sure to input a low level to one or more of pins KI0 to KI3 when

POC is released by supply voltage rising (Can be left open. When open, leave the pull-down resistor

connected).

3. ×:Refers to the value based on a decrease of power supply voltage (0 when VDD ≤ VID).

Remark VID: RAM retention detection voltage

32

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

7. POC CIRCUIT

The POC circuit monitors the power supply voltage and applies an internal reset to the microcontroller when the

battery is replaced.

Cautions 1. There are cases in which the POC circuit cannot detect a low power supply voltage of less

than 1 ms. Therefore, if the power supply voltage has become low for a period of less than

1 ms, the POC circuit may malfunction because it does not generate an internal reset signal.

2. Clock oscillation is stopped by the resonator due to low power supply voltage before the

POC circuit generates the internal reset signal. In this case, malfunction may result when

the power supply voltage is recovered after the oscillation is stopped. This type of

phenomenon takes place because the POC circuit does not generate an internal reset signal

(because the power supply voltage recovers before the low power supply voltage is

detected) even though the clock has stopped. If, by any chance, a malfunction has taken

place, remove the battery for a short time and put it back. In most cases, normal operation

will be resumed.

3. In order to prevent malfunction, be sure to input a low level to one or more of pins KI0 to

KI3 when POC is released due to supply voltage rising (Can be left open. When open, leave

the pull-down resistor connected).

33

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

7.1 Functions of POC Circuit

The POC circuit has the following functions:

• Generates an internal reset signal when VDD ≤ VPOC.

• Cancels an internal reset signal when VDD > VPOC.

Here, VDD: power supply voltage, VPOC: POC detection voltage.

Notes 1. Actually, oscillation stabilization wait time must elapse before the circuit is switched to operation mode.

The oscillation stabilization wait time is about 534/fX to 918/fX (when about 134 to 230

µ

s; @ fX = 4 MHz).

2. For the POC circuit to generate an internal reset signal when the power supply voltage has fallen,

it is necessary for the power supply voltage to be kept less than the VPOC for the period of 1 ms or

more. Therefore, in reality, there is the time lag of up to 1 ms until the reset takes effect.

3. The POC detection voltage (VPOC) varies between approximately 1.7 to 2.0 V; thus, the reset may

be canceled at a power supply voltage smaller than the guaranteed range (VDD = 2.0 to 3.6 V).

However, as long as the conditions for operating the POC circuit are met, the actual lowest operating

power supply voltage becomes lower than the POC detection voltage. Therefore, there is no

malfunction occurring due to a shortage of power supply voltage. However, malfunction for such

reasons as the clock not oscillating due to low power supply voltage may occur (refer to Cautions

3 in 7 POC CIRCUIT).

7.2 Oscillation Check at Low Supply Voltage

A reliable reset operation can be expected of the POC circuit if it satisfies the condition that the clock can oscillate

even at low power supply voltage (the oscillation start voltage of the resonator being even lower than the POC

detection voltage). Whether this condition is met or not can be checked by measuring the oscillation status in a

product that actually includes a POC circuit, as follows.

<1> Connect a storage oscilloscope to the XOUT pin so that the oscillation status can be measured.

<2> Connect a power supply whose output voltage can be varied and then gradually raise the power supply

voltage VDD from 0 V (making sure to avoid VDD > 3.6V).

At first (during VDD < approx. 1.7 V), the XOUT pin is 0 V regardless of the VDD. However, at the point that VDD

reaches the POC detection voltage (VPOC = 1.85 V (TYP.)), the voltage of the XOUT pin jumps to about 0.5VDD.

Maintain this power supply voltage for a while to measure the waveform of the XOUT pin. If by any chance the

oscillation start voltage of the resonator is lower than the POC detection voltage, the growing oscillation of the XOUT

pin can be confirmed within several ms after the VDD has reached the VPOC.

VDD

3.6 V

2.0 V

VPOC

Approx. 1.7 V

0 V

Internal reset signal

Reset

Operating ambient temperature TA = – 40 to + 85°C

Clock frequency fX = 3.5 to 4.5 MHz

←POC detection voltage VPOC = 1.85 V (TYP.)

Note 3

→ t

Operation mode ↑ Reset

Note 2

↑

Note 1

34

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

8. SYSTEM CLOCK OSCILLATOR

The system clock oscillator consists of oscillators for ceramic resonators (fX = 3.5 to 4.5 MHz).

Figure 8-1. System Clock

The system clock oscillator stops oscillating when a reset is applied or in STOP mode.

Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines

in the above figure to avoid an adverse effect from wiring capacitance.

•Keep the wiring length as short as possible.

•Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line

through which a high fluctuating current flows.

•Always make the ground point of the oscillator capacitor the same potential as GND. Do not

ground the capacitor to a ground pattern through which a high current flows.

•Do not fetch signals from the oscillator.

A capacitor (15 pF) for the oscillator can be incorporated via a mask option.

XOUT XIN GND

Ceramic resonator

35

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

9. INSTRUCTION SET

9.1 Machine Language Output by Assembler

The bit length of the machine language of this product is 10 bits per word. However, the machine language that

is output by the assembler is extended to 16 bits per word. As shown in the example below, the extension is made

by inserting 3-bit extended bits (111) in two locations.

Figure 9-1. Example of Assembler Output (10 Bits Extended to 16 Bits)

<1> In the case of “ANL A, @R0H”

1

1

1010 1 0000

1010 10000111111

Extended bitsExtended bits

= FAF0

<2> In the case of “OUT P0, #data8”

0

0

0110 1 1000

0110 11000111111

Extended bitsExtended bits

= E6F8

36

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

9.2 Circuit Symbol Description

A: Accumulator

ASR: Address stack register

addr: Program memory address

CY: Carry flag

data4: 4-bit immediate data

data8: 8-bit immediate data

data10: 10-bit immediate data

F: Status flag

M0: Modulo register for setting the low-level period

M00: Modulo register for setting the low-level period (lower 4 bits)

M01: Modulo register for setting the low-level period (higher 4 bits)

M1: Modulo register for setting the high-level period

M10: Modulo register for setting the high-level period (lower 4 bits)

M11: Modulo register for setting the high-level period (higher 4 bits)

PC: Program Counter

Pn: Port register pair (n = 0, 1, 3, 4)

P0n: Port register (lower 4 bits)

P1n: Port register (higher 4 bits)

ROMn: Bit n of the program memory’s (n = 0 to 9)

Rn: Register pair

R0n: Data memory (General-purpose register; n = 0 to F)

R1n: Data memory (General-purpose register; n = 0 to F)

SP: Stack Pointer

T: Timer register

T0: Timer register (lower 4 bits)

T1: Timer register (higher 4 bits)

(×): Content addressed with ×

37

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

9.3 Mnemonic to/from Machine Language (Assembler Output) Contrast Table

Accumulator Operation Instructions

Mnemonic Operand Instruction Code Operation Instruction Instruction

1st Word 2nd Word 3rd Word Length Cycle

ANL A, R0n FBEn (A) ← (A) (Rmn) m = 0, 1 n = 0 to F 1 1

A, R1n FAEn CY ← A3 • Rmn3

A, @R0H FAF0 (A) ← (A) ((P13), (R0))7-4

CY ← A3 • ROM7

A, @R0L FBF0 (A) ← (A) ((P13), (R0))3-0

CY ← A3 • ROM3

A, #data4 FBF1 data4 (A) ← (A) data4 2

CY ← A3 • data43

ORL A, R0n FDEn (A) ← (A) ∨ (Rmn) m = 0, 1 n = 0 to F 1

A, R1n FCEn CY ← 0

A, @R0H FCF0 (A) ← (A) ∨ ((P13), (R0))7-4

CY ← 0

A, @R0L FDF0 (A) ← (A) ∨ ((P13), (R0))3-0

CY ← 0

A, #data4 FDF1 data4 (A) ← (A) ∨ data4 2

CY ← 0

XRL A, R0n F5En (A) ← (A) ∨ (Rmn) m = 0, 1 n = 0 to F 1

A, R1n F4En CY ← A3 • Rmn3

A, @R0H F4F0 (A) ← (A) ∨ ((P13), (R0))7-4

CY ← A3 • ROM7

A, @R0L F5F0 (A) ← (A) ∨ ((P13), (R0))3-0

CY ← A3 • ROM3

A, #data4 F5F1 data4 (A) ← (A) ∨ data4 2

CY ← A3 • data43

INC A F4F3 (A) ← (A) + 1 1

if (A) = 0 CY ← 1

else CY ← 1

RL A FCF3 (An+1) ← (An), (A0) ← (A3)

CY ← A3

RLZ A FEF3 if A = 0 reset

else (An+1) ← (An), (A0) ← (A3)

CY ← A3

∨

∨

∨

∨

38

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

I/O Instructions

Mnemonic Operand Instruction Code Operation Instruction Instruction

1st Word 2nd Word 3rd Word Length Cycle

IN A, P0n FFF8 + n — — (A) ← (Pmn) m = 0, 1 n = 0, 1, 3, 4 1 1

A, P1n FEF8 + n — — CY ← 0

OUT P0n, A E5F8 + n — — (Pmn) ← (A) m = 0, 1 n = 0, 1, 3, 4

P1n, A E4F8 + n — —

ANL A, P0n FBF8 + n — —

(A) ← (A) (Pmn) m = 0, 1 n = 0, 1, 3, 4

A, P1n FAF8 + n — — CY ← A3 • Pmn3

ORL A, P0n FDF8 + n — —

(A) ← (A) ∨ (Pmn) m = 0, 1 n = 0, 1, 3, 4

A, P1n FCF8 + n — — CY ← 0

XRL A, P0n F5F8 + n — —

(A) ← (A) ∨ (Pmn) m = 0, 1 n = 0, 1, 3, 4

A, P1n F4F8 + n — — CY ← A3 • Pmn3

Mnemonic Operand Instruction Code Operation Instruction Instruction

1st Word 2nd Word 3rd Word Length Cycle

OUT Pn, #data8 E6F8 + n data8 (Pn) ← data8 n = 0, 1, 3, 4 2 1

Remark Pn: P1n to P0n are dealt with in pairs.

Data Transfer Instruction

Mnemonic Operand Instruction Code Operation Instruction Instruction

1st Word 2nd Word 3rd Word Length Cycle

MOV A, R0n FFEn (A) ← (Rmn) m = 0, 1 n = 0 to F 1 1

A, R1n FEEn CY ← 0

A, @R0H FEF0 (A) ← ((P13), (R0))7-4

CY ← 0

A, @R0L FFF0 (A) ← ((P13), (R0))3-0

CY ← 0

A, #data4 FFF1 data4 (A) ← data4 2

CY ← 0

R0n, A E5En (Rmn) ← (A) m = 0, 1 n = 0 to F 1

R1n, A E4En

Mnemonic Operand Instruction Code Operation Instruction Instruction

1st Word 2nd Word 3rd Word Length Cycle

MOV Rn, #data8 E6En data8 — (R1n to R0n) ← data8 n = 0 to F 2 1

Rn, @R0 E7En — — (R1n to R0n) ← ((P13), (R0))n = 1 to F 1

Remark Rn: R1n to R0n are handled in pairs.

∨

39

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

Branch Instructions

Mnemonic Operand Instruction Code Operation Instruction Instruction

1st Word 2nd Word 3rd Word Length Cycle

JMP

addr (Page 0)

E8F1 addr PC ← addr 2 1

addr (Page 1)

E9F1 addr

addr (Page 2)

E8F4 addr

addr (Page 3)

E9F4 addr

JC

addr (Page 0)

ECF1 addr if CY = 1 PC ← addr

addr (Page 1)

EAF1 addr else PC ← PC + 2

addr (Page 2)

ECF4 addr

addr (Page 3)

EAF4 addr

JNC

addr (Page 0)

EDF1 addr if CY = 0 PC ← addr

addr (Page 1)

EBF1 addr else PC ← PC + 2

addr (Page 2)

EDF4 addr

addr (Page 3)

EBF4 addr

JF

addr (Page 0)

EEF1 addr if F = 1 PC ← addr

addr (Page 1)

F0F1 addr else PC ← PC + 2

addr (Page 2)

EEF4 addr

addr (Page 3)

F0F4 addr

JNF

addr (Page 0)

EFF1 addr if F = 0 PC ← addr

addr (Page 1)

F1F1 addr else PC ← PC + 2

addr (Page 2)

EFF4 addr

addr (Page 3)

F1F4 addr

Caution 0 and 4, which refer to PAGE0 and 4, are not written when describing mnemonics.

Subroutine Instructions

Mnemonic Operand Instruction Code Operation Instruction Instruction

1st Word 2nd Word 3rd Word Length Cycle

CALL

addr (Page 0)

E6F2 E8F1 addr SP ← SP + 1, ASR ← PC, PC ← addr 3 2

addr (Page 1)

E6F2 E9F1 addr

addr (Page 2)

E6F2 E8F4 addr

addr (Page 3)

E6F2 E9F4 addr

RET E8F2 PC ← ASR, SP ← SP – 1 1 1

Caution 0 and 4, which refer to PAGE0 and 4, are not written when describing mnemonics.

40

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

Timer Operation Instructions

Mnemonic Operand Instruction Code Operation Instruction Instruction

1st Word 2nd Word 3rd Word Length Cycle

MOV A, T0 FFFF (A) ← (Tn) n = 0, 1 1 1

A, T1 FEFF CY ← 0

A, M00 FFF6 (A) ← (M0n) n = 0, 1

A, M01 FEF6 CY ← 0

A, M10 FFF7 (A) → (M1n) n = 0, 1

A, M11 FEF7 CY → 0

T0, A E5FF (Tn) ← (A) n = 0, 1

T1, A F4FF (T) n ← 0

M00, A E5F6 (M0n) ← (A) n = 0, 1

M01, A E4F6 CY ← 0

M10, A E5F7 (M1n) ← (A) n = 0, 1

M11, A E4F7 CY ← 0

Mnemonic Operand Instruction Code Operation Instruction Instruction

1st Word 2nd Word 3rd Word Length Cycle

MOV T, #data10 E6FF data10 (T) ← data10 2 1

M0, #data10

E6F6 data10 (M0) ← data10

M1, #data10

E6F7 data10 (M1) ← data10

T, @R0 F4FF (T) ← ((P13), (R0)) 1

M0, @R0 E7F6 (M0) ← ((P13), (R0))

M1, @R0 E7F7 (M1) ← ((P13), (R0))

Others

Mnemonic Operand Instruction Code Operation Instruction Instruction

1st Word 2nd Word 3rd Word Length Cycle

HALT #data4 E2F1 data4 Standby mode 2 1

STTS #data4 E3F1 data4 if statuses match F ← 1

else F ← 0

R0n E3En if statuses match F ← 11

else F ← 0n = 0 to F

SCAF FAF3 if A = 0FH CY ← 1

else CY ← 0

NOP E0E0 PC ← PC + 1

41

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

9.4 Accumulator Manipulation Instructions

ANL A, R0n

ANL A, R1n

<1> Instruction code: 1101R40R3R2R1R0

<2> Cycle count: 1

<3> Function: (A) ← (A) (Rmn) m = 0, 1 n = 0 to F

CY ← A3 • Rmn3

The accumulator contents and the register Rmn contents are ANDed and the results are entered in the

accumulator.

ANL A, @R0H

ANL A, @R0L

<1> Instruction code: 11010/110000

<2> Cycle count: 1

<3> Function: (A) ← (A) ((P13), (R0))7-4 (in the case of ANL A, @R0H)

CY ← A3 • ROM7

(A) ← (A) ((P13), (R0))3-0 (in the case of ANL A, @R0L)

CY ← A3 • ROM3

The accumulator contents and the program memory contents specified by the control register P13 and

register pair R10 to R00 are ANDed and the results are entered in the accumulator.

If H is specified, b7, b6, b5 and b4 take effect. If L is specified, b3, b2, b1 and b0 take effect.

•Program memory (ROM) organization

ANL A, #data4

<1> Instruction code: 1101110001

000000d

3d2d1d0

<2> Cycle count: 1

<3> Function: (A) ← (A) data4

CY ← A3 • data43

The accumulator contents and the immediate data are ANDed and the results are entered in the

accumulator.

∨

∨

∨

∨

b

9

b

8

b

7

b

6

b

5

b

4

b

3

b

2

b

1

b

0

H↓L↓

Valid bits at the time of accumulator manipulation

42

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

ORL A, R0n

ORL A, R1n

<1> Instruction code: 1110R40R3R2R1R0

<2> Cycle count: 1

<3> Function: (A) ← (A) ∨ (Rmn) m = 0, 1 n = 0 to F

CY ← 0

The accumulator contents and the register Rmn contents are ORed and the results are entered in the

accumulator.

ORL A, @R0H

ORL A, @R0L

<1> Instruction code: 11100/110000

<2> Cycle count: 1

<3> Function: (A) ← (A) ∨ (P13), (R0))7-4 (in the case of ORL A, @R0H)

(A) ← (A) ∨ (P13), (R0))3-0 (in the case of ORL A, @R0L)

CY ← 0

The accumulator contents and the program memory contents specified by the control register P13 and

register pair R10-R00 are ORed and the results are entered in the accumulator.

If H is specified, b7, b6, b5 and b4 take effect. If L is specified, b3, b2, b1 and b0 take effect.

ORL A, #data4

<1> Instruction code: 1110110001

000000d

3d2d1d0

<2> Cycle count: 1

<3> Function: (A) ← (A) ∨ data4

CY ← 0

The accumulator contents and the immediate data are exclusive-ORed and the results are entered in

the accumulator.

XRL A, R0n

XRL A, R1n

<1> Instruction code: 1010R40R3R2R1R0

<2> Cycle count: 1

<3> Function: (A) ← (A) ∨ (Rmn) m = 0, 1 n = 0 to F

CY ← A3 • Rmn3

The accumulator contents and the register Rmn contents are ORed and the results are entered in the

accumulator.

43

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

XRL A, @R0H

XRL A, @R0L

<1> Instruction code: 10100/110000

<2> Cycle count: 1

<3> Function: (A) ← (A) ∨ (P13), (R0))7-4 (in the case of XRL A, @R0H)

CY ← A3 • ROM7

(A) ← (A) ∨ (P13), (R0))3-0 (in the case of XRL A, @R0L)

CY ← A3 • ROM3

The accumulator contents and the program memory contents specified by the control register P13 and

register pair R10-R00 are exclusive-ORed and the results are entered in the accumulator.

If H is specified, b7, b6, b5, and b4 take effect. If L is specified, b3, b2, b1, and b0 take effect.

XRL A, #data4

<1> Instruction code: 1010110001

000000d3d2d1d0

<2> Cycle count: 1

<3> Function: (A) ← (A) ∨ data4

CY ← A3 • data43

The accumulator contents and the immediate data are exclusive-ORed and the results are entered in

the accumulator.

INC A

<1> Instruction code: 1010010011

<2> Cycle count: 1

<3> Function: (A) ← (A) + 1

if A = 0 CY ← 1

else CY ← 0

The accumulator contents are incremented (+1).

RL A

<1> Instruction code: 1110010011

<2> Cycle count: 1

<3> Function: (An + 1) ← (An), (A0) ← (A3)

CY ← A3

The accumulator contents are rotated anticlockwise bit by bit.

RLZ A

<1> Instruction code: 1111010011

<2> Cycle count: 1

<3> Function: if A = 0 reset

else (An + 1) ← (An), (A0) ←(A3)

CY ← A3

The accumulator contents are rotated anticlockwise bit by bit.

If A = 0H at the time of command execution, an internal reset takes effect.

44

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

9.5 I/O Instructions

IN A, P0n

IN A, P1n

<1> Instruction code: 1111P411P2P1P0

<2> Cycle count: 1

<3> Function: (A) ← (Pmn) m = 0, 1 n = 0, 1, 3, 4

CY ← 0

The port Pmn data is loaded (read) onto the accumulator.

OUT P0n, A

OUT P1n, A

<1> Instruction code: 0010P411P2P1P0

<2> Cycle count: 1

<3> Function: (Pmn) ← (A) m = 0, 1 n = 0, 1, 3, 4

The accumulator contents are transferred to port Pmn to be latched.

ANL A, P0n

ANL A, P1n

<1> Instruction code: 1101P411P2P1P0

<2> Cycle count: 1

<3> Function: (A) ← (A) (Pmn) m = 0, 1 n = 0, 1, 3, 4

CY ← A3 • Pmn

The accumulator contents and the port Pmn contents are ANDed and the results are entered in the

accumulator.

ORL A, P0n

ORL A, P1n

<1> Instruction code: 1110P411P2P1P0

<2> Cycle count: 1

<3> Function: (A) ← (A) ∨ (Pmn) m = 0, 1 n = 0, 1, 3, 4

CY ← 0

The accumulator contents and the port Pmn contents are ORed and the results are entered in the

accumulator.

XRL A, P0n

XRL A, P1n

<1> Instruction code: 1010P411P2P1P0

<2> Cycle count: 1

<3> Function: (A) ← (A) ∨ (Pmn) m = 0, 1 n = 0, 1, 3, 4

CY ← A3 • Pmn

The accumulator contents and the port Pmn contents are exclusive-ORed and the results are entered

in the accumulator.

∨

45

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

OUT Pn, #data8

<1> Instruction code: 0011011P2P1P0

: 0d7d6d5d40d3d2d1d0

<2> Cycle count: 1

<3> Function: (Pn) ← data8 n = 0, 1, 3, 4

The immediate data is transferred to port Pn. In this case, port Pn refers to P1n to P0n operating in pairs.

9.6 Data Transfer Instructions

MOV A, R0n

MOV A, R1n

<1> Instruction code: 1111R40R3R2R1R0

<2> Cycle count: 1

<3> Function: (A) ← (Rmn) m = 0, 1 n = 0 to F

CY ← 0

The register Rmn contents are transferred to the accumulator.

MOV A, @R0H

<1> Instruction code: 1111010000

<2> Cycle count: 1

<3> Function: (A) ← ((P13), (R0))7-4

CY ← 0

The higher 4 bits (b7 b6 b5 b4) of the program memory specified by control register P13 and register pair

R10-R00 are transferred to the accumulator. b9 is ignored.

MOV A, @R0L

<1> Instruction code: 1111110000

<2> Cycle count: 1

<3> Function: (A) ← ((P13), (R0))3-0

CY ← 0

The lower 4 bits (b3 b2 b1 b0) of the program memory specified by control register P13 and register pair

R10 to R00 are transferred to the accumulator. b8 is ignored.

• Program memory (ROM) contents

b9b8

b7b6b5b4b3b2b1b0

@R0 H@R0 L

MOV A, #data4

<1> Instruction code: 1111110001

: 000000d3d2d1d0

<2> Cycle count: 1

<3> Function: (A) ← data4

CY ← 0

The immediate data is transferred to the accumulator.

46

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

MOV R0n, A

MOV R1n, A

<1> Instruction code: 0010R40R3R2R1R0

<2> Cycle count: 1

<3> Function: (Rmn) ← (A) m = 0, 1 n = 0 to F

The accumulator contents are transferred to register Rmn.

MOV Rn, #data8

<1> Instruction code: 001100R3R2R1R0

: 0 d7d6d5d40d3d2d1d0

<2> Cycle count: 1

<3> Function: (R1n-R0n) ← data8 n = 0 to F

The immediate data is transferred to the register. Using this instruction, registers operate as register

pairs.

The pair combinations are as follows:

R0: R10 - R00

R1: R11 - R01

:

RE: R1E - R0E

RF: R1F - R0F

Lower column

Higher column

MOV Rn, @R0

<1> Instruction code: 001110R3R2R1R0

<2> Cycle count: 1

<3> Function: (R1n-R0n) ← ((P13), R0)) n = 1 to F

The program memory contents specified by control register P13 and register pair R10 to R00 are

transferred to register pair R1n to R0n. The program memory consists of 10 bits and has the following

state after the transfer to the register.

b9b8

b7b6b5b4b3b2b1b0

b9b8

b7b6b5b4b3b2b1b0

@R0

→

R1n R0n

Program memory

The higher 2 to 4 bits of the program memory address are specified by the control register (P13).

47

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

9.7 Branch Instructions

The program memory consists of pages in steps of 1K (000H to 3FFH). However, as the assembler automatically

performs page optimization, it is unnecessary to designate pages. The pages allowed for each product are as

follows.

µ

PD67, 67A (ROM: 1K steps): Page 0

µ

PD68, 68A (ROM: 2K steps): Pages 0, 1

µ

PD69 (ROM: 4K steps): Pages 0 to 3

µ

PD6P9 (PROM: 4K steps): Pages 0 to 3

JMP addr

<1> Instruction code: Page 0 0100010001 ; page 1 0100110001

Page 2 0100010100 ; page 3 0100110100

a9a7a6a5a4a8a3a2a1a0

<2> Cycle count: 1

<3> Function: PC ← addr

The 10 bits (PC9-0) of the program counter are replaced directly by the specified address addr (a9 to

a0).

JC addr

<1> Instruction code: Page 0 0110010001 ; page 1 0101010001

Page 2 0110010100 ; page 3 0101010100

a9a7a6a5a4a8a3a2a1a0

<2> Cycle count: 1

<3> Function: if CY = 1 PC ← addr

else PC ← PC + 2

If the carry flag CY is set (to 1), a jump is made to the address specified by addr (a9 to a0).

JNC addr

<1> Instruction code: Page 0 0110110001 ; page 1 0101110001

Page 2 0110110100 ; page 3 0101110100

a9a7a6a5a4a8a3a2a1a0

<2> Cycle count: 1

<3> Function: if CY = 0 PC ← addr

else PC ← PC + 2

If the carry flag CY is cleared (to 0), a jump is made to the address specified by addr (a9 to a0).

JF addr

<1> Instruction code: Page 0 0111010001 ; page 1 1000010001

Page 2 0111010100 ; page 3 1000010100

a9a7a6a5a4a8a3a2a1a0

<2> Cycle count: 1

<3> Function: if F = 1 PC ← addr

else PC ← PC + 2

If the status flag F is set (to 1), a jump is made to the address specified by addr (a9 to a0).

48

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

JNF addr

<1> Instruction code: Page 0 0111110001 ; page 1 1000110001

Page 2 0111110100 ; page 3 1000110100

a9a7a6a5a4a8a3a2a1a0

<2> Cycle count: 1

<3> Function: if F = 0 PC ← addr

else PC ← PC + 2

If the status flag F is cleared (to 0), a jump is made to the address specified by addr (a9 to a0).

9.8 Subroutine Instructions

The program memory consists of pages in steps of 1K (000H to 3FFH). However, as the assembler automatically

performs page optimization, it is unnecessary to designate pages. The pages allowed for each product are as

follows.

µ

PD67, 67A (ROM: 1K steps): Page 0

µ

PD68, 68A (ROM: 2K steps): Pages 0, 1

µ

PD69 (ROM: 4K steps): Pages 0 to 3

µ

PD6P9 (PROM: 4K steps): Pages 0 to 3

CALL addr

<1> Instruction code: 0011010010

Page 0 0100010001 ; page 1 0100110001

Page 2 0100010100 ; page 3 0100110100

a9a7a6a5a4a8a3a2a1a0

<2> Cycle count: 2

<3> Function: SP ← SP + 1

ASR ← PC

PC ← addr

Increments (+1) the stack pointer value and saves the program counter value in the address stack

register. Then, enters the address specified by the operand addr (a9 to a0) into the program counter.

If a carry is generated when the stack pointer value is incremented (+1), an internal reset takes effect.

RET

<1> Instruction code: 0100010010

<2> Cycle count: 1

<3> Function: PC ← ASR

SP ← SP – 1

Restores the value saved in the address stack register to the program counter. Then, decrements

(–1) the stack pointer.

If a borrow is generated when the stack pointer value is decremented (–1), an internal reset takes effect.

49

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

9.9 Timer Operation Instructions

MOV A, T0

MOV A, T1

<1> Instruction code: 11110/1 1 1 1 1 1

<2> Cycle count: 1

<3> Function: (A) ← (Tn) n = 0, 1

CY ← 0

The timer register Tn contents are transferred to the accumulator. T1 corresponds to (t9, t8, t7, t6); T0

corresponds to (t5, t4, t3, t2).

↓

t9t8t7t6t5t4t3t2t1t0

Can be set with

T1 T0

MOV T, #data10

MOV T, @R0

T

MOV A, M00

MOV A, M01

<1> Instruction code: 11110/1 1 0 1 1 0

<2> Cycle count: 1

<3> Function: (A) ← (M0n) n = 0, 1

CY ← 0

The modulo register M0n contents are transferred to the accumulator. M01 corresponds to (t9, t8, t7,

t6); M00 corresponds to (t5, t4, t3, t2).

↓

t

9

t

8

t

7

t

6

t

5

t

4

t

3

t

2

t

1

t

0

Can be set with

M01 M00

MOV M0, #data10

MOV M0, @R0

M0

50

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

MOV A, M10

MOV A, M11

<1> Instruction code: 11110/1 1 0 1 1 1

<2> Cycle count: 1

<3> Function: (A) ← (M1n) n = 0, 1

CY ← 0

The modulo register M1n contents are transferred to the accumulator. M11 corresponds to (t9, t8, t7,

t6); M10 corresponds to (t5, t4, t3, t2).

↓

t

9

t

8

t

7

t

6

t

5

t

4

t

3

t

2

t

1

t

0

Can be set with

M11 M10

MOV M1, #data10

MOV M1, @R0

M1

MOV T0, A

MOV T1, A

<1> Instruction code: 00100/1 1 1 1 1 1

<2> Cycle count: 1

<3> Function: (Tn) ← (A) n = 0, 1

The accumulator contents are transferred to the timer register Tn. T1 corresponds to (t9, t8, t7, t6); T0

corresponds to (t5, t4, t3, t2). After executing this instruction, if data is transferred to T1, t1 becomes

0; if data is transferred to T0, t0 becomes 0.

MOV M00, A

MOV M01, A

<1> Instruction code: 00100/1 1 0 1 1 0

<2> Cycle count: 1

<3> Function: (M0n) ← (A) n = 0, 1

CY ← 0

The accumulator contents are transferred to the modulo register M0n. M01 corresponds to (t9, t8, t7,

t6); M00 corresponds to (t5, t4, t3, t2). After executing this instruction, if data is transferred to M01,

t1 becomes 0; if data is transferred to M00, t0 becomes 0.

MOV M10, A

MOV M11, A

<1> Instruction code: 00100/1 1 0 1 1 1

<2> Cycle count: 1

<3> Function: (M1n) ← (A) n = 0, 1

CY ← 0

The accumulator contents are transferred to the modulo register M1n. M11 corresponds to (t9, t8, t7,

t6); M10 corresponds to (t5, t4, t3, t2). After executing this instruction, if data is transferred to M11,

t1 becomes 0; if data is transferred to M10, t0 becomes 0.

51

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

MOV T, #data10

<1> Instruction code: 0011011111

t1t9t8t7t6t0t5t4t3t2

<2> Cycle count: 1

<3> Function: (T) ← data10

The immediate data is transferred to the timer register T (t9 to t0).

Remark The timer time is set as follows.

(a)

µ

PD67, 68, and 69

(Set value + 1) × 64/fX

(b)

µ

PD67A and 68A

(Set value + 1) × 64/fX – 4/fX

MOV M0, #data10

<1> Instruction code: 0011010110

t1t9t8t7t6t0t5t4t3t2

<2> Cycle count: 1

<3> Function: (M0) ← data10

The immediate data is transferred to the modulo register M0 (t9 to t0).

MOV M1, #data10

<1> Instruction code: 0011010111

t1t9t8t7t6t0t5t4t3t2

<2> Cycle count: 1

<3> Function: (M1) ← data10

The immediate data is transferred to the modulo register M1 (t9 to t0).

MOV T, @R0

<1> Instruction code: 0011111111

<2> Cycle count: 1

<3> Function: (T) ← ((P13), (R0))

Transfers the program memory contents to the timer register T (t9 to t0) specified by the control register

P13 and the register pair R10 to R00.

The program memory, which consists of 10 bits, is placed in the following state after the transfer to the

register.

t

9

t

8

t

7

t

6

t

5

t

4

t

3

t

2

t

1

t

0

T1 T0

t

1

t

0

t

9

t

8

t

7

t

6

t

5

t

4

t

3

t

2

@R

0

→

Program memory Timer

T

The higher 2 to 4 bits of the program memory address are specified by the control register (P13).

Caution When setting a timer value in the program memory, be sure to use the DT

quasi-directive.

52

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

MOV M0, @R0

<1> Instruction code: 0011110110

<2> Cycle count: 1

<3> Function: (M0) ← ((P13), (R0))

Transfers the program memory contents to the modulo register M0 (t9 to t0) specified by the control

register P13 and the register pair R10 to R00.

The program memory, which consists of 10 bits, is placed in the following state after the transfer to the

register.

t

9

t

8

t

7

t

6

t

5

t

4

t

3

t

2

t

1

t

0

M01 M00

t

1

t

0

t

9

t

8

t

7

t

6

t

5

t

4

t

3

t

2

@R

0

→

Program memory Modulo register

M0

The higher 2 to 4 bits of the program memory address are specified by the control register (P13).

Caution When setting a timer value in the program memory, be sure to use the DT

quasi-directive.

MOV M1, @R0

<1> Instruction code: 0011110111

<2> Cycle count: 1

<3> Function: (M1) ← ((P13), (R0))

Transfers the program memory contents to the modulo register M1 (t9 to t0) specified by the control

register P13 and the register pair R10 to R00.

The program memory, which consists of 10 bits, is placed in the following state after the transfer to the

register.

t

9

t

8

t

7

t

6

t

5

t

4

t

3

t

2

t

1

t

0

M11 M10

t

1

t

0

t

9

t

8

t

7

t

6

t

5

t

4

t

3

t

2

@R

0

→

Program memory Modulo register

M1

The higher 2 to 4 bits of the program memory address are specified by the control register (P13).

Caution When setting a timer value in the program memory, be sure to use the DT

quasi-directive.

9.10 Others

HALT #data4

<1> Instruction code: 0001010001

: 000000d3d2d1d0

<2> Cycle count: 1

<3> Function: Standby mode

Places the CPU in standby mode.

The condition for having the standby mode (HALT/STOP mode) canceled is specified by the immediate

data.

53

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

STTS R0n

<1> Instruction code: 000110R3R2R1R0

<2> Cycle count: 1

<3> Function: if statuses match F ← 1

else F ← 0n = 0 to F

Compares the S0, S1, KI/O, KI, and TIMER statuses with the register R0n contents. If at least one of the

statuses matches the bits that have been set, the status flag F is set (to 1).

If none of them match, the status flag F is cleared (to 0).

STTS #data4

<1> Instruction code: 0001110001

: 000000d3d2d1d0

<2> Cycle count: 1

<3> Function: if statuses match F ← 1

else F ← 0

Compares the S0, S1, S2, KI/O, KI, and TIMER statuses with the immediate data contents. If at least one

of the statuses matches the bits that have been set, the status flag F is set (to 1).

If none of them match, the status flag F is cleared (to 0).

SCAF (Set Carry If ACC = FH)

<1> Instruction code: 1101010011

<2> Cycle count: 1

<3> Function: if A = 0FH CY ← 1

else CY ← 0

Sets the carry flag CY (to 1) if the accumulator contents are FH.

The accumulator values after executing the SCAF instruction are as follows:

Accumulator Value Carry Flag

Before Execution After Execution

×××00000 0 (clear)

××01 0001 0 (clear)

×011 0011 0 (clear)

0111 0111 0 (clear)

1111 1111 1 (set)

Remark ×: don’t care

NOP

<1> Instruction code: 0000000000

<2> Cycle count: 1

<3> Function: PC ← PC + 1

No operation

54

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

10. ASSEMBLER RESERVED WORDS

10.1 Mask Option Directives

When creating a program in the

µ

PD67, 67A, 68, 68A, and 69, it is necessary to use a mask option quasi-directive

in the assembler’s source program.

10.1.1 OPTION and ENDOP quasi-directives

The quasi-directives from the OPTION quasi-directive down to the ENDOP quasi-directive are called the mask

option definition block. The format of the mask option definition block is as follows:

Format

Symbol field Mnemonic field Operand field Comment field

[Label:] OPTION [; Comment]

:

:

ENDOP

10.1.2 Mask option definition quasi-directives

The quasi-directives that can be used in the mask option definition block are listed in Table 10-1.

The mask option definition can only be specified as follows. Be sure to specify the following quasi-directives.

Example

Symbol field Mnemonic field Operand field Comment field

OPTION

USECAP ; Capacitor for oscillation

ENDOP incorporated

Table 10-1. Mask Option Definition Directives

Name Mask Option Definition Quasi-Directive PRO File

Address Value Data Value

CAP USECAP 2043H 01

(Capacitor for oscillation incorporated)

NOUSECAP 00

(Capacitor for oscillation not incorporated)

55

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

11. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (TA = +25°C)

Item Symbol Conditions Ratings Unit

Power supply voltage VDD –0.3 to +3.8 V

Input voltage VIKI/O, KI, S0, S1, S2–0.3 to VDD + 0.3 V

Output voltage VO–0.3 to VDD + 0.3 V

Output current, high IOHNote REM Peak value –30 mA

rms value –20 mA

LED Peak value –7.5 mA

rms value –5 mA

One KI/O pin Peak value –13.5 mA

rms value –9 mA

Total for LED and KI/O pins Peak value –18 mA

rms value –12 mA

Output current, low IOLNote REM Peak value 7.5 mA

rms value 5 mA

LED Peak value 7.5 mA

rms value 5 mA

Operating ambient TA–40 to +85 °C

temperature

Storage temperature Tstg –65 to +150 °C

Note The rms value should be calculated as follows: [rms value] = [Peak value] × Duty.

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for

any parameter. That is, the absolute maximum ratings are rated values at which the product

is on the verge of suffering physical damage, and therefore the product must be used under

conditions that ensure that the absolute maximum ratings are not exceeded.

Recommended Power Supply Voltage Range (TA = –40 to +85°C)

Item Symbol Conditions MIN. TYP. MAX. Unit

Power supply voltage VDD fX = 3.5 to 4.5 MHz 2.0 3.0 3.6 V

√

56

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

DC Characteristics (TA = –40 to +85°C, VDD = 2.0 to 3.6 V)

Item Symbol Conditions MIN. TYP. MAX. Unit

Input voltage, high VIH1 KI/O 0.7VDD VDD V

VIH2 KI, S0, S1, S20.65VDD VDD V

Input voltage, low VIL1 KI/O 00.3VDD V

VIL2 KI, S0, S1, S200.15VDD V

Input leakage current, ILH1 KI3

µ

A

high VI = VDD, pull-down resistor not incorporated

ILH2 S0, S1, S23

µ

A

VI = VDD, pull-down resistor not incorporated

Input leakage current, IUL1 KIVI = 0 V –3

µ

A

low IUL2 KI/O VI = 0 V –3

µ

A

IUL3 S0, S1, S2VI = 0 V –3

µ

A

Output voltage, high VOH1 REM, LED, KI/O IOH = –0.3 mA 0.8VDD V

Output voltage, low VOL1 REM, LED IOL = 0.3 mA 0.3 V

VOL2 KI/O IOL = 15

µ

A0.4 V

Output current, high IOH1 REM VDD = 3.0 V, VOH = 1.0 V –5 –12 mA

IOH2 KI/O VDD = 3.0 V, VOH = 2.2 V –2.5 –7 mA

Output current, low IOL1 KI/O VDD = 3.0 V, VOL = 0.4 V 47 70

µ

A

VDD = 3.0 V, VOL = 2.2 V 260 390

µ

A

On-chip pull-down resistor

R1KI, S0, S1, S275 150 300 kΩ

R2KI/O 130 250 500 kΩ

Data retention power VDDOR In STOP mode 0.9 3.6 V

supply voltage

RAM retention detection VID 1.4 1.5 V

voltage

Supply current IDD1 Operation fX = 4.0 MHz, VDD = 3 V ±10% 0.7 1.4 mA

mode

IDD2 HALT mode fX = 4.0 MHz, VDD = 3 V ±10% 0.65 1.3 mA

IDD3 STOP mode VDD = 3 V ±10% 2.0 9.0

µ

A

VDD = 3 V ±10%, TA = 25°C1.8 3.0

µ

A

57

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

AC Characteristics (TA = –40 to +85°C, VDD = 2.0 to 3.6 V)

Item Symbol Conditions MIN. TYP. MAX. Unit

Command execution time tCY 14 16 18.5

µ

s

KI, S0, S1, S2 high-level tH10

µ

s

width When releasing standby mode In HALT mode 10

µ

s

In STOP mode Note

µ

s

Note 10 + 278/fX + oscillation growth time

Remark tCY = 64/fX (fX: System clock oscillator frequency)

POC Circuit (TA = –40 to +85°C)

Item Symbol Conditions MIN. TYP. MAX. Unit

POC detection voltage

Note

VPOC 1.85 2.0 V

Note Refers to the voltage with which the POC circuit releases an internal reset. If VPOC < VDD, the internal

reset is released.

From the time of VPOC ≥ VDD until the internal reset takes effect, a delay of up to 1 ms occurs. When the

period of VPOC ≥ VDD lasts less than 1 ms, the internal reset may not take effect.

System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 2.0 to 3.6 V)

Item Symbol Conditions MIN. TYP. MAX. Unit

Oscillator frequency fX3.5 4.0 4.5 MHz

(ceramic resonator)

58

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

RECOMMENDED OSCILLATOR CONSTANT

Ceramic Resonator (TA = –40 to +85°C) (Without On-Chip Capacitor for Oscillator Specified by Mask Option)

Manufacturer Part Number Frequency Recommended Constant (pF)

Oscillation Voltage Range (VDD)

Remark

(MHz) C1 C2 MIN. MAX.

Murata Mfg. CSTLS3M50G53-B0 3.5 Unnecessary (on-chip C type) 2.0 3.6 –

Co., Ltd. CSTLS3M50G56-B0

CSALA4M00G55-B0 4.0 30 30

CSTLS4M00G53-B0 Unnecessary (on-chip C type)

CSTLS4M00G56-B0

CSTLS4M50G53-B0 4.5

CSTLS4M50G56-B0

TDK FCR3.52MC5 3.52 Unnecessary (on-chip C type)

FCR4.0MC5 4.0

Kyocera KBR-3.64MKE 3.64 Unnecessary (on-chip C type)

KBR-3.64MSE 33 33

KBR-4.0MKE 4.0 Unnecessary (on-chip C type)

KBR-4.0MSE 33 33

External circuit example

Caution These oscillator constants are reference values based on evaluation by the manufacturer of

the resonator under a specific environment .

If optimization of the oscillator characteristics is required for the actual application, apply to

the resonator manufacturer for evaluation on the mounting circuit.

The oscillation voltage and oscillation frequency only indicate the oscillator characteristics;

the oscillator must be used within the ratings of the DC and AC characteristics specified under

the internal operation conditions of the

µ

PD67, 67A, 68, 68A, and 69 .

Remark The incorporation of the oscillation capacitor by a mask option is under evaluation.

X

IN

X

OUT

C1 C2

59

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

12. CHARACTERISTIC CURVES (REFERENCE VALUES)

Power supply current I

DD

[mA]

Power supply voltage V

DD

[V]

I

DD

vs. V

DD

(fx = 4 MHz)

(T

A

= 25°C)

1.5 2 32.5 3.6 4

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Operation mode

HALT mode

25

20

15

10

5

0123

Low-level output current I

OL

[mA]

Low-level output voltage V

OL

[V]

I

OL

vs. V

OL

(REM, LED)

(T

A

= 25°C, V

DD

= 3.0 V)

− 20

− 18

− 16

− 14

− 12

− 10

− 8

− 6

− 4

− 2

0

VDD VDD − 1VDD − 2VDD − 3

High-level output current I

OH

[mA]

High-level output voltage V

OH

[V]

I

OH

vs. V

OH

(REM, LED, K

I/O

)

(T

A

= 25°C, V

DD

= 3.0 V)

500

450

400

350

300

250

200

150

100

50

0123

Low-level output current I

OL

[ A]

µ

Low-level output voltage V

OL

[V]

I

OL

vs. V

OL

(K

I/O

)

(T

A

= 25°C, V

DD

= 3.0 V)

60

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

13. APPLICATION CIRCUIT EXAMPLE

Example of Application in System

•Remote-control transmitter (48 keys; mode selection switch supported)

Notes 1. When incorporation of a capacitor for oscillation has not been specified by a mask option.

2. S2: Set to disable for STOP mode release.

3. Set pins KI0 to KI3 to "with pull-down resistors".

K

I/O6

K

I/O7

S

0

S

1

/LED

REM

V

DD

X

OUTNote 1

X

INNote 1

GND

S

2Note 2

K

I/O5

K

I/O4

K

I/O3

K

I/O2

K

I/O1

K

I/O0

K

I3Note 3

K

I2Note 3

K

I1Note 3

K

I0Note 3

Key matrix

8 × 6 = 48 keys

+

Mode selection

switch

61

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

•Remote-control transmitter (56 keys accommodated)

Notes 1. When incorporation of a capacitor for oscillation has not been specified by a mask option.

2. S2: Set to enable for STOP mode release.

3. Set pins KI0 to KI3 to "with pull-down resistors".

KI/O6

KI/O7

S0

S1/LED

REM

VDD

XOUTNote 1

XINNote 1

GND

S2Note 2

KI/O5

KI/O4

KI/O3

KI/O2

KI/O1

KI/O0

KI3Note 3

KI2Note 3

KI1Note 3

KI0Note 3

Key matrix

8 × 7 = 56 keys

+

62

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

• Remote-control transmitter (56 keys supported, mode selection switch supported)

Data can be read from the KI/O0 to KI/O7 pins by connecting a pull-up resistor of 50 kΩ and a switch to these

pins (which then become high level when the switch is on and low level when off). Set the KI/O0 to KI/O7 pins

to input mode at this time. Reading data from these pins enables multiple output data to be obtained for the

same key input.

A pull-up resistor can be connected to any of pins KI/O0 to KI/O7 (the figure below shows an example of when

a pull-up resistor is connected to the KI/O5 pin).

The mode may not be correctly read while a key is being pressed.

Notes 1. When incorporation of a capacitor for oscillation has not been specified by a mask option.

2. S2: Set to enable for STOP mode release.

3. Set pins KI0 to KI3 to "with pull-down resistors".

KI/O6

KI/O7

S0

S1/LED

REM

VDD

XOUTNote 1

XINNote 1

GND

S2Note 2

KI/O5

KI/O4

KI/O3

KI/O2

KI/O1

KI/O0

KI3Note 3

KI2Note 3

KI1Note 3

KI0Note 3

Key matrix

8 × 7 = 56 keys

+

VDD

Mode selection switch

63

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

NS

C

DM

M

PL

U

T

G

F

E

B

K

J

detail of lead end

S

20 11

110

A

H

I

ITEM

B

C

I

L

M

N

20-PIN PLASTIC SSOP (7.62 mm (300))

A

K

D

E

F

G

H

J

P

T

MILLIMETERS

0.65 (T.P.)

0.475 MAX.

0.13

0.5

6.1±0.2

0.10

0.17±0.03

0.1±0.05

0.24

1.3±0.1

8.1±0.2

1.2

+0.08

–0.07

1.0±0.2

3°+5°

−3°

0.25

0.6±0.15

U

NOTE

Each lead centerline is located within 0.13 mm of

its true position (T.P.) at maximum material condition.

S20MC-65-5A4-2

6.65±0.15

14. PACKAGE DRAWINGS

Remark The external dimensions and material of the ES version are the same as those of the mass produced

version.

64

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

15. RECOMMENDED SOLDERING CONDITIONS

The

µ

PD67, 67A, 68, 68A, and 69 should be soldered and mounted under the following recommended conditions.

For soldering and conditions other than those recommended below, contact an NEC Electronics sales

representative.

For technical information, see the following website.

Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)

Table 15-1. Surface Mounting Type Soldering Conditions

(1)

µ

PD67MC-×××-5A4: 20-pin plastic SSOP (7.62 mm (300))

µ

PD67AMC-×××-5A4: 20-pin plastic SSOP (7.62 mm (300))

µ

PD68MC-×××-5A4: 20-pin plastic SSOP (7.62 mm (300))

µ

PD68AMC-×××-5A4: 20-pin plastic SSOP (7.62 mm (300))

µ

PD69MC-×××-5A4: 20-pin plastic SSOP (7.62 mm (300))

Soldering Method Soldering Conditions Recommended

Condition Symbol

Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), IR35-00-3

Count: Three times or less

VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher), VP15-00-3

Count: Three times or less

Wave soldering Solder bath temperature: 260°C max., Time: 10 seconds max., Count: once, WS60-00-1

Preliminary heat temperature: 120°C max. (package surface temperature)

Partial heating Pin temperature: 350°C max., Time: 3 sec. max. (per pin row) —

(2)

µ

PD67MC-×××-5A4-A: 20-pin plastic SSOP (7.62 mm (300))

µ

PD67AMC-×××-5A4-A: 20-pin plastic SSOP (7.62 mm (300))

µ

PD68MC-×××-5A4-A: 20-pin plastic SSOP (7.62 mm (300))

µ

PD68AMC-×××-5A4-A: 20-pin plastic SSOP (7.62 mm (300))

µ

PD69MC-×××-5A4-A: 20-pin plastic SSOP (7.62 mm (300))

Soldering Method Soldering Conditions Recommended

Condition Symbol

Infrared reflow Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or higher), IR60-103-3

Count: Three times or less, Exposure limit: 3 daysNote

(after that, prebake at 125°C for 10 to 72 hours)

Wave soldering For details, contact an NEC Electronics sales representative. —

Partial heating Pin temperature: 350°C max., Time: 3 sec. max. (per pin row) —

Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.

Caution Do not use different soldering methods together (except for partial heating).

Remark Products that have the part numbers suffixed by “-A” are lead-free products.

65

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

APPENDIX A. DEVELOPMENT TOOLS

An emulator is provided as an emulation tool and a PROM programmer and program adapter are provided as

writing tools for the PROM product, the

µ

PD6P9.

Hardware

•Emulator (EB-69Note 1)

Tool to emulate the

µ

PD67, 67A, 68, 68A, 69, and 6P9.

•Emulation probe (NP-20GSNote 1)

Probe for 20-pin SOP/SSOP to connect the emulator to the target system.

•Flexible board (EV-9500GS-20)

20-pin flexible board to facilitate the connection between the emulation probe and the target system.

•PROM programmer (AF-9706Note 2, AF-9708Note 2, AF-9709Note 2)

PROM programmer supporting the

µ

PD6P9.

The

µ

PD6P9 can be programmed by connecting the program adapter.

•Program adapter (PA-61P34BMC)

Adapter to program the

µ

PD6P9. Use in combination with the AF-9706, AF-9708, and AF-9709.

Notes 1. This is a product of Naito Densei Machida Mfg. Co., Ltd.

For details, contact Naito Densei Machida Mfg. Co., Ltd. (TEL: +81-45-475-4191).

2. This is a product of Ando Electric Co., Ltd.

For details, contact Ando Electric Co., Ltd. (TEL: +81-3-3733-1151).

Software

• Assembler (AS6133 Ver. 2.22 or later)

Development tool for remote control transmitter software.

Ordering Number List of AS6133

Host Machine OS Supply Medium Ordering Number

PC-9800 series MS-DOS (Ver. 5.0 to Ver. 6.2) 3.5-inch 2HD

µ

S5A13AS6133

(CPU: 80,386 or more)

IBM PC/AT compatible MS-DOS (Ver. 6.0 to Ver. 6.22) 3.5-inch 2HC

µ

S7B13AS6133

PC DOS (Ver. 6.1 to Ver. 6.3)

Caution Although Ver.5.0 or later has a task swap function, this function cannot be used with this

software.

66

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

Item

µ

PD64

µ

PD65

µ

PD67A

µ

PD68A

µ

PD69

ROM capacity 1,002 × 10 bits 2,026 × 10 bits 1,002 × 10 bits 2,026 × 10 bits 4,074 × 10 bits

RAM capacity 32 × 4 bits 128 × 4 bits

(32 × 4 bits × 4 pages)

Stack 1 level (multiplexed with RF of RAM)

Key matrix 8 × 6 = 48 keys 8 × 7 = 56 keys

Key extended input S0, S1S0 to S2

Clock frequency Ceramic oscillation Ceramic oscillation Ceramic oscillation

• fX = 2.4 to 8 MHz • fX = 2.4 to 8 MHz • fX = 3.5 to 4.5 MHz

• fX = 2.4 to 4 MHz

(with POC circuit)

Timer Clock fX/64, fX/128 fX/64

Count start Writing count value

Output value (Set value + 1) × 64/fX (or 128/fX)(Set value + 1) × 64/fX – 4/fX

(Set value + 1) × 64/f

X

Carrier Frequency

• fX/8, fX/64, fX/96 (timer clock: fX/64) Each high-/low-level width can be set from 250 ns to 64

µ

s

•

fX/16, fX/128, fX/192 (timer clock: fX/128)

(@ fX = 4 MHz operation) via modulo registers (2 channels).

• No carrier

Output start Synchronized with timer

Instruction execution time 16

µ

s (fX = 4 MHz)

“MOV Rn, @R0” instruction n = 1 to F

Standby Reset

RESET input, POC

POC

mode Release • HALT mode for timer only.

condition • STOP mode for only releasing KI

(HALT (KI/O high-level output or KI/O0 high-level output)

instruction)

Relation between HALT HALT instruction not executed when F = 1

instruction execution and

status flag (F)

POC circuit • Mask option • Provided

• Low level output • Generates internal reset signal on detection

to RESET pin • VPOC = 1.85 V (TYP.)

on detection

•

VPOC = 1.6 V (TYP.)

RAM retention detector None • Provided

• VID = 1.4 V (TYP.)

Mask option POC circuit None Capacitor for oscillator (15 pF)

Supply voltage • VDD=1.8 to 3.6 V VDD = 2.0 to 3.6 V

• VDD=2.2 to 3.6 V

(with POC circuit)

Operating temperature • TA=–40 to +85°CTA=–40 to +85°C

• TA=–20 to +70°C

(with POC circuit)

Package • 20-pin plastic 20-pin plastic SSOP

SOP

• 20-pin plastic

SSOP

One-time PROM model

µ

PD6P4B

µ

PD6P5

µ

PD6P9

APPENDIX B. FUNCTIONAL COMPARISON BETWEEN

µ

PD67A, 68A, 69, AND OTHER PRODUCTS

67

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

REM output

13.5 ms

Leader code

9 ms

4.5 ms

Custom code

8 bits

Custom code'

8 bits

Data code

8 bits

Data code

8 bits

27 ms

18 to 36 ms

58.5 to 76.5 ms

Stop bit

1 bit

< 3 >

APPENDIX C. EXAMPLE OF REMOTE-CONTROL TRANSMISSION FORMAT

(in the case of NEC transmission format in command one-shot transmission mode)

Caution When using the NEC transmission format, please apply to NEC for a custom code.

(1) REM output waveform (From <2> on, the output is made only when the key is held down)

REM output

58.5 to 76.5 ms

108 ms 108 ms

< 1 > < 2 >

Remark If the key is repeatedly pressed, the power consumption of the infrared light-emitting diode (LED) can

be reduced by sending the reader code and the stop bit from the second time.

(2) Enlarged waveform of <1>

(3) Enlarged waveform of <3>

REM output

9 ms

13.5 ms

0

4.5 ms

1100

2.25 ms

1.125 ms

0.56 ms

(4) Enlarged waveform of <2>

REM output

9 ms

11.25 ms

2.25 ms

0.56 ms

Stop bit

Leader code

68

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

(5) Carrier waveform (enlarged waveform of each code’s high period)

(6) Bit array of each code

C

0

C

1

C

2

C

3

C

4

C

5

C

6

C

7

C

0

'

C

0

or

C

o

C

1

'

C

1

or

C

1

C

2

'

C

2

or

C

2

C

3

'

C

3

or

C

3

C

4

'

C

4

or

C

4

C

5

'

C

5

or

C

5

C

6

'

C

6

or

C

6

C

7

'

C

7

or

C

7

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

=

=

=

=

=

=

=

=

Data codeData codeCustom code'Custom codeLeader code

Caution To prevent malfunction with other systems when receiving data in the NEC transmission

format, not only fully decode (make sure to check Data code as well) the total 32 bits of the

16-bit custom codes (Custom code, Custom code’) and the 16-bit data codes (Data code,

Data code), but also check to make sure that no signals are present.

REM output

8.77 s

9 ms or 0.56 ms

Carrier frequency: 38 kHz

26.3 s

µ

µ

69

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

1

2

3

4

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the

CMOS device stays in the area between V

IL

(MAX) and V

IH

(MIN) due to noise, etc., the device may

malfunction. Take care to prevent chattering noise from entering the device when the input level is

fixed, and also in the transition period when the input level passes through the area between V

IL

(MAX)

and V

IH

(MIN).

HANDLING OF UNUSED INPUT PINS

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is

possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V

DD

or

GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins

must be judged separately for each device and according to related specifications governing the device.

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as

much as possible, and quickly dissipate it when it has occurred. Environmental control must be

adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that

easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work

benches and floors should be grounded. The operator should be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for

PW boards with mounted semiconductor devices.

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power

source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does

not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the

reset signal is received. A reset operation must be executed immediately after power-on for devices

with reset functions.

POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external

interface, as a rule, switch on the external power supply after switching on the internal power supply.

When switching the power supply off, as a rule, switch off the external power supply and then the

internal power supply. Use of the reverse power on/off sequences may result in the application of an

overvoltage to the internal elements of the device, causing malfunction and degradation of internal

elements due to the passage of an abnormal current.

The correct power on/off sequence must be judged separately for each device and according to related

specifications governing the device.

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current

injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and

the abnormal current that passes in the device at this time may cause degradation of internal elements.

Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

NOTES FOR CMOS DEVICES

5

6

70

µ

PD67, 67A, 68, 68A, 69

Data Sheet U14935EJ2V1DS

Regional Information

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary

from country to country.

[GLOBAL SUPPORT]

http://www.necel.com/en/support/support.html

NEC Electronics America, Inc. (U.S.)

Santa Clara, California

Tel: 408-588-6000

800-366-9782

NEC Electronics Hong Kong Ltd.

Hong Kong

Tel: 2886-9318

NEC Electronics Hong Kong Ltd.

Seoul Branch

Seoul, Korea

Tel: 02-558-3737

NEC Electronics Shanghai Ltd.

Shanghai, P.R. China

Tel: 021-5888-5400

NEC Electronics Taiwan Ltd.

Taipei, Taiwan

Tel: 02-2719-2377

NEC Electronics Singapore Pte. Ltd.

Novena Square, Singapore

Tel: 6253-8311

J05.6

N

EC Electronics (Europe) GmbH

Duesseldorf, Germany

Tel: 0211-65030

•

Sucursal en España

Madrid, Spain

Tel: 091-504 27 87

Vélizy-Villacoublay, France

Tel: 01-30-67 58 00

•

Succursale Française

•

Filiale Italiana

Milano, Italy

Tel: 02-66 75 41

•

Branch The Netherlands

Eindhoven, The Netherlands

Tel: 040-265 40 10

•

Tyskland Filial

Taeby, Sweden

Tel: 08-63 87 200

•

United Kingdom Branch

Milton Keynes, UK

Tel: 01908-691-133

Some information contained in this document may vary from country to country. Before using any NEC

Electronics product in your application, pIease contact the NEC Electronics office in your country to

obtain a list of authorized representatives and distributors. They will verify:

µ

PD67, 67A, 68, 68A, 69

MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States

and/or other countries.

PC/AT and PC DOS are trademarks of International Business Machines Corporation.

The information in this document is current as of August, 2005. The information is subject to

change without notice. For actual design-in, refer to the latest publications of NEC Electronics data

sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not

all products and/or types are available in every country. Please check with an NEC Electronics sales

representative for availability and additional information.

No part of this document may be copied or reproduced in any form or by any means without the prior

written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may

appear in this document.

NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual

property rights of third parties by or arising from the use of NEC Electronics products listed in this document

or any other liability arising from the use of such products. No license, express, implied or otherwise, is

granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.

Descriptions of circuits, software and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these

circuits, software and information in the design of a customer's equipment shall be done under the full

responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by

customers or third parties arising from the use of these circuits, software and information.

While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,

customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To

minimize risks of damage to property or injury (including death) to persons arising from defects in NEC

Electronics products, customers must incorporate sufficient safety measures in their design, such as

redundancy, fire-containment and anti-failure features.

NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and

"Specific".

The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-

designated "quality assurance program" for a specific application. The recommended applications of an NEC

Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of

each NEC Electronics product before using it in a particular application.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC

Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications

not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to

determine NEC Electronics' willingness to support a given application.

(Note)

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M8E 02. 11-1

(1)

(2)

"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

majority-owned subsidiaries.

"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as

defined above).

Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment

and industrial robots.

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support).

Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

"Standard":

"Special":

"Specific":

These commodities, technology or software, must be exported in accordance

with the export administration regulations of the exporting country.

Diversion contrary to the law of that country is prohibited.