19-2694; Rev B, 07/04 !#"!%$'&)(+* ,-&.$ /0/0/0/0/0/0/0/0/0/0/0/0/0/0/0/ 13254625798;:=<>25?;@579ACBEDFAHG54 J0J0J0J0J0J0J0J0J0J0J0J0J0J0J0J0J0J0J0J0J0J0J0J0J0J0J0J K=LNMPORQTSULTV The MAX3740A evaluation kit (EV kit) is an assembled demonstration board that provides complete optical and electrical evaluation of the MAX3740A VCSEL driver. I The output of the evaluation kit can be interfaced to an SMA connector, which can be connected to a 50 terminated oscilloscope. With slight modifications, the evaluation kit can also be used to evaluate the MAX3740A operation with a common-cathode VCSEL. m0m0m0m0m0m0m0m0m0m0m0m0m0m0m0m0m0m0m0m nEo5p+qro5s6t5svuxw;yaz{u DESIGNATION QTY DESCRIPTION C1, C2, C5, C9, 0.1F 10% ceramic capacitors 8 C13, C15, C16, (0402) C17 Fully Assembled and Tested Single +3.3V Power Supply Operation Allows Optical and Electrical Evaluation W0W0W0W0W0W0W0W0W0W0W0W0W0W0W XZY\[;]TY_^a;b%cd6egf5Yihkj6lF^Hf5 PART TEMP. RANGE IC PACKAGE MAX3740AEVKIT -40C to +85C 24 QFN DESIGNATION QTY DESCRIPTION R16 1 500k potentiometer Q1, Q2 2 NPN transistors (SOT23) Q3 1 MOSFET (SOT23) JU1-JU8, JU10 9 2-pin headers, 0.1in centers J1-J7 7 SMA connectors, round contacts 1 0.047F 10% ceramic capacitor (0402) C4, C6, C7, C8, C11, C12 6 0.01F 10% ceramic capacitors (0402) C10 1 Open C14 1 10F 10% ceramic capacitor (0805) U1 1 MAX3740AETG (24QFN) U2 1 MAX495ESA (8 SO) C18 1 10F 10% tantalum capacitor (B Case) None 9 Shunts D1 1 VCSEL laser and photodiode* None 1 MAX3740A EV board D2 1 LED, red T1 package None 1 MAX3740A data sheet L1, L2, L3 3 L4 1 1H inductor (1008CS) R1, R2 2 10k potentiometers R3 1 350 1% resistor (0402) R4 1 2.49k 1% resistor (0402) R5, R12 2 499 1% resistors (0402) R6, R13 2 10k 5% resistors (0402) R7 1 0 1% resistor (0402)* R8 1 4.7k 1% resistor (0402) R9, R11 2 49.9 1% resistors (0402) R10, R26, R27, R34, R35, R36 6 Open R14 1 20k potentiometer R15 1 50k potentiometer |0|0|0|0|0|0|0|0|0|0|0| }~5+x~56Tv=ZH;~5C C3 iR FFR'FiRi| TP1-TP11, TP20, 13 Test points TP21 * These components are not supplied but can be populated for VCSEL testing. 0000000000000 E(c)5+r(c)565v(R)v;vdH5i SUPPLIER PHONE FAX AVX 843-444-2863 843-626-3123 Coilcraft 847-639-6400 847-639-1469 Digi-Key 218-681-6674 218-681-3380 EF Johnson 402-474-4800 402-474-4858 Murata 415-964-6321 415-964-8165 Note: Please indicate that you are using the MAX3701 when ordering from these suppliers. _________________________________________________________________Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 * 1/4* 1/23/4A!A#A!%AAA)AE+C EEA.A UUO U0U0U0U0U0U0U0U0U0U0U0U0U0U0U0U0U0U0U0eU0U0eiIe.U0ii.U0inHU0gU oiIii.Y3ooeoNeTHa5oe0o/oa%eiIo.axoi.aainHacoIiuoaeeu a OUx OO OO OIN IIII IE E I = MD In the electrical configuration, an automatic power control (APC) test circuit is included to emulate a semiconductor laser with a monitor photodiode. Monitor diode current is provided by transistor Q1, which is controlled by an operational amplifier (U2). The APC test circuit, consisting of U2 and Q1, applies the simulated monitor diode current to the MD pin of the MAX3740. To ensure proper operation in the electrical configuration, set up the evaluation board as follows: 1) 2) 3) I BIAS = V 2x R PWRMON PWRSET 9x V 350 BIASMON Note: If the voltage at TP1 exceeds VPMTH (0.8V typ) or TP3 exceeds VBMTH (0.8V typ), the FAULT signal will be asserted and latched. Place shunts on JU4 - JU8 and JU10 (see the Adjustment and Control Description section for details). Remove shunts JU1 and JU2. To enable the output connect TX_DISABLE to GND by placing a shunt on JU3. 14) Adjust R2 until the desired laser modulation current is achieved. Note: When performing the following resistance checks, autoranging DMMs may forward bias the onchip ESD protection and cause inaccurate measurements. To avoid this, manually set the DMM to a high range. 15) Adjust R14 (RPEAKSET) until the desired amount of peaking is achieved. 4) Adjust R15, the RBIASSET potentiometer, for 1.7k resistance between TP4 (BIASSET) and ground. 5) Adjust R1, the RPWRSET potentiometer, for 10k resistance between TP2 (REF) and pin 1 (MD) of JU2. 6) Adjust R14, the RPEAKSET potentiometer, for 20k resistance between TP10 (PEAKSET) and ground, to disable peaking. 7) Adjust R16, the RTC potentiometer, for 0 resistance between TP7 (TC1) and TP8 (TC2), to disable temperature compensation. 8) Adjust R2, the RMODSET potentiometer, for 10k resistance between TP9 (MODSET) and ground. 9) Apply a differential input signal (250mVP-P to 2200mVP-P) between SMA connectors J5 and J7 (IN+ and IN-). 10) Attach a high-speed oscilloscope with a 50 input to SMA connector J6 (OUT). 11) Connect a +3.3V supply between TP20 (VCC) and TP21 (GND). Adjust the power supply until the voltage between TP11 and ground is +3.3V. 12) Adjust R1 (RPWRSET) until desired laser bias current is achieved. I BIAS = V 49.9 PIN 1 _ JU 5 13) The MD and BIAS currents can be monitored at TP1 (VPWRMON) and TP3 (VBIASMON) using the equations below: IMOD = Signal Amplitude (V ) 50 u'u5yHiIy .yHn For optical evaluation of the MAX3740A, configure the evaluation kit as follows: 1) 2) 3) 4) 5) Place shunts on JU2, JU6, JU7, JU8 and JU10 (See the Adjustment and Control Description section for details). Remove components L2 and C9. Remove the shunts from JU1, JU4 and JU5. Install a 0 resistor at R7 to connect the anode of the VCSEL to the output. To enable the output connect TX_DISABLE to GND by placing a shunt on JU3. Connect a common cathode VCSEL as shown in Figure 1. Keep leads short to reduce reflection. Note: When performing the following resistance checks, autoranging DMMs may forward bias the onchip ESD protection and cause inaccurate measurements. To avoid this, manually set the DMM to a high range. 6) 7) 8) 9) Adjust R15, the RBIASSET potentiometer, for 1.7k resistance between TP4 (BIASSET) and ground. Adjust R1, the RPWRSET potentiometer, for 10k resistance between TP2 (REF) and pin 1 (MD) of JU2. Adjust R14, the RPEAKSET potentiometer, for 20k resistance between TP10 (PEAKSET) and ground, to disable peaking. Adjust R16, the RTC potentiometer, for 0 resistance between TP7 (TC1) and TP8 (TC2), to disable temperature compensation. 2 ________________________________________________________________________________________ 10) Adjust R2, the RMODSET potentiometer, for 10k resistance between TP9 (MODSET) and ground. 11) Apply a differential input signal (250mVP-P to 2200mVP-P) between SMA connectors J5 and J7 (IN+ and IN-). 12) Attach the VCSEL fiber connector to an optical/electrical converter. 13) Connect a +3.3V supply between TP20 (VCC) and TP21 (GND). Adjust the power supply until the voltage between TP11 and ground is +3.3V. 14) Adjust R1 (RPWRSET) until desired average optical power is achieved. 15) The MD and BIAS currents can be monitored at TP1 (VPWRMON) and TP3 (VBIASMON) using the equations below: V I = 2xR PWRMON I BIAS "!$#&%(' = )*#! 9xV 350 +, BIASMON -. Note: If the voltage at TP1 exceeds VPMTH (typical 0.8V) or TP3 exceeds VBMTH (typical 0.8V), the FAULT signal will be asserted and latched. 16) Adjust R2 (RMODSET) until the desired optical amplitude is achieved. Optical amplitude can be observed on an oscilloscope connected to an optical/electrical converter. VCSEL overshoot and ringing can be improved by appropriate selection of R10 and C10, as described in the Design Procedure section of the MAX3740 data sheet. MD ;<;<;<;<;<;<;<;<;<; / -0 12 3 45 6 78 9 :5 PWRSET =?>A@CBEDGFIH"JKLFNMOKP>RQTSKLFVUASXWZY[JED]\U_^aTFb^cSEKedfD]J]JRghBi^c\Ej"klFbMXU<FTmn^fUoDGFfp COMPONENT NAME FUNCTION D2 Fault Indicator JU1 COMP Enables/disables the APC circuit. Remove the shunt to enable the APC circuit. JU2 PHOTODIODE Installing a shunt connects the photodiode of the VCSEL to the MD pin. Used when a VCSEL is installed. JU3 TX_DISABLE Enable/disable the output currents. Install a shunt to enable output currents. JU4 IPD JU5 APCOPEN JU6 FAULT JU7 SQUELCH JU8 POWER Installing a shunt provides power to the part. JU10 VCCEXT Installing a shunt provides power to the emulation and fault-indicator circuits. R1 RPWRSET Adjusts transmit optical power to be maintained by the APC loop. R2 RMODSET Adjusts the laser modulation current. R14 RPEAKSET Adjusts the peaking for the falling edge of the VCSEL. R15 RBIASSET In a closed-loop configuration: adjusts the maximum bias current available to the APC. In an open-loop configuration: adjusts the bias level of the output. R16 RTC The LED is illuminated when a fault condition has occurred (refer to the Detailed Description section of the MAX3740 data sheet). Determines the gain of the photodiode emulator. When JU4 is open, the gain is 0.02A/A. When JU4 is shunted, the gain is 0.12A/A. Installing a shunt connects the electrical output of the part to the emulation circuit. Installing a shunt enables the external fault-indicator circuit. Installing a shunt enables the squelch function. Adjusts the temperature compensation of the modulation current. _________________________________________________________________________________________ 3 JU8 POWER VCC1 TP11 NOISEGEN L4 1H L3 BLM18HD102SN1 JU10 VCCEXT VCCEXT Q3 TP20 VCC C14 10F C15 0.1F C16 0.1F C18 10F C7 0.01F C17 0.1F JU2 PHOTODIODE R35 OPEN VCCEXT C12 0.01F VCC1 5 D2 FAULT R13 10k Q2 FMMT491A JU7 SQUELCH 6 VCC1 R8 4.7k SQUELCH 8 9 10 11 GND 17 VCC1 16 15 14 13 r w v u t s r TP7 TC1 C9 0.1F C11 0.01F R9 49.9 R7 OPEN C10 OPEN 12 R10 OPEN R2 10k MODSET TP8 TC2 L2 BLM18HD102SN1 C8 0.01F TP9 MODSET R26 OPEN R6 10k R11 49.9 R16 500k TC TP5 FAULT R5 499 R36 OPEN BIASMON VCC MD COMP OUT- C4 0.01F R12 499 REF FAULT 7 JU6 FAULT OUT+ 2 TP4 BIASSET TP10 PEAKSET R14 20k PEAKSET VCC1 IN- 4 2 4 1 3 D1 VCSEL PHOTODIODE J6 OUT q Figure 1. MAX3740A EV Kit Schematic Diagram VCCEXT VCC U1 MAX3740A 18 JU4 IPD R4 2.49k R34 OPEN 4 BIASSET R27 OPEN J7 IN- IN+ L1 BLM18HD102SN1 BIAS 3 U2 R3 350 19 PEAKSET C13 0.1F 20 MODSET 3 21 GND &" ( ~ z } | { z y x J5 IN+ TP3 BIASMON TX_DISABLE TC2 2 C5 0.1F GND 22 TC1 1 VCC ~ JU3 TX_DISABLE 23 PWRMON 24 6 MAX495 TP1 PWRMON J4 CALOUT- Q1 FMMT491A R15 50k BIASSET C3 0.047F C2 0.1F J3 CALIN- 7 C6 0.01F TP2 REF JU1 COMP J2 CALOUT+ JU5 APCOPEN R1 10k PWRSET C1 0.1F J1 CALIN+ 4 ________________________________________________________________________________________ TP6 PORTEST TP21 GND "$&( |* (c) (c) (R) Figure 2. MAX3740A EV Kit Component Placement Guide - Component Side Figure 3. MAX3740A EV Kit PC Board Layout Solder Side _________________________________________________________________________________________ 5 * 1/41/2 3/4{AA AA"AA&A(AE CAA O Ox OO O NO I II E EI E EE Figure 4. MAX3740A EV Kit PC Board Layout Ground Plane Figure 5. MAX3740A EV Kit PC Board Layout Power Plane Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 6 ___________________ Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.