© Semiconductor Components Industries, LLC, 2018
January, 2020 − Rev. 2
1Publication Order Number:
NCP12700/D
PWM Controller, Input
Current Mode, Ultra Wide
NCP12700
The NCP12700 is a fixed frequency, peak current mode, PWM
controller containing all of the features necessary for implementing
single−ended power converter topologies. The device features a high
voltage startup capable of operating over a wide input range and
supplying at least 15 mA to provide temporary bias to VCC during
system startup. The device contains a programmable oscillator
capable of operating from 100 kHz to 1 MHz and integrates slope
compensation to prevent subharmonic oscillations. The controller
offers an adjustable soft−start, input voltage UVLO protection, and an
adjustable Over−Power Protection circuit which limits the total power
capability of the circuit as the input voltage increases, easing the
system thermal design. The UVLO pin also features a shutdown
comparator which allows for an external signal to disable switching
and bring the controller into a low quiescent state.
The NCP12700 contains a suite of protection features including
cycle−by−cycle peak current limiting, timer−based overload
protection, and a FLT pin which can be interfaced with an NTC and an
auxiliary winding to provide system thermal protection and output
over−voltage protection. All protection features place the device into a
low quiescent fault mode and recovery from fault mode is dependent
on the device option.
Common General Features
•Wide Input Range (9 – 120/200 V; MSOP10/WQFN10)
•Startup Regulator Circuit with 15 mA Capability
•Current Mode Control with Integrated Slope Compensation
•Suitable for Flyback or Forward Converters
•Single Resistor Programmable Oscillator
•1 A / 2.8 A Source / Sink Gate Driver
•User Adjustable Soft−Start Ramp
•Input Voltage UVLO with Hysteresis
•Shutdown Threshold for External Disable
•Skip Cycle Mode for Low Standby Power
•This is a Pb−Free Device
Fault Protection Features
•User Adjustable Over−Power Protection
•Overload Protection with 30 ms Overload Timer
•NTC−Compatible Fault Interface for Thermal
Protection
•Output OVP Fault Interface
•Fault Auto−recovery Mode with 1 s Auto−recovery
Period
Typical Applications
•Single−ended Power Converters including CCM/DCM
Flyback and Forward Converters
•Telecommunications Power Converters
•Industrial Power Converter Modules
•Transportation & Railway Power Modules
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MARKING DIAGRAMS
WQFN10
MT SUFFIX
CASE 511DV
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
MSOP
DN SUFFIX
CASE 846AE
1
12700 or 700 = Specific Device Code
x = A or B
A = Assembly Site
L = Wafer Lot Number
YW = Assembly Start Week
G= Pb−Free Package
12700x
ALYWG
G
1
10
700x
ALYW
(Note: Microdot may be in either location)
NCP12700
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Figure 3. Block Diagram
9
7
3
2
8
5
6
4
1
10
VDRV
OSC
RT VDD
DRV
FLT
CLK
FAULT
Logic
DMAX
GND
SS
SS
CONTROL
OVLD
IFLT
ISS
VDD
VCOMP(skip)
VCOMP(skip_hys)
MAIN
LOGIC
VCCON
ENABLE
FAULT
START
VSS
FAULT
SHDN
SS_END
CCC
VCC
VIN
Regulation
HV Startup
INTERNAL
REGULATOR
VDD VDRV
VCC
LOGIC
VCCON
VCC(OVP)
VCC(OVP)
VCC(UVLO)
VCC(UVLO)
UVLO
IUVLO(HYS)
COMP
VSS
VDD
5k
1/6
1/6
CS
UVLO
Detection
SHDN
ENABLE
Over−Power
Protection ICS(OPP)
LEB
Block
VDD
ICS(OPP)
PWM
LOGIC
Slope
Comp
OVLD
S
Q
R
CLK
DRV
STOP
START
DMAX
SS_END
START
TSD TSD
TSD
STOP
NCP12700
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VIN
VCC
DRV
GND
CS
UVLO
FLT
SS
RT
COMP
VIN
VCC
DRV
GND
CS
UVLO
FLT
SS
RT
COMP
PINOUTS
(Top Views)
EP
Table 1. PIN FUNCTION DESCRIPTION
MSOP10 WQFN10 Pin Name Pin Description
1 9 UVLO The UVLO pin is the input to the Standby and UVLO comparators. A resistor divider between
the power supply input voltage and ground is connected to the UVLO pin to set the input volt-
age level at which the controller will be enabled. UVLO Hysteresis is set by a 5 mA pull−down
current source. An externally supplied pull−down signal can also be used to disable the con-
troller. The UVLO pin is also used to determine the Over−Power Protection current supplied to
the CS pin.
2 10 FLT The FLT pin is the input to a window comparator which provides an upper and lower fault
threshold. When either threshold is tripped, the controller enters the fault mode which can be a
permanent latch off or a minimum 1 s auto−recovery period. A precision current source is out-
put from the FLT pin allowing an NTC to ground to be placed at the pin for system Over−tem-
perature protection. The upper threshold can be used for output over−voltage protection
sensed through the auxiliary winding or as a general purpose fault.
3 1 SS The SS pin sets the soft−start ramp of the peak current limit when the controller is enabled. An
internal 15 mA current source and an external capacitor to ground are used to control the ramp
rate. Typical soft start capacitor values will be in the range of 10 nF to 100 nF.
4 2 RT The RT pin sets the oscillator frequency in the controller. This pin requires a resistor to ground
located close to the IC. Typical RT values are in the range of 10 kW – 100 kW.
5 3 COMP The COMP pin provides the compensated error voltage for the PWM and Skip comparators.
An internal 5 kW pull−up resistor is connected to the COMP pin and can be used to bias the
transistor of an opto−coupler.
6 4 CS The CS pin is the current sense input for the PWM and Current Limit comparators. The com-
parator input is held low for 60 ns after the DRV goes high to prevent leading edge current
spikes from tripping the comparators. An external low pass filter is recommended for improved
noise immunity. The external filter resistor is also used to determine the amount of Over−Pow-
er Protection applied to the current sense.
7 5 GND This pin is the controller ground. For the WQFN package the exposed pad (EP) should be
connected to GND.
8 6 DRV The DRV pin is a high current output used to drive the external MOSFET gate. DRV has
source and sink capability of 1 A and 2.8 A, respectively.
9 7 VCC The VCC pin provides bias to the controller. An external decoupling capacitor to ground in the
range of 1 – 10 mF is recommended.
10 8 VIN The VIN pin is the input to the high voltage startup regulator. The regulator is capable of sourc-
ing > 15 mA to temporarily bias VCC while the application is starting up.
ORDERING INFORMATION
Device Package OTP Fault OVP Fault Shipping
†
NCP12700ADNR2G MSOP10 Latch Latch 4000 / Tape & Reel
NCP12700BDNR2G MSOP10 Autorecovery Autorecovery 4000 / Tape & Reel
NCP12700BMTTXG WQFN10 Autorecovery Autorecovery 3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
NCP12700
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Table 2. MAXIMUM RATINGS
Rating Symbol Value Unit
High Voltage Startup Voltage (MSOP10)
(WQFN10)
VIN(MAX) 120
200
V
High Voltage Startup Current IIN(MAX) 50 mA
Supply Voltage VCC(MAX) −0.3 to 30 V
Supply Current ICC(MAX) 50 mA
DRV Voltage (Note 1) VDRV(MAX) −0.3 V to VDRV(high) V
DRV Current (Peak) IDRV(MAX) 3.25 A
FLT Voltage VFLT(MAX) VCC + 1.25 V
FLT Current IFLT(MAX) 10 mA
Max Voltage on Signal Pins VSIG(MAX) −0.3 to 5.5 V
Max Current on Signal Pins ISIG(MAX) 10 mA
Thermal Resistance Junction−to−Air (Note 2) (MSOP10)
(WQFN10)
RθJ−A165
51
°C/W
Junction−to−Top Thermal Characterization Parameter (MSOP10)
(WQFN10)
YJ−C10
12
°C/W
Maximum Junction Temperature TJMAX 150 °C
Maximum Power Dissipation (MSOP10)
(WQFN10)
PDInternally Limited W
Storage Temperature Range TSTG −55 to 150 °C
Operating Temperature Range TJ−40 to 125 °C
ESD Capability (Note 3)
Human Body Model per JEDEC Standard JESD22−A114E
Charge Device Model per JEDEC Standard JESD22−C101E
2000
1000
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Maximum driver voltage is limited by the driver clamp voltage, VDRV(high), when VCC exceeds the driver clamp voltage. Otherwise, the
maximum driver voltage is VCC.
2. Per JEDEC specification JESD51.7 using two 1 oz copper planes with board size = 80x80x1.6 mm
3. This device series contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per JEDEC Standard JESD22−A114E
Charge Device Model TBD per JEDEC Standard JESD22−C101E
4. This device contains latch−up protection and has been tested per JEDEC JESD78D, Class I and exceeds +/−100 mA (TBD).
Table 3. RECOMMENDED OPERATING CONDITIONS
Rating Symbol Value Unit
VIN Voltage (MSOP10)
(WQFN10)
VIN 9 – 100
12 – 160
V
Supply Voltage − All VCC 9 – 20 V V
Operating Temperature Range TJ−40 to 125 °C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
NCP12700
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Table 4. ELECTRICAL CHARACTERISTICS (VIN = 12 V, VCC = 12 V, VCOMP = Open, VFLT = Open, CDRV = 1 nF, RT = 49.9k, VCS
= 0 V, VSS = Open, VUVLO = 1.2, for typical values TJ = 25°C, for min/max values, TJ is – 40°C to 125°C, unless otherwise noted)
Characteristics Test Condition Symbol Min Typ Max Unit
HIGH VOLTAGE STARTUP REGULATOR
Regulated Voltage VCC = Open, ICC = 5 mA VCC(REG) 7.6 8 8.4 V
Current Source Capability VIN = 9 V, VCC = 7 V IVIN(SRC) 15 mA
Current Source Limit VCC = VCC(off) + 100 mV IVIN(LIM) 30 mA
Off−State Leakage Current (xMTTXG) VCC = Open, VIN = 160 V, VUVLO = 0 IVIN(OFF) 100 mA
Off−State Leakage Current (xDNR2G) VCC = Open, VIN = 120 V, VUVLO = 0 IVIN(OFF) 100 mA
SUPPLY CIRCUIT
Supply Voltage
Startup Threshold
Minimum Operating Voltage
VCC increasing
VCC decreasing
VCC(on)
VCC(off)
VCC(REG) –
350 mV
6.2 6.5
VCC(REG) –
100 mV
6.8
V
Supply Over−Voltage Protection VCC(OVP) 28 V
VCC OVP Detection Filter Delay tVCCOVP
(DLY)
3ms
Startup Delay Measured from VCC(ON) to SS tON(Dly) 25 ms
Supply Current
SHDN
STBY
Enable
Fault
VUVLO = 0 V
VUVLO = 0.7 V
CDRV = Open, VCOMP = 2 V
VFLT = 0 V
ICC(SHDN)
ICC(STBY)
ICC(EN)
ICC(FLT)
−
−
−
−
−
−
−
−
50
750
4
500
mA
mA
mA
mA
CURRENT SENSE
Current Limit Comparator Threshold VCS(LIM) 465 495 525 mV
Propagation Delay From Current
Sense Limit to DRV Low
Step VCS from 0 – 0.6 V tCS(DLY) − − 75 ns
Short Circuit Protection (SCP) Current
Limit Threshold
VSCP(LIM) 625 mV
Propagation Delay From Short Circuit
Limit to DRV Low
VCS = 0.75 V tSCP(DLY) − − 75 ns
Short Circuit Counter VCS = 0.75 V NSCP 4
CS Leading Edge Blanking (LEB) tLEB(CS) 75 100 125 ns
SCP Leading Edge Blanking tLEB(SCP) 45 60 75 ns
CS LEB Pull−down Resistance RPD(LEB) −55 W
Overload Timer Duration VCS = 0.6 V tCS(OVLD) 24 30 36 ms
Applied Slope Compensation @ Cur-
rent Limit Comparator
VCOMP = Open; Measured at D80% VSLP(ILIM) 83 102 123 mV
Duty Cycle Where Slope Compensat-
ing Ramp Begins
D40% 40 %
COMP SECTION
PWM to COMP Gain Through Resistor
Divider
VCOMP = 2 V KPWM 6
PWM Propagation Delay to DRV Low VCOMP = 2 V, Step from CS 0– 0.4 V tPWM(Dly) −75 ns
COMP Open Pin Voltage VCOMP(open) 4 4.7 V
COMP Output Current VCOMP = 0 ICOMP 0.84 1 1.2 mA
Maximum Duty Cycle VCOMP = Open DMAX 76 80 84 %
COMP Skip Threshold VCOMP(skip) 300 mV
NCP12700
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Table 4. ELECTRICAL CHARACTERISTICS (VIN = 12 V, VCC = 12 V, VCOMP = Open, VFLT = Open, CDRV = 1 nF, RT = 49.9k, VCS
= 0 V, VSS = Open, VUVLO = 1.2, for typical values TJ = 25°C, for min/max values, TJ is – 40°C to 125°C, unless otherwise noted)
Characteristics UnitMaxTypMinSymbolTest Condition
COMP SECTION
COMP Skip Hysteresis VCOMP
(skip_hys)
25 mV
Minimum Duty Cycle VCOMP = 0 DMIN 0 %
Applied Slope Compensation @ PWM
Comparator
VCOMP = 2 V; Measured at D80% VSLP(PWM) 77 98 117 mV
SOFT START
Soft−Start Open Pin Voltage VSS(open) 5.0 V
Soft−Start End Threshold VSS(end) 2.85 3 3.15 V
Soft−Start Current VSS = 3 V ISS 12 15 18 mA
Soft−Start to CS Divider KSS 6
Soft−Start Discharge Resistance RSS(DIS) 100 W
OSCILLATOR
Oscillator Frequency 1 FOSC1 185 200 215 kHz
Oscillator Frequency 2 RT = 100 kWFOSC2 95 100 105 kHz
Oscillator Frequency 3 RT = 20 kWFOSC3 450 500 550 kHz
Oscillator Frequency 4 RT = 9.09 kWFOSC4 1000 kHz
UNDER−VOLTAGE LOCKOUT (UVLO)
Standby Threshold VUVLO increasing VSTBY(th) 0.35 0.5 0.65 V
Reset Threshold VUVLO decreasing VRST(th) 0.3 0.45 0.6 V
Standby Hysteresis VUVLO decreasing VSTBY(HYS) 50 mV
Standby Detection RC Filter tSTBY(DLY) 5ms
UVLO Threshold VUVLO increasing VUVLO(th) 765 800 830 mV
UVLO Threshold Hysteresis VUVLO decreasing VUVLO(HYS) 15 mV
UVLO Hysteresis Current IUVLO(HYS) 4.5 5 5.5 mA
UVLO Detection Delay Filter VUVLO = VUVLO(th) − 20 mV tUVLO(DLY) 0.5 1 ms
OVER−POWER PROTECTION (OPP)
UVLO Voltage Above Which OPP Ap-
plied
VOPP(START) 1 V
OPP Gain Gm(OPP) 135 150 165 mA / V
Maximum Current (Operating Point) VUVLO = 2.33 V ICS(OPP1) 180 200 220 mA
Maximum Current VUVLO = 4 V ICS
(OPP_MAX)
200 mA
COMP Threshold Voltage Above Which
OPP is Applied
VOPP(0%) 0.8 V
COMP Threshold Voltage For 100%
OPP
VOPP(100%) 2 V
GATE DRIVE
DRV Rise Time VDRV = 1.2 V to 10.8 V tDRV(rise) 6 10 15 ns
DRV Fall Time VDRV = 10.8 V to 1.2 V tDRV(fall) 2.5 4 10 ns
DRV Source Current VDRV = 6 V IDRV(SRC) 1.0 A
DRV Sink Current VDRV = 6 V IDRV(SNK) 2.8 A
DRV Clamp Voltage VCC = 20 V, RDRV = 10 kWVDRV(clamp) 10 12 14 V
NCP12700
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Table 4. ELECTRICAL CHARACTERISTICS (VIN = 12 V, VCC = 12 V, VCOMP = Open, VFLT = Open, CDRV = 1 nF, RT = 49.9k, VCS
= 0 V, VSS = Open, VUVLO = 1.2, for typical values TJ = 25°C, for min/max values, TJ is – 40°C to 125°C, unless otherwise noted)
Characteristics UnitMaxTypMinSymbolTest Condition
GATE DRIVE
Minimum DRV Voltage VCC = VCC(OFF) + 100 mV,
RDRV = 10 kW
VDRV(MIN) 6 V
FAULT PROTECTION
Fault Source Current IFLT 80 85 90 mA
OTP Fault Threshold VFLT(OTP) 0.47 0.5 0.53 V
OTP Detection Filter Delay tOTP(DLY) 10 20 30 ms
OTP Fault Recovery Threshold VFLT(REC) 0.846 0.9 0.954 V
OVP Fault Threshold VFLT(OVP) 2.8 3 3.2 V
OVP Detection Filter Delay tOVP(DLY) 3 5 7 ms
Fault Clamp Voltage VFLT = Open VFLT(CLAMP) 1.13 1.35 1.57 V
Fault Clamp Resistance RFLT(CLAMP) 1.6 kW
Auto−recovery Timer tAR 0.8 1 1.2 s
THERMAL SHUTDOWN
Thermal Shutdown TSHDN 150 165 180 °C
Thermal Shutdown Hysteresis TSHDN(hys) 25 °C
NCP12700
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Application Information
The NCP12700 is a fixed frequency, peak current mode,
PWM controller containing all of the features necessary for
implementing single−ended power converter topologies.
The device features an ultra−wide range, high voltage
startup regulator capable of regulating VCC across an input
voltage range of 9 – 120 V (xDNR2G) or 9 – 200 V
(xMTTXG). The controller is designed for high speed
operation including a programmable oscillator capable of
operating from 100 kHz to 1 MHz and total propagation
delays less than 75 ns in the PWM path. The NCP12700
integrates slope compensation to prevent subharmonic
oscillations and an Input Voltage Compensation /
Over−Power Protection (OPP) feature that limits the
converter power delivery capability across input voltage,
easing system thermal design. The controller offers an
adjustable soft−start, input voltage UVLO protection, and a
suite of protection features including cycle−by−cycle
current limit and a FLT pin with a NTC interface for system
thermal protection. The UVLO pin also features a shutdown
comparator which allows for an externally applied
pull−down signal to disable switching and bring the
controller into a low quiescent state.
Ultra−Wide Range HV Startup Regulator
The NCP12700 features a high voltage startup regulator
capable of operating across input voltage ranges of 9−120 V
(xDNR2G) or 9−200 V (xMTTXG). The ultra−wide range
capability of the regulator allows for direct connection of
VIN to the converter input voltage without requiring
external components. The regulator’s input voltage
capabilities support a wide range of industrial, medical,
telecom, and transportation applications.
Figure 4 details the operation of the startup regulator.
When VIN is applied, the regulator will immediately begin
sourcing current to charge VCC. Initially the startup will
supply approximately 10 mA. Once VCC builds up to ~ 3 V,
the control loop for the HV regulator will activate and the
source current will be regulated to 30 mA until VCC reaches
the VCC(REG) level of 8 V. The HV startup is a linear
regulator which can continue to supply and regulate VCC at
8 V. The recommended VCC capacitance to ensure stability
of the regulator is 1 – 10 mF.
While the VCC voltage is below the VCC(ON) threshold the
controller will remain in a low quiescent state to allow for
rapid charging of VCC and fast startup of the application.
Once the VCC voltage reaches the VCC(ON) threshold,
approximately 200 mV below the VCC(REG) level, the
controller will exit the low quiescent state and begin
delivering drive pulses. While the output voltage is building
up, the startup regulator will continue to supply the current
necessary to maintain VCC at the VCC(REG) level. For low
input voltage applications, the startup regulator has been
designed to guarantee a minimum of 15 mA source
capability with 2 V of headroom.
In typical applications an auxiliary winding will be used
to provide bias to VCC once the converter is switching. This
allows for the most efficient operation of the system. Once
the auxiliary winding pulls the VCC voltage above
VCC(REG), the HV regulator will shut off. In normal
operation the VCC voltage can be biased above the voltage
at VIN and can support voltages up to 28 V. A VCC OVP
protection feature will trigger at 28 V, disabling switching of
the converter to prevent the auxiliary winding voltage from
damaging the controller.
NCP12700
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Figure 4. Startup Timing Diagram
Output
Voltage
time
VCC(OFF)
VCC(REG)
VCC
VIN = 12 V
VCC(ON)
VCC = 3 V
IVIN
IVIN = 30 mA
IVIN ~ 10 mA
IVIN = ICC
Once the device has begun delivering drive pulses it will
remain active as long as VCC remains above the VCC(OFF)
threshold of 6.5 V. Either the auxiliary winding or the HV
startup regulator will provide the bias necessary to keep VCC
above this level. If VCC does drop below the VCC(OFF)
threshold the controller will inhibit drive pulses, the device
will reset and once again enter a low quiescent state. This
should only occur if the input voltage to the converter has
been removed but can also be an indication of excessive
external loading on VCC.
Input Voltage UVLO Detection
The NCP12700 features line voltage UVLO detection to
ensure that the converter becomes operational only after
meeting a minimum input voltage threshold thereby
protecting the converter from thermal stress at low input
voltages. A functional block diagram of the UVLO
detection circuitry is shown in Figure 5. The input line
voltage is monitored through a resistor divider network
allowing the user to set the thresholds for when to enable and
disable the converter. Typical pull−down resistors in the
divider network will be in the range of 5 – 20 kW and pull−up
resistors will typically be in the range of 50 – 500 kW.
External capacitive filtering on the order of 10 nF is also
advisable.
When input voltage is initially applied to the converter the
device will be in a shutdown/reset (SHDN) state until the
UVLO voltage crosses the VSTBY(th) threshold of 0.5 V. In
the SHDN state the device consumption will be limited to
the ICC(SHDN) value of 50 mA. When the UVLO voltage goes
above VSTBY(th) the device transitions into standby mode
and the consumption increases to the ICC(STBY) limit of
750 mA maximum. The low current consumption in the
shutdown and standby modes allow VCC to rapidly charge
to the VCC(ON) threshold.
Once VCC has charged to VCC(ON) the device will enable
drive pulses when the UVLO voltage exceeds the VUVLO(th)
of 0.8 V and disables drive pulses when the UVLO voltage
falls below 0.8 V by VUVLO(HYS). Prior to enabling drive
pulses the device also activates a pull−down current source,
IUVLO(HYS), of 5 mA. The current source works in
combination with VUVLO(HYS) to set the input voltage
hysteresis for enabling and disabling switching operation of
the converter. A resistor, RUVLO(HYS), can be used to
provide additional hysteresis between the enable and disable
thresholds. Equation 1 and Equation 2 can be used to
calculate the necessary component values in the resistor
divider network.
NCP12700
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Figure 5. UVLO Block Diagram
VUVLO(th)
UVLO
ENABLE
VSTBY(th) STBY
SHDN
IUVLO(HYS)
RUVLO1
RUVLO2
VIN
5 ms
VRST(th)
S
R
Q
Q
RUVLO(HYS)
VIN,START +ǒVUVLO(th) )ǒRUVLO1RUVLO2
RUVLO1 )RUVLO2 )RUVLO(HYS)Ǔ IUVLO(HYS)ǓǒRUVLO1 )RUVLO2
RUVLO2 Ǔ(eq. 1)
VIN,STOP +ǒVUVLO(th) *VUVLO(HYS)Ǔ ǒRUVLO1 )RUVLO2
RUVLO2 Ǔ(eq. 2)
Input Voltage Compensation / Over−Power Protection
P+0.5 L ǒI2P*I2VǓ fSW (eq. 3)
In a CCM flyback converter the output power capability
is defined by Equation 3 where IP is the peak transformer
current, IV is the valley or minimum transformer current, L
is the primary inductance, and fSW is switching frequency.
In a DCM flyback converter the valley current becomes 0
and Equation 3 still applies. The peak current capability of
the converter can be impacted by several variables including
input voltage and the operating duty cycle due to the internal
slope compensation in the NCP12700. Managing the peak
current limit over the operating input voltage range will limit
the total power capability and ease system thermal design.
The NCP12700 features the Input Voltage Compensation
/ Over−Power Protection (OPP) circuitry shown in Figure 6.
The Over−Power Protection circuit functions as a
transconductance amplifier which senses an image of the
input line voltage through the UVLO pin. When the UVLO
voltage crosses the VOPP(START) threshold, typically 1 V, the
OTA begins sourcing a current out of the CS pin. The current
injected out of the CS pin will be according to Equation 4
where the typical transconductance, Gm(OPP), is 150 mA/V
and the maximum current is limited to the ICS(OPP_MAX)
value of 200 mA.
ICS(OPP) +Gm(OPP) @ǒVUVLO *VOPP(START)Ǔ(eq. 4)
Good SMPS design practice for current mode control
includes a small RC filter in series between the current sense
resistor and the CS pin of the controller. Typical values for
the resistor in the RC filter are 500 – 1 kW. The user can then
limit the peak current capability of the converter by setting
the RCS resistor value and can reduce the peak current
capability of the converter by 20 – 40% with these values.
Figure 6. Over−Power Protection Diagram
UVLO
VIN
CS
DRV
ICS(OPP)
COMP
RUVLO1
RUVLO2
RSNS
RCS
VOPP(START)
VDD
CCS
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Another aspect of the Over−Power Protection feature is
that the current sourced out of the CS pin is modulated as a
function of the COMP voltage to ensure that the current is
only available when necessary. This is detailed in Figure 7
below with typical values for VOPP(0%) = 0.8 V and
VOPP(100%) = 2 V. The typical values of 0.8 V and 2 V equate
to ~ 27% and 67% of the full load capability of the device,
hence the OPP current should begin being applied at 27%
load and should ramp up to 100% OPP current at 67% load.
Figure 7. OPP Current Profile vs. COMP Voltage
time
0.8 V
VCOMP
100%
2 V
0
ICS(OPP)
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PWM Operation
RT Pin & Oscillator
The oscillator in the NCP12700 uses an external resistor
from the RT pin to ground to set the switching frequency of
the converter. The frequency set by the RT resistor follows
FOSC +1
RT 100 10−12 (eq. 5)
where FOSC is the switching frequency. The curve in
Figure 8 below shows the Oscillator frequency vs. RT
resistor for values between ~10 kW to 100 kW. The
NCP12700 is designed to operate between 100 kHz and
1 MHz but will have tighter tolerance at lower switching
frequencies.
Figure 8. Oscillator Frequency vs. RT Resistor Value
0
100
200
300
400
500
600
700
800
900
1,000
0 102030405060708090
Oscillator Frequency (kHz)
100
RT Resistor Value (kΩ)
Gate Driver (DRV)
The NCP12700 is equipped with a gate driver for driving
the primary side MOSFET. The driver applies VCC up to the
clamped voltage, VDRV(clamp), of 12 V as a high signal and
0 V to the gate of the power MOSFET as a low signal. The
rate of charging and discharging of the gate of the MOSFET
is dependent upon the input capacitance of the MOSFET and
the impedance of the driver. The NCP12700 is equipped
with an IDRV(SRC) pull−up current, typically 1 A, and a pull
down current of IDRV(SNK), typically 2.8 A ensuring fast
turn on/off transitions of the power MOSFET and
minimizing the switching losses.
PWM Reset Path
The NCP12700 is intended for isolated DC−DC
converters where the control loop compensation circuitry is
located on the secondary side of the power converter. The
converter output voltage is compared against a reference
voltage and an error amplifier produces a compensated error
signal which is communicated to the NCP12700 through an
optocoupler. The compensated error signal interfaces with
the COMP pin where it is divided down by a 5R/R voltage
divider and sent to the PWM S/R to modulate the switching
duty cycle. A detailed functional diagram of the PWM path
is shown in Figure 9. The PWM comparator compares the
attenuated error signal from the COMP pin to the current
ramp signal sensed at the CS pin to determine when the drive
pulse should be terminated. This comparator serves as the
primary modulation path for the converter duty cycle.
NCP12700
www.onsemi.com
14
Figure 9. NCP12700 PWM Path
PWM
LOGIC
S
Q
R
VDD
COMP
PWM
COMPARATOR
CS
CURRENT LIMIT
COMPARATOR
SKIP
COMPARATOR
VCS(LIM)
LEB
VCOMP(skip)
VDD
DRV
CLK
tCS(OVLD) OVLD
5R
R
5k
VCOMP(skip_hys)
ICS(OPP)
SLOPE
COMPENSATION
SLOPE
COMPENSATION
DRV
SCP
COMPARATOR
tLEB(CS)
tLEB(SCP)
VSCP(LIM) Counter NSCP
SCP
SCP
Soft−Start
COMPARATOR
1/6
SS
Switching Disabled
VDD
ISS DMAX
Figure 10. Slope Compensation Timing Diagram
DRV
VSLP
VPWM
0
D80%
D40%
Slope Compensation
In fixed frequency peak current mode control, converters
operating at duty cycles greater than 50% of the switching
period are susceptible to sub−harmonic oscillation,
characterized by successive switching cycles with
alternating wide and narrow pulse−widths. To avoid
sub−harmonic oscillation the NCP12700 implements an
internal slope compensation circuit which is applied to the
attenuated COMP signal at the input of the PWM
comparator.
The slope compensation timing diagram is shown in
Figure 10. The compensating ramp begins reducing the
NCP12700
www.onsemi.com
15
attenuated COMP voltage when the switching duty cycle is
nominally 40% and reduces the voltage by a peak, VSLP(PK),
of 98 mV at the 80% duty cycle limit. The slope
compensating ramp is synchronized to the duty cycle of the
oscillator, effectively adjusting itself based on the switching
frequency, providing the converter with a compensating
dv/dt ramp appropriate for the particular switching
frequency. An image of the slope compensating ramp is also
applied at the input of the Current Limit comparator to
prevent sub−harmonic oscillations from occurring during
overload conditions. The chart below summarizes the dv/dt
of the compensating ramp at some common operating
frequencies.
FSW (kHz) TSW (ms) D = 40% (ms) D = 80% (ms) VSLP (mV) Ramp (mV/ms)
100 10.00 4.00 8.00 98 25
200 5.00 2.00 4.00 98 49
250 4.00 1.60 3.20 98 61
330 3.03 1.21 2.42 98 81
400 2.50 1.00 2.00 98 98
500 2.00 0.80 1.60 98 123
Cycle−by−Cycle Current Limit and Overload Protection
The NCP12700 implements cycle−by−cycle current
limiting with a dedicated Current Limit Comparator. The
input to the comparator is the primary FET current ramp
sensed at the CS pin. If the sensed voltage exceeds the
current limit threshold, VCS(LIM), of 495 mV then the drive
pulse is terminated. The Current Limit Comparator is very
fast with a total propagation delay, tCS(DLY), of 75 ns
maximum ensuring that drive pulses are quickly terminated
minimizing current overshoot in the converter.
The Current Limit comparator also triggers an overload
timer, tCS(OVLD), nominally 30 ms, and will disable drive
pulses and take the device into a Fault mode when the timer
has expired. The 30 ms timer allows the converter to sustain
a short term overload but still protects the converter from
thermal overstress in the event of a continuously applied
overload condition. The overload timer is also an integrating
timer, it will continue ramping up while the Current Limit
Comparator is terminating drive pulses but will begin
ramping down, not reset completely, if the drive pulse is
terminated by another signal such as the PWM comparator.
This operation is depicted in Figure 11.
Figure 11. Integrating Overload Timer
VCOMP
VDRV
Overload
Timer
time
t1t2t3t4t5t6
Short Circuit (SCP) Comparator
The NCP12700 also includes a fast Short Circuit
Comparator with a threshold, VSCP(LIM), of 625 mV. In
certain extreme fault conditions such as a shorted secondary
side rectifier or a shorted winding in the transformer it may
be possible to sense an abnormally high current pulse at the
CS pin and disable drive pulses to prevent the converter from
NCP12700
www.onsemi.com
16
further damage. If the voltage at the CS pin rapidly exceeds
625 mV and the SCP comparator trips, then the drive pulse
will be terminated and a counter will be incremented. If the
SCP comparator trips on 4 consecutive drive pulses then
drive pulses will be disabled and the controller is put into the
Fault mode.
Leading Edge Blanking (LEB)
Converters operating in peak current mode control require
a high quality current ramp signal to ensure stable and clean
PWM operation. In the NCP12700 the current ramp signal
is sensed at the CS pin and is routed through a LEB circuit
which blanks the current sense information for a brief period
after the DRV voltage is delivered to the primary MOSFET.
The LEB prevents noise generated during the switching
transition from terminating drive pulses prematurely. The
blanking is performed by an internal pulldown switch and
series disconnect switch. The internal pulldown switch has
an on resistance, RPD(LEB), specified as 55 ohms maximum.
The pulldown switch is turned on whenever the DRV is low
and remains on for a period of time equal to tLEB(SCP), 60 ns
typical, after the DRV is set high.
After tLEB(SCP) has expired the current ramp signal is
delivered to the SCP comparator allowing it to sense an
abnormal overcurrent situation. A longer series LEB,
tLEB(CS), of 100 ns continues to hold open the signal path to
the CS and PWM comparators. This switch closes when
tLEB(CS) has expired, allowing the CS information to be
delivered to the other two comparators. In addition to the
LEB network, the user of the controller will usually place a
small RC filter in between the current sense components and
the CS pin to provide noise suppression. The resistor value
in the RC filter is typically in the range of 500 – 1 kW, sized
appropriately for the Over−Power protection feature, and
the capacitor value is typically chosen to provide a time
constant for the RC filter of about 50 – 100 ns.
Skip Comparator
For a power converter operating at light loads it is
sometimes desired to skip drive pulses in order to maintain
output voltage regulation or improve the light load
efficiency of the system. The NCP12700 features a
dedicated Skip Comparator which monitors the voltage at
the COMP pin and blanks drive pulses if the COMP voltage
falls below the VCOMP(skip) threshold of 300 mV. To
re−enable new drive pulses, the COMP voltage must exceed
a skip hysteresis, VCOMP(skip_hys) of 25 mV above the
300 mV threshold. The skip hysteresis is designed to
prevent the converter from oscillating in and out of skip
mode due to noise on the COMP pin.
Maximum Duty Cycle
The NCP12700 also includes a maximum duty cycle
clamp which terminates a drive pulse which has been high
for DMAX of the switching period. The default value of
DMAX will be 80%.
Soft Start
The soft start feature in the NCP12700 is implemented
with a dedicated comparator that compares the current ramp
signal from the CS pin against an attenuated soft start ramp
generated at the SS pin. Prior to enabling switching, an
internal pull−down transistor with an on resistance,
RSS(DIS), of 100 W is activated to discharge the external soft
start capacitor and hold the SS pin to GND. Once switching
is enabled the pull−down transistor is released and a current
source, ISS, of 15 mA charges the soft start capacitor forming
the soft start ramp voltage. The soft start ramp voltage is then
divided down by a factor of 6 and fed into the soft start
comparator which resets drive pulses when the CS voltage
exceeds the soft start voltage. The soft start comparator will
continue to reset drive pulses until another comparator
enters the reset path which typically occurs when the
secondary side control loop responds allowing the PWM
comparator to take control.
The NCP12700 monitors the external soft start voltage
and sets a flag when the voltage exceeds 3 V, declaring that
the soft start period has ended. At 3 V, the drive pulse reset
control will have been handed off to either the PWM
comparator or the Current limit comparator. The SS_END
flag is used internally by the controller for fault
management, gating detection of certain faults that may be
erroneously triggered during power up of the converter. This
is shown in the FLT pin block diagram of Figure 12.
Figure 12. FLT Pin Block Diagram
VDD
VFLT(OTP)
SS_END
IFLT
To Fault Logic
VFLT(OVP)
VFLT(OTP_HYS)
tOTP(DLY)
tOVP(DLY)
To V CC
NCP12700
www.onsemi.com
17
Fault (FLT) Pin
The FLT pin is intended to provide the system with a NTC
interface for thermal protection and a pull−up fault which
can be coupled to the auxiliary winding to provide output
over−voltage protection. The FLT pin can also be used as a
general purpose fault where it interfaces with a simple
pull−down BJT, open collector comparator, or optocoupler
for monitoring of secondary side faults. The internal
circuitry includes a precision pull−up current source, IFLT, of
85 mA and a window comparator to signal a fault whenever
the pin voltage goes below the OTP fault threshold,
VFLT(OTP), of 0.5 V or above the OVP fault threshold,
VFLT(OVP), of 3 V. Both of the fault comparators also include
a delay filter to prevent noise or glitches from setting the
fault. The over−temperature fault filter, tOTP(DLY), is
nominally 20 ms and the over−voltage fault filter, tOVP(DLY),
is typically 5 ms. An external filter capacitor is also
advisable.
Both faults have an option to permanently latch off the
controller or restart after a 1 s auto−recovery period. The
OVP fault is intended to monitor an auxiliary winding and
when triggered, the controller will disable switching which
will inhibit the aux winding from generating voltage and
allow the controller to restart after the auto−recovery timer
has expired. If the OVP fault comparator is continuously
held above 3 V, the NCP12700 will remain in the fault mode
and not restart.
The OTP fault detection is gated by the SS_END flag to
prevent the comparator from triggering while the external
filter capacitor charges up. Once the SS_END flag is set the
OTP fault can be acknowledged so there is a practical limit
on the size of the filter capacitor. Equation 6 and Equation 7
should assist the user with properly setting the external
capacitance of the fault pin.
tSS_END +
CSS VSS_END
ISS
(eq. 6)
CFLT t
IFLT tSS_END
VFLT(OTP)
(eq. 7)
When the OTP fault is triggered the NCP12700 will again
disable drive pulses and transition into a fault mode. The
OTP fault is auto−recoverable based on the auto−recovery
timer and a hysteresis set by the VFLT(REC) threshold of
0.9 V. The auto−recovery timer must expire and the voltage
at the fault pin must exceed 0.9 V. This methodology
guarantees a minimum amount of time for the system to
recover from thermal overstress but will not allow the
converter to restart unless the hysteresis is met. Given the
IFLT and VFLT(OTP) specifications the critical NTC
resistance for declaring a fault is ~ 5.9 kW. The critical
resistance for recovering from the OTP fault becomes ~
10.6 kW. This fault recovery threshold provides for about
~20°C of hysteresis for many NTC resistors.
Summary of Fault Handling
The NCP12700 has 6 fault detectors which will place the
device into the fault mode. In the fault mode switching is
inhibited and the controller bias is maintained by the HV
startup regulator. The controller also reduces current
consumption to ICC(FLT), 500 mA maximum, so that the
regulator is not thermally overstressed. The NCP12700
remains in the fault mode until the fault signal has been
cleared and/or the auto−recovery timer has expired. The
fault signal can be cleared when the fault detector senses that
the fault has been removed or by a controller reset which
occurs if VCC drops below VCC(OFF) or the UVLO pin is
pulled below the VRST(th) level. Below is a brief summary
of the different fault detectors and their basic operation.
•Thermal Shutdown (TSD): Thermal shutdown is
declared when the internal junction temperature of the
device exceeds the TSHDN temperature of 165°C. The
thermal shutdown fault is auto−recoverable when the
device junction temperature reduces to TSHDN –
TSHDN(hys) where TSHDN(hys) is typically 25°C.
•Fault OTP: An OTP fault is declared when fault pin
voltage decreases below the VFLT(OTP) threshold of
0.5 V and the OTP filter, tOTP(DLY), expires. The OTP
filter delay is typically 20 ms. The OTP fault is blanked
at startup until the SS_END flag has been set to allow
the external capacitance of the pin to charge up. For the
device to recover from the Fault OTP, the
auto−recovery timer must expire and the voltage at the
fault pin must recover to VFLT(REC) value of 0.9 V.
•Fault OVP: The OVP fault is declared when fault pin
the voltage exceeds the VFLT(OVP) threshold of 3 V and
the OVP filter, tOVP(DLY), expiring. The OVP filter
delay is typically 5 ms. The OVP fault is cleared when
the auto−recovery timer expires. There is no hysteresis
on the OVP fault but if the pin voltage is permanently
held above 3 V, DRV will pulses will be permanently
inhibited.
•Overload (OVLD): The OVLD fault is set when the
overload timer, tOVLD, expires. The overload timer is
an integrating timer which counts up as long as the
Current Limit comparator is terminating DRV pulses.
The typical value for tOVLD is 30 ms. The controller
will recover from the OVLD fault when the
auto−recovery timer expires.
•SCP Fault: The SCP fault occurs when the NSCP
counter has reaches 4 consecutive DRV pulses
terminated by the SCP comparator. The controller will
recover from the SCP fault when the auto−recovery
timer expires.
•VCC OVP: The VCC OVP is set when VCC voltage
exceeds the VCC(OVP) threshold of 28 V and the VCC
OVP filter, tVCC_OVP(DLY), expires. The VCC OVP
filter is typically 3 ms. VCC OVP will permanently latch
the device off so that it remains in the Fault mode
indefinitely until the controller is reset.
NCP12700
www.onsemi.com
18
Evaluation Board Designs
Two evaluation boards have been developed to highlight
the features of the NCP12700. Detailed schematics,
operating waveforms, and bill of materials are available in
the design notes, DN05108 and DN05109. DN05108
describes the operation of a 9 – 36 V input flyback converter
delivering 12 V out at 15 W. This evaluation board switches
at 200 kHz and operates in both continuous and
discontinuous conduction modes. The key performance
specifications are shown in Table 5 below.
Table 5. LOW VOLTAGE FLYBACK EVALUATION
BOARD SPECIFICATIONS
Evaluation Board # 1
Vin 9 − 36 V Operating
Vo 12 V − 1.25 A
Po 15 W
Specifications
Startup time < 30 ms
Full Load Efficiency > 87 %
Transient Response < 250 ms
Over Power Protection 120% − 150%
Over Voltage Protection 16 VDC Max
No Load Output Ripple 200 mVpp Max
No Load Power Dissipation 120 mW Max
Input Current in SHDN < 1 mA
DN05109 describes the operation of a 18 – 160 V input
flyback converter delivering 12 V out at 15 W. This
demonstration board switches at 100 kHz and operates in
discontinuous conduction mode across the entire input
voltage range. The key performance specifications are
shown in Table 6.
Table 6. WIDE RANGE FLYBACK EVALUATION
BOARD SPECIFICATIONS
Evaluation Board # 2
Vin 18 − 160 V Operating
Vo 12 V − 1.25 A
Po 15 W
Specifications
Startup time < 20 ms
Full Load Efficiency > 85 %
Transient Response < 250 ms
Over Power Protection 115% − 155%
Over Voltage Protection 16 VDC Max
No Load Output Ripple 150 mVpp Max
No Load Power Dissipation 500 mW Max
Input Current in SHDN < 1 mA
WQFN10 4x3, 0.8P
CASE 511DV
ISSUE C
DATE 15 JUL 2019
1
SCALE 2:1
XXXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
GENERIC
MARKING DIAGRAM*
XXXXXX
XXXXXX
ALYWG
G
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
(Note: Microdot may be in either location)
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
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98AON30094G
DOCUMENT NUMBER:
DESCRIPTION:
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PAGE 1 OF 1
WQFN10 4x3, 0.8P
© Semiconductor Components Industries, LLC, 2018 www.onsemi.com
MSOP10, 3x3
CASE 846AE
ISSUE A
DATE 20 JUN 2017
GENERIC
MARKING DIAGRAM*
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 MM IN
EXCESS OF MAXIMUM MATERIAL CONDITION.
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH,
PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15
MM PER SIDE. DIMENSION E DOES NOT INCLUDE INTER-
LEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 MM PER SIDE.
DIMENSIONS D AND E ARE DETERMINED AT DATUM F.
5. DATUMS A AND B TO BE DETERMINED AT DATUM F.
6. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE
SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE
BODY.
DIM MIN NOM
MILLIMETERS
A−−− −−−
A1 0.00 0.05
b0.17 −−−
c0.13 −−−
D2.90 3.00
L2 0.25 BSC
e0.50 BSC
L0.40 0.70
L1 0.95 REF
E4.75 4.90
E1 2.90 3.00
XXXX = Specific Device Code
A = Assembly Location
Y = Year
W = Work Week
G= Pb−Free Package
1
10
SCALE 1:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present and may be in
either location. Some products may not
follow the Generic Marking.
XXXX
AYWG
G
(Note: Microdot may be in either location)
RECOMMENDED
ÉÉ
ÉÉ
D
E1
A
PIN ONE
SEATING
PLANE
15
610
E
B
e
TOP VIEW
SIDE VIEW
DETAIL A
END VIEW
10X b
C
A
c
L
L2
A1
INDICATOR
A
M
0.08 BC S S
F
C0.10
C
DETAIL A
10X
0.85
5.35
0.50
PITCH
10X 0.29
DIMENSIONS: MILLIMETERS
MAX
1.10
0.15
0.27
0.23
3.10
0.80
5.05
3.10
A2 0.75 0.85 0.95
q0−−− 8°°
q
L1
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON34098E
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
MSOP10, 3X3
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
www.onsemi.com
1
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