188
TM
March 1997
HM-65162/883
2kx8 Asynchronous
CMOS Static RAM
Features
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Fast Access Time . . . . . . . . . . . . . . . . . . . 70/90ns Max
• Low Standby Current. . . . . . . . . . . . . . . . . . . .50μA Max
• Low Operating Current . . . . . . . . . . . . . . . . . 70mA Max
• Data Retention at 2.0V. . . . . . . . . . . . . . . . . . .20μA Max
• TTL Compatible Inputs and Outputs
• JEDEC Approved Pinout (2716, 6116 Type)
• No Clocks or Strobes Required
• Wide Temperature Range . . . . . . . . . . -55oC to +125oC
• Equal Cycle and Access Time
• Single 5V Supply
• Gated Inputs
- No Pull-Up or Pull-Down Resistors Required
Description
The HM-65162/883 is a CMOS 2048 x 8 Static Random
Access Memory manufactured using the Intersil Advanced
SAJI V process. The device utilizes asynchronous circuit
design for fast cycle time and ease of use. The pinout is the
JEDEC 24 pin DIP, and 32 pad 8-bit wide standard which
allows easy memory board layouts flexible to accommodate
a variety of industry standard PROMs, RAMs, ROMs and
EPROMs. The HM-65162/883 is ideally suited for use in
microprocessor based systems with its 8-bit word length
organization. The convenient output enable also simplifies
the bus interface by allowing the data outputs to be con-
trolled independent of the chip enable. Gated inputs lower
operating current and also eliminate the need for pull-up or
pull-down resistors.
Pinouts
Ordering Information
70ns/20μA 90ns/40μA 90ns/300μA TEMP. RANGE PACKAGE PKG. NO.
HM1-65162B/883 HM1-65162/883 HM1-65162C/883 -55oC to 125oCCERDIP F24.6
HM4-65162B/883 HM4-65162/883 - -55oC to 125oC CLCC J32.A
HM-65162/883 (CERDIP)
TOP VIEW
HM-65162/883 (CLCC)
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
21
22
23
24
15
14
13
VCC
A9
W
G
A10
DQ7
DQ5
DQ4
DQ3
A8
E
DQ6
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
5
6
7
8
11
10
9
13
12
27
28
29
26
25
24
23
22
21
3 2 1
432 31 30
16 17 18 19 20
14 15
A6
A5
A4
A3
A2
A1
A0
NC
DQ0
DQ1
DQ2
GND
NC
DQ3
DQ4
DQ5
VCC
NC
NC
A7
NC
NC
NC
A8
A9
NC
G
A10
E
DQ7
DQ6
W
PIN DESCRIPTION
NC No Connect
A0 - A10 Address Input
EChip Enable/Power Down
VSS/GND Ground
DQ0 - DQ7 Data In/Data Out
VCC Power (+5V)
WWrite Enable
GOutput Enable
FN3001.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 |Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
189
Functional Diagram
ROW
DECODER
ROW
ADDRESS
BUFFER 128
7
7
A1
A2
A3
A4
A5
A6
A7 1 OF 8
8
DQ0
THRU
DQ7
128
E
W
128 X 128
MEMORY ARRAY
A
4
A
4
A0 A8 A9 A10
G
A
A
COLUMN DECODER
AND DATA
INPUT / OUTPUT (X8)
COLUMN
ADDRESS BUFFER
HM-65162/883
190
Absolute Maximum Ratings Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
Typical Derating Factor . . . . . . . . . .1.5mA/MHz Increase in ICCOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance θJA θJC
CERDIP Package . . . . . . . . . . . . . . . . 48oC/W 8oC/W
CLCC Package . . . . . . . . . . . . . . . . . . 66oC/W 12oC/W
Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26000 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating
and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC
Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V
Chip Enable High/Low Time. . . . . . . . . . . . . . . . . . . . . . . 40ns (Min)
Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.2V to VCC
Data Retention Supply Voltage. . . . . . . . . . . . . . . . . . . 2.0V to 4.5V
Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max
TABLE 1. 65162/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER SYMBOL
(NOTE 1)
CONDITIONS
GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITSMIN MAX
High Level Out-
put Voltage
VOH1 VCC = 4.5V, IO = -1.0mA 1, 2, 3 -55oC ≤ TA ≤ +125oC2.4 - V
Low Level Output
Voltage
VOL VCC = 4.5V, IO = 4.0mA 1, 2, 3 -55oC ≤ TA ≤ +125oC- 0.4 V
High Impedance
Output Leakage
Current
IIOZ VCC = 5.5V, G = 2.2V, or
E = 2.2V, VI/O = GND or VCC
1, 2, 3 -55oC ≤ TA ≤ +125oC-1.0 1.0 μA
Input Leakage
Current
II VCC = 5.5V,
VI = GND or VCC
1, 2, 3 -55oC ≤ TA ≤ +125oC-1.0 1.0 μA
Standby Supply
Current
ICCSB1 HM-65162B/883, IO = 0mA,
VCC = 5.5V, E = VCC -0.3V
1, 2, 3 -55oC ≤ TA ≤ +125oC - 50 μA
HM-65162/883, IO = 0mA,
VCC = 5.5V, E = VCC - 0.3V
1, 2, 3 -55oC ≤ TA ≤ +125oC - 100 μA
HM-65162C/883, IO = 0mA,
VCC = 5.5V, E = VCC - 0.3V
1, 2, 3 -55oC ≤ TA ≤ +125oC - 900 μA
Standby Supply
Current
ICCSB VCC = 5.5V, IO = 0mA,
E = 2.2V
1, 2, 3 -55oC ≤ TA ≤ +125oC- 8 mA
Operating Supply
Current
ICCOP VCC = 5.5V, G = 5.5V,
(Note 2), f = 1MHz, E = 0.8V
1, 2, 3 -55oC ≤ TA ≤ +125oC - 70 mA
Enable Supply
Current
ICCEN VCC = 5.5V, IO = 0mA,
E = 0.8V
1, 2, 3 -55oC ≤ TA ≤ +125oC- 70mA
Data Retention
Supply Current
ICCDR HM-65162B/883, IO = 0mA,
VCC = 2.0V, E = VCC - 0.3V
1, 2, 3 -55oC ≤ TA ≤ +125oC- 20 μA
HM-65162/883, IO = 0mA,
VCC = 2.0V, E = VCC - 0.3V
1, 2, 3 -55oC ≤ TA ≤ +125oC- 40 μA
HM-65162C/883, IO = 0mA,
VCC = 2.0V, E = VCC - 0.3V
1, 2, 3 -55oC ≤ TA ≤ +125oC - 300 μA
Functional Test FT VCC = 4.5V (Note 3) 7, 8A, 8B -55oC ≤ TA ≤ +125oC- - -
NOTES:
1. All voltages referenced to device GND.
2. Input pulse levels: 0.8V to VCC - 2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1
TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time by 0.15ns per pF.
3. TAVQV = TELQV + TAVEL.
HM-65162/883
191
TABLE 2. HM-65162/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested.
PARAMETER SYMBOL
(NOTES 1, 2)
CONDITIONS
GROUP
A SUB-
GROUPS
TEMPERA-
TURE
LIMITS
UNITS
HM-65162B
/883
HM-65162
/883
HM-65162C
/883
MIN MAX MIN MAX MIN MAX
Read/Write/
Cycle Time
(1) TAVAX VCC = 4.5V
and 5.5V
9, 10, 11 -55oC ≤ TA ≤ +125oC70 - 90 - 90 - ns
Address
Access Time
(2) TAVQV VCC = 4.5V
and 5.5V
9, 10, 11 -55oC ≤ TA ≤ +125oC-70-90-90 ns
Chip Enable
Access Time
(3) TELQV VCC = 4.5V
and 5.5V
9, 10, 11 -55oC ≤ TA ≤ +125oC-70-90-90 ns
Output Enable
Access Time
(5) TGLQV VCC = 4.5V
and 5.5V
9, 10, 11 -55oC ≤ TA ≤ +125oC-50-65-65 ns
Chip Selection
to End of Write
(11) TELWH VCC = 4.5V
and 5.5V
9, 10, 11 -55oC ≤ TA ≤ +125oC45 - 55 - 55 - ns
Address Setup
Time
(12) TAVWL VCC = 4.5V
and 5.5V
9, 10, 11 -55oC ≤ TA ≤ +125oC10 - 10 - 10 - ns
Write Enable
Pulse Write
(13) TWLWH VCC = 4.5V
and 5.5V
9, 10, 11 -55oC ≤ TA ≤ +125oC40 - 55 - 55 - ns
Write Enable
Read Setup
Time
(14) TWHAX VCC = 4.5V
and 5.5V
9, 10, 11 -55oC ≤ TA ≤ +125oC10 - 10 - 10 - ns
Data Setup
Time
(17) TDVWH VCC = 4.5V
and 5.5V
9, 10, 11 -55oC ≤ TA ≤ +125oC30 - 30 - 30 - ns
Data Hold Time (18) TWHDX VCC = 4.5V
and 5.5V
9, 10, 11 -55oC ≤ TA ≤ +125oC10 - 15 - 15 - ns
Write Enable
Pulse Setup
Time
(20) TWLEH VCC = 4.5V
and 5.5V
9, 10, 11 -55oC ≤ TA ≤ +125oC40 - 55 - 55 - ns
Chip Enable
Data Setup
Time
(21) TDVEH VCC = 4.5V
and 5.5V
9, 10, 11 -55oC ≤ TA ≤ +125oC30 - 30 - 30 - ns
Address Valid
to End of Write
(22) TAVWH VCC = 4.5V
and 5.5V
9, 10, 11 -55oC ≤ TA ≤ +125oC50 - 65 - 65 - ns
NOTES:
1. All voltages referenced to device GND.
2. Input pulse levels: 0.8V to VCC -2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL
gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
3. TAVQV = TELQV + TAVEL.
HM-65162/883
192
TABLE 3. HM-65162/883 ELECTRICAL PERFORMANCE SPECIFICATIONS, AC AND DC
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITS
HM-
65162B/883
HM-
65162/883
HM-
65162C/883
MIN MAX MIN MAX MIN MAX
Input
Capacitance
CIN VCC = Open,
F = 1MHz, All
Measurements
Referenced To
Device Ground
1, 2 +25oC - 10 - 10 - 10 pF
1, 3 +25oC -8-8-8pF
I/O
Capacitance
CI/O VCC = Open,
F = 1MHz, All
Measurements
Referenced To
Device Ground
1, 2 +25oC - 12 - 12 - 12 pF
1, 3 +25oC - 10 - 10 - 10 pF
Chip Enable to
Output ON
(4) TELQX VCC = 4.5V and
5.5V
1-55
oC ≤ TA ≤
+125oC
5-0-5-ns
Output Enable
to Output ON
(6) TGLQX VCC = 4.5V and
5.5V
1-55
oC ≤ TA ≤
+125oC
5-5-5-ns
Chip Enable
High to Output
In High Z
(7) TEHQZ VCC = 4.5V and
5.5V
1-55
oC ≤ TA ≤
+125oC
-35-50-50ns
Output Disable
to Output in
High Z
(8) TGHQZ VCC = 4.5V and
5.5V
1-55
oC ≤ TA ≤
+125oC
-35-40-40ns
Output Hold
from Address
Change
(9) TAVQX VCC = 4.5V and
5.5V
1-55
oC ≤ TA ≤
+125oC
5-5-5-ns
Write Enable to
Output in High Z
(16) TWLQZ VCC = 4.5V and
5.5V
1-55
oC ≤ TA ≤
+125oC
-40-50-50ns
Write Enable
High to Output
ON
(19) TWHQX VCC = 4.5V and
5.5V
1-55
oC ≤ TA ≤
+125oC
0-0-0-ns
Output High
Voltage
VOH2 VCC = 4.5V,
IO = -100μA
1-55
oC ≤ TA ≤
+125oC
VCC
-
0.4V
-VCC
-
0.4V
-VCC
-
0.4V
-V
NOTES:
1. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are
characterized upon initial design release and upon design changes which would affect these characteristics.
2. Applies to DIP device types only.
3. Applies to LCC device types only.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS METHOD SUBGROUPS
Initial Test 100%/5004 -
Interim Test 100%/5004 1, 7, 9
PDA 100%/5004 1
Final Test 100%/5004 2, 3, 7, 8A, 8B, 10, 11
Group A Samples/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Groups C & D Samples/5005 1, 7, 9
HM-65162/883
193
Timing Waveforms
Addresses must remain stable for the duration of the read
cycle. To read, G and E must be ≤ VIL and W ≥ VIH. The
output buffers can be controlled independently by G while E
is low. To execute consecutive read cycles, E may be tied
low continuously until all desired locations are accessed.
When E is low, addresses must be driven by stable logic
levels and must not be in the high impedance state.
To write, addresses must be stable, E low and W falling low
for a period no shorter than TWLWH. Data in is referenced
with the rising edge of W, (TDVWH and TWHDX). While
addresses are changing, W must be high. When W falls low,
the I/O pins are still in the output state for a period of TWLQZ
and input data of the opposite phase to the outputs must not
be applied, (Bus contention). If E transitions low
simultaneously with the W line transitioning low or after the
W transition, the output will remain in a high impedance
state. G is held continuously low.
(9) TAVQX
(6) TGLQX
(5) TGLQV
ADDRESS
G
E
Q
(1) TAVAX
(2) TAVQV
(8) TGHQZ
(7) TEHQZ
(3) TELQV
(4) TELQX
FIGURE 1. READ CYCLE
NOTE:
1. W is High for a Read Cycle.
(14) TWHAX
(16) TWLQZ
(21)
(17) TDVWH (18) TWHDX
ADDRESS
E
W
Q
D
(10) TAVAX
(11) TELWH
(12) TAVWL (13) TWLWH
(20) TWLEH
TDVEH
(22) TAVWH
FIGURE 2. WRITE CYCLE I
(19) TWHQX
NOTE:
1. G is Low throughout Write Cycle.
HM-65162/883
194
Timing Waveforms (Continued)
In this write cycle G has control of the output after a period,
TGHQZ. G switching the output to a high impedance state
allows data in to be applied without bus contention after
TGHQZ. When W transitions high, the data in can change
after TWHDX to complete the write cycle.
Low Voltage Data Retention
Intersil CMOS RAMs are designed with battery backup in
mind. Data retention voltage and supply current are guaran
teed over temperature. The following rules ensure data
retention:
1. Chip Enable (E) must be held high during data retention; within
VCC -0.3V to VCC +0.3V.
2. On RAMs which have selects or output enables (e.g., S, G), one
of the selects or output enables should be held in the deselected
state to keep the RAM outputs high impedance, minimizing
power dissipation.
3. Inputs which are to be held high (e.g., E) must be kept between
VCC +0.3V and 70% of VCC during the power up and down tran-
sitions.
4. The RAM can begin operation > 55ns after VCC reaches the min-
imum operating voltage (4.5V).
(17) TDVWH
(21) TDVEH
(18) TWHDX
(15)
TGHQZ
ADDRESS
G
E
W
Q
D
(10) TAVAX
(22) TAVWH
(14)
TWHAX
(11) TELWH
(12) TAVWL
FIGURE 3. WRITE CYCLE II
(13) TWLWH
VCC -0.3V TO VCC +0.3V
VCC ≥ 02.0V
4.5V
VCC
E
4.5V
>55ns
DATA
RETENTION
TIMING
FIGURE 4. DATA RETENTION TIMING
HM-65162/883
195
Test Circuit
NOTE:
1. Test head capacitance includes stray and jig capacitance.
Burn-In Circuits
DUT
1.5V IOLIOH +
-
(NOTE 1) CL
EQUIVALENT CIRCUIT
HM-65162/883
CERDIP
TOP VIEW
NOTES:
All resistors 47kW ±5%.
F0 = 100kHz ±10%.
F1 = F0 ÷ 2, F2 = F1 ÷ 2, F3 = F2 ÷ 2 . . . F13 = F12 ÷ 2.
VCC = 5.5V ±0.5V.
VIH = 4.5V ±10%.
VIL = -0.2V to +0.4V.
C = 0.01μF Min.
HM-65162/883
CLCC
TOP VIEW
NOTES:
All resistors 47kW ±5%.
F0 = 100kHz ±10%.
F1 = F0 ÷ 2, F2 = F1 ÷ 2, F3 = F2 ÷ 2 . . . F13 = F12 ÷ 2.
VCC = 5.5V ±0.5V.
VIH = 4.5V ±10%.
VIL = -0.2V to +0.4V.
C = 0.01μF Min.
C
F10
F9
F8
F7
F6
F5
F4
F3
F2
F2
F2
F1
F11
F12
F13
F0
F0
F2
F2
F2
F2
F2
VCC
A8
A9
W
A10
DQ7
DQ6
DQ5
DQ4
DQ3
A7
A6
A5
A4
A3
A2
A0
DQ0
DQ1
DQ2
A1
GND
VCC
G
E
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
21
22
23
24
15
14
13
DQ1
DQ2
GND
NC
DQ4
DQ5
A6
A5
A4
A3
A2
A1
A0
NC
F2
F2
F2
F2
F2
F2
DQ3
14 15 16 17 18 19 20
F9
F8
F7
F6
F5
F4
F3
DQ0
5
6
7
8
11
9
13
12
10
A8
A9
NC
A10
27
28
29
26
25
24
23
22
21
F11
F12
F0
F13
F0
F2
F2
VCC
NC
NC
A7 F10
3 2 1
432 31 30
C
VCC
F1
NC
NC
NC
E
DQ6
W
G
DQ7
HM-65162/883
196
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
Die Characteristics
DIE DIMENSIONS:
180.3 x 194.9 x 19 ±1mils
METALLIZATION:
Type: Si - Al
Thickness: 11kÅ ±2kÅ
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
1.7 x 105 A/cm2
Metallization Mask Layout
HM-65162/883
A3 A4 A5 A6 A7 VCC A8 A9 W G
A10
A1
A0
DQ0 DQ1 DQ2 GND DQ3 DQ4 DQ5 DQ6
DQ7
E
A2
HM-65162/883
