128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs DDR SDRAM DIMM MT9VDDT1672, MT18VDDT3272D, MT9VDDT3272, MT18VDDT6472D For the latest data sheet, please refer to the Micron Web site: www.micron.com/datasheets FEATURES * * * * * * * * * * * * * * * * * * * * * * 184-Pin DIMM MO-206 184-pin, dual in-line memory modules (DIMM) Fast data transfer rates, PC2100 or PC1600 ECC-optimized pinout Registered inputs with one-clock delay Phase-lock loop (PLL) clock driver to reduce loading Utilizes 200 MT/s and 266 MT/s DDR SDRAM components 128MB (16 Meg x 72), 256MB (32 Meg x 72), and 512MB (64 Meg x 72) VDD= VDDQ= +2.5V 0.2V VDDSPD = +2.2V to +5.5V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; centeraligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture Differential clock inputs (CK0 and CK0#) Four internal device banks for concurrent operation Selectable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes 15.6s (MT9VDDT1672, MT18VDDT3272D); 7.8125s (MT9VDDT3272, MT18VDDT6472D) maximum average periodic refresh interval Serial Presence Detect (SPD) with EEPROM Selectable READ CAS latency OPTIONS STANDARD PCB LOW PROFILE PCB MARKING * Package Dual-Bank Module D 184-pin DIMM (gold) G * Standard or Low Profile PCB Contact Factory * Gold-plated edge contacts * Memory Clock/Data Frequency/CAS Latency* 7.5ns/266 MT/s/CL = 2 -26A 7.5ns/266 MT/s/CL = 2.5 -265 10ns/200 MT/s/CL = 2 -202 * CL = Device CAS (READ) Latency; add one clock cycle for registered DIMMs due to the input register. 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs ADDRESS TABLE MT9VDDT1672 4K 4K (A0-A11) 4 (BA0, BA1) 16 Meg x 8 1K (A0-A9) 1 (S0#) Refresh Count Row Addressing Device Bank Addressing Base Device Configuration Column Addressing Module Bank Addressing MT9VDDT3272 8K 8K (A0-A12) 4 (BA0, BA1) 32 Meg x 8 1K (A0-A9) 1 (S0#) MT18VDDT3272D 4K 4K (A0-A11) 4 (BA0, BA1) 16 Meg x 8 1K (A0-A9) 2 (S0#, S1#) MT18VDDT6472D 8K 8K (A0-A12) 4 (BA0, BA1) 32 Meg x 8 1K (A0-A9) 2 (S0#, S1#) PART NUMBERS AND TIMING PARAMETERS PART NUMBER MT9VDDT1672G-26A__ MT9VDDT1672G-265__ MT9VDDT1672G-202__ MT9VDDT3272G-26A__ MT9VDDT3272G-265__ MT9VDDT3272G-202__ MT18VDDT3272DG-26A__ MT18VDDT3272DG-265__ MT18VDDT3272DG-202__ MT18VDDT6472DG-26A__ MT18VDDT6472DG-265__ MT18VDDT6472DG-202__ PART MARKING -26A -265 -202 -26A -265 -202 -26A -265 -202 -26A -265 -202 MODULE CONFIGURATION DENSITY 128MB 16 Meg x 72 128MB 16 Meg x 72 128MB 16 Meg x 72 256MB 32 Meg x 72 256MB 32 Meg x 72 256MB 32 Meg x 72 256MB 32 Meg x 72 256MB 32 Meg x 72 256MB 32 Meg x 72 512MB 64 Meg x 72 512MB 64 Meg x 72 512MB 64 Meg x 72 TRANSFER RATE 2.1 GB/s 2.1 GB/s 1.6 GB/s 2.1 GB/s 2.1 GB/s 1.6 GB/s 2.1 GB/s 2.1 GB/s 1.6 GB/s 2.1 GB/s 2.1 GB/s 1.6 GB/s MEMORY CLOCK / DATA FREQUENCY 7.5ns/266 MT/s 7.5ns/266 MT/s 10ns/200 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 10ns/200 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 10ns/200 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 10ns/200 MT/s LATENCY (CL - tRCD - tRP)* 2-3-3 2.5-3-3 2-2-2 2-3-3 2.5-3-3 2-2-2 2-3-3 2.5-3-3 2-2-2 2-3-3 2.5-3-3 2-2-2 NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT18VDDT3272DG-265A1 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs PIN ASSIGNMENT (184-Pin DIMM FRONT) PIN SYMBOL PIN SYMBOL 1 VREF 24 DQ17 2 DQ0 25 DQS2 3 VSS 26 VSS 4 DQ1 27 A9 5 DQS0 28 DQ18 6 DQ2 29 A7 7 VDD 30 VDDQ 8 DQ3 31 DQ19 9 NC 32 A5 10 RESET# 33 DQ24 11 VSS 34 VSS 12 DQ8 35 DQ25 13 DQ9 36 DQS3 14 DQS1 37 A4 15 VDDQ 38 VDD 16 DNU 39 DQ26 17 DNU 40 DQ27 18 VSS 41 A2 19 DQ10 42 VSS 20 DQ11 43 A1 21 CKE0 44 CB0 22 VDDQ 45 CB1 23 DQ16 46 VDD PIN 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 SYMBOL DQS8 A0 CB2 VSS CB3 BA1 DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VDDQ WE# DQ41 CAS# VSS DQS5 DQ42 DQ43 PIN 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 PIN ASSIGNMENT (184-Pin DIMM BACK) PIN SYMBOL PIN SYMBOL PIN 93 VSS 116 VSS 139 94 DQ4 117 DQ21 140 95 DQ5 118 A11 141 96 VDDQ 119 DQS11/ DM2 142 97 DQS9/DM0 120 VDD 143 98 DQ6 121 DQ22 144 99 DQ7 122 A8 145 100 VSS 123 DQ23 146 101 NC 124 VSS 147 102 NC 125 A6 148 103 NC 126 DQ28 149 104 VDDQ 127 DQ29 150 105 DQ12 128 VDDQ 151 106 DQ13 129 DQS12/ DM3 152 107 DQS10/ DM1 130 A3 153 108 VDD 131 DQ30 154 109 DQ14 132 VSS 155 110 DQ15 133 DQ31 156 111 NC/CKE1* 134 CB4 157 112 VDDQ 135 CB5 158 113 NC 136 VDDQ 159 114 DQ20 137 CK0 160 115 NC/A12* 138 CK0# 161 SYMBOL VDD NC DQ48 DQ49 VSS DNU DNU VDDQ DQS6 DQ50 DQ51 VSS NC DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL SYMBOL VSS PIN 162 DQS17/DM8 163 A10 164 CB6 165 VDDQ 166 CB7 167 VSS 168 DQ36 169 DQ37 170 VDD 171 DQS13/DM4 172 DQ38 173 DQ39 174 VSS 175 DQ44 176 RAS# 177 DQ45 178 VDDQ 179 S0# 180 NC/S1#* 181 DQS14/DM5 182 VSS 183 DQ46 184 SYMBOL DQ47 NC VDDQ DQ52 DQ53 NC VDD DQS15/DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DQS16/DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD *Pins 111, 115, and 158 are no connect (NC) for MT9VDDT1672 and MT18VDDT3272. For MT9VDDT3272D and MT18VDDT6472D, pin 111 is CKE1, pin 115 is address input A12, and pin 158 is S1#. PIN LOCATIONS (184-Pin DIMM) Standard Single Bank FRONT VIEW Standard Dual Bank FRONT VIEW U10 U10 U3 U1 U5 U11 U7 U3 PIN 52 U4 U11 PIN 92 PIN 53 U5 U6 U7 U8 U9 U13 U12 PIN 52 PIN 1 BACK VIEW PIN 92 PIN 53 BACK VIEW U15 PIN 184 U2 U13 U12 PIN 1 U1 U9 U17 PIN 145 U19 PIN 144 Indicates a VDD or VDDQ pin 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 U21 U14 PIN 184 PIN 93 U15 U16 U17 PIN 145 Indicates a VDD or VDDQ pin Indicates a VSS pin 3 U19 U18 U20 PIN 144 U21 U22 PIN 93 Indicates a VSS pin Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs PIN ASSIGNMENT (184-Pin DIMM FRONT) PIN SYMBOL PIN SYMBOL 1 VREF 24 DQ17 2 DQ0 25 DQS2 3 VSS 26 VSS 4 DQ1 27 A9 5 DQS0 28 DQ18 6 DQ2 29 A7 7 VDD 30 VDDQ 8 DQ3 31 DQ19 9 NC 32 A5 10 RESET# 33 DQ24 11 VSS 34 VSS 12 DQ8 35 DQ25 13 DQ9 36 DQS3 14 DQS1 37 A4 15 VDDQ 38 VDD 16 DNU 39 DQ26 17 DNU 40 DQ27 18 VSS 41 A2 19 DQ10 42 VSS 20 DQ11 43 A1 21 CKE0 44 CB0 22 VDDQ 45 CB1 23 DQ16 46 VDD PIN 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 SYMBOL DQS8 A0 CB2 VSS CB3 BA1 DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VDDQ WE# DQ41 CAS# VSS DQS5 DQ42 DQ43 PIN 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 PIN ASSIGNMENT (184-Pin DIMM BACK) PIN SYMBOL PIN SYMBOL PIN 93 VSS 116 VSS 139 94 DQ4 117 DQ21 140 95 DQ5 118 A11 141 96 VDDQ 119 DQS11/ DM2 142 97 DQS9/DM0 120 VDD 143 98 DQ6 121 DQ22 144 99 DQ7 122 A8 145 100 VSS 123 DQ23 146 101 NC 124 VSS 147 102 NC 125 A6 148 103 NC 126 DQ28 149 104 VDDQ 127 DQ29 150 105 DQ12 128 VDDQ 151 106 DQ13 129 DQS12/ DM3 152 107 DQS10/ DM1 130 A3 153 108 VDD 131 DQ30 154 109 DQ14 132 VSS 155 110 DQ15 133 DQ31 156 111 NC/CKE1* 134 CB4 157 112 VDDQ 135 CB5 158 113 NC 136 VDDQ 159 114 DQ20 137 CK0 160 115 NC/A12* 138 CK0# 161 SYMBOL VDD NC DQ48 DQ49 VSS DNU DNU VDDQ DQS6 DQ50 DQ51 VSS NC DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL SYMBOL VSS PIN 162 DQS17/DM8 163 A10 164 CB6 165 VDDQ 166 CB7 167 VSS 168 DQ36 169 DQ37 170 VDD 171 DQS13/DM4 172 DQ38 173 DQ39 174 VSS 175 DQ44 176 RAS# 177 DQ45 178 VDDQ 179 S0# 180 NC/S1#* 181 DQS14/DM5 182 VSS 183 DQ46 184 SYMBOL DQ47 NC VDDQ DQ52 DQ53 NC VDD DQS15/DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DQS16/DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD *Pins 111, 115, and 158 are no connect (NC) for MT9VDDT1672 and MT18VDDT3272. For MT9VDDT3272D and MT18VDDT6472D, pin 111 is CKE1, pin 115 is address input A12, and pin 158 is S1#. PIN LOCATIONS (184-Pin DIMM) Low Profile Single Bank FRONT VIEW Low Profile Dual Bank FRONT VIEW U11 U11 U1 U3 U5 U7 U1 U9 U2 U3 U4 PIN 52 PIN 52 PIN 1 PIN 92 PIN 53 BACK VIEW U8 U9 PIN 92 BACK VIEW U17 U13 U19 U14 U21 U15 U16 U17 U18 PIN 145 PIN 144 Indicates a VDD or VDDQ pin 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 U19 U20 U21 U22 U10 U10 PIN 184 U7 PIN 53 U13 U15 U6 U12 U12 PIN 1 U5 PIN 184 PIN 93 Indicates a VSS pin PIN 145 Indicates a VDD or VDDQ pin 4 PIN 144 PIN 93 Indicates a VSS pin Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs PIN DESCRIPTIONS PIN NUMBERS SYMBOL TYPE DESCRIPTION 1 VREF Input SSTL_2 reference voltage. 63, 65, 154 WE#, CAS#, RAS# Input Command Inputs: RAS#, CAS#, and WE# (along with S0#) define the command being entered. 137, 138 CK0, CK0# Input Clock: CK0 and CK0# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK0 and negative edge of CK0#. Output data (DQs and DQS) is referenced to the crossings of CK0 and CK0#. 21, 111 CKE0 (Single Bank) CKE0 - CKE1 (Dual Bank) Input Clock Enable: CKE0 or CKE1 HIGH activates and CKE0 or CKE1 LOW deactivates the internal clock, input buffers and output drivers. Taking CKE0 or CKE1 LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all device banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any device bank). CKE0 or CKE1 is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE0 or CKE1 is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE0 or CKE1 must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK0, CK0# and CKE0 or CKE1) are disabled during POWER-DOWN. Input buffers (excluding CKE0 or CKE1) are disabled during SELF REFRESH. CKE0 or CKE1 is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied. 157, 158 S0# (Single Bank) S0# - S1# (Dual Bank) Input Chip Select: S0#, S1# enable (registered LOW) and disable (registered HIGH) the command decoder. All commands are masked when S0#, S1# are registered HIGH. S0#, S1# are considered part of the command code. 52, 59 BA0, BA1 Input Bank Address: BA0 and BA1 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. 27, 29, 32, 37, 41, 43, 48, 115 (A12), 118, 122, 125, 130, 141 A0-A11 MT9VDDT1672 MT18VDDT3272 A0-A12 MT9VDDT3272 MT18VDDT6472 Input Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. 91 SDA Input/ Output Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module. NOTE: Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables for pin number and symbol information. 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs PIN DESCRIPTIONS (continued) PIN NUMBERS SYMBOL TYPE DESCRIPTION 92 SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. 181, 182, 183 SA0-SA2 Input Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. 10 RESET# Input Asynchronously forces all register outputs LOW when RESET# is LOW. This signal can be used during powerup to ensure CKE0/1 are LOW and SDRAM DQs are High-Z. 44, 45, 49, 51, 134, 135, 142, 144 CB0-CB7 Input/ Output Data I/Os: Check bits. 5, 14, 25, 36, 47, 56, 67, 78, 86, 97, 107, 119, 129, 140, 149, 159, 169, 177 DQS0-DQS17 Input/ Output Data Strobe: DQS0-DQS8, Output with READ data, input with WRITE data. DQS is edge-aligned with READ data, centered in WRITE data. Used to capture data. Data Mask: DQS9-DQS17 function as DM0-DM8 to mask WRITE data when when HIGH. 2, 4, 6, 8, 12, 13, 19, 20, 23, 24, 28, 31, 33, 35, 39, 40, 53, 55, 57, 60, 61, 64, 68, 69, 72, 73, 79, 80, 83, 84, 87, 88, 94, 95, 98, 99, 105, 106, 109, 110, 114, 117, 121, 123, 126, 127, 131, 133, 146, 147, 150, 151, 153, 155, 161, 162, 165, 166, 170, 171, 174, 175, 178, 179 DQ0-DQ63 Input/ Output Data I/Os: Data bus. 15, 22, 30, 54, 62, 77, 96, 104, 112, 128, 136, 143, 156, 164, 172, 180 VDDQ Supply DQ Power Supply: +2.5V +0.2V. 7, 38, 46, 70, 85, 108, 120, 148, 168 VDD Supply Power Supply: +2.5V +0.2V. 3, 11, 18, 26, 34, 42, 50, 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176 VSS Supply Ground. 184 VDDSPD Supply Serial EEPROM positive power supply. 9, 71, 82, 90, 101, 102, 103, 113, 115 (MT9VDDT1672 and MT18VDDT3272), 163, 167, 173 NC -- No Connect: These pins should be left unconnected. 16, 17, 75, 76 DNU - Do Not Use: These pins are not connected on this module but are assigned pins on other modules in this product family. NOTE: Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables for pin number and symbol information. 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM MT9VDDT1672 (128MB), MT9VDDT3272 (256 MB) RS0# DQS0 DQS4 DM0 DM4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS# DQS DQ0 DQ1 U1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM CS# DQS DQ0 DQ1 U17 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM CS# DQS DQ0 U7 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM CS# DQS DQ0 DQ1 U15 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS# DQS DQ0 U9 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS5 DM1 DM5 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM CS# DQS DQ0 DQ1 U21 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS2 DQS6 DM2 DM6 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM CS# DQS DQ0 U3 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS3 DQS7 DM3 DM7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM CS# DQS DQ0 DQ1 U19 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM CS# DQS DQ0 U5 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS8 DM8 U12 120 CK0 CK0# PLL DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM REGISTER X 2 U11, U13 S0# BA0, BA1 A0-A11/12 RAS# CAS# CKE0 WE# CK R E G I S T E R S SERIAL PD SCL WP RS0# U10 A1 A2 SDA SA0 SA1 SA2 RA0-RA11/12: DDR SDRAMS RRAS#: DDR SDRAMS RCAS#: DDR SDRAMS RCKE0: DDR SDRAMS RWE#: DDR SDRAMS RESET# CK# NOTE: All resistor values are 22 ohms unless otherwise specified. 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 A0 RBA0, RBA1: DDR SDRAMS 7 VDDSPD SPD VDDQ DDR SDRAMS VDD DDR SDRAMS VREF DDR SDRAMS VSS DDR SDRAMS MT46V16M8TG DDR SDRAMs for MT9VDDT1672 MT46V32M8TG DDR SDRAMs for MT9VDDT3272 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM MT18VDDT3272D (256MB), MT18VDDT6472D (512 MB) RS1# RS0# DQS0 DQS4 DM0 DM4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS# DQS DQ0 U1 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS# DQS DQ0 DQ1 U22 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM CS# DQS DQ0 U17 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS# DQS DQ0 U6 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM CS# DQS DQ0 U7 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS# DQS DQ0 DQ1 U16 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM CS# DQS DQ0 DQ1 U15 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS# DQS DQ0 DQ1 U18 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS# DQS DQ0 U9 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS# DQS DQ0 DQ1 U14 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS5 DM1 DM5 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM CS# DQS DQ0 DQ1 U21 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS# DQS DQ0 U2 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS2 DQS6 DM2 DM6 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM CS# DQS DQ0 U3 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS# DQS DQ0 DQ1 U20 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS3 DQS7 DM3 DM7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM CS# DQS DQ0 DQ1 U19 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS# DQS DQ0 DQ1 U4 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM CS# DQS DQ0 U5 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS# DQS DQ0 DQ1 U18 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS8 DM8 U12 120 CK0 CK0# PLL DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 2 REGISTER X 2 U11, U13 S0# S1# BA0, BA1 A0-A11/12 RAS# CAS# CKE0 CKE1 WE# CK R E G I S T E R S RS0#, Bank 0 RS1#, Bank 1 SCL RBA0, RBA1: DDR SDRAMS SDA RA0-RA11/12: DDR SDRAMS SA0 SA1 SA2 RRAS#: DDR SDRAMS RCAS#: DDR SDRAMS RCKE0: DDR SDRAMS, Bank 0 RCKE1: DDR SDRAMS, Bank 1 RWE#: DDR SDRAMS RESET# CK# NOTE: All resistor values are 22 ohms unless otherwise specified. 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 WP SERIAL PD U10 A0 A1 A2 8 VDDSPD SPD VDDQ DDR SDRAMS VDD DDR SDRAMS VREF DDR SDRAMS VSS DDR SDRAMS MT46V16M8TG DDR SDRAMs for MT18VDDT3272D MT46V32M8TG DDR SDRAMs for MT18VDDT6472D Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs modules allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible. For more information regarding DDR SDRAM operation, refer to the 128Mb and 256Mb DDR SDRAM data sheet. GENERAL DESCRIPTION The MT9VDDT1672, MT9VDDT3272, MT18VDDT3272D, and MT18VDDT6472D are highspeed CMOS, dynamic random-access, 128MB, 256MB, and 512MB registered memory modules organized in a x72 (ECC) configuration. These modules use internally configured quad-bank DDR SDRAM devices. These DDR SDRAM modules use a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2nprefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM module effectively consists of a single 2n-bit wide, oneclock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is an intermittent strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. These DDR SDRAM modules operate from a differential clock (CK0 and CK0#); the crossing of CK0 going HIGH and CK0# going LOW will be referred to as the positive edge of CK0. Commands (address and control signals) are registered at every positive edge of CK0. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK0. Read and write accesses to the DDR SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1 select devices bank; A0-A11 select device row for MT9VDDT1672 and MT18VDDT3272D; A0-A12 select device row for MT9VDDT3272 and MT18VDDT6472D). The address bits registered coincident with the READ or WRITE command are used to select the device bank and the starting device column location for the burst access. These DDR SDRAM modules provide for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDR SDRAM modules, the pipelined, multibank architecture of DDR SDRAM 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 PLL AND REGISTER OPERATION The DDR SDRAM module is operated in registered mode where the control/address input signals are latched in the register on one rising clock edge and sent to the DDR SDRAM devices on the following rising clock edge (data access is delayed by one clock). A phase-lock loop (PLL) on the module is used to redrive the differential clock signals CK0 and CK0# to the DDR SDRAM devices to minimize system clock loading. SERIAL PRESENCE-DETECT OPERATION These DDR SDRAM modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard IIC bus using the DIMM's SCL (clock) and SDA (data) signals, together with SA(2:0), which provide eight unique DIMM/EEPROM addresses. REGISTER DEFINITION MODE REGISTER The mode register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency and an operating mode, as shown in the Mode Register Diagram. The mode register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing). Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded) when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs Mode register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A11 (MT9VDDT1672 and MT18VDDT3272D) or A7-A12 (MT9VDDT3272 and MT18VDDT6472D) specify the operating mode. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-An when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts. Burst Length Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Mode Register Diagram. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Mode Register Definition Diagram Burst Definition Table MT9VDDT1672, MT18VDDT3272D MODULE ADDRESS BUS BA1 BA0 A11 A10 A9 A8 13 12 0* 0* A7 A6 A5 A4 A3 A2 A1 A0 8 6 5 4 1 11 10 9 7 3 2 0 Operating Mode CAS Latency BT Burst Length Address Bus Burst Length Mode Register (Mx) 2 * M13 and M12 (BA0 and BA1) must be "0, 0" to select the base mode register (vs. the extended mode register). MT9VDDT3272, MT18VDDT6472D MODULE ADDRESS BUS BA1 BA0 A12 A11 A10 A9 A8 14 13 12 11 10 9 8 Operating Mode 0* 0* A7 A6 A5 A4 A3 A2 A1 A0 7 6 5 4 1 3 2 0 CAS Latency BT Burst Length * M14 and M13 (BA0 and BA1) must be "0, 0" to select the base mode register (vs. the extended mode register). 4 Address Bus Mode Register (Mx) Burst Length M2 M1 M0 M3 = 0 M3 = 1 0 0 0 Reserved Reserved 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Reserved Reserved M3 Burst Type 0 Sequential 1 Interleaved 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 2.5 1 1 1 Reserved M6-M0 0-1 1-0 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Operating Mode 0 0 0 0 0 0 Valid Normal Operation 0 0 0 0 1 0 Valid Normal Operation/Reset DLL - - - - - - - 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 A0 0 1 A1 A0 0 0 0 1 1 0 1 1 A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 NOTE: 1. For a burst length of two, A1-Ai select the twodata-element block; A0 selects the first access within the block. 2. For a burst length of four, A2-Ai select the fourdata-element block; A0-A1 select the first access within the block. 3. For a burst length of eight, A3-Ai select the eightdata-element block; A0-A2 select the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. CAS Latency M6 M5 M4 M12 M11 M10 M9 M8 M7 8 Starting Column Order of Accesses Within a Burst Address Type = Sequential Type = Interleaved i = 11 for MT9VDDT1672, MT18VDDT3272D, or 12 for MT9VDDT3272, MT18VDDT6472D All other states reserved 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs CAS LATENCY (CL) TABLE Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Burst Definition Table. ALLOWABLE OPERATING CLOCK FREQUENCY (MHz) SPEED -26A -265 -202 Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or 2.5 clocks, as shown in CAS Latency Diagram. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. The CAS Latency Table indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. T1 T2 READ NOP NOP T2n T3 T3n CK# CK COMMAND CL = 2.5 75 f 133 75 f 133 75 f 125 Operating Mode The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7-A11 (for the 256MB), or A7-A12 (for the 512MB module) each set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9-A11 (MT9VDDT1672 and MT18VDDT3272D), or A7 and A9-A12 (MT9VDDT3272 and MT18VDDT6472D) each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. Although not required by the Micron device, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operating mode. All other combinations of values for A7-A11, or A7A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. CAS Latency Diagram T0 CL = 2 75 f 133 75 f 100 75 f 100 NOP CL = 2 DQS DQ CK# T0 T1 T2 READ NOP NOP T2n T3 T3n CK COMMAND NOP CL = 2.5 DQS DQ Burst Length = 4 in the cases shown Shown with nominal tAC and nominal tDSDQ TRANSITIONING DATA 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 DON'T CARE 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 EXTENDED MODE REGISTER The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable, output drive strength, and QFC#. These functions are controlled via the bits shown in the Extended Mode Register Definition Diagram. The extended mode register is programmed via the LOAD MODE REGISTER command to the mode register (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL. The extended mode register must be loaded when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. MT9VDDT1672 and MT18VDDT3272D 13 12 11 10 9 11 01 8 7 6 5 4 Operating Mode 3 2 1 0 Extended Mode Register (Ex) QFC DS DLL BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 MT9VDDT3272 and MT18VDDT6472D 14 13 12 11 10 9 8 7 6 5 Operating Mode 11 01 4 3 2 1 0 E0 DLL 0 Enable Disable Drive Strength E1 0 E2, E1, E0 Address Bus Extended Mode Register (Ex) QFC# DS DLL 1 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 Address Bus Normal E2 QFC# Function 0 Disabled Operating Mode 0 0 0 0 0 0 0 0 0 0 Valid Reserved - - - - - - - - - - - Reserved NOTE: 1. E13 and E12 (128MB module), or E14 and E13 (256MB Module) (BA0 and BA1) must be "1, 0" to select the Extended Mode Register (vs. the base Mode Register). 2. The QFC# option is not supported. Output Drive Strength The normal full drive strength for all outputs are specified to be SSTL2, Class II. For detailed information on output drive strength option, refer to 128Mb and 256Mb DDR SDRAM data sheets. Extended Mode Register Definition Diagram DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued. 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs Commands commands and operations, refer to the Micron 128Mb or 256Mb DDR SDRAM data sheet. Truth Table 1 provides a general reference of available commands. For a more detailed description of TRUTH TABLE 1 - COMMANDS (Note: 1) NAME (FUNCTION) CS# RAS# CAS# WE# ADDR NOTES DESELECT (NOP) H X X X X 9 NO OPERATION (NOP) L H H H X 9 ACTIVE (Select device bank and activate row) L L H H Bank/Row 3 READ (Select device bank and column, and start READ burst) L H L H Bank/Col 4 WRITE (Select device bank and column, and start WRITE burst) L H L L Bank/Col 4 BURST TERMINATE L H H L X 8 PRECHARGE (Deactivate row in device bank or banks) L L H L Code 5 AUTO REFRESH or SELF REFRESH (Enter self refresh mode) L L L H X 6, 7 LOAD MODE REGISTER L L L L Op-Code 2 TRUTH TABLE 1A - DM OPERATION (Note: 10) NAME (FUNCTION) DM DQs Write Enable L Valid Write Inhibit H X NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH. 2. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A11 provide the op-code to be written to the selected mode register. 3. BA0-BA1 provide device bank address and A0-A11 (MT9VDDT1672, MT18VDDT3272D), or A0-A12 (MT9VDDT3272, MT18VDDT6472D) provide row address. 4. BA0-BA1 provide device bank address; A0-A9, 11 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature. 5. A10 LOW: BA0-BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0-BA1 are "Don't Care." 6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE. 8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ bursts with auto precharge enabled and for WRITE bursts. 9. DESELECT and NOP are functionally interchangeable. 10. Used to mask write data; provided coincident with the corresponding data. 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ABSOLUTE MAXIMUM RATINGS* Voltage on VDD Supply Relative to VSS .............................................. -1V to +3.6V Voltage on VDDQ Supply Relative to VSS .............................................. -1V to +3.6V Voltage on VREF and Inputs Relative to VSS .............................................. -1V to +3.6V Voltage on I/O Pins Relative to VSS ................................. -0.5V to VDDQ +0.5V Operating Temperature, TA (ambient) ... 0C to +70C Storage Temperature (plastic) ............ -55C to +150C Power Dissipation (Single Module Bank) ................ 9W (Dual Module Bank) ................ 18W Short Circuit Output Current ................................. 50mA DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (ALL MODULES) (Notes: 1-5, 14; notes appear following parameter tables) (0C TA +70C; VDD = +2.5V 0.2V, VDDQ = +2.5V 0.2V) PARAMETER/CONDITION SYMBOL MIN MAX VDD 2.3 2.7 V 32, 36 VDDQ 2.3 2.7 V 32, 36, 39 I/O Reference Voltage VREF 0.49 x VDDQ 0.51 x VDDQ V 6, 39 I/O Termination Voltage (system) VTT VREF - 0.04 VREF + 0.04 V 7, 39 Input High (Logic 1) Voltage VIH(DC) VREF + 0.15 VDD + 0.3 V 25 Input Low (Logic 0) Voltage VIL(DC) -0.3 VREF - 0.15 V 25 II -5 5 A 48 IOZ -45 45 A 48 IOZ -90 90 A 48 IOH IOL -16.8 16.8 - - mA mA 33, 34 Supply Voltage I/O Supply Voltage INPUT LEAKAGE CURRENT (All Modules) Any input 0V VIN VDD, VREF pin 0V VIN 1.35V (All other pins not under test = 0V) OUTPUT LEAKAGE CURRENT (Single Bank Modules) (DQs are disabled; 0V VOUT VDDQ) OUTPUT LEAKAGE CURRENT (Dual Bank Modules) (DQs are disabled; 0V VOUT VDDQ) OUTPUT LEVELS: High Current (VOUT = VDDQ-0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF, maximum VTT) 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 14 UNITS NOTES Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs IDD SPECIFICATIONS AND CONDITIONS* (128MB - MT9VDDT1672) (Notes: 1-5, 8, 10, 12; notes appear following parameter tables) (0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V) MAX PARAMETER/CONDITION SYMBOL -26A/-265 -202 UNITS OPERATING CURRENT: One device bank; Active-Precharge; IDD0 945 900 mA tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles; OPERATING CURRENT: One device bank; Active-Read-Precharge; IDD1 1,080 990 mA Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks IDD2P 27 27 mA idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; IDD2F 405 315 mA tCK = tCK MIN; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; IDD3P 162 162 mA Power-down mode; tCK = tCK (MIN); CKE = LOW 405 315 mA ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device IDD3N bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; IDD4R 990 810 mA One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA 990 810 mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; IDD4W One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle tRC = tRFC (MIN) AUTO REFRESH CURRENT IDD5 1,980 1,845 mA tRC = 15.625s IDD5A 45 45 mA SELF REFRESH CURRENT: CKE 0.2V IDD6 18 27 mA OPERATING CURRENT: Four bank interleaving READs (BL=4) with IDD7 2,925 2,340 mA auto precharge with, tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during Active READ, or WRITE commands. NOTES 20, 43 20, 43 21, 28, 45 46 21, 28, 45 42 20, 43 20 20, 45 24, 45 9 20, 44 *DDR SDRAM components only. 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs IDD SPECIFICATIONS AND CONDITIONS* (256MB - MT9VDDT3272) (Notes: 1-5, 8, 10, 12; notes appear following parameter tables) (0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V) MAX PARAMETER/CONDITION SYMBOL -26A/-265 -202 OPERATING CURRENT: One device bank; Active-Precharge; IDD0 TBD TBD tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles; OPERATING CURRENT: One device bank; Active-Read-Precharge; IDD1 TBD TBD Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks IDD2P 27 27 idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; IDD2F 315 270 tCK = tCK MIN; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; IDD3P TBD TBD Power-down mode; tCK = tCK (MIN); CKE = LOW 315 270 ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device IDD3N bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; IDD4R TBD TBD One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA TBD TBD OPERATING CURRENT: Burst = 2; Writes; Continuous burst; IDD4W One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle tRC = tRC (MIN) AUTO REFRESH CURRENT IDD5 TBD TBD tRC = 7.8125s IDD5A 54 54 SELF REFRESH CURRENT: CKE 0.2V IDD6 TBD TBD OPERATING CURRENT: Four bank interleaving READs (BL=4) with I DD7 TBD TBD auto precharge with, tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during Active READ, or WRITE commands. UNITS mA NOTES 20, 43 mA 20, 43 mA 21, 28, 45 46 mA mA mA 21, 28, 45 42 mA 20, 43 mA 20 mA mA mA mA 20, 45 24, 45 9 20, 44 * DDR SDRAM components only. 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs IDD SPECIFICATIONS AND CONDITIONS* (256MB - MT18VDDT3272D) (Notes: 1-5, 8, 10, 12; notes appear following parameter tables) (0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V) PARAMETER/CONDITION MAX SYMBOL -26A/-265 -202 UNITS NOTES OPERATING CURRENT: One device bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles; IDD0a 972 927 mA 20, 43 OPERATING CURRENT: One device bank; Active-Read-Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle IDD1a 1,107 1,017 mA 20, 43 PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDD2Pb 54 54 mA 21, 28, 45 IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK MIN; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM IDD2Fb 810 630 mA 46 ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD3Pb 324 324 mA 21, 28, 45 ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD3Nb 810 630 mA 42 OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA IDD4Ra 1,017 837 mA 20, 43 OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle IDD4Wa 1,017 837 mA 20 IDD5b IDD5Ab 3,960 90 3,690 90 mA mA 20, 45 24, 45 IDD6b IDD7a 36 2,979 54 2,367 mA mA 9 20, 44 AUTO REFRESH CURRENT tRC = tRC (MIN) tRC = 15.625s SELF REFRESH CURRENT: CKE 0.2V OPERATING CURRENT: Four bank interleaving READs (BL=4) with auto precharge with, tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during Active READ, or WRITE commands. * DDR SDRAM components only. a - Value calculated as one module bank in this operating condition, and all other module banks in IDD2P (CKE LOW) mode. b- Value calculated reflects all module banks in this operating condition. 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs IDD SPECIFICATIONS AND CONDITIONS* (512MB - MT18VDDT6472D) (Notes: 1-5, 8, 10, 12; notes appear following parameter tables) (0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V) PARAMETER/CONDITION MAX SYMBOL -26A/-265 -202 UNITS NOTES OPERATING CURRENT: One device bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles; IDD0a TBD TBD mA 20, 43 OPERATING CURRENT: One device bank; Active-Read-Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle IDD1a TBD TBD mA 20, 43 PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDD2Pb 54 54 mA 21, 28, 45 IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK MIN; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM IDD2Fb 630 540 mA 46 ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD3Pb TBD TBD mA 21, 28, 45 ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD3Nb 630 540 mA 42 OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA IDD4Ra TBD TBD mA 20, 43 OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle IDD4Wa TBD TBD mA 20 IDD5b IDD5Ab TBD 108 TBD 108 mA mA 20, 45 24, 45 IDD6b IDD7a TBD TBD TBD TBD mA mA 9 20, 44 AUTO REFRESH CURRENT tRC = tRC (MIN) tRC = 7.8125s SELF REFRESH CURRENT: CKE 0.2V OPERATING CURRENT: Four bank interleaving READs (BL=4) with auto precharge with, tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during Active READ, or WRITE commands. * DDR SDRAM components only. a - Value calculated as one module bank in this operating condition, and all other module banks in IDD2P (CKE LOW) mode. b- Value calculated reflects all module banks in this operating condition. 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs CAPACITANCE (MT9VDDT1672, MT9VDDT3272) (Note: 11; notes appear following parameter tables) PARAMETER Input/Output Capacitance: DQs, DQS Input Capacitance: Command and Address Input Capacitance: S0# Input Capacitance: CK0, CK0# Input Capacitance: CKE0 SYMBOL MIN CIO 4.0 CI1 2.5 CI1 2.5 CI2 2.5 CI3 2.5 MAX UNITS 5.0 pF 3.5 pF 3.5 pF 3.5 pF 3.5 pF SYMBOL MIN CIO 8.0 CI1 2.5 CI1 2.5 CI2 2.5 2.5 CI3 MAX UNITS 10.0 pF 3.5 pF 3.5 pF 3.5 pF 3.5 pF CAPACITANCE (MT18VDDT3272D, MT18VDDT6472D) (Note: 11; notes appear following parameter tables) PARAMETER Input/Output Capacitance: DQs, DQS Input Capacitance: Command and Address Input Capacitance: S0#, S1# Input Capacitance: CK0, CK0# Input Capacitance: CKE0, CKE1 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Notes: 1-5, 12-15, 29; notes appear following parameter tables) (0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V) AC CHARACTERISTICS PARAMETER Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time CL = 2.5 CL = 2 DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK/CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access Write command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access Data Hold Skew Factor ACTIVE to PRECHARGE command ACTIVE to READ with auto precharge command, MT9VDDT1672 and MT1832VDD3272D ACTIVE to READ with auto precharge command, MT9VDD3272 and MT18VDD6472D ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 SYMBOL tAC tCH tCL tCK (2.5) tCK (2) tDH tDS tDIPW tDQSCK tDQSH tDQSL tDQSQ tDQSS tDSS tDSH tHP tHZ tLZ tIH S t IS S tIH F t IS F tMRD tQH tQHS tRAS tRAP -26A -265 -202 MIN MAX MIN MAX MIN MAX UNITS -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns tCK 0.45 0.55 0.45 0.55 0.45 0.55 tCK 0.45 0.55 0.45 0.55 0.45 0.55 7.5 13 7.5 13 8 13 ns 7.5 13 10 13 10 13 ns 0.5 0.5 0.6 ns 0.5 0.5 0.6 ns 1.75 1.75 2 ns -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns tCK 0.35 0.35 0.35 tCK 0.35 0.35 0.35 0.5 0.5 0.6 ns tCK 0.75 1.25 0.75 1.25 0.75 1.25 tCK 0.2 0.2 0.2 tCK 0.2 0.2 0.2 tCH,tCL tCH,tCL tCH,tCL ns +0.75 +0.75 +0.8 ns -0.75 -0.75 -0.8 ns 1 1 1.1 ns 1 1 1.1 ns 0.9 0.9 1.1 ns 0.9 0.9 1.1 ns 15 15 16 ns tHP tHP tHP ns t t t - QHS - QHS - QHS 0.75 0.75 1 ns 40 120,000 40 120,000 40 120,000 ns tRAS(MIN) - (burst length t ns * CK/2) tRAP 20 20 20 ns tRC 65 75 20 20 0.9 0.4 15 0.25 0 0.4 15 1 65 75 20 20 0.9 0.4 15 0.25 0 0.4 15 1 70 80 20 20 0.9 0.4 15 0.25 0 0.4 15 1 ns ns ns ns tCK tCK ns tCK ns tCK ns tCK tRFC tRCD tRP tRPRE tRPST tRRD tWPRE tWPRES tWPST tWR tWTR 20 1.1 0.6 0.6 1.1 0.6 0.6 1.1 0.6 0.6 NOTES 26 26 40, 47 40, 47 23, 27 23, 27 27 22, 23 30 16, 37 16, 38 12 12 12 12 22, 23 31 41 45 18, 19 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (continued) AC CHARACTERISTICS PARAMETER Data valid output window (DVW) REFRESH to REFRESH command interval, MT9VDD1672 and MT18VDDT3272D REFRESH to REFRESH command interval, MT9VDD3272 and MT18VDD6472D Average periodic refresh interval, MT9VDD1672 and MT18VDDT3272D Average periodic refresh interval, MT9VDD3272 and MT18VDDT6472D Terminating voltage delay to VDD Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 -26A SYMBOL MIN MAX t t na QH - DQSQ tREFC 140.6 -265 MIN MAX tQH - tDQSQ 140.6 -202 MIN MAX tQH - tDQSQ 140.6 UNITS ns s NOTES 22 21 tREFC 70.3 70.3 70.3 s 21 tREFI 15.6 15.6 15.6 s 21 tREFI 7.8 7.8 7.8 s 21 tVTD tXSNR tXSRD 0 75 200 21 0 75 200 0 80 200 ns ns tCK Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs 11. This parameter is sampled. VDD = +2.5V 0.2V, VDDQ = +2.5V 0.2V, VREF = VSS, f = 100 MHz, TA = 25C, VOUT(DC) = VDDQ/2, VOUT (peak to peak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. 12. Command/Address input slew rate = 0.5V/ns. For -75 with slew rates 1V/ns and faster, tIS and tIH are reduced to 900ps. If the slew rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100mV/ns reduction in slew rate from the 500mV/ns. tIH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain. 13. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is VREF. 14. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE 0.3 x VDDQ is recognized as LOW. 15. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. 16. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). 17. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 18. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 19. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 20. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. NOTES 1. 2. 3. All voltages referenced to VSS. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. Outputs measured with equivalent load: VTT Output (VOUT) 50 Reference Point 30pF 4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed 2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed 25mV for DC error and an additional 25mV for AC noise. This measurement is to be taken at the nearest VREF by-pass capacitor. 7. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 8. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time at CL = 2 for -26A and -202, CL = 2.5 for -265 with the outputs open. 9. Enables on-chip refresh and address counters. 10. IDD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs NOTES (continued) 25. To maintain a valid level, the transitioning edge of the input must: a) Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) or VIH(AC). b) Reach at least the target AC level. c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC). 26. JEDEC specifies CK and CK# input slew rate must be 1V/ns (2V/ns differentially). 27. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mv/ns reduction in slew rate. If slew rate exceeds 4V/ns, functionality is uncertain.28. VDD must not vary more than 4% if CKE is not active while any bank is active. 28. VDD must not vary more than 4% if CKE is not active while any bank is active. 29. The clock is allowed up to 150ps of jitter. Each timing parameter is allowed to vary by the same amount. 21. The refresh period 64ms. This equates to an average refresh rate of 15.625s for 128Mb-based DIMMS, and 7.8/70.3 for 256Mb-based DIMMs. However, an AUTO REFRESH command must be asserted at least once every 140.6s; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. 22. The valid data window is derived by achieving other specifications - tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55. 23. Referenced to each output group: x8 = DQS with DQ0-DQ7. 24. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby). DERATING DATA VALID WINDOW (tQH - tDQSQ) 3.8 3.750 3.6 3.4 3.400 3.700 3.650 3.600 3.550 3.500 3.350 3.300 3.450 3.400 3.250 3.200 3.2 3.100 ---- u -75 @ CK = 10ns t ns 3.0 3.350 3.150 3.300 3.250 3.050 3.000 # ---- -8 @ tCK = 10ns 2.950 ---- n -75 @ tCK = 7.5ns 2.8 2.6 2.900 ---- l -8 @ tCK = 8ns 2.500 2.463 2.425 2.4 2.388 2.350 2.313 2.275 2.238 2.200 2.2 2.163 2.125 2.0 1.8 50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 47/53 46.5/54.5 46/54 45.5/55.5 45/55 Clock Duty Cycle 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs NOTES (continued) 30. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK/ inputs, collectively during bank active. 31. READs and WRITEs with auto precharge are not allowed to be issued until tRAS(MIN) can be satisfied prior to the internal precharge command being issued. 32. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or 2.9 volts, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either -300mV or 2.2 volts, whichever is more positive. 33. Normal Output Drive Curves: a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure A. b)The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure A. c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure B. d)The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure B. 34. 35. 36. 37. 38. 39. Figure A Pull-Down Characteristics 160 e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between .71 and 1.4, for device drainto-source voltages from 0.1V to 1.0 Volt, and at the same voltage and temperature. f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity 10%, for device drain-to-source voltages from 0.1V to 1.0 Volt. The voltage levels used are derived from a minimum VDD level and the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. VIH overshoot: VIH(MAX) = VDDQ+1.5V for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL(MIN) = -1.5V for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VDD and VDDQ must track each other. This maximum value is derived from the referenced test load. In practice, the values obtained in a typical terminated design may reflect up to 310ps less for tHZ(MAX) and the last DVW. tHZ(MAX) will prevail over tDQSCK(MAX) + tRPST(MAX) condition. tLZ(MIN) will prevail over tDQSCK(MIN) + tRPRE(MAX) condition. For slew rates greater than 1V/ns the (LZ) transition will start about 310ps earlier. During initialization, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VDD/VDDQ are 0 volts, provided a minimum of 42 ohms of series resistance is used between the VTT supply and the input pin. Figure B Pull-Up Characteristics 0 -20 140 -40 120 -60 IOUT (mA) IOUT (mA) 100 80 60 -80 -100 -120 -140 40 -160 20 -180 0 -200 0.0 0.5 1.0 1.5 2.0 2.5 0.0 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 0.5 1.0 1.5 2.0 2.5 VDDQ - VOUT (V) VOUT (V) 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs NOTES (continued) 40. The current Micron part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. 41. tRAP tRCD. 42. For the -26A and -265 speed grade, IDD3N is specified to be the same as the -202 speed grade when operating at 100 MHz (or DDR200 speed). 43. Random addressing changing 50% of data changing at every transfer. 44. Random addressing changing 100% of data changing at every transfer. 45. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tREF later. 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 46. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is "worst case." 47. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles. 48. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs REGISTER TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS (Note: 1) TA = 0-70 C VDD = 2.5V 0.2V REGISTER SYMBOL Clock Frequency t PD Clock to Output Time t RST Reset to Output Time tS L 1:1 14 bit SSTL PARAMETER t CK CONDITIONS 30pF to GND and 50 ohms to VTT MAX 60 170 UNITS NOTES MHz 1.1 2.7 ns - 5 ns 0.5 4 V/ns Setup time, fast slew rate (see Notes 1 and 3) - 0.75 ns 2, 4 Setup time, slow slew rate (see Notes 2 and 3) - 0.9 ns 3, 4 Hold time, fast slew rate (see Notes 1 and 3) - 0.75 ns 2, 4 Hold time, slow slew rate (see Notes 2 and 3) - 0.9 ns 3, 4 CIN(CK) Clock Input Capacitance 2.5 3.5 pF CIN(data) Data Input Capacitance 2.5 3.5 pF t su th Output Slew Rate MIN NOTE: 1. The timing specifications for the register listed above are critical for proper operation of the DDR SDRAM Registered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed information on this part has been shown at the JEDEC JC-40 Committee. Please contact Micron Technology's Module Applications Team if further information on the specific register model is required. 2. For data signal, input slew rate 1 V/ns. 3. For data signal, input slew rate 0.5 V/ns and < 1 V/ns. 4. For CK and CK# signals, input slew rates are 1 V/ns. 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs PLL CLOCK DRIVER TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS (Specifications for the PLL component used on the module.) PARAMETER Clock frequency SYMBOL TEST CONDITIONS fC Input clock duty cycle Stabilization MIN NOM MAX UNITS 66 167 40% 60% time1 MHz 0.1 ms 3.5 6 ns 3.5 6 ns Low-to high level propagation delay time t PLH CK mode/CK to any output 1.5 High-to low level propagation delay time t PHL CK mode/CK to any output 1.5 Output enable time t en CK mode/G to any Y output 3 ns Output disable time t dis CK mode/G to any Y output 3 ns Jitter (peak-to-peak) t(jitter) Jitter (cycle-to-cycle) t(jitter) Phase error t (phase 66 MHz 120 100/125/133/167 MHz 75 66 MHz 110 100/125/133/167 MHz 65 Terminated with 120 ohm/16pF -150 ps ps 150 ns error) Output skew Pulse skew tskew(o) Terminated with 120 ohm/16pF 100 ns t dis Terminated with 120 ohm/16pF 100 ns Duty cycle Output rise and fall times (20% - 80%) tr, tf 66 MHz to 100 MHz 49.5% 101 MHz to 167 MHz 49% Load = 120 ohm/16pF 650 50.5% 51% 800 950 ps NOTE: 1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs SPD ACKNOWLEDGE Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data as indicated in Figure 5. The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a WRITE operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eight-bit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. SPD CLOCK AND DATA CONVENTIONS Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions as indicated in Figures 3 and 4. SPD START CONDITION All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD STOP CONDITION All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. Figure 3 Data Validity Figure 4 Definition of Start and Stop SCL SCL SDA DATA STABLE DATA CHANGE DATA STABLE SDA START BIT STOP BIT Figure 5 Acknowledge Response From Receiver SCL from Master 8 9 Data Output from Transmitter Data Output from Receiver Acknowledge 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs EEPROM DEVICE SELECT CODE The most significant bit (b7) is sent first DEVICE TYPE IDENTIFIER b7 b6 b5 b4 Memory Area Select Code (two arrays) Protection Register Select Code 1 0 0 1 1 1 0 0 CHIP ENABLE b3 b2 b1 RW b0 E2 E2 RW RW E1 E1 E0 E0 EEPROM OPERATING MODES MODE Current Address Read RW BIT 1 WC 1 X BYTES 1 Random Address Read 0 1 1 0 0 X X X VIL VIL 1 1 1 1 START, Device Select, RW = `0', Address reSTART, Device Select, RW = `1' Similar to Current or Random Address Read START, Device Select, RW = `0' 16 START, Device Select, RW = `0' Sequential Read Byte Write Page Write INITIAL SEQUENCE START, Device Select, RW = `1' NOTE: 1. X = VIH or VIL. SPD EEPROM TIMING DIAGRAM tF t HIGH tR t LOW SCL t HD:STA t SU:STA t SU:DAT t HD:DAT t SU:STO SDA IN t DH t AA t BUF SDA OUT UNDEFINED SERIAL PRESENCE-DETECT EEPROM TIMING PARAMETERS SYMBOL MIN MAX UNITS 3.5 tBUF 0.3 4.7 s s tDH 300 tAA tHD:DAT 0 ns ns s tHD:STA 4 s tF 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 300 SYMBOL tHIGH tLOW 29 MIN 4 MAX tSU:DAT 250 s s ns tSU:STA 4.7 4.7 s s tR tSU:STO 4.7 UNITS s 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs SERIAL PRESENCE-DETECT EEPROM DC OPERATING CONDITIONS (Note: 1) (VDD = +3.3V 0.3V) PARAMETER/CONDITION SYMBOL MIN MAX UNITS VDDSPD 2.2 5.5 V INPUT HIGH VOLTAGE: Logic 1; All inputs VIH VDD x 0.7 VDD + 0.5 V INPUT LOW VOLTAGE: Logic 0; All inputs VIL -1 VDD x 0.3 V OUTPUT LOW VOLTAGE: IOUT = 3mA SUPPLY VOLTAGE VOL - 0.4 V INPUT LEAKAGE CURRENT: VIN = GND to VDD ILI - 10 A OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD ILO - 10 A STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = GND or 3.3V +10% ISB - 30 A POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz IDD - 2 mA SERIAL PRESENCE-DETECT EEPROM AC OPERATING CONDITIONS (Note: 2) (VDD = +3.3V 0.3V) PARAMETER/CONDITION SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time SYMBOL tAA tBUF tDH tF tHD:DAT tHD:STA tHIGH tI tLOW tR tSCL tSU:DAT tSU:STA tSU:STO tWRC MIN 0.3 4.7 300 MAX 3.5 300 0 4 4 100 4.7 1 100 250 4.7 4.7 10 UNITS s s ns ns s s s ns s s KHz ns s s ms NOTES 3 NOTE: 1. All voltages referenced to VSS. 2. All voltages referenced to VSS. 3. Timing actually specified by tWR. 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 30 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs SERIAL PRESENCE-DETECT MATRIX (Note: 1) BYTE 0 1 2 3 4 5 6 7 8 9 DESCRIPTION NUMBER OF SPD BYTES USED BY MICRON TOTAL NUMBER OF BYTES IN SPD DEVICE FUNDAMENTAL MEMORY TYPE NUMBER OF ROW ADDRESSES ON ASSEMBLY NUMBER OF COLUMN ADDRESSES ON ASSEMBLY NUMBER OF PHYSICAL BANKS ON DIMM MODULE DATA WIDTH MODULE DATA WIDTH (continued) MODULE VOLTAGE INTERFACE LEVELS (VDDQ) SDRAM CYCLE TIME, (tCK) (CAS LATENCY = 2.5) (Note:2) ENTRY (VERSION) 128 256 SDRAM DDR 12 or 13 10 1 72 0 SSTL 2.5V 7ns (-26A) 7.5ns (-265) 8ns (-202) MT9VDDT1672 80 08 07 0C 0A 01 48 00 04 70 75 80 MT9VDDT3272 80 08 07 0D 0A 01 48 00 04 70 75 80 10 SDRAM ACCESS FROM CLOCK,(tAC) (CAS LATENCY = 2.5) (Note:2) 0.75ns (-26A/-265) 0.8ns (-202) 75 80 75 80 11 12 13 14 15 MODULE CONFIGURATION TYPE REFRESH RATE/TYPE SDRAM DEVICE WIDTH (PRIMARY SDRAM) ERROR-CHECKING SDRAM DATA WIDTH MINIMUM CLOCK DELAY, BACK-TO-BACK RANDOM COLUMN ACCESS ECC 7.8s or 15.6s/SELF x8 x8 1 clock 02 80 08 08 01 02 82 08 08 01 16 17 18 19 20 21 22 23 BURST LENGTHS SUPPORTED NUMBER OF BANKS ON SDRAM DEVICE CAS LATENCIES SUPPORTED CS LATENCY WE LATENCY SDRAM MODULE ATTRIBUTES SDRAM DEVICE ATTRIBUTES: GENERAL SDRAM CYCLE TIME, (tCK) (CAS LATENCY = 2)(Note:2) 2, 4, 8 4 2, 2.5 0 1 REGISTERED, PLL Fast/concurrent A/P 7.5ns (-26A) 10ns (-265/-202) 0E 04 0C 01 02 26 00/C0* 75 A0 0E 04 0C 01 02 26 C0 75 A0 24 SDRAM ACCESS FROM CK , (tAC) (CAS LATENCY = 2)(Note:2) 0.75ns (-26A/-265) 0.8ns (-202) 75 80 75 80 25 SDRAM CYCLE TIME, (tCK) (CAS LATENCY = 1.5) N/A 00 00 26 SDRAM ACCESS FROM CK , (tAC) (CAS LATENCY = 1.5) N/A 00 00 27 28 29 30 MINIMUM ROW PRECHARGE TIME, (tRP) MINIMUM ROW ACTIVE TO ROW ACTIVE, (tRRD) MINIMUM RAS# TO CAS# DELAY, (tRCD) MINIMUM ACTIVE TO PRECHARGE TIME, (tRAS) (Note: 3) 20ns 15ns 20ns 45ns (-26A/-265) 40ns (-202) 50 3C 50 2D 28 50 3C 50 2D 28 31 MODULE BANK DENSITY 128MB or 256MB 20 40 *Supports fast/concurrent auto precharge. Contact factory for additional information regarding this option. NOTE: 1. "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW." 2. The value of tCK for -26A modules is set at 7.0ns. Component spec. value is 7.5ns. 3. The value of tRAS used for the -26A/-265 module is calculated from tRC - tRP. Actual device spec. value is 40ns. 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 31 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs SERIAL PRESENCE-DETECT MATRIX (continued) (Note: 2) BYTE 32 DESCRIPTION ADDRESS AND COMMAND SETUP TIME, (tIS) ENTRY (VERSION) 1.0ns (-26A/-265) 1.1ns (-202) MT9VDDT1672 A0 B0 33 ADDRESS AND COMMAND HOLD TIME, (tIH) 1.0ns (-26A/-265) 1.1ns (-202) A0 B0 A0 B0 34 DATA/DATA MASK INPUT SETUP TIME, (tDS) 0.5ns (-26A/-265) 0.6ns (-202) 50 60 50 60 35 DATA/DATA MASK INPUT HOLD TIME, (tDH) 0.5ns (-26A/-265) 0.6ns (-202) 50 60 50 60 65ns (-26A/-265) 70ns (-202) 00 41 46 00 41 46 75ns (-26A/-265) 80ns (-202) 4B 50 4B 50 tCK = (MAX) = 13.0ns 34 34 0.5ns (-26A/-265) 0.6ns (-202) 0.75ns (-26A/-265) 1.0ns (-202) 1-11 32 3C 75 A0 00 00 0B/CB* 3B/FB* D6/96* 2C 00 01-0B 32 3C 75 A0 00 00 EE 1E B9 2C 00 01-0B x x 1-9 0 01-09 00 01-09 00 x x x x 36-40 41 RESERVED MINIMUM ACTIVE/AUTO REFRESH TIME, (tRC) 42 MINIMUM AUTO REFRESH TO ACTIVE/ AUTO REFRESH COMMAND PERIOD, (tRFC) 43 MAXIMUM CYCLE TIME, (tCK (MAX)) 44 46-61 62 63 MAXIMUM DQS-DQ SKEW TIME, (tDQSQ) MAXIMUM READ DATA HOLD SKEW FACTOR, (tQHS) RESERVED SPD REVISION CHECKSUM FOR BYTES 0-62 64 65-71 72 73-90 91 92 93 94 95-98 99-127 MANUFACTURER'S JEDEC ID CODE MANUFACTURER'S JEDEC ID CODE (continued) MANUFACTURING LOCATION MODULE PART NUMBER (ASCII) PCB IDENTIFICATION CODE IDENTIFICATION CODE (continued) YEAR OF MANUFACTURE IN BCD WEEK OF MANUFACTURE IN BCD MODULE SERIAL NUMBER MANUFACTURER-SPECIFIC DATA (RSVD) 45 Release 0.0 -26A -265 -202 MICRON MT9VDDT3272 A0 B0 x x - - *Supports fast/concurrent auto precharge. Contact factory for additional information regarding this option. NOTE: 2. x = Variable Data. 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 32 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs SERIAL PRESENCE-DETECT MATRIX (Note: 1) BYTE 0 1 2 3 4 5 6 7 8 9 DESCRIPTION NUMBER OF SPD BYTES USED BY MICRON TOTAL NUMBER OF BYTES IN SPD DEVICE FUNDAMENTAL MEMORY TYPE NUMBER OF ROW ADDRESSES ON ASSEMBLY NUMBER OF COLUMN ADDRESSES ON ASSEMBLY NUMBER OF PHYSICAL BANKS ON DIMM MODULE DATA WIDTH MODULE DATA WIDTH (continued) MODULE VOLTAGE INTERFACE LEVELS (VDDQ) SDRAM CYCLE TIME, (tCK) (CAS LATENCY = 2.5) (Note:2) ENTRY (VERSION) 128 256 SDRAM DDR 12 or 13 10 2 72 0 SSTL 2.5V 7ns (-26A) 7.5ns (-265) 8ns (-202) MT18VDDT3272D (Hex) MT18VDDT6472D (Hex) 80 80 08 08 07 07 0C 0D 0A 0A 02 02 48 48 00 00 04 04 70 70 75 75 80 80 10 SDRAM ACCESS FROM CLOCK,(tAC) (CAS LATENCY = 2.5) (Note:2) 0.75ns (-26A/-265) 0.8ns (-202) 75 80 75 80 11 12 13 14 15 MODULE CONFIGURATION TYPE REFRESH RATE/TYPE SDRAM DEVICE WIDTH (PRIMARY SDRAM) ERROR-CHECKING SDRAM DATA WIDTH MINIMUM CLOCK DELAY, BACK-TO-BACK RANDOM COLUMN ACCESS ECC 7.8s or 15.6s/SELF x8 x8 1 clock 02 80 08 08 01 02 82 08 08 01 16 17 18 19 20 21 22 23 BURST LENGTHS SUPPORTED NUMBER OF BANKS ON SDRAM DEVICE CAS LATENCIES SUPPORTED CS LATENCY WE LATENCY SDRAM MODULE ATTRIBUTES SDRAM DEVICE ATTRIBUTES: GENERAL SDRAM CYCLE TIME, (tCK) (CAS LATENCY = 2)(Note:2) 2, 4, 8 4 2, 2.5 0 1 REGISTERED, PLL Fast / Concurrent A/P 7.5ns (-26A) 10ns (-265/-202) 0E 04 0C 01 02 26 00/C0* 75 A0 0E 04 0C 01 02 26 C0 75 A0 24 SDRAM ACCESS FROM CK , (tAC) (CAS LATENCY = 2)(Note:2) 0.75ns (-26A/-265) 0.8ns (-202) 75 80 75 80 25 SDRAM CYCLE TIME, (tCK) (CAS LATENCY = 1.5) N/A 00 00 26 SDRAM ACCESS FROM CK , (tAC) (CAS LATENCY = 1.5) N/A 00 00 27 28 29 30 MINIMUM ROW PRECHARGE TIME, (tRP) MINIMUM ROW ACTIVE TO ROW ACTIVE, (tRRD) MINIMUM RAS# TO CAS# DELAY, (tRCD) MINIMUM ACTIVE TO PRECHARGE TIME, (tRAS) (Note: 3) 20ns 15ns 20ns 45ns (-26A/-265) 40ns (-202) 50 3C 50 2D 28 50 3C 50 2D 28 31 MODULE BANK DENSITY 128MB or 256MB 20 40 *Supports fast/concurrent auto precharge. Contact factory for additional information regarding this option. NOTE: 1. "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW." 2. Device latencies used for SPD values. 3. The value of tRAS used for the -26A/-265 module is calculated from tRC - tRP. Actual device spec. value is 40ns. 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs SERIAL PRESENCE-DETECT MATRIX (continued) (Note: 2) BYTE 32 DESCRIPTION ADDRESS AND COMMAND SETUP TIME, (tIS) ENTRY (VERSION) 1.0ns (-26A/-265) 1.1ns (-202) 33 ADDRESS AND COMMAND HOLD TIME, (tIH) 1.0ns (-26A/-265) 1.1ns (-202) A0 B0 A0 B0 34 DATA/DATA MASK INPUT SETUP TIME, (tDS) 0.5ns (-26A/-265) 0.6ns (-202) 50 60 50 60 35 DATA/DATA MASK INPUT HOLD TIME, (tDH) 0.5ns (-26A/-265) 0.6ns (-202) 50 60 50 60 65ns (-26A/-265) 70ns (-202) 00 41 46 00 41 46 75ns (-26A/-265) 80ns (-202) 4B 50 4B 50 tCK (MAX) = 13.0ns 34 34 0.5ns (-26A/-265) 0.6ns (-202) .75ns (-26A/-265) 1.0ns (-202) 1-11 32 3C 75 A0 00 00 0C/CC* 3C/FC* D7/97* 2C 00 01-0B SH 3C 75 A0 00 00 EF 1F BA 2C 00 01-0B x x 1-9 0 01-09 00 01-09 00 x x x x 36-40 41 RESERVED MINIMUM ACTIVE/AUTO REFRESH TIME, (tRC) 42 MINIMUM AUTO REFRESH TO ACTIVE/ AUTO REFRESH COMMAND PERIOD, (tRFC) 43 MAXIMUM CYCLE TIME, (tCK (MAX)) 44 46-61 62 63 MAXIMUM DQS-DQ SKEW TIME, (tDQSQ) MAXIMUM READ DATA HOLD SKEW FACTOR, (tQHS) RESERVED SPD REVISION CHECKSUM FOR BYTES 0-62 64 65-71 72 73-90 91 92 93 94 95-98 99-127 MANUFACTURER'S JEDEC ID CODE MANUFACTURER'S JEDEC ID CODE (continued) MANUFACTURING LOCATION MODULE PART NUMBER (ASCII) PCB IDENTIFICATION CODE IDENTIFICATION CODE (continued) YEAR OF MANUFACTURE IN BCD WEEK OF MANUFACTURE IN BCD MODULE SERIAL NUMBER MANUFACTURER-SPECIFIC DATA (RSVD) 45 Release 0.0 (-26A) (-265) (-202) MICRON MT18VDDT3272D(Hex) MT18VDDT6472D (Hex) A0 A0 B0 B0 x x - - *Supports fast/concurrent auto precharge. Contact factory for additional information regarding this option. NOTE: 2. x = Variable Data. 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 34 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs STANDARD 184-PIN DIMM (SINGLE BANK) FRONT VIEW .125 (3.175) MAX 5.256 (133.50) 5.244 (133.20) U10 U1 U3 U5 U9 U7 1.705 (43.31) 1.695 (43.05) .079 (2.00) R (4X) U11 U13 U12 .700 (17.78) TYP. .098 (2.50) D (2X) .091 (2.30) TYP. .035 (0.90) R PIN 1 .050 (1.27) TYP. 2.55 (64.77) .091 (2.30) TYP. .040 (1.02) TYP. .394 (10.00) TYP. .250 (6.35) TYP. 1.95 (49.53) .054 (1.37) .046 (1.17) PIN 92 4.750 (120.65) BACK VIEW U15 U17 U19 PIN 184 U21 PIN 93 NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 35 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs STANDARD 184-PIN DIMM (DUAL BANK) FRONT VIEW .125 (3.175) MAX 5.256 (133.50) 5.244 (133.20) U10 U1 U2 U3 U4 U5 U6 U8 U7 U9 1.705 (43.31) 1.695 (43.05) .079 (2.00) R (4X) U11 U13 U12 .700 (17.78) TYP. .098 (2.50) D (2X) .091 (2.30) TYP. .035 (0.90) R PIN 1 .050 (1.27) TYP. 2.55 (64.77) .091 (2.30) TYP. .040 (1.02) TYP. .394 (10.00) TYP. .250 (6.35) TYP. 1.95 (49.53) .054 (1.37) .046 (1.17) PIN 92 4.750 (120.65) BACK VIEW U14 U15 U16 U17 U18 U19 U20 PIN 184 U21 U22 PIN 93 NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 36 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs LOW-PROFILE 184-PIN DIMM (SINGLE BANK) FRONT VIEW .125 (3.175) MAX 5.256 (133.50) 5.244 (133.20) .079 (2.00) R (4X) U11 U1 U5 U3 U7 U9 1.205 (30.61) 1.195 (30.35) U12 .700 (17.78) TYP. .098 (2.50) D (2X) .091 (2.30) TYP. .035 (0.90) R PIN 1 .050 (1.27) TYP. 2.55 (64.77) .091 (2.30) TYP. .040 (1.02) TYP. .394 (10.00) TYP. .250 (6.35) TYP. 1.95 (49.53) .054 (1.37) .046 (1.17) PIN 92 4.750 (120.65) BACK VIEW U13 U15 U17 U19 U21 U10 PIN 93 PIN 184 NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 37 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. 128MB, 256MB, 512MB (x72) 184-PIN REGISTERED DDR SDRAM DIMMs LOW-PROFILE 184-PIN DIMM (DUAL BANK) FRONT VIEW .125 (3.175) MAX 5.256 (133.50) 5.244 (133.20) .079 (2.00) R (4X) U11 U1 U2 U3 U4 U5 U6 U7 U8 U9 1.205 (30.61) 1.195 (30.35) U12 .700 (17.78) TYP. .098 (2.50) D (2X) .091 (2.30) TYP. .035 (0.90) R PIN 1 .050 (1.27) TYP. 2.55 (64.77) .091 (2.30) TYP. .040 (1.02) TYP. .394 (10.00) TYP. .250 (6.35) TYP. 1.95 (49.53) .054 (1.37) .046 (1.17) PIN 92 4.750 (120.65) BACK VIEW U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U10 PIN 93 PIN 184 NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark and the Micron logo and M logos are trademarks of Micron Technology, Inc. 16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM DD9_18C16_32_64X72G_DG_B.p65 - Pub.1/02 38 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.