MT9VDDT1672G-202 - Micron - Datasheet.Directory

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT9VDDT1672, MT18VDDT3272D,

MT9VDDT3272, MT18VDDT6472D

For the latest data sheet, please refer to the Micron Web site:

www.micron.com/datasheets

FEATURES

• 184-pin, dual in-line memory modules (DIMM)

• Fast data transfer rates, PC2100 or PC1600

• ECC-optimized pinout

• Registered inputs with one-clock delay

• Phase-lock loop (PLL) clock driver to reduce

• Utilizes 200 MT/s and 266 MT/s DDR SDRAM

components

• 128MB (16 Meg x 72), 256MB (32 Meg x 72), and

512MB (64 Meg x 72)

•VDD= VDDQ= +2.5V ±0.2V

•VDDSPD = +2.2V to +5.5V

• 2.5V I/O (SSTL_2 compatible)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

• Internal, pipelined double data rate (DDR)

architecture; two data accesses per clock cycle

• Bidirectional data strobe (DQS) transmitted/

received with data, i.e., source-synchronous data

capture

• Differential clock inputs (CK0 and CK0#)

• Four internal device banks for concurrent

operation

• Selectable burst lengths: 2, 4, or 8

• Auto precharge option

• Auto Refresh and Self Refresh Modes

• 15.6µs (MT9VDDT1672, MT18VDDT3272D);

7.8125µs (MT9VDDT3272, MT18VDDT6472D)

maximum average periodic refresh interval

• Serial Presence Detect (SPD) with EEPROM

• Selectable READ CAS latency

184-Pin DIMM

MO-206

OPTIONS MARKING

• Package

Dual-Bank Module D

184-pin DIMM (gold) G

• Standard or Low Profile PCB Contact Factory

• Gold-plated edge contacts

• Memory Clock/Data Frequency/CAS Latency*

7.5ns/266 MT/s/CL = 2 -26A

7.5ns/266 MT/s/CL = 2.5 -265

10ns/200 MT/s/CL = 2 -202

* CL = Device CAS (READ) Latency; add one clock cycle for registered

DIMMs due to the input register.

DDR SDRAM

DIMM

STANDARD PCB

LOW PROFILE PCB

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

PART NUMBERS AND TIMING PARAMETERS

PART NUMBER PART MODULE CONFIGURATION TRANSFER MEMORY CLOCK LATENCY

MARKING DENSITY RATE / DATA FREQUENCY (CL - tRCD - tRP)*

MT9VDDT1672G-26A__ -26A 128MB 16 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3

MT9VDDT1672G-265__ -265 128MB 16 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3

MT9VDDT1672G-202__ -202 128MB 16 Meg x 72 1.6 GB/s 10ns/200 MT/s 2-2-2

MT9VDDT3272G-26A__ -26A 256MB 32 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3

MT9VDDT3272G-265__ -265 256MB 32 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3

MT9VDDT3272G-202__ -202 256MB 32 Meg x 72 1.6 GB/s 10ns/200 MT/s 2-2-2

MT18VDDT3272DG-26A__ -26A 256MB 32 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3

MT18VDDT3272DG-265__ -265 256MB 32 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3

MT18VDDT3272DG-202__ -202 256MB 32 Meg x 72 1.6 GB/s 10ns/200 MT/s 2-2-2

MT18VDDT6472DG-26A__ -26A 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3

MT18VDDT6472DG-265__ -265 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3

MT18VDDT6472DG-202__ -202 512MB 64 Meg x 72 1.6 GB/s 10ns/200 MT/s 2-2-2

NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for

current revision codes. Example: MT18VDDT3272DG-265A1

ADDRESS TABLE

MT9VDDT1672 MT9VDDT3272 MT18VDDT3272D MT18VDDT6472D

Refresh Count 4K 8K 4K 8K

Row Addressing 4K (A0–A11) 8K (A0–A12) 4K (A0–A11) 8K (A0–A12)

Device Bank Addressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)

Base Device Configuration 16 Meg x 8 32 Meg x 8 16 Meg x 8 32 Meg x 8

Column Addressing 1K (A0–A9) 1K (A0–A9) 1K (A0–A9) 1K (A0–A9)

Module Bank Addressing 1 (S0#) 1 (S0#) 2 (S0#, S1#) 2 (S0#, S1#)

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

PIN LOCATIONS (184-Pin DIMM)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

1VREF 24 DQ17 47 DQS8 70 VDD

2 DQ0 25 DQS2 48 A0 71 N C

3VSS 26 VSS 49 CB2 72 DQ48

4 DQ1 27 A9 50 VSS 73 DQ49

5 DQS0 28 DQ18 51 CB3 74 VSS

6 DQ2 29 A7 52 BA 1 75 DNU

7VDD 30 VDDQ53 DQ32 76 DNU

8 DQ3 31 DQ19 54 VDDQ77 VDDQ

9NC32 A5 55 DQ33 78 DQS6

10 RESET# 33 DQ24 56 DQS4 79 DQ50

11 VSS 34 V SS 57 DQ34 80 DQ51

12 DQ8 35 DQ25 58 V SS 81 VSS

13 DQ9 36 DQS3 59 BA0 82 N C

14 DQS1 37 A4 60 DQ35 83 DQ56

15 VDDQ38 VDD 61 DQ40 84 DQ57

16 DNU 39 DQ26 62 VDDQ85 VDD

17 DNU 40 DQ27 63 WE# 86 DQS7

18 VSS 41 A2 64 DQ41 87 DQ58

19 DQ10 42 VSS 65 CAS# 88 DQ59

20 DQ11 43 A1 66 VSS 89 V SS

21 CKE0 44 CB0 67 DQS5 90 NC

22 VDDQ 45 CB1 68 DQ42 91 SDA

23 DQ16 46 VDD 69 DQ43 92 SCL

PIN ASSIGNMENT (184-Pin DIMM FRONT)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

93 VSS 116 VSS 139 VSS 162 DQ47

94 DQ4 117 DQ21 140 DQS17/DM8 163 N C

95 DQ5 118 A11 141 A10 164 VDDQ

96 VDDQ 119 DQS11/ DM2 142 CB6 165 DQ52

97 DQS9/DM0 120 VDD 143 VDDQ166 DQ53

98 DQ6 121 DQ22 144 CB7 167

99 DQ7 122 A8 145 VSS 168 VDD

100 VSS 123 DQ23 146 DQ36 169 DQS15/DM6

101 N C 124 V SS 147 DQ37 170 DQ54

102 N C 125 A6 148 VDD 171 DQ55

103 NC 126 DQ28 149 DQS13/DM4 172 VDDQ

104 VDDQ127 DQ29 150 DQ38 173 N C

105 DQ12 128 VDDQ151 DQ39 174 DQ60

106 DQ13 129 DQS12/ DM3 152 VSS 175 DQ61

107 DQS10/ DM1 130 A3 153 DQ44 176 VSS

108 VDD 131 DQ30 154 RAS# 177 DQS16/DM7

109 DQ14 132 VSS 155 DQ45 178 DQ62

110 DQ15 133 DQ31 156 VDDQ179 DQ63

111 NC/CKE1* 134 CB4 157 S0# 180 VDDQ

112 VDDQ 135 CB5 158 NC/S1#* 181 SA0

113 N C 136 VDDQ 159 DQS14/DM5 182 SA1

114 DQ20 137 CK0 160 VSS 183 SA2

115 NC/A12* 138 CK0# 161 DQ46 184 VDDSPD

PIN ASSIGNMENT (184-Pin DIMM BACK)

*Pins 111, 115, and 158 are no connect (NC) for MT9VDDT1672 and MT18VDDT3272. For MT9VDDT3272D and MT18VDDT6472D, pin 111

is CKE1, pin 115 is address input A12, and pin 158 is S1#.

PIN 1

U1 U2 U3 U4 U5 U6 U7 U8 U9

U14 U15 U16 U17 U18 U19 U20 U21 U22

PIN 52 PIN 53 PIN 92

BACK VIEW

Indicates a VDD or VDDQ pin Indicates a VSS pin

U10

PIN 1

U1 U5 U7 U9

U15 U17 U19 U21

PIN 52 PIN 53 PIN 92

BACK VIEW

FRONT VIEW

Indicates a VDD or VDDQ pin Indicates a VSS pin

U10

U11 U12 U13 U11 U12

Single Bank FRONT VIEW Dual Bank

Standard Standard

U13

PIN 93

PIN 144

PIN 145

PIN 184 PIN 93

PIN 144

PIN 145

PIN 184

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

PIN 1 PIN 52 PIN 53 PIN 92

U1 U2 U3 U4

U11

U12

U5 U6 U7 U8 U9

U10

U14 U15 U17 U18U16

U13

U19 U20 U21 U22

PIN 1 PIN 52 PIN 53 PIN 92

U1 U3

U11

U12

U5 U7 U9

U10

U15 U17

U13

U19 U21

Indicates a V

or V

Q pin Indicates a V

pin Indicates a V

or V

Q pin Indicates a V

FRONT VIEW

Single Bank

FRONT VIEW

Dual Bank

BACK VIEW

Low Profile Low Profile

PIN 93

PIN 144

PIN 145

PIN 184 PIN 93

PIN 144

PIN 145

PIN 184

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

1VREF 24 DQ17 47 DQS8 70 VDD

2 DQ0 25 DQS2 48 A0 71 N C

3VSS 26 VSS 49 CB2 72 DQ48

4 DQ1 27 A9 50 VSS 73 DQ49

5 DQS0 28 DQ18 51 CB3 74 VSS

6 DQ2 29 A7 52 BA 1 75 DNU

7VDD 30 VDDQ53 DQ32 76 DNU

8 DQ3 31 DQ19 54 VDDQ77 VDDQ

9NC32 A5 55 DQ33 78 DQS6

10 RESET# 33 DQ24 56 DQS4 79 DQ50

11 VSS 34 V SS 57 DQ34 80 DQ51

12 DQ8 35 DQ25 58 V SS 81 VSS

13 DQ9 36 DQS3 59 BA0 82 N C

14 DQS1 37 A4 60 DQ35 83 DQ56

15 VDDQ38 VDD 61 DQ40 84 DQ57

16 DNU 39 DQ26 62 VDDQ85 VDD

17 DNU 40 DQ27 63 WE# 86 DQS7

18 VSS 41 A2 64 DQ41 87 DQ58

19 DQ10 42 VSS 65 CAS# 88 DQ59

20 DQ11 43 A1 66 VSS 89 V SS

21 CKE0 44 CB0 67 DQS5 90 NC

22 VDDQ 45 CB1 68 DQ42 91 SDA

23 DQ16 46 VDD 69 DQ43 92 SCL

PIN ASSIGNMENT (184-Pin DIMM FRONT)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

93 VSS 116 VSS 139 VSS 162 DQ47

94 DQ4 117 DQ21 140 DQS17/DM8 163 N C

95 DQ5 118 A11 141 A10 164 VDDQ

96 VDDQ 119 DQS11/ DM2 142 CB6 165 DQ52

97 DQS9/DM0 120 VDD 143 VDDQ166 DQ53

98 DQ6 121 DQ22 144 CB7 167

99 DQ7 122 A8 145 VSS 168 VDD

100 VSS 123 DQ23 146 DQ36 169 DQS15/DM6

101 N C 124 V SS 147 DQ37 170 DQ54

102 N C 125 A6 148 VDD 171 DQ55

103 NC 126 DQ28 149 DQS13/DM4 172 VDDQ

104 VDDQ127 DQ29 150 DQ38 173 N C

105 DQ12 128 VDDQ151 DQ39 174 DQ60

106 DQ13 129 DQS12/ DM3 152 VSS 175 DQ61

107 DQS10/ DM1 130 A3 153 DQ44 176 VSS

108 VDD 131 DQ30 154 RAS# 177 DQS16/DM7

109 DQ14 132 VSS 155 DQ45 178 DQ62

110 DQ15 133 DQ31 156 VDDQ179 DQ63

111 NC/CKE1* 134 CB4 157 S0# 180 VDDQ

112 VDDQ 135 CB5 158 NC/S1#* 181 SA0

113 N C 136 VDDQ 159 DQS14/DM5 182 SA1

114 DQ20 137 CK0 160 VSS 183 SA2

115 NC/A12* 138 CK0# 161 DQ46 184 VDDSPD

PIN ASSIGNMENT (184-Pin DIMM BACK)

*Pins 111, 115, and 158 are no connect (NC) for MT9VDDT1672 and MT18VDDT3272. For MT9VDDT3272D and MT18VDDT6472D, pin 111

is CKE1, pin 115 is address input A12, and pin 158 is S1#.

PIN LOCATIONS (184-Pin DIMM)

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

PIN DESCRIPTIONS

PIN NUMBERS SYMBOL TYPE DESCRIPTION

1VREF Input SSTL_2 reference voltage.

63, 65, 154 WE#, CAS#, Input Command Inputs: RAS#, CAS#, and WE# (along with

RAS# S0#) define the command being entered.

137, 138 CK0, CK0# Input Clock: CK0 and CK0# are differential clock inputs. All

address and control input signals are sampled on the

crossing of the positive edge of CK0 and negative

edge of CK0#. Output data (DQs and DQS) is

referenced to the crossings of CK0 and CK0#.

21, 111 CKE0 Input

Clock Enable: CKE0 or CKE1 HIGH activates and CKE0 or

(Single Bank)

CKE1 LOW deactivates the internal clock, input buffers

CKE0 - CKE1 and output drivers. Taking CKE0 or CKE1 LOW provides

(Dual Bank) PRECHARGE POWER-DOWN and SELF REFRESH opera-

tions (all device banks idle), or ACTIVE POWER-DOWN

(row ACTIVE in any device bank). CKE0 or CKE1 is

synchronous for POWER-DOWN entry and exit, and for

SELF REFRESH entry. CKE0 or CKE1 is asynchronous for

SELF REFRESH exit and for disabling the outputs. CKE0 or

CKE1 must be maintained HIGH throughout read and

write accesses. Input buffers (excluding CK0, CK0# and

CKE0 or CKE1) are disabled during POWER-DOWN. Input

buffers (excluding CKE0 or CKE1) are disabled during SELF

REFRESH. CKE0 or CKE1 is an SSTL_2 input but will detect

an LVCMOS LOW level after V

is applied.

157, 158 S0# (Single Bank) Input Chip Select: S0#, S1# enable (registered LOW) and

S0# - S1# disable (registered HIGH) the command decoder. All

(Dual Bank) commands are masked when S0#, S1# are registered

HIGH. S0#, S1# are considered part of the command

code.

52, 59 BA0, BA1 Input Bank Address: BA0 and BA1 define to which device

bank an ACTIVE, READ, WRITE, or PRECHARGE

command is being applied.

27, 29, 32, 37, 41, 43, A0-A11 Input

Address Inputs: Provide the row address for ACTIVE

48, 115 (A12), 118, 122, MT9VDDT1672

commands, and the column address and auto precharge

125, 130, 141 MT18VDDT3272

bit (A10) for READ/WRITE commands, to select one

A0-A12

location out of the memory array in the respective device

MT9VDDT3272 bank. A10 sampled during a PRECHARGE command

MT18VDDT6472 determines whether the PRECHARGE applies to one

device bank (A10 LOW, device bank selected by BA0,

BA1) or all device banks (A10 HIGH). The address inputs

also provide the op-code during a MODE REGISTER SET

command. BA0 and BA1 define which mode register

(mode register or extended mode register) is loaded

during the LOAD MODE REGISTER command.

91 SDA Input/ Serial Presence-Detect Data: SDA is a bidirectional pin

Output used to transfer addresses and data into and out of

the presence-detect portion of the module.

NOTE: Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables for pin number and symbol information.

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

PIN DESCRIPTIONS (continued)

PIN NUMBERS SYMBOL TYPE DESCRIPTION

92 SCL Input Serial Clock for Presence-Detect: SCL is used to

synchronize the presence-detect data transfer to and

from the module.

181, 182, 183 SA0-SA2 Input Presence-Detect Address Inputs: These pins are used

to configure the presence-detect device.

10 RESET# Input Asynchronously forces all register outputs LOW when

RESET# is LOW. This signal can be used during power-

up to ensure CKE0/1 are LOW and SDRAM DQs are

High-Z.

44, 45, 49, 51, 134, 135, CB0-CB7 Input/ Data I/Os: Check bits.

142, 144 Output

5, 14, 25, 36, 47, 56, 67, DQS0-DQS17 Input/

Data Strobe: DQS0-DQS8, Output with READ data, input

78, 86, 97, 107, 119, 129, Output

with WRITE data. DQS is edge-aligned with READ data,

140, 149, 159, 169, 177

centered

in WRITE

data. Used to capture data. Data

Mask: DQS9-DQS17 function as DM0-DM8 to mask

WRITE data when when HIGH.

2, 4, 6, 8, 12, 13, 19, 20, DQ0-DQ63 Input/ Data I/Os: Data bus.

23, 24, 28, 31, 33, 35, 39, Output

40, 53, 55, 57, 60, 61, 64,

68, 69, 72, 73, 79, 80, 83,

84, 87, 88, 94, 95, 98, 99,

105, 106, 109, 110, 114,

117, 121, 123, 126, 127,

131, 133, 146, 147, 150,

151, 153, 155, 161, 162,

165, 166, 170, 171, 174,

175, 178, 179

15, 22, 30, 54, 62, 77, 96, VDDQ Supply DQ Power Supply: +2.5V +0.2V.

104, 112, 128, 136, 143,

156, 164, 172, 180

7, 38, 46, 70, 85, 108, VDD Supply Power Supply: +2.5V +0.2V.

120, 148, 168

3, 11, 18, 26, 34, 42, 50, VSS Supply Ground.

58, 66, 74, 81, 89, 93,

100, 116, 124, 132, 139,

145, 152, 160, 176

184 VDDSPD Supply Serial EEPROM positive power supply.

9, 71, 82, 90, 101, 102, NC —No Connect: These pins should be left unconnected.

103, 113, 115

(MT9VDDT1672 and

MT18VDDT3272),

163, 167, 173

16, 17, 75, 76 DNU –Do Not Use: These pins are not connected on this

module but are assigned pins on other modules in

this product family.

NOTE: Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables for pin number and symbol information.

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

FUNCTIONAL BLOCK DIAGRAM

MT9VDDT1672 (128MB), MT9VDDT3272 (256 MB)

NOTE: All resistor values are 22 ohms unless otherwise specified.

SA0

SERIAL PD

SDA

SA1

SA2

S0#

BA0, BA1

A0-A11/12

RAS#

RS0#

RBA0, RBA1: DDR SDRAMS

RA0-RA11/12: DDR SDRAMS

RRAS#: DDR SDRAMS

RCAS#: DDR SDRAMS

RCKE0: DDR SDRAMS

RWE#: DDR SDRAMS

RESET#

CAS#

CKE0

WE#

CK#

REF

DDR SDRAMS

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

U17

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

U19

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

U21

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DM CS# DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM0

RS0#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

PLL

DDR SDRAM

SCL

DM CS# DQS

DQS0

DM4

DQS4

DM1

DQS1

DM5

DQS5

DM2

DQS2

DM6

DQS6

DM CS# DQS

U15

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM CS# DQS

DM CS# DQS DM CS# DQS

DM CS# DQS

DM3

DQS3

DM7

DQS7

DM8

DQS8

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

DDQ

DDR SDRAMS

CK0

CK0#

120 U12

U10

U11, U13

MT46V16M8TG DDR SDRAMs for MT9VDDT1672

MT46V32M8TG DDR SDRAMs for MT9VDDT3272

SPD

DDSPD

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

FUNCTIONAL BLOCK DIAGRAM

MT18VDDT3272D (256MB), MT18VDDT6472D (512 MB)

SA0

SERIAL PD

SDA

SA1

SA2

S0#

S1#

BA0, BA1

A0-A11/12

RAS#

RS0#, Bank 0

RS1#, Bank 1

RBA0, RBA1: DDR SDRAMS

RA0-RA11/12: DDR SDRAMS

RRAS#: DDR SDRAMS

RCAS#: DDR SDRAMS

RCKE0: DDR SDRAMS, Bank 0

RCKE1: DDR SDRAMS, Bank 1

RWE#: DDR SDRAMS

RESET#

CAS#

CKE0

CKE1

WE#

CK# V

REF

DDR SDRAMS

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

U17

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

U19

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

U21

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DM CS# DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM0

RS0#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

PLL

DDR SDRAM X 2

SCL

U22

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U20

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

RS1#

DM CS# DQS

DM CS# DQS DM CS# DQS

DM CS# DQS

DQS0

DM4

DQS4

DM1

DQS1

DM5

DQS5

U16

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM CS# DQS

DM2

DQS2

DM6

DQS6

DM CS# DQS

U15

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U18

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM CS# DQS

DM CS# DQS DM CS# DQS

DM CS# DQS

DM3

DQS3

DM7

DQS7

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM CS# DQS

U14

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM CS# DQS

DM8

DQS8

U18

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM CS# DQS

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

DDQ

DDR SDRAMS

CK0

CK0#

120

U11, U13

U10

U12

NOTE: All resistor values are 22 ohms unless otherwise specified. MT46V16M8TG DDR SDRAMs for MT18VDDT3272D

MT46V32M8TG DDR SDRAMs for MT18VDDT6472D

SPD

DDSPD

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

GENERAL DESCRIPTION

The MT9VDDT1672, MT9VDDT3272,

MT18VDDT3272D, and MT18VDDT6472D are high-

speed CMOS, dynamic random-access, 128MB, 256MB,

and 512MB registered memory modules organized in a

x72 (ECC) configuration. These modules use inter-

nally configured quad-bank DDR SDRAM devices.

These DDR SDRAM modules use a double data rate

architecture to achieve high-speed operation. The

double data rate architecture is essentially a 2n-

prefetch architecture with an interface designed to

transfer two data words per clock cycle at the I/O pins.

A single read or write access for the DDR SDRAM mod-

ule effectively consists of a single 2n-bit wide, one-

clock-cycle data transfer at the internal DRAM core and

two corresponding n-bit wide, one-half-clock-cycle

data transfers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted ex-

ternally, along with data, for use in data capture at the

receiver. DQS is an intermittent strobe transmitted by

the DDR SDRAM during READs and by the memory

controller during WRITEs. DQS is edge-aligned with

data for READs and center-aligned with data for

WRITEs.

These DDR SDRAM modules operate from a differ-

ential clock (CK0 and CK0#); the crossing of CK0 going

HIGH and CK0# going LOW will be referred to as the

positive edge of CK0. Commands (address and control

signals) are registered at every positive edge of CK0.

Input data is registered on both edges of DQS, and

output data is referenced to both edges of DQS, as well

as to both edges of CK0.

Read and write accesses to the DDR SDRAM mod-

ules are burst oriented; accesses start at a selected

location and continue for a programmed number of

locations in a programmed sequence. Accesses begin

with the registration of an ACTIVE command, which is

then followed by a READ or WRITE command. The

address bits registered coincident with the ACTIVE

command are used to select the device bank and row to

be accessed (BA0, BA1 select devices bank; A0-A11 se-

lect device row for MT9VDDT1672 and

MT18VDDT3272D; A0-A12 select device row for

MT9VDDT3272 and MT18VDDT6472D). The address

bits registered coincident with the READ or WRITE com-

mand are used to select the device bank and the start-

ing device column location for the burst access.

These DDR SDRAM modules provide for program-

mable READ or WRITE burst lengths of 2, 4, or 8 loca-

tions. An auto precharge function may be enabled to

provide a self-timed row precharge that is initiated at

the end of the burst access.

As with standard SDR SDRAM modules, the

pipelined, multibank architecture of DDR SDRAM

modules allows for concurrent operation, thereby pro-

viding high effective bandwidth by hiding row

precharge and activation time.

An auto refresh mode is provided, along with a

power-saving power-down mode. All inputs are com-

patible with the JEDEC Standard for SSTL_2. All out-

puts are SSTL_2, Class II compatible. For more infor-

mation regarding DDR SDRAM operation, refer to the

128Mb and 256Mb DDR SDRAM data sheet.

PLL AND REGISTER OPERATION

The DDR SDRAM module is operated in registered

mode where the control/address input signals are

latched in the register on one rising clock edge and sent

to the DDR SDRAM devices on the following rising clock

edge (data access is delayed by one clock). A phase-lock

loop (PLL) on the module is used to redrive the differen-

tial clock signals CK0 and CK0# to the DDR SDRAM de-

vices to minimize system clock loading.

SERIAL PRESENCE-DETECT OPERATION

These DDR SDRAM modules incorporate serial pres-

ence-detect (SPD). The SPD function is implemented

using a 2,048-bit EEPROM. This nonvolatile storage

device contains 256 bytes. The first 128 bytes can be

programmed by Micron to identify the module type

and various SDRAM organizations and timing param-

eters. The remaining 128 bytes of storage are available

for use by the customer. System READ/WRITE opera-

tions between the master (system logic) and the slave

EEPROM device (DIMM) occur via a standard IIC bus

using the DIMM’s SCL (clock) and SDA (data) signals,

together with SA(2:0), which provide eight unique

DIMM/EEPROM addresses.

MODE REGISTER

The mode register is used to define the specific mode

of operation of the DDR SDRAM. This definition in-

cludes the selection of a burst length, a burst type, a

CAS latency and an operating mode, as shown in the

Mode Register Diagram. The mode register is pro-

grammed via the MODE REGISTER SET command (with

BA0 = 0 and BA1 = 0) and will retain the stored informa-

tion until it is programmed again or the device loses

power (except for bit A8, which is self-clearing).

Reprogramming the mode register will not alter the

contents of the memory, provided it is performed cor-

rectly. The mode register must be loaded (reloaded)

when all device banks are idle and no bursts are in

progress, and the controller must wait the specified time

before initiating the subsequent operation. Violating

either of these requirements will result in unspecified

operation.

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

M3 = 0

Reserved

M3 = 1

Reserved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

Valid

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

2.5

Reserved

Burst Length

Burst LengthCAS Latency BT0*

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Mode Register (Mx)

Address Bus

976543

8210

M6-M0

M8 M7

Operating Mode

A10

A12 A11

BA0

BA1

* M14 and M13 (BA0 and BA1)

must be “0, 0” to select the

base mode register (vs. the

extended mode register).

M9M10M12 M11

Mode Register Definition

Diagram Burst Definition

Table

Burst Starting Column Order of Accesses Within a Burst

Length Address Type = Sequential Type = Interleaved

20 0-1 0-1

1 1-0 1-0

A1 A0

0 0 0-1-2-3 0-1-2-3

40 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1

1 1 3-0-1-2 3-2-1-0

A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

80 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

MT9VDDT3272, MT18VDDT6472D MODULE ADDRESS BUS

Burst LengthCAS Latency BT0*0*

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Mode Register (Mx)

Address Bus

976543

8210

Operating Mode

A10

A11

BA0

BA1

* M13 and M12 (BA0 and BA1)

must be “0, 0” to select the

base mode register (vs. the

extended mode register).

MT9VDDT1672, MT18VDDT3272D MODULE ADDRESS BUS

NOTE: 1. For a burst length of two, A1-Ai select the two-

data-element block; A0 selects the first access

within the block.

2. For a burst length of four, A2-Ai select the four-

data-element block; A0-A1 select the first access

within the block.

3. For a burst length of eight, A3-Ai select the eight-

data-element block; A0-A2 select the first access

within the block.

4. Whenever a boundary of the block is reached

within a given sequence above, the following

access wraps within the block.

i = 11 for MT9VDDT1672, MT18VDDT3272D, or 12 for

MT9VDDT3272, MT18VDDT6472D

Mode register bits A0-A2 specify the burst length,

A3 specifies the type of burst (sequential or inter-

leaved), A4-A6 specify the CAS latency, and A7-A11

(MT9VDDT1672 and MT18VDDT3272D) or A7-A12

(MT9VDDT3272 and MT18VDDT6472D) specify the

operating mode.

Burst Length

Read and write accesses to the DDR SDRAM are

burst oriented, with the burst length being program-

mable, as shown in Mode Register Diagram. The burst

length determines the maximum number of column

locations that can be accessed for a given READ or

WRITE command. Burst lengths of 2, 4, or 8 locations

are available for both the sequential and the inter-

leaved burst types.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may

result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively se-

lected. All accesses for that burst take place within this

block, meaning that the burst will wrap within the block

if a boundary is reached. The block is uniquely se-

lected by A1-An when the burst length is set to two, by

A2-Ai when the burst length is set to four and by A3-Ai

when the burst length is set to eight (where Ai is the

most significant column address bit for a given con-

figuration). The remaining (least significant) address

bit(s) is (are) used to select the starting location within

the block. The programmed burst length applies to

both READ and WRITE bursts.

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

CK#

COMMAND

DQS

CL = 2

READ NOP NOP NOP

Burst Length = 4 in the cases shown

Shown with nominal tAC and nominal tDSDQ

CK#

COMMAND

DQS

CL = 2.5

T0 T1 T2 T2n T3 T3n

DON’T CARETRANSITIONING DATA

CAS Latency

Diagram

ALLOWABLE OPERATING

CLOCK FREQUENCY (MHz)

SPEED CL = 2 CL = 2.5

-26A 75 ≤ f ≤ 133 75 ≤ f ≤133

-265 75 ≤ f ≤ 100 75 ≤ f ≤133

-202 75 ≤ f ≤ 100 75 ≤ f ≤125

CAS LATENCY (CL)

TABLE

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to

as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type and the start-

ing column address, as shown in Burst Definition Table.

Read Latency

The READ latency is the delay, in clock cycles, be-

tween the registration of a READ command and the

availability of the first bit of output data. The latency

can be set to 2 or 2.5 clocks, as shown in CAS Latency

Diagram.

If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available

nominally coincident with clock edge n + m. The CAS

Latency Table indicates the operating frequencies at

which each CAS latency setting can be used.

Reserved states should not be used as unknown

operation or incompatibility with future versions may

result.

Operating Mode

The normal operating mode is selected by issuing a

MODE REGISTER SET command with bits A7-A11 (for

the 256MB), or A7-A12 (for the 512MB module) each set

to zero, and bits A0-A6 set to the desired values. A DLL

reset is initiated by issuing a MODE REGISTER SET

command with bits A7 and A9-A11 (MT9VDDT1672 and

MT18VDDT3272D), or A7 and A9-A12 (MT9VDDT3272

and MT18VDDT6472D) each set to zero, bit A8 set to

one, and bits A0-A6 set to the desired values. Although

not required by the Micron device, JEDEC specifica-

tions recommend when a LOAD MODE REGISTER com-

mand is issued to reset the DLL, it should always be

followed by a LOAD MODE REGISTER command to se-

lect normal operating mode.

All other combinations of values for A7-A11, or A7-

A12 are reserved for future use and/or test modes. Test

modes and reserved states should not be used because

unknown operation or incompatibility with future ver-

sions may result.

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

Operating Mode

Reserved

–

Valid

–

DLL

Enable

Disable

DLL

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Extended Mode

Address Bus

976543

8210

Drive Strength

Normal

QFC# Function

Disabled

E1,

Operating Mode

A10

A11A12

BA1 BA0

1314

NOTE: 1. E13 and E12 (128MB module), or E14 and E13 (256MB Module)

(BA0 and BA1) must be “1, 0” to select the Extended

Mode Register (vs. the base Mode Register).

2. The QFC# option is not supported.

E2,E3E4

–

E6 E5

E7E8E9

–

E10E11

–

E12

QFC#

DLL

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Extended Mode

Address Bus

976543

8210

Operating Mode

A10

A11

BA1 BA0

DSQFC

MT9VDDT1672 and

MT18VDDT3272D

MT9VDDT3272 and

MT18VDDT6472D

Extended Mode Register Definition

Diagram

EXTENDED MODE REGISTER

The extended mode register controls functions be-

yond those controlled by the mode register; these addi-

tional functions are DLL enable/disable, output drive

strength, and QFC#. These functions are controlled via

the bits shown in the Extended Mode Register Defini-

tion Diagram. The extended mode register is pro-

grammed via the LOAD MODE REGISTER command to

the mode register (with BA0 = 1 and BA1 = 0) and will

retain the stored information until it is programmed

again or the device loses power. The enabling of the DLL

should always be followed by a LOAD MODE REGISTER

command to the mode register (BA0/BA1 both LOW) to

reset the DLL.

The extended mode register must be loaded when

all device banks are idle and no bursts are in progress,

and the controller must wait the specified time before

initiating any subsequent operation. Violating either

of these requirements could result in unspecified op-

eration.

Output Drive Strength

The normal full drive strength for all outputs are

specified to be SSTL2, Class II.

For detailed information on output drive strength

option, refer to 128Mb and 256Mb DDR SDRAM data

sheets.

DLL Enable/Disable

The DLL must be enabled for normal operation.

DLL enable is required during power-up initialization

and upon returning to normal operation after having

disabled the DLL for the purpose of debug or evalua-

tion. (When the device exits self refresh mode, the DLL

is enabled automatically.) Any time the DLL is en-

abled, 200 clock cycles must occur before a READ com-

mand can be issued.

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.

2. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0

= 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A11 provide the op-code

to be written to the selected mode register.

3. BA0-BA1 provide device bank address and A0-A11 (MT9VDDT1672, MT18VDDT3272D), or A0-A12 (MT9VDDT3272,

MT18VDDT6472D) provide row address.

4. BA0-BA1 provide device bank address; A0-A9, 11 provide column address; A10 HIGH enables the auto precharge feature

(nonpersistent), and A10 LOW disables the auto precharge feature.

5. A10 LOW: BA0-BA1 determine which device bank is precharged.

A10 HIGH: all device banks are precharged and BA0-BA1 are “Don’t Care.”

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ

bursts with auto precharge enabled and for WRITE bursts.

9. DESELECT and NOP are functionally interchangeable.

10. Used to mask write data; provided coincident with the corresponding data.

TRUTH TABLE 1 – COMMANDS

(Note: 1)

NAME (FUNCTION) CS# RAS# CAS# WE# ADDR NOTES

DESELECT (NOP) H X X X X 9

NO OPERATION (NOP) L H H H X 9

ACTIVE (Select device bank and activate row) L L H H Bank/Row 3

READ (Select device bank and column, and start READ burst) L H L H Bank/Col 4

WRITE (Select device bank and column, and start WRITE burst) L H L L Bank/Col 4

BURST TERMINATE L H H L X 8

PRECHARGE (Deactivate row in device bank or banks) L L H L Code 5

AUTO REFRESH or SELF REFRESH L L L H X 6, 7

(Enter self refresh mode)

LOAD MODE REGISTER LLLLOp-Code 2

TRUTH TABLE 1A – DM OPERATION

(Note: 10)

NAME (FUNCTION) DM DQs

Write Enable L Valid

Write Inhibit HX

Commands

Truth Table 1 provides a general reference of avail-

able commands. For a more detailed description of

commands and operations, refer to the Micron 128Mb

or 256Mb DDR SDRAM data sheet.

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

ABSOLUTE MAXIMUM RATINGS*

Voltage on VDD Supply

Relative to VSS .............................................. -1V to +3.6V

Voltage on VDDQ Supply

Relative to VSS .............................................. -1V to +3.6V

Voltage on VREF and Inputs

Relative to VSS .............................................. -1V to +3.6V

Voltage on I/O Pins

Relative to VSS ................................. -0.5V to VDDQ +0.5V

Operating Temperature, TA (ambient) ... 0°C to +70°C

Storage Temperature (plastic) ............ -55°C to +150°C

Power Dissipation (Single Module Bank) ................ 9W

(Dual Module Bank) ................ 18W

Short Circuit Output Current................................. 50mA

*Stresses greater than those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only, and functional

operation of the device at these or any other conditions

above those indicated in the operational sections of

this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may

affect reliability.

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(ALL MODULES)

(Notes: 1–5, 14; notes appear following parameter tables)

(0°C ≤ TA ≤ +70°C; VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

Supply Voltage VDD 2.3 2.7 V 32, 36

I/O Supply Voltage VDDQ 2.3 2.7 V 32, 36,

I/O Reference Voltage VREF 0.49 x VDDQ 0.51 x VDDQ V 6, 39

I/O Termination Voltage (system) VTT VREF - 0.04 VREF + 0.04 V 7, 39

Input High (Logic 1) Voltage VIH(DC)VREF + 0.15 VDD + 0.3 V 25

Input Low (Logic 0) Voltage VIL(DC) -0.3 VREF - 0.15 V 25

INPUT LEAKAGE CURRENT (All Modules)

Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 1.35V II-5 5 µA 48

(All other pins not under test = 0V)

OUTPUT LEAKAGE CURRENT (Single Bank Modules) IOZ -45 45 µA 48

(DQs are disabled; 0V ≤ VOUT ≤ VDDQ)

OUTPUT LEAKAGE CURRENT (Dual Bank Modules) IOZ -90 90 µA 48

(DQs are disabled; 0V ≤ VOUT ≤ VDDQ)

OUTPUT LEVELS:

High Current (VOUT = VDDQ-0.373V, minimum VREF, minimum VTT)IOH -16.8 –mA 33, 34

Low Current (VOUT = 0.373V, maximum VREF, maximum VTT)IOL 16.8 –mA

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

IDD SPECIFICATIONS AND CONDITIONS* (128MB - MT9VDDT1672)

(Notes: 1-5, 8, 10, 12; notes appear following parameter tables)

(0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)

PARAMETER/CONDITION SYMBOL

-26A/-265 -202

UNITS NOTES

OPERATING CURRENT: One device bank; Active-Precharge; IDD0945 900 mA 20, 43

tRC = tRC (MIN); t

CK = tCK (MIN); DQ, DM and DQS inputs changing

once per clock cyle; Address and control inputs changing once

every two clock cycles;

OPERATING CURRENT: One device bank; Active-Read-Precharge; IDD11,080 990 mA 20, 43

Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA;

Address and control inputs changing once per clock cycle

PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks IDD2P 27 27 mA 21, 28,

idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) 45

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; IDD2F 405 315 mA 46

tCK = tCK MIN; CKE = HIGH; Address and other control inputs

changing once per clock cycle.

VIN

VREF for DQ, DQS, and DM

ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; IDD3P 162 162 mA 21, 28,

Power-down mode; tCK = tCK (MIN); CKE = LOW 45

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device IDD3N 405 315 mA 42

bank; Active-Precharge; t

RC = tRAS (MAX); tCK = tCK (MIN); DQ, DM

and DQS inputs changing twice per clock cycle; Address and other

control inputs changing once per clock cycle

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; IDD4R 990 810 mA 20, 43

One device bank active; Address and control inputs changing once

per clock cycle; tCK = tCK (MIN); IOUT = 0mA

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; IDD4W 990 810 mA 20

One device bank active; Address and control inputs changing once

per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing

twice per clock cycle

AUTO REFRESH CURRENT tRC = t

RFC (MIN) IDD51,980 1,845 mA 20, 45

tRC = 15.625µs IDD5A 45 45 mA 24, 45

SELF REFRESH CURRENT: CKE ≤ 0.2V IDD

18 27 mA 9

OPERATING CURRENT: Four bank interleaving READs (BL=4) with I

72,925 2,340 mA 20, 44

auto precharge with,

RC =

RC (MIN);

CK =

CK (MIN); Address and

control inputs change only during Active READ, or WRITE commands.

MAX

*DDR SDRAM components only.

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

MAX

IDD SPECIFICATIONS AND CONDITIONS* (256MB - MT9VDDT3272)

(Notes: 1-5, 8, 10, 12; notes appear following parameter tables)

(0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)

PARAMETER/CONDITION SYMBOL

-26A/-265 -202

UNITS NOTES

OPERATING CURRENT: One device bank; Active-Precharge; IDD0 TBD TBD mA 20, 43

tRC = tRC (MIN); t

CK = tCK (MIN); DQ, DM and DQS inputs changing

once per clock cyle; Address and control inputs changing once

every two clock cycles;

OPERATING CURRENT: One device bank; Active-Read-Precharge; IDD1TBD TBD mA 20, 43

Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA;

Address and control inputs changing once per clock cycle

PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks IDD2P 27 27 mA 21, 28,

idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) 45

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; IDD2F 315 270 mA 46

tCK = tCK MIN; CKE = HIGH; Address and other control inputs

changing once per clock cycle.

VIN

VREF for DQ, DQS, and DM

ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; IDD3P TBD TBD mA 21, 28,

Power-down mode; tCK = tCK (MIN); CKE = LOW 45

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device IDD3N 315 270 mA 42

bank; Active-Precharge; t

RC = tRAS (MAX); tCK = tCK (MIN); DQ, DM

and DQS inputs changing twice per clock cycle; Address and other

control inputs changing once per clock cycle

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; IDD4R TBD TBD mA 20, 43

One device bank active; Address and control inputs changing once

per clock cycle; tCK = tCK (MIN); IOUT = 0mA

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; IDD4W TBD TBD mA 20

One device bank active; Address and control inputs changing once

per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing

twice per clock cycle

AUTO REFRESH CURRENT tRC = t

RC (MIN) IDD5TBD TBD mA 20, 45

tRC = 7.8125µs IDD5A 54 54 mA 24, 45

SELF REFRESH CURRENT: CKE ≤ 0.2V IDD6TBD TBD mA 9

OPERATING CURRENT: Four bank interleaving READs (BL=4) with I

TBD TBD mA 20, 44

auto precharge with,

RC =

RC (MIN);

CK =

CK (MIN); Address and

control inputs change only during Active READ, or WRITE commands.

* DDR SDRAM components only.

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

MAX

IDD SPECIFICATIONS AND CONDITIONS* (256MB - MT18VDDT3272D)

(Notes: 1-5, 8, 10, 12; notes appear following parameter tables)

(0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)

PARAMETER/CONDITION SYMBOL

-26A/-265

-202

UNITS NOTES

OPERATING CURRENT: One device bank; Active-Precharge; IDD0a 972 927 mA 20, 43

tRC = tRC (MIN); t

CK = tCK (MIN); DQ, DM and DQS inputs changing

once per clock cyle; Address and control inputs changing once

every two clock cycles;

OPERATING CURRENT: One device bank; Active-Read-Precharge; IDD1a 1,107 1,017 mA 20, 43

Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA;

Address and control inputs changing once per clock cycle

PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks IDD2Pb54 54 mA 21, 28,

idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) 45

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; IDD2Fb810 630 mA 46

tCK = tCK MIN; CKE = HIGH; Address and other control inputs

changing once per clock cycle.

VIN

VREF for DQ, DQS, and DM

ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; IDD3Pb 324 324 mA 21, 28,

Power-down mode; tCK = tCK (MIN); CKE = LOW 45

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device IDD3Nb 810 630 mA 42

bank; Active-Precharge; t

RC = tRAS (MAX); tCK = tCK (MIN); DQ, DM

and DQS inputs changing twice per clock cycle; Address and other

control inputs changing once per clock cycle

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; IDD4Ra 1,017 837 mA 20, 43

One device bank active; Address and control inputs changing once

per clock cycle; tCK = tCK (MIN); IOUT = 0mA

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; IDD4Wa 1,017 837 mA 20

One device bank active; Address and control inputs changing once

per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing

twice per clock cycle

AUTO REFRESH CURRENT tRC = t

RC (MIN) IDD5b 3,960 3,690 mA 20, 45

tRC = 15.625µs IDD5Ab90 90 mA 24, 45

SELF REFRESH CURRENT: CKE ≤ 0.2V IDD6b 36 54 mA 9

OPERATING CURRENT: Four bank interleaving READs (BL=4) with I

2,979 2,367 m A

20, 44

auto precharge with,

RC =

RC (MIN);

CK =

CK (MIN); Address and

control inputs change only during Active READ, or WRITE commands.

* DDR SDRAM components only.

a - Value calculated as one module bank in this operating condition, and all other module banks in IDD2P (CKE LOW) mode.

b- Value calculated reflects all module banks in this operating condition.

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

MAX

IDD SPECIFICATIONS AND CONDITIONS* (512MB - MT18VDDT6472D)

(Notes: 1-5, 8, 10, 12; notes appear following parameter tables)

(0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)

PARAMETER/CONDITION SYMBOL

-26A/-265 -202

UNITS NOTES

OPERATING CURRENT: One device bank; Active-Precharge; IDD0a TBD TBD mA 20, 43

tRC = tRC (MIN); t

CK = tCK (MIN); DQ, DM and DQS inputs changing

once per clock cyle; Address and control inputs changing once

every two clock cycles;

OPERATING CURRENT: One device bank; Active-Read-Precharge; IDD1a TBD TBD mA 20, 43

Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA;

Address and control inputs changing once per clock cycle

PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks IDD2Pb54 54 mA 21, 28,

idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) 45

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; IDD2Fb630 540 mA 46

tCK = tCK MIN; CKE = HIGH; Address and other control inputs

changing once per clock cycle.

VIN

VREF for DQ, DQS, and DM

ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; IDD3PbTBD TBD mA 21, 28,

Power-down mode; tCK = tCK (MIN); CKE = LOW 45

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device IDD3Nb630 540 mA 42

bank; Active-Precharge; t

RC = tRAS (MAX); tCK = tCK (MIN); DQ, DM

and DQS inputs changing twice per clock cycle; Address and other

control inputs changing once per clock cycle

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; IDD4Ra TBD TBD mA 20, 43

One device bank active; Address and control inputs changing once

per clock cycle; tCK = tCK (MIN); IOUT = 0mA

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; IDD4Wa TBD TBD mA 20

One device bank active; Address and control inputs changing once

per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing

twice per clock cycle

AUTO REFRESH CURRENT tRC = t

RC (MIN) IDD5b TBD TBD mA 20, 45

tRC = 7.8125µs IDD5Ab108 108 mA 24, 45

SELF REFRESH CURRENT: CKE ≤ 0.2V IDD6b TBD TBD mA 9

OPERATING CURRENT: Four bank interleaving READs (BL=4) with I

TBD TBD mA 20, 44

auto precharge with,

RC =

RC (MIN);

CK =

CK (MIN); Address and

control inputs change only during Active READ, or WRITE commands.

* DDR SDRAM components only.

a - Value calculated as one module bank in this operating condition, and all other module banks in IDD2P (CKE LOW) mode.

b- Value calculated reflects all module banks in this operating condition.

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

CAPACITANCE (MT9VDDT1672, MT9VDDT3272)

(Note: 11; notes appear following parameter tables)

PARAMETER SYMBOL MIN MAX UNITS

Input/Output Capacitance: DQs, DQS CIO 4.0 5.0 pF

Input Capacitance: Command and Address CI12.5 3.5 pF

Input Capacitance: S0# CI12.5 3.5 pF

Input Capacitance: CK0, CK0# CI22.5 3.5 pF

Input Capacitance: CKE0 CI32.5 3.5 pF

CAPACITANCE (MT18VDDT3272D, MT18VDDT6472D)

(Note: 11; notes appear following parameter tables)

PARAMETER SYMBOL MIN MAX UNITS

Input/Output Capacitance: DQs, DQS CIO 8.0 10.0 p F

Input Capacitance: Command and Address CI12.5 3.5 pF

Input Capacitance: S0#, S1# CI12.5 3.5 pF

Input Capacitance: CK0, CK0# CI22.5 3.5 pF

Input Capacitance: CKE0, CKE1 CI32.5 3.5 pF

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Notes: 1–5, 12–15, 29; notes appear following parameter tables)

(0°C ≤ TA ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)

AC CHARACTERISTICS -26A -265 -202

PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES

Access window of DQs from CK/CK# tAC -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns

CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK 26

CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK 26

Clock cycle time CL = 2.5 tCK (2.5) 7.5 13 7.5 13 8 13 ns 40, 47

CL = 2 tCK (2) 7.5 13 10 13 10 13 ns 40, 47

DQ and DM input hold time relative to DQS tDH 0.5 0.5 0.6 ns 23, 27

DQ and DM input setup time relative to DQS tDS 0.5 0.5 0.6 ns 23, 27

DQ and DM input pulse width (for each input) tDIPW 1.75 1.75 2 ns 27

Access window of DQS from CK/CK# tDQSCK -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns

DQS input high pulse width tDQSH 0.35 0.35 0.35 tCK

DQS input low pulse width tDQSL 0.35 0.35 0.35 tCK

DQS-DQ skew, DQS to last DQ valid, per group, per access tDQSQ 0.5 0.5 0.6 ns 22, 23

Write command to first DQS latching transition tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK

DQS falling edge to CK rising - setup time tDSS 0.2 0.2 0.2 tCK

DQS falling edge from CK rising - hold time tDSH 0.2 0.2 0.2 tCK

Half clock period tHP tCH,tCL tCH,tCL tCH,tCL ns 30

Data-out high-impedance window from CK/CK# tHZ +0.75 +0.75 +0.8 ns 16, 37

Data-out low-impedance window from CK/CK# tLZ -0.75 -0.75 -0.8 ns 16, 38

Address and control input hold time (slow slew rate) tIHS1 1 1.1 ns 12

Address and control input setup time (slow slew rate) tISS1 1 1.1 ns 12

Address and control input hold time (fast slew rate) tIHF0.9 0.9 1.1 ns 12

Address and control input setup time (fast slew rate) tISF0.9 0.9 1.1 ns 12

LOAD MODE REGISTER command cycle time tMRD 15 15 16 ns

DQ-DQS hold, DQS to first DQ to go non-valid, per access tQH tHP tHP tHP ns 22, 23

-tQHS -tQHS -tQHS

Data Hold Skew Factor tQHS 0.75 0.75 1 ns

ACTIVE to PRECHARGE command tRAS 40 120,000 40 120,000 40 120,000 ns 31

ACTIVE to READ with auto precharge command, tRAP tRAS(MIN) - (burst length * tCK/2) ns 41

MT9VDDT1672 and MT1832VDD3272D

ACTIVE to READ with auto precharge command, tRAP 20 20 20 ns

MT9VDD3272 and MT18VDD6472D

ACTIVE to ACTIVE/AUTO REFRESH command period tRC 65 65 70 ns

AUTO REFRESH command period tRFC 75 75 80 ns 45

ACTIVE to READ or WRITE delay tRCD 20 20 20 ns

PRECHARGE command period tRP 20 20 20 ns

DQS read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK

DQS read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK

ACTIVE bank a to ACTIVE bank b command tRRD 15 15 15 ns

DQS write preamble tWPRE 0.25 0.25 0.25 tCK

DQS write preamble setup time tWPRES 0 0 0 ns 18, 19

DQS write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK 17

Write recovery time tWR 15 15 15 ns

Internal WRITE to READ command delay tWTR 1 1 1 tCK

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(continued)

AC CHARACTERISTICS -26A -265 -202

PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES

Data valid output window (DVW) na tQH - tDQSQ tQH - tDQSQ tQH - tDQSQ ns 22

REFRESH to REFRESH command interval, tREFC 140.6 140.6 140.6 µs 21

MT9VDD1672 and MT18VDDT3272D

REFRESH to REFRESH command interval, tREFC 70.3 70.3 70.3 µs 21

MT9VDD3272 and MT18VDD6472D

Average periodic refresh interval, tREFI 15.6 15.6 15.6 µs 21

MT9VDD1672 and MT18VDDT3272D

Average periodic refresh interval, tREFI 7.8 7.8 7.8 µs 21

MT9VDD3272 and MT18VDDT6472D

Terminating voltage delay to VDD tVTD 0 0 0 ns

Exit SELF REFRESH to non-READ command tXSNR 75 75 80 ns

Exit SELF REFRESH to READ command tXSRD 200 200 200 tCK

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTES

1. All voltages referenced to VSS.

2. Tests for AC timing, IDD, and electrical AC and DC

characteristics may be conducted at nominal

reference/supply voltage levels, but the related

specifications and device operation are guaran-

teed for the full voltage range specified.

3. Outputs measured with equivalent load:

11. This parameter is sampled. VDD = +2.5V ±0.2V,

VDDQ = +2.5V ±0.2V, VREF = VSS, f = 100 MHz,

TA = 25°C, VOUT(DC) = VDDQ/2, VOUT (peak to peak) =

0.2V. DM input is grouped with I/O pins,

reflecting the fact that they are matched in

12. Command/Address input slew rate = 0.5V/ns. For

-75 with slew rates 1V/ns and faster, tIS and tIH

are reduced to 900ps. If the slew rate is less than

0.5V/ns, timing must be derated: tIS has an

additional 50ps per each 100mV/ns reduction in

slew rate from the 500mV/ns. tIH has 0ps added,

that is, it remains constant. If the slew rate

exceeds 4.5V/ns, functionality is uncertain.

13. The CK/CK# input reference level (for timing

referenced to CK/CK#) is the point at which CK

and CK# cross; the input reference level for

signals other than CK/CK# is VREF.

14. Inputs are not recognized as valid until VREF

stabilizes. Exception: during the period before

VREF stabilizes, CKE ≤ 0.3 x VDDQ is recognized as

LOW.

15. The output timing reference level, as measured

at the timing reference point indicated in Note 3,

is VTT.

16. tHZ and tLZ transitions occur in the same access

time windows as valid data transitions. These

parameters are not referenced to a specific

voltage level, but specify when the device output

is no longer driving (HZ) or begins driving (LZ).

17. The maximum limit for this parameter is not a

device limit. The device will operate with a

greater value for this parameter, but system

performance (bus turnaround) will degrade

accordingly.

18. This is not a device limit. The device will operate

with a negative value, but system performance

could be degraded due to bus turnaround.

19. It is recommended that DQS be valid (HIGH or

LOW) on or before the WRITE command. The

case shown (DQS going from High-Z to logic LOW)

applies when no WRITEs were previously in

progress on the bus. If a previous WRITE was in

progress, DQS could be HIGH during this time,

depending on tDQSS.

20. MIN (tRC or tRFC) for IDD measurements is the

smallest multiple of tCK that meets the minimum

absolute value for the respective parameter. tRAS

(MAX) for IDD measurements is the largest

multiple of tCK that meets the maximum

absolute value for tRAS.

Output

(VOUT)

Reference

Point

50Ω

VTT

30pF

4. AC timing and IDD tests may use a VIL-to-VIH swing

of up to 1.5V in the test environment, but input

timing is still referenced to VREF (or to the crossing

point for CK/CK#), and parameter specifications

are guaranteed for the specified AC input levels

under normal use conditions. The minimum slew

rate for the input signals used to test the device is

1V/ns in the range between VIL(AC) and VIH(AC).

5. The AC and DC input level specifications are as

defined in the SSTL_2 Standard (i.e., the receiver

will effectively switch as a result of the signal

crossing the AC input level, and will remain in

that state as long as the signal does not ring back

above [below] the DC input LOW [HIGH] level).

6. VREF is expected to equal VDDQ/2 of the transmit-

ting device and to track variations in the DC level

of the same. Peak-to-peak noise (non-common

mode) on VREF may not exceed ±2 percent of the

DC value. Thus, from VDDQ/2, VREF is allowed

±25mV for DC error and an additional ±25mV for

AC noise. This measurement is to be taken at the

nearest VREF by-pass capacitor.

7. VTT is not applied directly to the device. VTT is a

system supply for signal termination resistors, is

expected to be set equal to VREF and must track

variations in the DC level of VREF.

8. IDD is dependent on output loading and cycle

rates. Specified values are obtained with

minimum cycle time at CL = 2 for -26A and -202,

CL = 2.5 for -265 with the outputs open.

9. Enables on-chip refresh and address counters.

10. IDD specifications are tested after the device is

properly initialized, and is averaged at the

defined cycle rate.

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTES (continued)NOTES (continued) 25. To maintain a valid level, the transitioning edge

of the input must:

a) Sustain a constant slew rate from the current

AC level through to the target AC level, VIL(AC)

or VIH(AC).

b) Reach at least the target AC level.

c) After the AC target level is reached, continue

to maintain at least the target DC level, VIL(DC)

or VIH(DC).

26. JEDEC specifies CK and CK# input slew rate must

be ≥ 1V/ns (2V/ns differentially).

27. DQ and DM input slew rates must not deviate

from DQS by more than 10%. If the DQ/DM/DQS

slew rate is less than 0.5V/ns, timing must be

derated: 50ps must be added to tDS and tDH for

each 100mv/ns reduction in slew rate. If slew rate

exceeds 4V/ns, functionality is uncertain.28.

VDD must not vary more than 4% if CKE is not

active while any bank is active.

28. VDD must not vary more than 4% if CKE is not

active while any bank is active.

29. The clock is allowed up to ±150ps of jitter. Each

timing parameter is allowed to vary by the same

amount.

21. The refresh period 64ms. This equates to an

average refresh rate of 15.625µs for 128Mb-based

DIMMS, and 7.8/70.3 for 256Mb-based DIMMs.

However, an AUTO REFRESH command must be

asserted at least once every 140.6µs; burst

refreshing or posting by the DRAM controller

greater than eight refresh cycles is not allowed.

22. The valid data window is derived by achieving

other specifications - tHP (tCK/2), tDQSQ, and

tQH (tQH = tHP - tQHS). The data valid window

derates directly porportional with the clock duty

cycle and a practical data valid window can be

derived. The clock is allowed a maximum duty

cycle variation of 45/55. Functionality is uncer-

tain when operating beyond a 45/55 ratio. The

data valid window derating curves are provided

below for duty cycles ranging between 50/50 and

45/55.

23. Referenced to each output group: x8 = DQS with

DQ0-DQ7.

24. This limit is actually a nominal value and does

not result in a fail value. CKE is HIGH during

REFRESH command period (tRFC [MIN]) else

CKE is LOW (i.e., during standby).

DERATING DATA VALID WINDOW

(tQH - tDQSQ)

3.750 3.700 3.650 3.600

3.550

3.500 3.450

3.400 3.350 3.300

3.250

3.400 3.350 3.300

3.250

3.200 3.150

3.100 3.050

3.000 2.950 2.900

2.500 2.463 2.425 2.388 2.350 2.313 2.275 2.238 2.200 2.163 2.125

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 47/53 46.5/54.5 46/54 45.5/55.5 45/55

Clock Duty Cycle

—— -75 @ tCK = 10ns

—— -8 @ tCK = 10ns

—— -75 @ tCK = 7.5ns

—— -8 @ tCK = 8ns

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTES (continued)

30. tHP min is the lesser of tCL minimum and tCH

minimum actually applied to the device CK and

CK/ inputs, collectively during bank active.

31. READs and WRITEs with auto precharge are not

allowed to be issued until tRAS(MIN) can be

satisfied prior to the internal precharge com-

mand being issued.

32. Any positive glitch must be less than 1/3 of the

clock and not more than +400mV or 2.9 volts,

whichever is less. Any negative glitch must be

less than 1/3 of the clock cycle and not exceed

either

-300mV or 2.2 volts, whichever is more positive.

33. Normal Output Drive Curves:

a) The full variation in driver pull-down current

from minimum to maximum process, tempera-

ture and voltage will lie within the outer

bounding lines of the V-I curve of Figure A.

b)The variation in driver pull-down current

within nominal limits of voltage and tempera-

ture is expected, but not guaranteed, to lie

within the inner bounding lines of the V-I

curve of Figure A.

c) The full variation in driver pull-up current from

minimum to maximum process, temperature

and voltage will lie within the outer bounding

lines of the V-I curve of

Figure B.

d)The variation in driver pull-up current within

nominal limits of voltage and temperature is

expected, but not guaranteed, to lie within

the inner bounding lines of the V-I curve of

Figure B.

e) The full variation in the ratio of the maximum to

minimum pull-up and pull-down current

should be between .71 and 1.4, for device drain-

to-source voltages from 0.1V to 1.0 Volt, and at

the same voltage and temperature.

f) The full variation in the ratio of the nominal

pull-up to pull-down current should be unity

±10%, for device drain-to-source voltages from

0.1V to 1.0 Volt.

34. The voltage levels used are derived from a

minimum VDD level and the referenced test load.

In practice, the voltage levels obtained from a

properly terminated bus will provide significantly

different voltage values.

35. VIH overshoot: VIH(MAX) = VDDQ+1.5V for a

pulse width ≤ 3ns and the pulse width can not

be greater than 1/3 of the cycle rate. VIL

undershoot: VIL(MIN) = -1.5V for a pulse width

≤ 3ns and the pulse width can not be greater than

1/3 of the cycle rate.

36. VDD and VDDQ must track each other.

37. This maximum value is derived from the

referenced test load. In practice, the values

obtained in a typical terminated design may

reflect up to 310ps less for tHZ(MAX) and the last

DVW. tHZ(MAX) will prevail over tDQSCK(MAX) +

tRPST(MAX) condition. tLZ(MIN) will prevail over

tDQSCK(MIN) + tRPRE(MAX) condition.

38. For slew rates greater than 1V/ns the (LZ)

transition will start about 310ps earlier.

39. During initialization, VDDQ, VTT, and VREF must be

equal to or less than VDD + 0.3V. Alternatively, VTT

may be 1.35V maximum during power up, even

if VDD/VDDQ are 0 volts, provided a minimum of

42 ohms of series resistance is used between the

VTT supply and the input pin.

Figure B

Pull-Up Characteristics

-200

-180

-160

-140

-120

-100

-80

-60

-40

-20

0.0 0.5 1.0 1.5 2.0 2.5

IOUT (mA)

Q - V

OUT

(V)

Figure A

Pull-Down Characteristics

100

120

140

160

0.0 0.5 1.0 1.5 2.0 2.5

VOUT (V)

IOUT (mA)

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTES (continued)

40. The current Micron part operates below the

slowest JEDEC operating frequency of 83 MHz.

As such, future die may not reflect this option.

41. tRAP ≥ tRCD.

42. For the -26A and -265 speed grade, IDD3N is

specified to be the same as the -202 speed grade

when operating at 100 MHz (or DDR200 speed).

43. Random addressing changing 50% of data

changing at every transfer.

44. Random addressing changing 100% of data

changing at every transfer.

45. CKE must be active (high) during the entire time

a refresh command is executed. That is, from the

time the AUTO REFRESH command is registered,

CKE must be active at each rising clock edge,

until t

REF later.

46. IDD2N specifies the DQ, DQS, and DM to be

driven to a valid high or low logic level. IDD2Q is

similar to IDD2F except IDD2Q specifies the

address and control inputs to remain stable.

Although IDD2F, IDD2N, and IDD2Q are similar,

IDD2F is “worst case.”

47. Whenever the operating frequency is altered, not

including jitter, the DLL is required to be reset.

This is followed by 200 clock cycles.

48. Leakage number reflects the worst case leakage

possible through the module pin, not what each

memory device contributes.

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

(Note: 1)

TA = 0-70° C

VDD = 2.5V ± 0.2V

tCK Clock Frequency 60 170 MHz

tPD Clock to Output Time 30pF to GND and 1.1 2.7 ns

50 ohms to VTT

tRST Reset to Output Time –5ns

tSL Output Slew Rate 0.5 4 V/ns

Setup time, fast slew rate –0.75 ns 2, 4

1:1 (see Notes 1 and 3)

tsu

14 bit SSTL Setup time, slow slew rate –0.9 ns 3, 4

(see Notes 2 and 3)

Hold time, fast slew rate –0.75 ns 2, 4

(see Notes 1 and 3)

thHold time, slow slew rate –0.9 ns 3, 4

(see Notes 2 and 3)

CIN(CK) Clock Input Capacitance 2.5 3.5 pF

CIN(data) Data Input Capacitance 2.5 3.5 pF

NOTE: 1. The timing specifications for the register listed above are critical for proper operation of the DDR SDRAM Registered

DIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed

information on this part has been shown at the JEDEC JC-40 Committee. Please contact Micron Technology's Module

Applications Team if further information on the specific register model is required.

2. For data signal, input slew rate ≥ 1 V/ns.

3. For data signal, input slew rate ≥ 0.5 V/ns and < 1 V/ns.

4. For CK and CK# signals, input slew rates are ≥ 1 V/ns.

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

PLL CLOCK DRIVER TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS

(Specifications for the PLL component used on the module.)

PARAMETER SYMBOL TEST CONDITIONS MIN NOM MAX UNITS

Clock frequency fC 66 167 MHz

Input clock duty cycle 40% 60%

Stabilization time10.1 ms

Low-to high level tPLH CK mode/CK to any output 1.5 3.5 6 ns

propagation delay time

High-to low level tPHL CK mode/CK to any output 1.5 3.5 6 ns

propagation delay time

Output enable time ten CK mode/G to any Y output 3 ns

Output disable time tdis CK mode/G to any Y output 3 ns

Jitter (peak-to-peak) t(jitter) 66 MHz 120 ps

100/125/133/167 MHz 75

Jitter (cycle-to-cycle) t(jitter) 66 MHz 110 ps

100/125/133/167 MHz 65

Phase error t(phase Terminated with 120 ohm/16pF -150 150 ns

error)

Output skew tskew(o) Terminated with 120 ohm/16pF 100 ns

Pulse skew tdis Terminated with 120 ohm/16pF 100 ns

Duty cycle 66 MHz to 100 MHz 49.5% 50.5%

101 MHz to 167 MHz 49% 51%

Output rise and fall times tr, tf Load = 120 ohm/16pF 650 800 950 ps

(20% - 80%)

NOTE: 1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal.

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

SCL

SDA

DATA STABLE DATA STABLEDATA

CHANGE

Figure 3

Data Validity

SCL

SDA

START

BIT

STOP

BIT

Figure 4

Definition of Start and Stop

SCL from Master

Data Output

from Transmitter

Data Output

from Receiver

Acknowledge

Figure 5

Acknowledge Response From Receiver

SPD CLOCK AND DATA CONVENTIONS

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are

reserved for indicating start and stop conditions as

indicated in Figures 3 and 4.

SPD START CONDITION

All commands are preceded by the start condition,

which is a HIGH-to-LOW transition of SDA when SCL is

HIGH. The SPD device continuously monitors the SDA

and SCL lines for the start condition and will not re-

spond to any command until this condition has been

met.

SPD STOP CONDITION

All communications are terminated by a stop condi-

tion, which is a LOW-to-HIGH transition of SDA when

SCL is HIGH. The stop condition is also used to place

the SPD device into standby power mode.

SPD ACKNOWLEDGE

Acknowledge is a software convention used to indi-

cate successful data transfers. The transmitting de-

vice, either master or slave, will release the bus after

transmitting eight bits. During the ninth clock cycle,

the receiver will pull the SDA line LOW to acknowledge

that it received the eight bits of data as indicated in

Figure 5.

The SPD device will always respond with an ac-

knowledge after recognition of a start condition and its

slave address. If both the device and a WRITE opera-

tion have been selected, the SPD device will respond

with an acknowledge after the receipt of each subse-

quent eight-bit word. In the read mode the SPD device

will transmit eight bits of data, release the SDA line and

monitor the line for an acknowledge. If an acknowl-

edge is detected and no stop condition is generated by

the master, the slave will continue to transmit data. If

an acknowledge is not detected, the slave will termi-

nate further data transmissions and await the stop con-

dition to return to standby power mode.

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

SCL

SDA IN

SDA OUT

tLOW

tSU:STA tHD:STA

tFtHIGH tR

tBUF

tDH

tAA

tSU:STO

tSU:DAT

tHD:DAT

UNDEFINED

SPD EEPROM TIMING DIAGRAM

SERIAL PRESENCE-DETECT EEPROM TIMING

PARAMETERS

SYMBOL MIN MAX UNITS

tAA 0.3 3.5 µs

tBUF 4.7 µs

tDH 300 ns

tF 300 ns

tHD:DAT 0 µs

tHD:STA 4 µs

SYMBOL MIN MAX UNITS

tHIGH 4 µs

tLOW 4.7 µs

tR1µs

tSU:DAT 250 ns

tSU:STA 4.7 µs

tSU:STO 4.7 µs

EEPROM DEVICE SELECT CODE

The most significant bit (b7) is sent first

DEVICE TYPE IDENTIFIER CHIP ENABLE RW

b7 b6 b5 b4 b3 b2 b1 b0

Memory Area Select Code (two arrays) 1 0 1 0 E2 E1 E0 RW

Protection Register Select Code 0 1 1 0 E2 E1 E0 RW

EEPROM OPERATING MODES

MODE RW BIT WC1BYTES INITIAL SEQUENCE

Current Address Read 1 X 1 START, Device Select, RW = ‘1’

Random Address Read 0 X 1 START, Device Select, RW = ‘0’, Address

1 X 1 reSTART, Device Select, RW = ‘1’

Sequential Read 1 X ≥≥

≥≥

≥ 1 Similar to Current or Random Address Read

Byte Write 0 VIL 1 START, Device Select, RW = ‘0’

Page Write 0 VIL ≤ 16 START, Device Select, RW = ‘0’

NOTE: 1. X = VIH or VIL.

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

SERIAL PRESENCE-DETECT EEPROM DC OPERATING CONDITIONS

(Note: 1) (VDD = +3.3V ±0.3V)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS

SUPPLY VOLTAGE VDDSPD 2.2 5.5 V

INPUT HIGH VOLTAGE: Logic 1; All inputs VIH VDD x 0.7 VDD + 0.5 V

INPUT LOW VOLTAGE: Logic 0; All inputs VIL -1 VDD x 0.3 V

OUTPUT LOW VOLTAGE: IOUT = 3mA VOL –0.4 V

INPUT LEAKAGE CURRENT: VIN = GND to VDD ILI –10 µA

OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD ILO –10 µA

STANDBY CURRENT: ISB –30 µA

SCL = SDA = VDD - 0.3V; All other inputs = GND or 3.3V +10%

POWER SUPPLY CURRENT: IDD –2mA

SCL clock frequency = 100 KHz

SERIAL PRESENCE-DETECT EEPROM AC OPERATING CONDITIONS

(Note: 2) (VDD = +3.3V ±0.3V)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

SCL LOW to SDA data-out valid tAA 0.3 3.5 µs

Time the bus must be free before a new transition can start tBUF 4.7 µs

Data-out hold time tDH 300 ns

SDA and SCL fall time tF 300 ns

Data-in hold time tHD:DAT 0 µs

Start condition hold time tHD:STA 4 µs

Clock HIGH period tHIGH 4 µs

Noise suppression time constant at SCL, SDA inputs tI 100 ns

Clock LOW period tLOW 4.7 µs

SDA and SCL rise time tR1µs

SCL clock frequency tSCL 100 KHz

Data-in setup time tSU:DAT 250 ns

Start condition setup time tSU:STA 4.7 µs

Stop condition setup time tSU:STO 4.7 µs

WRITE cycle time tWRC 10 ms 3

NOTE: 1. All voltages referenced to VSS.

2. All voltages referenced to VSS.

3. Timing actually specified by tWR.

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

SERIAL PRESENCE-DETECT MATRIX

(Note: 1)

BYTE DESCRIPTION ENTRY (VERSION) MT9VDDT1672 MT9VDDT3272

0 NUMBER OF SPD BYTES USED BY MICRON 128 80 80

1 TOTAL NUMBER OF BYTES IN SPD DEVICE 256 08 08

2 FUNDAMENTAL MEMORY TYPE SDRAM DDR 07 07

3 NUMBER OF ROW ADDRESSES ON ASSEMBLY 12 or 13 0C 0D

4 NUMBER OF COLUMN ADDRESSES ON ASSEMBLY 10 0A 0A

5 NUMBER OF PHYSICAL BANKS ON DIMM 1 01 01

6 MODULE DATA WIDTH 72 48 48

7 MODULE DATA WIDTH (continued) 0 00 00

8 MODULE VOLTAGE INTERFACE LEVELS (VDDQ) SSTL 2.5V 04 04

9 SDRAM CYCLE TIME, (tCK) 7ns (-26A) 70 70

(CAS LATENCY = 2.5) (Note:2) 7.5ns (-265) 75 75

8ns (-202) 80 80

10 SDRAM ACCESS FROM CLOCK,(tAC) 0.75ns (-26A/-265) 75 75

(CAS LATENCY = 2.5) (Note:2) 0.8ns (-202) 80 80

11 MODULE CONFIGURATION TYPE ECC 02 02

12 REFRESH RATE/TYPE 7.8µs or 15.6µs/SELF 80 82

13 SDRAM DEVICE WIDTH (PRIMARY SDRAM) x8 08 08

14 ERROR-CHECKING SDRAM DATA WIDTH x8 08 08

15 MINIMUM CLOCK DELAY, BACK-TO-BACK 1 clock 01 01

RANDOM COLUMN ACCESS

16 BURST LENGTHS SUPPORTED 2, 4, 8 0E 0E

17 NUMBER OF BANKS ON SDRAM DEVICE 4 04 04

18 CAS LATENCIES SUPPORTED 2, 2.5 0C 0C

19 CS LATENCY 0 01 01

20 WE LATENCY 1 02 02

21 SDRAM MODULE ATTRIBUTES REGISTERED, PLL 26 26

22 SDRAM DEVICE ATTRIBUTES: GENERAL Fast/concurrent A/P 00/C0* C0

23 SDRAM CYCLE TIME, (tCK) 7.5ns (-26A) 75 75

(CAS LATENCY = 2)(Note:2) 10ns (-265/-202) A0 A0

24 SDRAM ACCESS FROM CK , (tAC) 0.75ns (-26A/-265) 75 75

(CAS LATENCY = 2)(Note:2) 0.8ns (-202) 80 80

25 SDRAM CYCLE TIME, (tCK) N/A 00 00

(CAS LATENCY = 1.5)

26 SDRAM ACCESS FROM CK , (tAC) N/A 00 00

(CAS LATENCY = 1.5)

27 MINIMUM ROW PRECHARGE TIME, (tRP) 20ns 50 50

28 MINIMUM ROW ACTIVE TO ROW ACTIVE, (tRRD) 15ns 3C 3C

29 MINIMUM RAS# TO CAS# DELAY, (tRCD) 20ns 50 50

30 MINIMUM ACTIVE TO PRECHARGE TIME, (tRAS) 45ns (-26A/-265) 2D 2D

(Note: 3) 40ns (-202) 28 28

31 MODULE BANK DENSITY 128MB or 256MB 20 40

NOTE: 1. “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW.”

2. The value of tCK for -26A modules is set at 7.0ns. Component spec. value is 7.5ns.

3. The value of tRAS used for the -26A/-265 module is calculated from tRC - tRP. Actual device spec. value is 40ns.

*Supports fast/concurrent auto precharge. Contact factory for additional information regarding this option.

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

SERIAL PRESENCE-DETECT MATRIX (continued)

(Note: 2)

BYTE DESCRIPTION ENTRY (VERSION) MT9VDDT1672 MT9VDDT3272

32 ADDRESS AND COMMAND SETUP TIME, (tIS) 1.0ns (-26A/-265) A0 A0

1.1ns (-202) B0 B0

33 ADDRESS AND COMMAND HOLD TIME, (tIH) 1.0ns (-26A/-265) A0 A0

1.1ns (-202) B0 B0

34 DATA/DATA MASK INPUT SETUP TIME, (tDS) 0.5ns (-26A/-265) 50 50

0.6ns (-202) 60 60

35 DATA/DATA MASK INPUT HOLD TIME, (tDH) 0.5ns (-26A/-265) 50 50

0.6ns (-202) 60 60

36-40 RESERVED 00 00

41 MINIMUM ACTIVE/AUTO REFRESH TIME, (tRC) 65ns (-26A/-265) 41 41

70ns (-202) 46 46

42 MINIMUM AUTO REFRESH TO ACTIVE/ 75ns (-26A/-265) 4B 4B

AUTO REFRESH COMMAND PERIOD, (tRFC) 80ns (-202) 50 50

43 MAXIMUM CYCLE TIME, (tCK (MAX)) tCK = (MAX) = 13.0ns 34 34

44 MAXIMUM DQS-DQ SKEW TIME, 0.5ns (-26A/-265) 32 32

(tDQSQ) 0.6ns (-202) 3C 3C

45 MAXIMUM READ DATA HOLD SKEW FACTOR, 0.75ns (-26A/-265) 75 75

(tQHS) 1.0ns (-202) A0 A0

46-61 RESERVED 00 00

62 SPD REVISION Release 0.0 00 00

63 CHECKSUM FOR BYTES 0-62 -26A 0B/CB* EE

-265 3B/FB* 1E

-202 D6/96* B9

64 MANUFACTURER’S JEDEC ID CODE MICRON 2C 2C

65-71 MANUFACTURER’S JEDEC ID CODE (continued) 00 00

72 MANUFACTURING LOCATION 1–11 01–0B 01–0B

73-90 MODULE PART NUMBER (ASCII) xx

91 PCB IDENTIFICATION CODE 1–901–09 01–09

92 IDENTIFICATION CODE (continued) 0 00 00

93 YEAR OF MANUFACTURE IN BCD xx

94 WEEK OF MANUFACTURE IN BCD xx

95-98 MODULE SERIAL NUMBER xx

99-127 MANUFACTURER-SPECIFIC DATA (RSVD) ––

NOTE: 2. x = Variable Data.

*Supports fast/concurrent auto precharge. Contact factory for additional information regarding this option.

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

SERIAL PRESENCE-DETECT MATRIX

(Note: 1)

BYTE DESCRIPTION ENTRY (VERSION) MT18VDDT3272D (Hex) MT18VDDT6472D (Hex)

0 NUMBER OF SPD BYTES USED BY MICRON 128 80 80

1 TOTAL NUMBER OF BYTES IN SPD DEVICE 256 08 08

2 FUNDAMENTAL MEMORY TYPE SDRAM DDR 07 07

3 NUMBER OF ROW ADDRESSES ON ASSEMBLY 12 or 13 0C 0D

4 NUMBER OF COLUMN ADDRESSES ON ASSEMBLY 10 0A 0A

5 NUMBER OF PHYSICAL BANKS ON DIMM 2 02 02

6 MODULE DATA WIDTH 72 48 48

7 MODULE DATA WIDTH (continued) 0 00 00

8 MODULE VOLTAGE INTERFACE LEVELS (VDDQ) SSTL 2.5V 04 04

9 SDRAM CYCLE TIME, (tCK) 7ns (-26A) 70 70

(CAS LATENCY = 2.5) (Note:2) 7.5ns (-265) 75 75

8ns (-202) 80 80

10 SDRAM ACCESS FROM CLOCK,(tAC) 0.75ns (-26A/-265) 75 75

(CAS LATENCY = 2.5) (Note:2) 0.8ns (-202) 80 80

11 MODULE CONFIGURATION TYPE ECC 02 02

12 REFRESH RATE/TYPE 7.8µs or 15.6µs/SELF 80 82

13 SDRAM DEVICE WIDTH (PRIMARY SDRAM) x8 08 08

14 ERROR-CHECKING SDRAM DATA WIDTH x8 08 08

15 MINIMUM CLOCK DELAY, BACK-TO-BACK 1 clock 01 01

RANDOM COLUMN ACCESS

16 BURST LENGTHS SUPPORTED 2, 4, 8 0E 0E

17 NUMBER OF BANKS ON SDRAM DEVICE 4 04 04

18 CAS LATENCIES SUPPORTED 2, 2.5 0C 0C

19 CS LATENCY 0 01 01

20 WE LATENCY 1 02 02

21 SDRAM MODULE ATTRIBUTES REGISTERED, PLL 26 26

22 SDRAM DEVICE ATTRIBUTES: GENERAL Fast / Concurrent A/P 00/C0* C0

23 SDRAM CYCLE TIME, (tCK) 7.5ns (-26A) 75 75

(CAS LATENCY = 2)(Note:2) 10ns (-265/-202) A0 A0

24 SDRAM ACCESS FROM CK , (tAC) 0.75ns (-26A/-265) 75 75

(CAS LATENCY = 2)(Note:2) 0.8ns (-202) 80 80

25 SDRAM CYCLE TIME, (tCK) N/A 00 00

(CAS LATENCY = 1.5)

26 SDRAM ACCESS FROM CK , (tAC) N/A 00 00

(CAS LATENCY = 1.5)

27 MINIMUM ROW PRECHARGE TIME, (tRP) 20ns 50 50

28 MINIMUM ROW ACTIVE TO ROW ACTIVE, (tRRD) 15ns 3C 3C

29 MINIMUM RAS# TO CAS# DELAY, (tRCD) 20ns 50 50

30 MINIMUM ACTIVE TO PRECHARGE TIME, (tRAS) 45ns (-26A/-265) 2D 2D

(Note: 3) 40ns (-202) 28 28

31 MODULE BANK DENSITY 128MB or 256MB 20 40

NOTE: 1. “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW.”

2. Device latencies used for SPD values.

3. The value of tRAS used for the -26A/-265 module is calculated from tRC - tRP. Actual device spec. value is 40ns.

*Supports fast/concurrent auto precharge. Contact factory for additional information regarding this option.

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

SERIAL PRESENCE-DETECT MATRIX (continued)

(Note: 2)

BYTE DESCRIPTION ENTRY (VERSION) MT18VDDT3272D(Hex) MT18VDDT6472D (Hex)

32 ADDRESS AND COMMAND SETUP TIME, (tIS) 1.0ns (-26A/-265) A0 A0

1.1ns (-202) B0 B0

33 ADDRESS AND COMMAND HOLD TIME, (tIH) 1.0ns (-26A/-265) A0 A0

1.1ns (-202) B0 B0

34 DATA/DATA MASK INPUT SETUP TIME, (tDS) 0.5ns (-26A/-265) 50 50

0.6ns (-202) 60 60

35 DATA/DATA MASK INPUT HOLD TIME, (tDH) 0.5ns (-26A/-265) 50 50

0.6ns (-202) 60 60

36-40 RESERVED 00 00

41 MINIMUM ACTIVE/AUTO REFRESH TIME, (tRC) 65ns (-26A/-265) 41 41

70ns (-202) 46 46

42 MINIMUM AUTO REFRESH TO ACTIVE/ 75ns (-26A/-265) 4B 4B

AUTO REFRESH COMMAND PERIOD, (tRFC) 80ns (-202) 50 50

43 MAXIMUM CYCLE TIME, (tCK (MAX)) tCK (MAX) = 13.0ns 34 34

44 MAXIMUM DQS-DQ SKEW TIME, 0.5ns (-26A/-265) 32 SH

(tDQSQ) 0.6ns (-202) 3C 3C

45 MAXIMUM READ DATA HOLD SKEW FACTOR, .75ns (-26A/-265) 75 75

(tQHS) 1.0ns (-202) A0 A0

46-61 RESERVED 00 00

62 SPD REVISION Release 0.0 00 00

63 CHECKSUM FOR BYTES 0-62 (-26A) 0C/CC* EF

(-265) 3C/FC* 1F

(-202) D7/97* BA

64 MANUFACTURER’S JEDEC ID CODE MICRON 2C 2C

65-71 MANUFACTURER’S JEDEC ID CODE (continued) 00 00

72 MANUFACTURING LOCATION 1–11 01–0B 01–0B

73-90 MODULE PART NUMBER (ASCII) xx

91 PCB IDENTIFICATION CODE 1–901–09 01–09

92 IDENTIFICATION CODE (continued) 0 00 00

93 YEAR OF MANUFACTURE IN BCD xx

94 WEEK OF MANUFACTURE IN BCD xx

95-98 MODULE SERIAL NUMBER xx

99-127 MANUFACTURER-SPECIFIC DATA (RSVD) ––

NOTE: 2. x = Variable Data.

*Supports fast/concurrent auto precharge. Contact factory for additional information regarding this option.

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

STANDARD 184-PIN DIMM

(SINGLE BANK)

NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted.

MIN

1.705 (43.31)

1.695 (43.05)

PIN 1

.700 (17.78)

TYP.

.098 (2.50) D

(2X)

.091 (2.30) TYP.

.250 (6.35) TYP.

4.750 (120.65)

.050 (1.27)

TYP.

.091 (2.30)

TYP.

.040 (1.02)

TYP.

.079 (2.00) R

(4X)

.035 (0.90) R

PIN 92

FRONT VIEW

.054 (1.37)

.046 (1.17)

5.256 (133.50)

5.244 (133.20)

2.55 (64.77) 1.95 (49.53)

.394 (10.00)

TYP.

.125 (3.175)

MAX

BACK VIEW

PIN 184 PIN 93

U1 U3 U5

U11 U12

U13

U10

U15 U17 U19 U21

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

STANDARD 184-PIN DIMM

(DUAL BANK)

NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted.

MIN

1.705 (43.31)

1.695 (43.05)

PIN 1

.700 (17.78)

TYP.

.098 (2.50) D

(2X)

.091 (2.30) TYP.

.250 (6.35) TYP.

4.750 (120.65)

.050 (1.27)

TYP.

.091 (2.30)

TYP.

.040 (1.02)

TYP.

.079 (2.00) R

(4X)

.035 (0.90) R

PIN 92

FRONT VIEW

.054 (1.37)

.046 (1.17)

5.256 (133.50)

5.244 (133.20)

2.55 (64.77) 1.95 (49.53)

.394 (10.00)

TYP.

.125 (3.175)

MAX

BACK VIEW

PIN 184 PIN 93

U1 U2 U3 U4 U5

U11 U12

U6 U7

U13

U8 U9

U10

U14 U15 U16 U17 U18 U19 U20 U21 U22

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

LOW-PROFILE 184-PIN DIMM

(SINGLE BANK)

U1 U3

U11

U12

U5 U7 U9

U15 U17

U13

U10

U19 U21

.054 (1.37)

.046 (1.17)

.125 (3.175)

MAX

1.205 (30.61)

1.195 (30.35)

PIN 1

.700 (17.78)

TYP.

.098 (2.50) D

(2X)

.091 (2.30) TYP.

.250 (6.35) TYP.

4.750 (120.65)

.050 (1.27)

TYP.

.091 (2.30)

TYP.

.040 (1.02)

TYP.

.079 (2.00) R

(4X)

.035 (0.90) R

PIN 92

FRONT VIEW

5.256 (133.50)

5.244 (133.20)

2.55 (64.77) 1.95 (49.53)

.394 (10.00)

TYP.

BACK VIEW

PIN 184 PIN 93

NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted.

MIN

128MB, 256MB, 512MB (x72)

184-PIN REGISTERED DDR SDRAM DIMMs

16, 32, 64 Meg (x72) 184 Pin Registered DDR SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.

LOW-PROFILE 184-PIN DIMM

(DUAL BANK)

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron is a registered trademark and the Micron logo and M logos are trademarks of Micron Technology, Inc.

NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted.

MIN

U1 U2 U3 U4

U11

U12

U5 U6 U7 U8 U9

U14 U15 U16 U17 U18

U13

U10

U19 U20 U21 U22

.054 (1.37)

.046 (1.17)

.125 (3.175)

MAX

1.205 (30.61)

1.195 (30.35)

PIN 1

.700 (17.78)

TYP.

.098 (2.50) D

(2X)

.091 (2.30) TYP.

.250 (6.35) TYP.

4.750 (120.65)

.050 (1.27)

TYP.

.091 (2.30)

TYP.

.040 (1.02)

TYP.

.079 (2.00) R

(4X)

.035 (0.90) R

PIN 92

FRONT VIEW

5.256 (133.50)

5.244 (133.20)

2.55 (64.77) 1.95 (49.53)

.394 (10.00)

TYP.

BACK VIEW

PIN 184 PIN 93