Interfacing LVPECL to LVDS
An LVPECL driver consists of a differential pair with coupled
emitters connected to GND via a current source. This drives
a pair of emitter-followers that require a 50 ohm to VCC-2.0
load. A modern LVPECL driver will typically include the ter-
mination scheme within the device for the emitter follower. If
the driver does not include the load, then an external scheme
must be used. The 1.3 V supply is usually not readily available
on a PCB, therefore, a load scheme without a unique power
supply requirement may be used.
20157461
FIGURE 2. DC Coupled LVPECL to LVDS Interface
Figure 2 is a separated π termination scheme for a 3.3 V
LVPECL driver. R1 and R2 provides proper DC load for the
driver emitter followers, and may be included as part of the
driver device (Note 16). The DS08MB200 includes a 100 ohm
input termination for the transmission line. The common mode
voltage will be at the normal LVPECL levels – around 2 V.
This scheme works well with LVDS receivers that have rail-
to-rail common mode voltage, VCM, range. Most National
Semiconductor LVDS receivers have wide VCM range. The
exceptions are noted in devices’ respective datasheets.
Those LVDS devices that do have a wide VCM range do not
vary in performance significantly when receiving a signal with
a common mode other than standard LVDS VCM of 1.2 V.
20157462
FIGURE 3. AC Coupled LVPECL to LVDS Interface
An AC coupled interface is preferred when transmitter and
receiver ground references differ more than 1 V. This is a
likely scenario when transmitter and receiver devices are on
separate PCBs. Figure 3 illustrates an AC coupled interface
between a LVPECL driver and LVDS receiver. R1 and R2, if
not present in the driver device (Note 16), provide DC load for
the emitter followers and may range between 140-220 ohms
for most LVPECL devices for this particular configuration. The
DS08MB200 includes an internal 100 ohm resistor to termi-
nate the transmission line for minimal reflections. The signal
after ac coupling capacitors will swing around a level set by
internal biasing resistors (i.e. fail-safe) which is either VDD/2
or 0 V depending on the actual failsafe implementation. If in-
ternal biasing is not implemented, the signal common mode
voltage will slowly wander to GND level.
Interfacing LVDS to LVPECL
An LVDS driver consists of a current source (nominal 3.5mA)
which drives a CMOS differential pair. It needs a differential
resistive load in the range of 70 to 130 ohms to generate
LVDS levels. In a system, the load should be selected to
match transmission line characteristic differential impedance
so that the line is properly terminated. The termination resistor
should be placed as close to the receiver inputs as possible.
When interfacing an LVDS driver with a non-LVDS receiver,
one only needs to bias the LVDS signal so that it is within the
common mode range of the receiver. This may be done by
using separate biasing voltage which demands another pow-
er supply. Some receivers have required biasing voltage
available on-chip (VT, VTT or VBB).
20157463
FIGURE 4. DC Coupled LVDS to LVPECL Interface
Figure 4 illustrates interface between an LVDS driver and a
LVPECL with a VT pin available. R1 and R2, if not present in
the receiver (Note 16), provide proper resistive load for the
driver and termination for the transmission line, and VT sets
desired bias for the receiver.
20157464
FIGURE 5. AC Coupled LVDS to LVPECL Interface
Figure 5 illustrates AC coupled interface between an LVDS
driver and LVPECL receiver without a VT pin available. The
resistors R1, R2, R3, and R4, if not present in the receiver
(Note 16), provide a load for the driver, terminate the trans-
mission line, and bias the signal for the receiver.
Note 16: The bias networks shown above for LVPECL drivers and receivers
may or may not be present within the driver device. The LVPECL driver and
receiver specification must be reviewed closely to ensure compatibility
between the driver and receiver terminations and common mode operating
ranges.
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DS08MB200