SO8
MiniSO8
Features
• Wide common mode voltage: - 20 to 70 V
• Offset voltage: ± 200 µV max.
• 2.7 to 5.5 V supply voltage
• Different gain available:
– TSC2011: 60 V/V
– TSC2012: 100 V/V
• Gain error: 0.3% max.
• Offset drift: 5 µV/°C max.
• Quiescent current: 20 µA in shutdown mode
• SO8 and MiniSO8 package
Applications
• High-side current sensing
• Low-side current sensing
• Data acquisition and instrumentation
• Test and measurement equipment
• Industrial process control
• Motor control
• Solenoid control
Description
The TSC2011 and TSC2012 are precision bidirectional current sense amplifiers.
They can sense the current thanks to a shunt resistor over a wide range of common
mode voltages, from - 20 to + 70 V, whatever the supply voltage is. They are
available with an amplifier gain of 60 V/V for TSC2011 and 100 V/V for TSC2012.
They are able to sense very low drop voltages as low as 10 mV full scale minimizing
the measurement error.
The TSC2011 and TSC2012 can also be used in other functions such as: precision
current measurement, overcurrent protection, current monitoring, and feedback
loops.
This device fully operates over the broad supply voltage range from 2.7 to 5.5 V and
over the industrial temperature range from - 40 to 125 °C.
Maturity status link
TSC2011, TSC2012
High voltage, precision, bidirectional current sense amplifiers
TSC2011, TSC2012
Datasheet
DS13057 - Rev 2 - January 2020
For further information contact your local STMicroelectronics sales office. www.st.com
1Diagram
Figure 1. Block diagram
TSC2011, TSC2012
Diagram
DS13057 - Rev 2 page 2/49
2Pin configuration
Figure 2. Pin connection (top view)
Table 1. Pin description
Pin Pin name Description
1 IN - Negative input
2 GND Ground
3 VREF2 Reference voltage 2
4 SHDN Shutdown
5 OUT Output
6 VCC Supply voltage
7 VREF1 Reference voltage 1
8 IN + Positive input
TSC2011, TSC2012
Pin configuration
DS13057 - Rev 2 page 3/49
3Maximum ratings
Table 2. Absolute maximum ratings
Symbol Parameter Value Unit
VCC Supply voltage (1) -0.3 to 7 V
VICM Common mode voltage on input pins -25 to 76 V
VDIF Differential voltage between input pins (In+, In-) 7 V
VREF1 VREF2 VOUT Voltage present on pins Ref1, Ref2, Out Gnd - 0.3 to Vcc + 0.3 V
IIN Input current to any pins (2) 5 mA
TSTG Storage temperature -65 to 150 °C
TJJunction temperature 150 °C
RTHJA
Thermal resistance junction to ambient (3)(4)
SO8
MiniSO8
125
190
°C/W
ESD Human body model (HBM) (5) 2000 V
Charged device model (CDM) (6) 1000
Latch-up immunity 200 mA
1. All voltage values, except the differential voltage are with respect to the network ground terminal.
2. Input voltage can go beyond supply voltage but input current must be limited. Using a serial resistor with the input is highly
recommended in that case.
3. Short-circuits can cause excessive heating and destructive dissipation.
4. Rth are typical values.
5. According to JEDEC standard JESD22-A114F.
6. According to ANSI/ESD STM5.3.1.According to ANSI/ESD STM5.3.1.
Table 3. Operating conditions
Symbol Parameter Value Unit
Vcc Supply voltage 2.7 to 5.5 V
Vicm Common mode voltage on input pins -20 to +70 V
Vref Output offset adjustment range 0 to Vcc V
T Operating free-air temperature range -40 to 125 °C
TSC2011, TSC2012
Maximum ratings
DS13057 - Rev 2 page 4/49
4Electrical characteristics
Table 4. Electrical characteristics Vcc = 2.7 V, Vicm = 12 V, T = 25 °C (unless otherwise specified).
Symbol Parameter Conditions Min. Typ. Max. Unit
Power supply
Icc
Current consumption Vicm = -20 to 70 V
Tmin < T < Tmax
1.5 2.3
2.3 mA
Current consumption with
shutdown active
Vicm = - 20 to 70 V
Tmin < T < Tmax
20 50
150 µA
Input
|Vos|Offset voltage (RTI) (1)
Vicm = 1 V
Tmin < T < Tmax
200
700
µV
Vicm = 12 V
Tmin < T < Tmax
500
1100
|ΔVos/ΔT| Offset drift vs. temperature
Vicm = 1 V, Tmin < T < Tmax 5µV/°C
Vicm = 12 V, Tmin < T < Tmax 8
CMR Common mode rejection Vicm = -20 to 70 V, DC mode
Tmin < T < Tmax
90
85
115 dB
Iib+ Input bias current Vicm = 12 V
Tmin < T < Tmax, Vicm = -20 to 70 V -400
350
600 µA
Iib- Input bias current Vicm = 12 V
Tmin < T < Tmax, Vicm= - 20 to 70 V -150
100
350
|Vsense|Vsense operating range with
Eg ≤ 0.3% (2)
TSC2011
Tmin < T < Tmax
40.5
39.3 mV
TSC2012
Tmin < T < Tmax
23.9
22.7
Output
G Gain TSC2011 60 V/V
TSC2012 100
Eg Gain error vs. temperature ΔVout = 100 mV to (Vcc - 100 mV)
Tmin < T < Tmax
0.3
0.3 %
ΔEg/ΔT Gain error drift Tmin < T < Tmax 25 ppm/°C
NLE Linearity error Vicm = 12 V 0.03 %
Vcc - Voh Drop voltage output high Isource = 0.2 mA
Tmin < T < Tmax
8 15
20 mV
Vol Output voltage low Isink = 0.2 mA
Tmin < T < Tmax
12 20
30 mV
TSC2011, TSC2012
Electrical characteristics
DS13057 - Rev 2 page 5/49
Symbol Parameter Conditions Min. Typ. Max. Unit
Iout Output current
Sink mode
Tmin < T < Tmax
12
15
20 25
30
mA
Source mode
Tmin < T < Tmax
6
8
10 14
17
Reg Load Load regulation Iout = - 10 to +4 mA 0.3 1.5 mV/mA
OFFSET adjustment
RtRatiometric accuracy 0.5 V/V
Acc Accuracy, RTO Voltage applied to Vref1 and Vref2 in
parallel 0.1 %
Dynamic performances
BW Small signal -3 dB bandwidth
Rl = 10 kΩ, Cl = 100 pF
kHz
TSC2011
Tmin < T < Tmax
500
250
620
TSC2012
Tmin < T < Tmax
330
170
415
SR Slew rate
Rl = 10 kΩ, Cl = 100 pF, Vicm = 1 V
V/µs
TSC2011, Vsense = 40 mV
Tmin < T < Tmax
2.7
2.5
3.5
TSC2012, Vsense = 24 mV
Tmin < T < Tmax
2.0
1.8
2.8
En
Noise, RTI
Spectral density, RTI
0.1 Hz to 10 Hz
f = 1 kHz
37
100
µVpp
nV/√Hz
Shutdown function (active high)
Vil Logical low level 0 0.3xVcc V
Vih Logical high level 0.7xVcc Vcc
Iih Leakage current Vshdn = Vcc (Shutdown mode) 0.9 µA
Ton Turn-on time
Vshdn= 2.7 V to 0 V, Rl = 10 kΩ
µs
TSC2011 6
TSC2012 8
Toff Turn-off time
Vshdn = 0 V to 2.7 V, Rl= 10 kΩ
µs
TSC2011 4
TSC2012 5
Iout Output leakage current Shdn active 50 nA
1. RTI stands for “Related to input”.
2. Vsense=(Vin+) – (Vin-).
TSC2011, TSC2012
Electrical characteristics
DS13057 - Rev 2 page 6/49
Table 5. Electrical characteristics (Vcc = 5 V, Vicm = 12 V, T = 25 °C unless otherwise specified)
Symbol Parameter Conditions Min. Typ. Max. Unit
Power supply
Icc
Current consumption Vicm = -20 to 70 V
Tmin < T < Tmax
1.6 2.4
2.4 mA
Current consumption with
shutdown active
Vicm = - 20 to 70 V
Tmin < T < Tmax
20 50
150 µA
SVR Supply voltage rejection Vcc = 2.7 to 5.5 V
Tmin < T < Tmax
80
75
100 dB
Input
|Vos|Offset voltage (RTI) (1)
Vicm = 1 V
Tmin < T < Tmax
200
700
µV
Vicm = 12 V
Tmin < T < Tmax
500
1100
|ΔVos/ΔT| Offset drift vs. temperature
Vicm = 1 V, Tmin < T < Tmax 5µV/°C
Vicm = 12 V, Tmin < T < Tmax 8
CMR Common mode rejection Vicm = -20 to 70 V, DC mode
Tmin < T < Tmax
90
85
120 dB
Iib+ Input bias current Vicm = 12 V
Tmin < T < Tmax, Vicm = -20 to 70 V -400
350
600 µA
Iib- Input bias current Vicm = 12 V
Tmin < T < Tmax, Vicm= - 20 to 70 V -150
100
350
|Vsense|Vsense operating range with
Eg ≤ 0.3% (2)
TSC2011
Tmin < T < Tmax
78
77.6 mV
TSC2012
Tmin < T < Tmax
46.9
45.7
Output
G Gain TSC2011 60 V/V
TSC2012 100
Eg Gain error vs. temperature ΔVout = 100 mV to (Vcc - 100 mV)
Tmin < T < Tmax
0.3
0.3 %
ΔEg/ΔT Gain error drift Tmin < T < Tmax 25 ppm/°C
NLE Linearity error Vicm = 12 V 0.03 %
Vcc - Voh Drop voltage output high Isource = 0.2 mA
Tmin < T < Tmax
15 30
35 mV
Vol Output voltage low Isink = 0.2 mA
Tmin < T < Tmax
26 40
50 mV
TSC2011, TSC2012
Electrical characteristics
DS13057 - Rev 2 page 7/49
Symbol Parameter Conditions Min. Typ. Max. Unit
Iout Output current
Sink mode
Tmin < T < Tmax
25
30
36 50
60
mA
Source mode
Tmin < T < Tmax
12
18
25 45
55
Reg Load Load regulation Iout = -10 to +10 mA 0.3 1.5 mV/mA
OFFSET adjustment
RtRatiometric accuracy 0.5 V/V
Acc Accuracy, RTO Voltage applied to Vref1 and Vref2 in
parallel 0.1 %
Dynamic performance
BW Small signal -3 dB bandwidth
Rl = 10 kΩ, Cl = 100 pF
kHz
TSC2011
Tmin < T < Tmax
600
300
750
TSC2012
Tmin < T < Tmax
390
200
490
SR Slew rate
Rl = 10 kΩ, Cl = 100 pF, Vicm = 1 V
V/µs
TSC2011, Vsense = 78 mV
Tmin < T < Tmax
6.2
4.8
8
TSC2012, Vsense = 47 mV
Tmin < T < Tmax
4.4
3.2
5.2
En
Noise, RTI
Spectral density, RTI
0.1 Hz to 10 Hz
f = 1 kHz
37
100
µVpp
nV/√Hz
Shutdown function (active high)
Vil Logical low level 0 0.3xVcc V
Vih Logical high level 0.7xVcc Vcc
Iih Leakage current Vshdn = Vcc (Shutdown mode) 1.2 µA
Ton Turn-on time
Vshdn= 5 V to 0 V, Rl = 10 kΩ
µs
TSC2011 6
TSC2012 8
Toff Turn-off time
Vshdn = 0 V to 5 V, Rl= 10 kΩ
µs
TSC2011 4
TSC2012 5
Iout Output leakage current Shdn active 50 nA
1. RTI stands for “Related to input”.
2. Vsense = (Vin+) – (Vin-).
TSC2011, TSC2012
Electrical characteristics
DS13057 - Rev 2 page 8/49
4.1 Typical characteristics
TSC2011 is used for typical characteristics, unless otherwise noted.
Figure 3. Supply current vs. supply voltage
2.8 3.1 3.5 3.9 4.2 4.5 4.9 5.32.8 3.5 4.2 4.9
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.4
1.6
1.8
Vicm=70V
Vicm=12V
Vref=Vcc/2
Vsense=0V
T=25°C
Vicm=2.5V
Vicm=0V
Supply Current (mA)
Supply voltage (V)
Figure 4. Supply current vs. input common mode
-20 -10 0 10 20 30 40 50 60 70-20 0 20 40 60
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.4
1.6
1.8
Vcc=2.7V
Vref=Vcc/2
Vsense=0V
T=25°C
Vcc=3.3V
Vcc=5V
Supply current (mA)
Vicm (V)
Figure 5. Supply current vs. temperature
-40 -20 0 20 40 60 80 100 120-40 0 40 80 120
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.4
1.6
1.8
Vicm=70V
Vicm=48V
Vicm=12V
Vref=Vcc/2
Vsense=0V
Vcc=5V
Vicm=-20V
Vicm=0V
Supply Current (mA)
Temperature (°C)
Figure 6. Supply current vs. input common mode with
active shutdown mode
-20 -10 0 10 20 30 40 50 60 70-20 0 20 40 60
0
2
4
6
8
10
12
14
16
18
20
22
24
0
4
8
12
16
20
24
Vcc=2.7V
Vref=Vcc/2
SHDN=Vcc
Vsense=0V
T=25°C
Vcc=5V
Vcc=3.3V
Supply Current (µA)
Vicm (V)
TSC2011, TSC2012
Typical characteristics
DS13057 - Rev 2 page 9/49
Figure 7. Input bias current vs. input common mode with
shutdown active
-20 -10 0 10 20 30 40 50 60 70-20 0 20 40 60
-400
-300
-200
-100
0
100
200
300
400
-400
-200
0
200
400
Vref=Vcc/2
SHDN=Vcc
Vsense=0V
T=25 °C
Vcc=2.7 to 5.5V
Iibp
Iibn
Iib (µA)
Vicm (V)
Figure 8. Input bias current vs. temperature VCC = 2.7 V
-20 -10 0 10 20 30 40 50 60 70-20 0 20 40 60
-600
-500
-400
-300
-200
-100
0
100
200
300
400
500
600
-600
-400
-200
0
200
400
600
Iibp -40 °C
Iibp 125°C
Vref=V
CC/2
Vsense=0V
Vcc=2.7V
Iibp 25°C
Iibn [-40° : 125°]
Iib (µA)
Vicm (V)
Figure 9. Input bias current vs. temperature with VCC = 5 V
-20 -10 0 10 20 30 40 50 60 70-20 0 20 40 60
-600
-500
-400
-300
-200
-100
0
100
200
300
400
500
600
-600
-400
-200
0
200
400
600
Iibp -40 °C
Iibp 125°C
Vref=Vcc/2
Vsense=0V
Vcc=5V
Iibp 25°C Iibn [ -40 °:125 °]
Iib (µA)
Vicm (V)
Figure 10. Input offset voltage vs. temperature
-40 -20 0 20 40 60 80 100 120-40 0 40 80 120
-700
-600
-500
-400
-300
-200
-100
0
100
200
300
400
500
600
700
-600
-400
-200
0
200
400
600
Vicm=70V
Vicm=48V
Vicm=0V
Vref=Vcc/2
Vsense=0V
Vcc=5V
Vicm=-20V
Vicm=12V
Vio (µV)
Temperature (°C)
TSC2011, TSC2012
Typical characteristics
DS13057 - Rev 2 page 10/49
Figure 11. Input offset voltage vs. input common mode
with VCC = 2.7 V
-20 -10 0 10 20 30 40 50 60 70
-700
-600
-500
-400
-300
-200
-100
0
100
200
300
400
500
600
700
T=-40°C
T=0°C
T=-20°C
T=85°C
Vref=Vcc/2
Vsense=0V
Vcc=2.7V
T=25°C
T=125°C
Vio (µV)
Vicm (V)
Figure 12. Input offset voltage vs. input common mode
with VCC = 5 V
-20 -10 0 10 20 30 40 50 60 70-20 0 20 40 60
-700
-600
-500
-400
-300
-200
-100
0
100
200
300
400
500
600
700
-600
-400
-200
0
200
400
600
T=-40°C T=0°C
T=-20°C
T=85 °C
Vref=Vcc/2
Vsense=0V
Vcc=5V
T=25 °C
T=125 °C
Vio (µV)
Vicm (V)
Figure 13. Input offset voltage vs. supply voltage
3.0 3.5 4.0 4.5 5.0 5.53.0 3.5 4.0 4.5 5.0 5.5
-500
-400
-300
-200
-100
0
100
200
300
400
500
-400
-200
0
200
400 Vicm=5V
Vicm=48V Vicm= -20V
Vicm=1V
Vicm= -10V
Vref=Vcc/2
Vsense=0V
T=25°C
Vicm=12V
Vicm=70V
Vio (µV)
Vcc (V)
Figure 14. Output current vs. output voltage
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.50.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
-40
-30
-20
-10
0
10
20
30
40
Isource
Isink
Vcc=5.5V
Vcc=2.7V
Vref=Vcc/2
Vsense=100mV
Vicm=12V
T=25°C
Vcc=3.3V
Iout (mA)
Vout (V)
TSC2011, TSC2012
Typical characteristics
DS13057 - Rev 2 page 11/49
Figure 15. Voh and Vol vs. input common mode voltage
with VCC = 5 V
-20 -10 0 10 20 30 40 50 60 70-20 0 20 40 60
0
9
17
26
34
43
0
17
34
Vcc=5V; Vref=Vcc/2
Vsense= 100mV
Rl=10kΩconnected to Vcc/2
T=25 °C
VOH
VOL
VOH and VOL drop (mV)
Vicm (V)
Figure 16. (Output voltage - Vref) vs. Vsense unidirectionnal
with VCC = 5 V
-10 0 10 20 30 40 50 60 70 80 900 20 40 60 80
-0.6
0.0
0.6
1.2
1.8
2.4
3.0
3.6
4.2
4.8
5.4
6.0
0.0
1.2
2.4
3.6
4.8
6.0
Vref=0V
Vcc=5V
T=25 °C
Unidirectionnal
Vout (V)
Vsense (mV)
Figure 17. (Output voltage - Vref) vs. Vsense bidirectionnal
with VCC = 5 V
-50 -40 -30 -20 -10 0 10 20 30 40 50-40 -20 0 20 40
-0.6
0.0
0.6
1.2
1.8
2.4
3.0
3.6
4.2
4.8
5.4
6.0
0.0
1.2
2.4
3.6
4.8
6.0
Vref=Vcc/2
Vcc=5V
T=25°C
Bidirectionnal
Vout (V)
Vsense (mV)
Figure 18. Output rail linearity vs. load with VCC = 5 V
-50
-45
-40
35
40
45
50
-50
-45
-40
35
40
45
50
-0.5
0.0
4.5
5.0
5.5
-0.5
0.0
4.5
5.0
5.5
No load
Rl=1kΩ
Rl=2kΩ
Rl=10k Ω
Vcc=5V
Vicm=12V
Vref=Vcc/2
T=25°C
Rl=4.7k Ω
Vout (V)
Vsense (mV)
TSC2011, TSC2012
Typical characteristics
DS13057 - Rev 2 page 12/49
Figure 19. Linearity vs. Vsense with VCC = 5 V
-50 -40 -30 -20 -10 0 10 20 30 40 50-50 -40 -30 -20 -10 0 10 20 30 40 50
-0.15
-0.12
-0.09
-0.06
-0.03
0.00
0.03
0.06
0.09
0.12
0.15
-0.15
-0.12
-0.09
-0.06
-0.03
0.00
0.03
0.06
0.09
0.12
0.15
Vicm=12V
Vicm=-10V
Vref=Vcc/2
Vcc=5V
T=25°C
Vicm=1V
Linearity error (%)
Vsense (mV)
Figure 20. Linearity vs. Vsense and temperature
-50 -40 -30 -20 -10 0 10 20 30 40 50
-0.15
-0.12
-0.09
-0.06
-0.03
0.00
0.03
0.06
0.09
0.12
0.15
T=125°C
T=-40°C
Vref=Vcc/2
Vcc=5V
Vicm=12V
T=25°C
Linearity error (%)
Vsense (mV)
Figure 21. Gain error vs. input common mode
-20 -10 0 10 20 30 40 50 60 70
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
0.25
0.30
Vcc=5V
Vref=Vcc/2
T=25°C
Vcc=2.7V
Vcc=3.3V
Gain error(%)
Vicm (V)
Figure 22. Gain error vs. input common mode and
temperature
-20 -10 0 10 20 30 40 50 60 70
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
0.25
0.30
T=-40°C
Vref=Vcc/2
Vcc=5V
T=25°C
T=125°C
Gain error(%)
Vicm (V)
TSC2011, TSC2012
Typical characteristics
DS13057 - Rev 2 page 13/49
Figure 23. Load regulation with VCC = 5 V
-15.0 -10.0 -5.0 0.0 5.0 10.0 15.0
1.10
1.15
1.20
1.25
1.30
Vicm=12V
Vicm=70V
Vicm=0V
Isource Isink
Vicm=-20V
Vref=Vcc/2
Vsense=19.8mV
Vcc=5V
T=25°C
Vout (V)
Iout (mA)
Figure 24. Gain vs. frequency
1 10 100 1000 10000
-40
-20
0
20
40
Gain (dB)
Frequency (kHz)
Vicm = 12 V, Vref = Vcc / 2
Rl = 10kΩ , Cl = 100 pF connected to Vcc / 2
Vcc = 3.3 V
Vcc = 2.7 V
Vcc = 5 V
Figure 25. Gain vs. frequency (VCC = 5 V)
1 10 100 1000 10000
-40
-20
0
20
40
Gain (dB)
Frequency (kHz)
Vicm = 12 V, Vref = Vcc / 2
RI = 10k Ω , Cl = 100pF connected to Vcc / 2
TSC2012
TSC2011
Figure 26. Gain vs. frequency for different load
1 10 100 1000 10000
-40
-20
0
20
40
Gain (dB)
Frequency (kHz)
Vcc=5V, Vicm=12V, Vref=Vcc/2
RI=10kΩ connected to Vcc/2
CI = 330 pF
CI = 100 pF
CI = 470 pF
TSC2011, TSC2012
Typical characteristics
DS13057 - Rev 2 page 14/49
Figure 27. Gain vs. different capacitive load (TSC2012)
1 10 100 1000 10000
-40
-20
0
20
40
Gain (dB)
Frequency (kHz)
Cl = 680 pF
Vcc = 5 V, Vicm = 12 V, Vref = Vcc / 2
RI = 10kΩ connected to Vcc / 2
Cl = 330 pF
Cl = 100 pF
Cl = 470 pF
Figure 28. Bandwidth vs. input common mode
-20 -10 0 10 20 30 40 50 60 70
0.0
100.0k
200.0k
300.0k
400.0k
500.0k
600.0k
700.0k
800.0k
900.0k
1.0M
1.1M
T = -40°C
Vref=Vcc/2
Vcc=5V
Rl=10kΩ , Cl=100pF connected to Vcc/2
T =125°C
T = 25°C
Bandwidth -3dB (Hz)
Vicm (V)
Figure 29. Bandwidth vs. input common mode (TSC2012)
-20 -10 0 10 20 30 40 50 60 70-20 0 20 40 60
0.0
100.0k
200.0k
300.0k
400.0k
500.0k
600.0k
700.0k
800.0k
900.0k
0.0
200.0k
400.0k
600.0k
800.0k
Vref = Vcc / 2
Vcc = 5 V
Rl = 10 kΩ , Cl = 100pF connected to Vcc / 2
T = 125 °C
Bandwidth -3dB (Hz)
Vicm (V)
T = 25 °C
T = - 40 °C
Figure 30. Overshoot vs. capacitive load
100 200 300 400 500 600 700
0
5
10
15
20
25
30
35
40
0
10
20
30
40
TSC2012
Vsense step = 6 mVpp
TSC2011
Vsense step = 10 mVpp
Vcc = 5 V,
Vref = Vcc / 2, Vicm [-20 V : 70 V],
Rl = 10 kΩ , Cl connected to Vcc / 2
Overshoot (%)
Capacitive load (pF)
TSC2011, TSC2012
Typical characteristics
DS13057 - Rev 2 page 15/49
Figure 31. Small signal response with VCC = 5 V
-60µ -40µ -20µ 0 20µ
-1.0
-0.5
0.0
0.5
1.0
-50
-25
0
25
50
Vout (V)
Time (s)
Vout
Vsense
Vcc=5V, Vicm=12V, Vsense=10mVpp
T=25°C, Cl=100pF
Vsense (mV)
Figure 32. Small signal response with VCC = 5 V
(TSC2012)
-60µ -40µ -20µ 0 20µ
-1.0
-0.5
0.0
0.5
1.0
-50
-25
0
25
50
Vout (V)
Time (s)
Vout
Vsense
Vcc = 5 V, Vicm = 12 V, Vsense = 6 mVpp
T = 25 °C, Cl = 100 pF
Vsense (mV)
Figure 33. Small signal response with VCC = 2.7 V
-60µ -40µ -20µ 0 20µ
-1.0
-0.5
0.0
0.5
1.0
-50
-25
0
25
50
Vout (V)
Time (s)
Vout
Vsense
Vcc=2.7V, Vicm=12V, Vsense=10mVpp
T=25°C, Cl=100pF
Vsense (mV)
Figure 34. Large signal response with VCC = 5 V
-5µ 0 5µ 10µ 15µ
-3
-2
-1
0
1
2
3
-50
-25
0
25
50
Vout (V)
Time (s)
Vout
Vsense
Vcc=5V,
Vicm=12V,
Vsense=80mVpp
Cl=100pF,
T=25°C
Vsense (mV)
TSC2011, TSC2012
Typical characteristics
DS13057 - Rev 2 page 16/49
Figure 35. Large signal response with VCC = 2.7 V
-5µ 0 5µ 10µ 15µ
-3
-2
-1
0
1
2
3
-50
-25
0
25
50
Vout (V)
Time (s)
Vout
Vsense
Vcc=2.7V,
Vicm=12V,
Vsense=40mVpp
Cl=100pF,
T=25°C
Vsense (mV)
Figure 36. 12 V common mode step response recovery
-10µ 0 10µ 20µ 30µ
-2
-1
0
1
2
3
4
5
-20
-15
-10
-5
0
5
10
15
20
Vout (V)
Time (s)
Vout
Vicm
Vcc=5V,
Vicm edge 10ns,
Vsense=0V, Vref=2.5V
Rl=10kΩ, Cl=100pF,
T=25°C
Vicm (V)
Figure 37. 50 V common mode step response recovery
-10µ 0 10µ 20µ 30µ
-2
-1
0
1
2
3
4
5
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
Vout (V)
Time (s)
Vout
Vicm
Vcc=5V,
Vicm edge 10ns,
Vsense=0V, Vref=2.5V
Rl=10kΩ, Cl=100pF,
T=25°C
Vicm (V)
Figure 38. PSRR vs. frequency
100 1k 10k 100k 1M 10M
0
-20
-40
-60
-80
-100
-120
Vcc=5V
Vcc=3.3V
Vcc=2.7V
Vicm=12V
Vripple=100mVpp
T=25°C
PSRR (dB)
Frequency (Hz)
TSC2011, TSC2012
Typical characteristics
DS13057 - Rev 2 page 17/49
Figure 39. CMRR vs. frequency
100 1k 10k 100k 1M 10M
0
-20
-40
-60
-80
-100
-120
Vcc=5V
Vcc=3.3V Vcc=2.7V
Vicm=12V
Vripple=100mVpp
T=25°C
CMRR (dB)
Frequency (Hz)
Figure 40. Positive overvoltage recovery VCC = 2.7 V
-3µ -2µ -1µ 0 1µ 2µ 3µ 4µ 5µ 6µ
-3
-2
-1
0
-200
-150
-100
-50
0
50
100
Vout (V)
Time (s)
Vout
Vsense
Vcc=2.7V,
Vicm=12V,
CI=100pF,
T=25°C
Vsense (mV)
Figure 41. Negative overvoltage recovery VCC = 2.7 V
-3µ -2µ -1µ 0 1µ 2µ 3µ 4µ 5µ 6µ
0
1
2
3
-100
-50
0
50
100
150
200
Vout (V)
Time (s)
Vout
Vsense
Vcc=2.7V,
Vicm=12V,
CI=100pF
T=25°C
Vsense (mV)
Lorem ipsum
Figure 42. Overvoltage recovery vs. Vicm, VCC = 5 V
-20 -10 0 10 20 30 40
0.0
0.3
0.5
0.8
1.0
1.3
1.5
1.8
2.0
Positive recovery time
Negative recovery time
Vref = Vcc / 2
Vcc = 5 V,
T = 25 °C
Vout = 100 mV drop after Vsense edge
Over Voltage Recovery (µs)
Vicm (V)
TSC2011, TSC2012
Typical characteristics
DS13057 - Rev 2 page 18/49
Figure 43. Noise vs. frequency
100m 1 10 100 1k 10k 100k 1M
1
10
100
1000
10000
Equivalent Input Voltage Noise (nV/√√Hz)
Frequency (Hz)
5V
2.7V
3.3V
Vicm=Vcc/2
Tamb=25°C
Figure 44. ON/OFF delay for shutdown mode
-10µ 0 10µ 20µ 30µ 40µ 50µ 60µ 70µ
-3
-2
-1
0
1
2
3
VSHDN
Vref=Vcc/2
Vsense=20mV,
Vcc=5V, Vicm=12V,
RI=10kΩ connected to Vcc-,
T=25°C
Vout
1V/div
Time (s)
Figure 45. Output voltage vs. Vsense beyond the sense
operating
-7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7
-4.0
-3.2
-2.4
-1.6
-0.8
0.0
0.8
1.6
2.4
3.2
4.0
Vout phase reversal for Vsense<-4V
Vref=Vcc/2
Vcc=5V
Vicm=12V
T=25°C
Vout (V)
Vsense (V)
Figure 46. Power up time delay
-40µ -20µ 0 20µ 40µ 60µ 80µ 100µ 120µ 140µ
-3
-2
-1
0
1
2
3
4
5
6
Vcc
Vref=0V
Vsense=20mV,
Vcc=5V, Vicm=12V,
RI=10kΩ, Cl=100pF connected to Vcc-,
T=25°C
Vout
1V/div
Time (s)
TSC2011, TSC2012
Typical characteristics
DS13057 - Rev 2 page 19/49
5Application information
5.1 Overview
The TSC2011 is especially designed to accurately measure the current by amplifying the voltage across a shunt
resistor connected to its input. This voltage drop Vsense is then amplified by an instrumentation amplifier providing
a max. input offset voltage of 500 µV (25°C) for an input common voltage of 12 V.
The TSC2011 is a fixed gain current sensing amplifier of 60 V/V. Thanks to a thin film resistor, the TSC2011 offers
an extremely precise gain and a very high CMRR performance even in a high frequency range. Moreover, by
fixing the output common mode voltage, the TSC2011 can be either used as unidirectional or bidirectional current
sensing amplifier.
The TSC2011 provides an extended input common range from - 20 V below the negative supply voltage, and up
to 70 V allowing either low-side or high-side current sensing, while the TSC2011 device can operate from 2.7 to
5.5 V.
The parameters are very stable in the full Vcc range and characterization curves show the TSC2011
characteristics at 2.7 V and 5.0 V. Moreover, the main specifications are guaranteed in an extended temperature
range from -40 to 125 °C.
5.2 Theory of operation
The main feature of the TSC2011 is the ability to work with an input common mode voltage largely beyond the
power supply Vcc range (2.7 V to 5.5 V). It is ideal, for example for automotive applications where a reverse
battery can be supported by the TSC2011 without any damage. It also works with 48 V battery applications as the
TSC2011 can support and measure the current on line at voltage up to 70 V. No additional protective components
are needed in that range.
•Vcc < Vicm < 70 V
In this case, the power supply of the TSC2011 is issued by the input and not only by the Vcc power supply. More
precisely, a current is drawn by the common mode rail as depicted in the Figure 47. Power supply when Vicm >
Vcc to power it.
Figure 47. Power supply when Vicm > Vcc
TSC2011, TSC2012
Application information
DS13057 - Rev 2 page 20/49
In Figure 48. Input bias current vs. common mode voltage Vcc = 5 V, the current used to power the TSC2011
increases together with the Vicm voltage. The slope represents the internal common mode resistances. The most
part of the current is drawn by the pin In+ as we can see on the iibp curve of Figure 9. Input bias current vs.
temperature with VCC = 5 V the current is around 450 µA. Some of it being Vicm / (R4+R1) and some supplies the
input stage of the circuit, roughly 250 µA. On the In- pin 250 µA is drawn only.
So due to the architecture of the TSC2011, the current to be measured must be much larger than the input bias
current. In case of small current to measure the Iib current must be taken into account.
Figure 48. Input bias current vs. common mode voltage Vcc = 5 V
-20 -10 0 10 20 30 40 50 60 70
-600
-500
-400
-300
-200
-100
0
100
200
300
400
500
600
Iibp
Vref=Vcc/2
Vsense=0V
Vcc=5V
Iibn
Iib (µA)
Vicm (V)
•Gnd < Vicm < Vcc
In this manner, the TSC2011 is only powered by the power supply Vcc, and the iib currents are very close to 0 µA
and do not have any impact on the current measurement.
•- 20 V < Vicm < Gnd
The TSC2011 is fully functional in this range of common mode voltage and has also been characterized.
As the high positive common mode voltage, in this specific range, the TSC2011 is also powered by the input, see
Figure 49. Power supply when Vicm < Gnd.
TSC2011, TSC2012
Theory of operation
DS13057 - Rev 2 page 21/49
Figure 49. Power supply when Vicm < Gnd
Most part of the current is still due to the pin In+ as we can see on the iibp curve of Figure 9. Input bias current vs.
temperature with VCC = 5 V. The current is about - 300 µA, some of it being Vicm / (R4 + R1) and some other
supplies the circuit, roughly 250 µA. A small part of the current, coming from the common mode rail, is also due to
the input In– in order to power the TSC2011, in a range of - 100 µV.
•Output common mode range
The TSC2011 output common mode voltage level can be set thanks to voltages applied on the Vref1 and Vref2
pins. These two pins allow the device to be set either in bidirectional or in unidirectional operation. The voltage
applied to those pins must not exceed the Vcc range. The different configurations are detailed in the section
Unidirectionnal/Bidirectionnal operation.
As depicted by the Figure 50. Vref powered by an external voltage source, Vref1 and Vref2 pins can be driven by
an external voltage source capable of sourcing/sinking a current following the equation below:
Iref =Vicm − Vref
5kΩ + 275kΩ + 25kΩ(1)
Figure 50. Vref powered by an external voltage source
TSC2011, TSC2012
Theory of operation
DS13057 - Rev 2 page 22/49
When the output common mode voltage is supplied by an external power supply, in order to improve the output
voltage measurement, it is recommended to measure the Vout differentially with respect to Vref voltage. It provides
a better CMRR measurement, better noise immunity and also a more accurate Vout voltage. A decoupling
capacitance of 1 nF minimum can be also added to better filter the power supply, and can also be used as a tank
capacitance in case an ADC is connected to this reference voltage.
TSC2011, TSC2012
Theory of operation
DS13057 - Rev 2 page 23/49
5.3 Unidirectionnal / bidirectionnal operation
•Unidirectional operation
Unidirectional mode of operation allows the device to measure the current through a shunt resistor in one
direction only. The output reference can be ground or Vcc and can be set by using Vref1 and Vref2 pins for
adjustment.
•Ground referenced
Figure 51. Output reference to ground
In this configuration Vref1 pin and Vref2 pin are connected together to the ground. The output common mode
voltage is then automatically set to GND when no current flows through the Rshunt resistance. This configuration
allows the full scale output in unidirectional mode. It allows a current to be measured as described in
Figure 51. Output reference to ground.
•Vcc referenced
Figure 52. Output reference to Vcc
TSC2011, TSC2012
Unidirectionnal / bidirectionnal operation
DS13057 - Rev 2 page 24/49
In this configuration Vref1 pin and Vref2 pin are connected together to the Vcc power supply. The output common
mode voltage is then automatically set to Vcc voltage when no current flows through the Rshunt resistance. This
configuration allows the full scale output in unidirectional mode. It measures the current as described in
Figure 52. Output reference to Vcc.
•Bidirectional operation
Bidirectional mode of operation allows the device to measure currents through a shunt resistor in two directions.
The output reference can be set anywhere within the power supply range. If the output common mode voltage is
set at mid-range, the full scale current measurement range is equal in both directions. This is achieved by
connecting one Vref pin to Vcc and the other Vref pin to Gnd as described by Figure 53. Split supply. It can be
done as well connecting both Vref pins to Vcc / 2 voltage as described by Figure 54. External supply. In case the
current measurement is not equal in both directions, user can set the output in a non-symmetrical configuration,
adjusting Vref according to the user's needs.
•Split supply
Figure 53. Split supply
The great advantage of this configuration, is that the TSC2011 can be used in bidirectional mode with an output
common mode voltage set at the middle of scale, with an accuracy of 0.1%, without any added external
component or power supply. This configuration creates a midscale offset ratiometric to the power supply.
TSC2011, TSC2012
Unidirectionnal / bidirectionnal operation
DS13057 - Rev 2 page 25/49
•External
Figure 54. External supply
In this configuration, Vref1 pin and Vref2 pin are connected together to a reference voltage. The output common
mode voltage is then automatically set to this reference voltage value when no current flows through the Rshunt
resistance. This configuration adjusts the output offset as needed by the application. A DAC for calibration of the
analog chain could also be used.
5.4 RSENSE selection
The selection of the shunt resistor is a tradeoff between the dynamic range and power dissipation.
Generally, in high current sensing application, the main focus is to reduce as much as possible the power
dissipation (I²R) by choosing the smallest value of shunt. It could be quite easy if a full scale current to measure is
small.
In low current applications the Rsense value could be higher, to minimize the impact of the offset voltage on the
circuit. Due to input bias current of several µA, the TSC2011 cannot measure the current in the same range, when
the common mode voltage overpasses the power supply voltage (refer to section about theory of operation).
The tradeoff is mainly when a dynamic range of current to measure is large, meaning ability to measure with the
same shunt value from low current to high current. Generally, the current full scale (Imax-Imin) defines the shunt
value thanks to the full output voltage range, the gain of the TSC2011. The TSC2011 can work with a full scale
∆Vout = 100 mV to Vcc - 100 mV with maximum gain accuracy of 0.3%.
At first order, the full current range to measure through Rsense can be defined by equation 2, just by taking the
gain error and input offset voltage as inaccuracy parameters:
Isense_full_scale*Rsense =Vcc − 200mV
TSC_Gain 1 + Eg −2Vio (2)
The Vsense parameter is defined in the electrical characteristics following the equation 2.
Its purpose is to highlight that the product Rsense*TSC_gain is determined by the application, and that once one of
these two parameters is selected, the maximum value of the second one can be calculated.
• If power dissipation in the shunt is the key point, RSense should be chosen as follows:
Rsense ≤ Pmax
Imax²
and then choosing the right gain. For example, for high current to sense, the TSC2012 can offer a gain of
100, in this manner a smaller shunt can be used and so limited power losses. However accuracy can be
lower.
• Or choosing the product available on the shelf, and then size the shunt resistor value accordingly.
TSC2011, TSC2012
RSENSE selection
DS13057 - Rev 2 page 26/49
5.5 Input offset voltage drift overtemperature
The maximum input offset voltage drift overtemperature is defined as the offset variation related to the offset value
measured at 25 °C. The signal chain accuracy at 25 °C can be compensated during production at application
level. The maximum input voltage drift overtemperature enables the system designer to anticipate the effect of
temperature variations.
The maximum input voltage drift over temperature is computed using equation 3:
ΔVio
ΔT= max Vio T − Vio 25°C
T − 25°C(3)
Where T = -40 °C and 125 °C.
The TSC2011 datasheet maximum value is guaranteed by measurements on a representative sample size
ensuring a Cpk (process capability index) greater than 1.3.
TSC2011, TSC2012
Input offset voltage drift overtemperature
DS13057 - Rev 2 page 27/49
5.6 Error calculation
The principal source of error, such as: input offset voltage, gain error, common mode rejection ration, are
described separately in the electrical characteristics. This chapter summarizes the most important error to take
into account during a design phase.
•Input offset voltage error
The equation 2 depicts a first order error calculation just by taking into account the input offset voltage. In a
temperature environment, the deviation of the Vio and the error linked to the input offset on the output voltage can
be written as equation 4:
VioError = ± Vio ±Dvio/Dt *Gain (4)
•Gain error and shunt resistance accuracy
Gainerror =Gain 1 + εgain (5)
Rsenseerror =Gain 1 + εRsense (6)
Where εgain is the gain error 0.3% max for the TSC2011.
Where εRsense is the shunt resistance error. Shunt resistors from 5 mΩ to 100 mΩ are available with 1%
accuracy or better.
•CMR error
In the electrical characteristics, CMR is specified at one input common mode voltage. So in order to take into
consideration the variation of the input voltage offset depending the Vicm, the calculus must be done till this known
point. Let us get the Vicm = 12 V as reference point.
So the error on Vout due to a common mode voltage variation can be written as the equation 7:
CMRerror = ± Vicm − 12V
CMR *Gain (7)
•Output common mode error (Vocm)
This error can be taken into account when the output common mode voltage is set like suggested in the
Figure 55. Schematic for Vocm error, and so by using the internal divider bridge. Otherwise it is important to take
into consideration the error linked to the voltage source applied on the VRef1 pin and Vref2 pin.
Figure 55. Schematic for Vocm error
The divider bridge is made by two resistances of 50 kΩ given an output common mode voltage of:
Vref1 + Vref2
2
TSC2011, TSC2012
Error calculation
DS13057 - Rev 2 page 28/49
Due to a small mismatch of the internal resistance the error, on the output common mode voltage, can be
described as equation 8:
Vocm =Vref1+Vref2
2. 1 + εAcc (8)
Where εAcc is the accuracy referred to the output with a typical value of 0.1%.
•Noise
The Figure 43. Noise vs. frequency expresses the noise referred to the input of the TSC2011. This device shows
a 1/f noise until 10 kHz frequency. Above this limit the white noise density is 29 nV/ Hz , until the bandwidth of
the TSC2011.
The noise can be then expressed as two terms, the former related to the 1/f noise and the latter due to the white
noise. If we consider that there is no additional filter on the TSC2011 and it is only bandwidth limited, it can be
considered that over the 750 kHz, there is an attenuation of the noise with a first order filtering. So the equivalent
noise bandwidth is 750kHz .π
2 .
The RMS value of the output noise is the integration of the spectral noise over the bandwidth of interest and can
be expressed as equation 9:
enRMS =∫
0.1
10000 29 . 10−9
f
10 . 103
2
df +∫
0.1
750000 . π
229 . 10−92df *Gain (9)
•Total error
The maximum total error expected on the output of the device can be described as the sum of the different source
described just above. The total output accuracy can be written as equation 10.
Vouterr =Gain*Rsense*Iload εgain +εRsense +Gain .Vio +Gain .Vicm − 12V
CMR +
Vocm εAcc +noise
(10)
Iload is described in Figure 56. Input current and the output noise is described by the equation 9.
Note that the input bias currents are not taken into account in this section, as they are already integrated in the
Vsense. The Figure 56. Input current below depicts the current flowing from the source to the load when the input
common mode voltage is higher than the supply voltage.
Figure 56. Input current
From a calculation approach, when Vicm voltage is beyond Vcc, Iload must be considered as the sum of Isource and
Input bias current (Iib). Note that the input bias current on the pin – is largely lower and can be neglected.
The Figure 56. Input current also expresses that the TSC2011 cannot measure the current in the same order as
input bias current (several hundreds of µA).
TSC2011, TSC2012
Error calculation
DS13057 - Rev 2 page 29/49
The linearity is not taken into account in the error calculus as it represents 0.03% of error only and it is negligible.
Nevertheless, as the gain error has been calculated thanks to the best fit line approach, it gives the information
that the gain error can be relatively constant throughout the linear input range of the TSC2011.
The equation 10 has been described for a temperature of 25 °C. For sure with a temperature variation, Dvio/DT
error term must be added. And if the power supply is susceptible to change, the SVR parameter must also be
taken into account.
•Example
Let us consider that the maximum total error can happen on the output of the TSC2011.
•Use case:
– Vcc = 5 V
– Vicm = 24 V
– Vocm = 2.5 V
– Temperature = 25 °C
– Iload = 5 A
– Shunt 5 mΩ with 1% accuracy
Theoretically the expected output voltage should be Vout = Rshunt * Iload *60 + Vocm = 4 V.
From the equations above, all the error terms are detailed by using the maximum value of the electrical
characteristics (when available), in order to express as much as possible, the worst case condition. The % error
on output of the following table is expressed in reference of Vout – Vref, so in this typical example: 1.5 V.
Table 6. Gain error
Error source Calculus Output voltage error % error on
output
Gain error 60*5 . 10−3*5*0.3% 4.5 mV 0.3%
Vio error 60*500µV30 mV 2%
CMRR error 60*24V−12V
1090
20
22.7 mV 1.5%
Vocm error 2.5*0.1% 2.5 mV 0.2%
Noise 60*29nV
Hz 10kHz* ln 10k − ln 0.1 + 750kHz*π
2−0.1Hz 1.98 mVRMS 0.4% (1)
Total
60 mV
+1.98 mVRMS
4.4%
1. The percentage is based on voltage peak value, which is 3 times RMS value.
So the maximum output voltage in the worst case condition at ambient temperature is 4.060 V + 1.98 mVRMS
instead of 4 V expected. This represents an error on the current reading about 4.4%. 1% more must be added
due to the shunt accuracy.
This calculus comes from all the maximum values and all the error terms which have been added to each other,
meaning that the chance to get 4.4% precision in the use case above is extremely low and on the whole
population, the error is largely smaller.
5.7 Shutdown mode
If the SHDN pin is driven between 0.7 x Vcc and Vcc the TSC2011 enters low power shutdown mode, drawing less
than 20 µA, over the Vcc and Vicm range. In SHDN mode the output is in HiZ state.
TSC2011, TSC2012
Shutdown mode
DS13057 - Rev 2 page 30/49
Although there is an internal current source of 500 nA on the SHDN pin, keeping a low state allowing the
TSC2011 to work without any voltage applied on the SHDN pin, it is strongly recommended to apply the dedicated
voltage on the SHDN pin to ensure the full functionality of the TSC2011, especially when fast common mode
variation appears.
The figure below depicts the architecture of the SHDN pin.
Figure 57. SHDN pin
• With GND applied to SHDN pin the TSC2011 is in active mode
• With Vcc applied to SHDN pin the TSC2011 is in shutdown mode
5.8 Stability
•Driving switched capacitive loads
Some ADCs get their signal thanks to a sample and hold capacitor. If before a sampling this capacitance is fully
discharged, a fast current load can appear on the output of the TSC2011 during the sampling phase.
The scope probe in the figure below shows the output voltage of the TSC2011 excited by a 40 pF capacitor with a
3.3 Vpp signal at 50 kHz to simulate the sample and hold circuit of the ADC120.
Figure 58. Capacitive load response at Vcc = 3.3 V
-4µ 0 4µ 8µ 12µ
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7
8
-1000
-900
-800
-700
-600
-500
-400
-300
-200
-100
0
100
200
300
400
500
600
700
800
900
1000
Simulated Sample and Hold (V)
Time (s)
Sample and hold
Vout
Vcc=3.3V, Vicm=1.65V, Vsense=0Vpp
T=25°C,
50kHz square signal of 3.3V amplitude
injected in the output through 40pF
Vout (mV)
The ADC120 has a conversion rate of 50 ksps, which is perfect to sample and hold the output of the TSC2011
without any error.
The graph shows the behavior of the output of the TSC2011 under the worst case condition, as for example,
when there is an ADC120 channel change between two measurements.
TSC2011, TSC2012
Stability
DS13057 - Rev 2 page 31/49
If a single channel is used, for sure the change on the sample and hold capacitance are very small, and so the
recovery time is extremely low as described by the figure below.
Figure 59. Capacitive load response at Vcc = 3.3 V with a step of 100 mV
-4µ 0 4µ 8µ 12µ
-100
-80
-60
-40
-20
0
20
40
60
80
100
-1000
-900
-800
-700
-600
-500
-400
-300
-200
-100
0
100
200
300
400
500
600
700
800
900
1000
Simulated Sample and Hold (mV)
Time (s)
Sample and hold
Vout
Vcc=3.3V, Vicm=1.65V, Vsense=0Vpp
T=25°C,
50kHz square signal of 100mV amplitude
injected in the output through 40pF
Vout (mV)
The effect of the ADC sampling and hold can be easily smoothed thanks to an RC filter. As suggested on the
schematic below. The capacitor of the external filter must be chosen much higher than the internal ADC capacitor,
in order to easily absorb the sudden voltage variation on the output due to the sampling and hold of the ADC. The
resistance must be chosen accordingly to the application speed of the system in order not to impact the whole
application. The main advantage of using an RC filter is to have an antialiasing system. For sure the used ADC
must have sample and hold conversion in accordance with the RC filter value, in order to let the output recover
before sampling.
Figure 60. RC filter when driving ADC
In the figure Figure 61. Capacitive load response at Vcc = 3.3 V with 720 kHz RC filter an Rs = 470 Ω resistance
and a Ct = 470 pF capacitance have been set. Given a low-pass filter of 720 kHz and a response time of roughly
660 ns.
In the figure Figure 62. Capacitive load response at Vcc = 3.3 V with 194 kHz RC filter an Rs = 820 Ω resistance
and a Ct = 1 nF capacitance have been set. Given a low-pass filter of 194 kHz and a response time of roughly 2.5
µs.
TSC2011, TSC2012
Stability
DS13057 - Rev 2 page 32/49
Figure 61. Capacitive load response at Vcc = 3.3 V with
720 kHz RC filter
-4µ 0 4µ 8µ 12µ
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7
8
-1000
-900
-800
-700
-600
-500
-400
-300
-200
-100
0
100
200
300
400
500
600
700
800
900
1000
Simulated Sample and Hold (V)
Time (s)
Sample and hold
Vout
Vcc=3.3V, Vicm=1.65V, Vsense=0Vpp
T=25°C,
Rs=470Ω,Ct=470pF
50kHz square signal of 3.3V amplitude
injected in the output through 40pF
Vout (mV)
Figure 62. Capacitive load response at Vcc = 3.3 V with
194 kHz RC filter
-4µ 0 4µ 8µ 12µ
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7
8
-1000
-900
-800
-700
-600
-500
-400
-300
-200
-100
0
100
200
300
400
500
600
700
800
900
1000
Simulated Sample and Hold (V)
Time (s)
Sample and hold
Vout
Vcc=3.3V, Vicm=1.65V, Vsense=0Vpp
T=25°C,
Rs=820Ω,Ct=1nF
50kHz square signal of 3.3V amplitude
injected in the output through 40pF
Vout (mV)
The value of the added external capacitor must be taken into account. Indeed, if this one is chosen with an
excessive value and the serial resistance with a too small value, the risk of instability on the output of the
TSC2011 is high.
•Driving large capacitive Cload
Increasing the load capacitance produces gain peaking in the frequency response, with an overshoot and ringing
in the step response.
The figure below, shows the serial resistors that must be added to the output, to make a system stable. The
chosen criteria ensures the stability of the system and it is an overshoot lower than 24%.
Figure 63. Stability criteria with a serial resistor at VCC = 5 V
0.1 1 10 100
0
100
200
300
400
500
Stable
Vcc=5V, Vicm=0V,
Vref=Vcc/2,
T=25°C,
Unstable
Serial Resistor (Ohm)
Capacitive Load (nF)
TSC2011, TSC2012
Stability
DS13057 - Rev 2 page 33/49
5.9 Power supply recommendation
In order to decouple correctly the TSC2011, a 100 nF bypass capacitor can be placed between Vcc and Gnd. This
capacitor must be placed as closer as possible to the supply pins. The figure below shows a start-up time with a
decoupling capacitance of 100 nF.
Figure 64. Start-up time with a decoupling capacitance of 100 nF
-200µ 0 200µ 400µ 600µ 800µ
-3
-2
-1
0
1
2
3
4
5
6
Vcc
Vref=0V
Vsense=20mV,
Vcc=5V, Vicm=12V,
RI=10k Ω, Cl=10pF connected to Vcc-,
T=25°C
Vout
Voltage (V)
Time (s)
Vref pin is used to fix the output common mode voltage and it is driven by a low impedance voltage source and
can be decoupled thanks to a 10 nF bypass capacitor.
A greater bypass capacitor added on Vcc pin and Vref pin helps to enhance CMRR and PSRR performance.
5.10 PCB layout recommendations
The layout of the PCB tracks connected to the current sensing, load and power supply is very important. It is a
good practice to use short and wide PCB traces to minimize voltage drops and parasitic inductance.
When a shunt resistance, lower than 1 Ω, is used, a 4-wire connection technique should be used to sense the
current as described in the schematic below. This technique separates pairs of current carrying and voltage-
sensing electrodes to make more accurate measurements by eliminating the lead and contact resistance from the
measurement.
The track connected to the input pin of the TSC2011 has to be considered as a differential pair, it must have the
same length and width, and ideally placed on the same PCB plane, and above all must be routed as far as
possible from noisy source. As this track carries the input bias current, in a range of hundreds of µA, it can be
designed small but always by taking care of its resistivity. Any via in these input tracks are non-recommended to
avoid any parasitic resistance in this path.
To minimize parasitic impedance over the entire surface, a multi-via technique that connects the bottom and top
layer ground planes together in many locations is often used.
A ground plane generally helps to reduce EMI, that is why a multilayer PCB use is suggested as well as the
ground planes as a shield to protect the internal track. In this case, the digital from the analog ground must be
separated and any ground loop must be avoided. Loop area or antenna must be reduced to minimize EMI impact.
The Figure 65. Recommended layout suggests a possible routing for the TSC2011, in order to minimum parasitic
effect.
TSC2011, TSC2012
Power supply recommendation
DS13057 - Rev 2 page 34/49
Figure 65. Recommended layout
5.11 EMI rejection ration (EMIRR)
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of current sensing
device. An adverse effect that is common to many current sensing is a change in the offset voltage as a result of
RF signal rectification. A first order internal low pass filter is included on the input of the TSC2011 to minimize
susceptibility to EMIRR. Figure below shows the EMIRR on pin IN+, the EMIRR on pin IN- of the TSC2011
measured from 400 MHz up to 2.4 GHz.
Figure 66. EMIRR on pin+
400 600 800 1000 1200 1400 1600 1800 2000 2200 2400
0
20
40
60
80
100
120
Vcc=5V, T=25°C
Prf=-10dBm
EMIRR In+(dB)
Frequency (MHz)
Figure 67. EMIRR on pin-
400 600 800 1000 1200 1400 1600 1800 2000 2200 2400
0
20
40
60
80
100
120
Vcc=5V, T=25°C
Prf=-10dBm
EMIRR In-(dB)
Frequency (MHz)
TSC2011, TSC2012
EMI rejection ration (EMIRR)
DS13057 - Rev 2 page 35/49
5.12 Overload recovery
Overload recovery is defined as the time required for the current sensing output to recover from a saturated state
to a linear state.
The saturation state occurs when the output voltage gets very close to rails in the application. It results from an
excessive input voltage.
When the output of the TSC2011 enters saturation state, less than 1 µs is needed to get back to a linear state as
shown by Figure 68. Negative overvoltage recovery VCC = ± 2.5 V and Figure 69. Positive overvoltage recovery
VCC = ± 2.5 V.
Figure 40. Positive overvoltage recovery VCC = 2.7 V and Figure 41. Negative overvoltage recovery VCC = 2.7 V
show the overvoltage recovery for a VCC = 2.7 V.
Figure 68. Negative overvoltage recovery VCC = ± 2.5 V
-3µ -2µ -1µ 0 1µ 2µ 3µ 4µ 5µ 6µ
-3
-2
-1
0
-200
-150
-100
-50
0
50
100
Vout (V)
Time (s)
Vout
Vsense
Vcc=2.7V,
Vicm=12V,
CI=100pF,
T=25°C
Vsense (mV)
Figure 69. Positive overvoltage recovery VCC = ± 2.5 V
-3µ -2µ -1µ 0 1µ 2µ 3µ 4µ 5µ 6µ
0
1
2
3
-100
-50
0
50
100
150
200
Vout (V)
Time (s)
Vout
Vsense
Vcc=2.7V,
Vicm=12V,
CI=100pF
T=25°C
Vsense (mV)
Lorem ipsum
TSC2011, TSC2012
Overload recovery
DS13057 - Rev 2 page 36/49
5.13 Application examples
5.13.1 Half-bridge motor control
The half-bridge topology is very popular in motor control, DC-DC converters, LED lighting control and other
bidirectional loads from a single supply potential.
The TSC2011 provides a feedback control system about current but also detects overload conditions.
The Figure 70. Half-bridge application describes a typical schematic using the TSC2011 in a motor control
application. A 20 mΩ shunt resistance in series with the motor monitors a measurable voltage drop representing
the load current, and the TSC2011 amplifies the Vsense in order to give some information about the current flowing
into the motor in real time. These information are then digitalizing by the 12-bit ADC (ADC120).
Figure 70. Half-bridge application
General overview:
To make the motor rotation occur, the NMOS H1, H2, L1, L2 are driven by a half-bridge quad power MOSFET
driver. We have to consider that the current flows from the 12 V to the GND, through H1 NMOS and L2 NMOS. A
PWM is applied on the NMOS L2 in order to control the current and thus the speed of the motor.
By PWM, the average voltage applied on the motor is controlled. H1 remains always ON and the PWM is applied
on L2. When L2 is turned off, H2 must be turned ON, for freewheeling, allowing the discharge of the motor
inductance current. This phenomenon generates a fast input common mode voltage transition on the TSC2011,
from 0 V to 12 V.
Thanks to a good recovery time due to fast input common mode change, the TSC2011 follows the current flowing
into the motor as depicted by the scope probe in Figure 71. TSC2011 H Bridge application.
The black curve represents the fast Vicm variation step of 12 V in 500 ns when the freewheeling is activated. The
blue curve represents the current flowing into the motor measured with a current probe.
The red curve represents the output voltage - 1.35 V (Vref voltage) of the TSC2011 probe after the RC filter.
The RC filter, used to drive the ADC120, smooths a bit the output signal and adds a small constant time, in the
range of 1 µs.
TSC2011, TSC2012
Application examples
DS13057 - Rev 2 page 37/49
Figure 71. TSC2011 H Bridge application
-50µ -40µ -30µ -20µ -10µ 0 10µ 20µ 30µ 40µ 50µ
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
-0.48
-0.24
0.00
0.24
0.48
0.72
0.96
1.20
input current (A)
Time (s)
Vicm variation from 0V to 12V
Vout
Current flowing into the motor
Vout - Vref (V)
After a fast variation of the input common mode, the TSC2011 needs less than 5 µs to recover its normal
behavior.
5.13.2 Solenoid valve
In automotive applications, the automatic transmission relies on bands and clutches to change gears, and the
only way they can be applied is by fluid pressure. The transmission solenoid is responsible for opening or closing
valves in the valve body to allow transmission fluid to enter, at which point the fluid can pressurize the clutches
and bands. Solenoids consist of a spring loaded plunger wrapped with a coil of wire, and it is generally driven
thanks to a MOS transistor.
In the schematic below the TSC2011 is used in mono directional mode. When the MOS is ON, the current can
flow through the solenoid and actuate this one. The input common mode is high in this case.
When the MOS is turned OFF, as the current stored into the solenoid cannot stop instantaneously, the diode turns
ON allowing a freewheeling to discharge the solenoid resulting in a common mode one diode voltage drop below
ground.
Thanks to its large input common mode range, the TSC2011 can be used for such applications depicted in figure
below.
In order not to saturate the output when no current is flowing into Rsense, a small voltage on Vref has to be applied.
TSC2011, TSC2012
Application examples
DS13057 - Rev 2 page 38/49
Figure 72. Solenoid valve application
TSC2011, TSC2012
Application examples
DS13057 - Rev 2 page 39/49
6Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
TSC2011, TSC2012
Package information
DS13057 - Rev 2 page 40/49
6.1 SO8 package information
Figure 73. SO8 package outline
Table 7. SO-8 mechanical data
Dim.
mm Inches
Min. Typ. Max. Min. Typ. Max.
A 1.75 0.069
A1 0.1 0.25 0.004 0.01
A2 1.25 0.049
b 0.28 0.48 0.011 0.019
c 0.17 0.23 0.007 0.01
D 4.8 4.9 5 0.189 0.193 0.197
E 5.8 6 6.2 0.228 0.236 0.244
E1 3.8 3.9 4 0.15 0.154 0.157
e 1.27 0.05
h 0.25 0.5 0.01 0.02
L 0.4 1.27 0.016 0.05
L1 1.04 0.04
k 0 8 ° 1 ° 8 °
ccc 0.1 0.004
TSC2011, TSC2012
SO8 package information
DS13057 - Rev 2 page 41/49
6.2 MiniSO8 package information
Figure 74. MiniSO8 package outline
Table 8. MiniSO8 mechanical data
Dim. Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 1.1 0.043
A1 0 0.15 0 0.006
A2 0.75 0.85 0.95 0.03 0.033 0.037
b 0.22 0.4 0.009 0.016
c 0.08 0.23 0.003 0.009
D 2.8 3 3.2 0.11 0.118 0.126
E 4.65 4.9 5.15 0.183 0.193 0.203
E1 2.8 3 3.1 0.11 0.118 0.122
e 0.65 0.026
L 0.4 0.6 0.8 0.016 0.024 0.031
L1 0.95 0.037
L2 0.25 0.01
k 0° 8° 0° 8°
ccc 0.1 0.004
TSC2011, TSC2012
MiniSO8 package information
DS13057 - Rev 2 page 42/49
7Ordering information
Table 9. Order codes
Order code Gain (V/V) Package Packaging Marking
TSC2011IDT 60 SO8
Tape and reel
TSC2011
TSC2011IST MiniSO8 O118
TSC2012IDT 100 SO8 TSC2012
TSC2012IST MiniSO8 O119
TSC2011, TSC2012
Ordering information
DS13057 - Rev 2 page 43/49
Revision history
Table 10. Document revision history
Date Revision Changes
11-Sep-2019 1 Initial release.
30-Jan-2020 2
Added new part number TSC2012, Figure 25. Gain vs. frequency (VCC = 5 V),
Figure 27. Gain vs. different capacitive load (TSC2012), Figure 29. Bandwidth vs.
input common mode (TSC2012) and Figure 32. Small signal response with VCC = 5 V
(TSC2012).
Updated description on the cover page, Figure 30. Overshoot vs. capacitive load,
Figure 42. Overvoltage recovery vs. Vicm, VCC = 5 V, Table 4. Electrical
characteristics Vcc = 2.7 V, Vicm = 12 V, T = 25 °C (unless otherwise specified).,
Table 5. Electrical characteristics (Vcc = 5 V, Vicm = 12 V, T = 25 °C unless otherwise
specified) and Table 9. Order codes.
TSC2011, TSC2012
DS13057 - Rev 2 page 44/49
Contents
1Diagram ...........................................................................2
2Pin configuration ..................................................................3
3Maximum ratings ..................................................................4
4Electrical characteristics...........................................................5
4.1 Typical characteristics...........................................................9
5Application information...........................................................20
5.1 Overview ....................................................................20
5.2 Theory of operation............................................................20
5.3 Unidirectionnal / bidirectionnal operation ..........................................24
5.4 RSENSE selection..............................................................26
5.5 Input offset voltage drift overtemperature..........................................26
5.6 Error calculation ..............................................................28
5.7 Shutdown mode ..............................................................30
5.8 Stability......................................................................31
5.9 Power supply recommendation ..................................................33
5.10 PCB layout recommendations ...................................................34
5.11 EMI rejection ration (EMIRR)....................................................35
5.12 Overload recovery.............................................................36
5.13 Application examples ..........................................................37
5.13.1 Half-bridge motor control..................................................37
5.13.2 Solenoid valve..........................................................38
6Package information..............................................................40
6.1 SOT23-3L package information..................................................41
6.2 MiniSO8 package information ...................................................41
7Ordering information .............................................................43
Revision history .......................................................................44
TSC2011, TSC2012
Contents
DS13057 - Rev 2 page 45/49
List of tables
Table 1. Pin description......................................................................3
Table 2. Absolute maximum ratings .............................................................4
Table 3. Operating conditions .................................................................4
Table 4. Electrical characteristics Vcc = 2.7 V, Vicm = 12 V, T = 25 °C (unless otherwise specified). ..................5
Table 5. Electrical characteristics (Vcc = 5 V, Vicm = 12 V, T = 25 °C unless otherwise specified)....................7
Table 6. Gain error ........................................................................ 30
Table 7. SO-8 mechanical data ...............................................................41
Table 8. MiniSO8 mechanical data .............................................................42
Table 9. Order codes ......................................................................43
Table 10. Document revision history ............................................................. 44
TSC2011, TSC2012
List of tables
DS13057 - Rev 2 page 46/49
List of figures
Figure 1. Block diagram ....................................................................2
Figure 2. Pin connection (top view) .............................................................3
Figure 3. Supply current vs. supply voltage .......................................................9
Figure 4. Supply current vs. input common mode ...................................................9
Figure 5. Supply current vs. temperature .........................................................9
Figure 6. Supply current vs. input common mode with active shutdown mode ...............................9
Figure 7. Input bias current vs. input common mode with shutdown active ................................. 10
Figure 8. Input bias current vs. temperature VCC = 2.7 V .............................................10
Figure 9. Input bias current vs. temperature with VCC = 5 V ........................................... 10
Figure 10. Input offset voltage vs. temperature..................................................... 10
Figure 11. Input offset voltage vs. input common mode with VCC = 2.7 V................................... 11
Figure 12. Input offset voltage vs. input common mode with VCC = 5 V .................................... 11
Figure 13. Input offset voltage vs. supply voltage ................................................... 11
Figure 14. Output current vs. output voltage ...................................................... 11
Figure 15. Voh and Vol vs. input common mode voltage with VCC = 5 V .................................... 12
Figure 16. (Output voltage - Vref) vs. Vsense unidirectionnal with VCC = 5 V ................................. 12
Figure 17. (Output voltage - Vref) vs. Vsense bidirectionnal with VCC = 5 V .................................. 12
Figure 18. Output rail linearity vs. load with VCC = 5 V................................................ 12
Figure 19. Linearity vs. Vsense with VCC = 5 V ..................................................... 13
Figure 20. Linearity vs. Vsense and temperature .................................................... 13
Figure 21. Gain error vs. input common mode ..................................................... 13
Figure 22. Gain error vs. input common mode and temperature ......................................... 13
Figure 23. Load regulation with VCC = 5 V ........................................................ 14
Figure 24. Gain vs. frequency ................................................................14
Figure 25. Gain vs. frequency (VCC = 5 V)........................................................ 14
Figure 26. Gain vs. frequency for different load ....................................................14
Figure 27. Gain vs. different capacitive load (TSC2012) ..............................................15
Figure 28. Bandwidth vs. input common mode .....................................................15
Figure 29. Bandwidth vs. input common mode (TSC2012).............................................15
Figure 30. Overshoot vs. capacitive load ......................................................... 15
Figure 31. Small signal response with VCC = 5 V ................................................... 16
Figure 32. Small signal response with VCC = 5 V (TSC2012) ........................................... 16
Figure 33. Small signal response with VCC = 2.7 V .................................................. 16
Figure 34. Large signal response with VCC = 5 V ................................................... 16
Figure 35. Large signal response with VCC = 2.7 V .................................................. 17
Figure 36. 12 V common mode step response recovery ..............................................17
Figure 37. 50 V common mode step response recovery ..............................................17
Figure 38. PSRR vs. frequency ...............................................................17
Figure 39. CMRR vs. frequency ............................................................... 18
Figure 40. Positive overvoltage recovery VCC = 2.7 V ................................................18
Figure 41. Negative overvoltage recovery VCC = 2.7 V ............................................... 18
Figure 42. Overvoltage recovery vs. Vicm, VCC = 5 V................................................. 18
Figure 43. Noise vs. frequency................................................................ 19
Figure 44. ON/OFF delay for shutdown mode .....................................................19
Figure 45. Output voltage vs. Vsense beyond the sense operating ........................................ 19
Figure 46. Power up time delay ............................................................... 19
Figure 47. Power supply when Vicm > Vcc ........................................................ 20
Figure 48. Input bias current vs. common mode voltage Vcc = 5 V ....................................... 21
Figure 49. Power supply when Vicm < Gnd .......................................................22
TSC2011, TSC2012
List of figures
DS13057 - Rev 2 page 47/49
Figure 50. Vref powered by an external voltage source ...............................................22
Figure 51. Output reference to ground ..........................................................24
Figure 52. Output reference to Vcc ............................................................. 24
Figure 53. Split supply .....................................................................25
Figure 54. External supply...................................................................26
Figure 55. Schematic for Vocm error ............................................................ 28
Figure 56. Input current.....................................................................29
Figure 57. SHDN pin ......................................................................31
Figure 58. Capacitive load response at Vcc = 3.3 V.................................................. 31
Figure 59. Capacitive load response at Vcc = 3.3 V with a step of 100 mV .................................. 32
Figure 60. RC filter when driving ADC........................................................... 32
Figure 61. Capacitive load response at Vcc = 3.3 V with 720 kHz RC filter .................................. 33
Figure 62. Capacitive load response at Vcc = 3.3 V with 194 kHz RC filter .................................. 33
Figure 63. Stability criteria with a serial resistor at VCC = 5 V ........................................... 33
Figure 64. Start-up time with a decoupling capacitance of 100 nF........................................ 34
Figure 65. Recommended layout .............................................................. 35
Figure 66. EMIRR on pin+...................................................................35
Figure 67. EMIRR on pin- ...................................................................35
Figure 68. Negative overvoltage recovery VCC = ± 2.5 V ..............................................36
Figure 69. Positive overvoltage recovery VCC = ± 2.5 V............................................... 36
Figure 70. Half-bridge application.............................................................. 37
Figure 71. TSC2011 H Bridge application ........................................................ 38
Figure 72. Solenoid valve application ...........................................................39
Figure 73. SO8 package outline ............................................................... 41
Figure 74. MiniSO8 package outline ............................................................ 42
TSC2011, TSC2012
List of figures
DS13057 - Rev 2 page 48/49
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TSC2011, TSC2012
DS13057 - Rev 2 page 49/49
