Semiconductor Components Industries, LLC, 2000
April, 2000 – Rev. 6 1Publication Order Number:
MC1741C/D
MC1741C
Internally Compensated,
High Performance
Operational Amplifier
The MC1741C was designed for use as a summing amplifier,
integrator, or amplifier with operating characteristics as a function of
the external feedback components.
•No Frequency Compensation Required
•Short Circuit Protection
•Offset Voltage Null Capability
•Wide Common Mode and Differential Voltage Ranges
•Low Power Consumption
•No Latch Up
Equivalent Circuit Schematic
(1/4 of Circuit Shown)
Offset
Null
Output
G
Noninverting
Input
Inverting
Input
VCC
VEE
39k
1.0k 1.0k50k 50k 50
50
25
4.5k
7.5k
30pF
5.0k
Device Package Shipping
ORDERING INFORMATION
MC1741CD SO–8 98 Units/Rail
MC1741CDR2 SO–8
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2500 Tape & Reel
PDIP–8
P1 SUFFIX
CASE 626
1
8
SO–8
D SUFFIX
CASE 751
1
8
MARKING
DIAGRAMS
ALYW
1741C
1
8
AWL
MC1741CP1
1
8
YYWW
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
PDIP–8
PIN CONNECTIONS
N.C.
VCC
Output
Offset Null
Offset Null 1
2
3
4
8
7
6
5
Noninv. Input
VEE
Inv. Input
(Top View)
+
MC1741CP1 50 Units/Rail
MC1741C
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2
MAXIMUM RATINGS
Rating Symbol Value Unit
Power Supply Voltage VCC, VEE ±18 Vdc
Input Differential Voltage VID ±30 V
Input Common Mode Voltage (Note 1.) VICM ±15 V
Output Short Circuit Duration (Note 2.) tSC Continuous –
Operating Ambient Temperature Range TA0 to +70 °C
Storage Temperature Range Tstg –55 to +125 °C
1. For supply voltages less than +15 V, the absolute maximum input voltage is equal to the supply voltage.
2. Supply voltage equal to or less than 15 V.
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = 25°C, unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Input Offset Voltage (RS ≤ 10 k) VIO – 2.0 6.0 mV
Input Offset Current IIO – 20 200 nA
Input Bias Current IIB – 80 500 nA
Input Resistance ri0.3 2.0 – MΩ
Input Capacitance Ci– 1.4 – pF
Offset Voltage Adjustment Range VIOR –±15 – mV
Common Mode Input Voltage Range VICR ±12 ±13 – V
Large Signal Voltage Gain (VO = ±10 V, RL ≥ 2.0 k) AVOL 20 200 – V/mV
Output Resistance ro– 75 – Ω
Common Mode Rejection (RS ≤ 10 k) CMR 70 90 – dB
Supply Voltage Rejection (RS ≤ 10 k) PSR 75 – – dB
Output Voltage Swing VOV
(RL ≥ 10 k) ±12 ±14 –
(RL ≥ 2.0 k) ±10 ±13 –
Output Short Circuit Current ISC – 20 – mA
Supply Current ID– 1.7 2.8 mA
Power Consumption PC– 50 85 mW
Transient Response (Unity Gain, Noninverting)
(VI = 20 mV, RL ≥ 2.0 k, CL ≤100 pF) Rise Time tTLH – 0.3 – µs
(VI = 20 mV, RL ≥ 2.0 k, CL ≤100 pF) Overshoot os – 15 – %
(VI = 10 V, RL ≥ 2.0 k, CL ≤100 pF) Slew Rate SR – 0.5 – V/µs
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = Tlow to Thigh, unless otherwise noted.)*
Characteristic Symbol Min Typ Max Unit
Input Offset Voltage (RS ≤ 10 kΩ) VIO – – 7.5 mV
Input Offset Current (TA = 0° to +70°C ) IIO – – 300 nA
Input Bias Current (TA = 0° to +70°C ) IIB – – 800 nA
Supply Voltage Rejection (RS ≤ 10 k) PSR 75 – – dB
Output Voltage Swing (RL ≥ 2.0 k) VO±10 ±13 – V
Large Signal Voltage Gain (RL ≥ 2.0 k, VO = ±10 V) AVOL 15 – – V/mV
* Tlow = 0°CT
high = 70°C
MC1741C
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3
Figure 1. Burst Noise versus Source Resistance Figure 2. RMS Noise versus Source Resistance
Figure 3. Output Noise versus Source Resistance Figure 4. Spectral Noise Density
Figure 5. Burst Noise Test Circuit
Unlike conventional peak reading or RMS meters, this system was
especially designed to provide the quick response time essential
to burst (popcorn) noise testing.
The test time employed is 10 sec and the 20 mV peak limit
refers to the operational amplifier input thus eliminating errors
in the closed loop gain factor of the operational amplifier.
RS, SOURCE RESISTANCE (Ω)
0
10
100
1000
10 100 1.0 k 10 k 100 k 1.0 M
BW = 1.0 Hz to 1.0 kHz
en, INPUT NOISE ( Vpk)µ
RS, SOURCE RESISTANCE (Ω)
0.1
1.0
10
100
10 100 1.0 10 k 100 k 1.0 M
BW = 1.0 Hz to 1.0 kHz
OUTPUT NOISE (mVrms)
RS, SOURCE RESISTANCE (Ω)
0.01
0.1
1.0
10
10 100 1.0 k 10 k 100 k 1.0 M
AV = 1000
10
1.0
en,
100
f, FREQUENCY (Hz)
10 100 1.0 k 100 k10 k
14.0
12.0
10.0
8.0
4.0
2.0
0
6.0
AV = 10, RS = 100 k Ω
INPUT NOISE ( nV/ Hz
√)
+
1.0 k
Operational Amplifier
Under Test
Low Pass
Filter
1.0 Hz to 1.0 kHz
100 k
x500 x2 To Pass / Fail
Indicator
-
100 k
100 k
-
+
-
+
Positive
Threshold
Voltage
Negative
Threshold
Voltage
en,en, INPUT NOISE ( Vpk)µ
MC1741C
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4
VO, OUTPUT VOLTAGE (V )
pp
VO, OUTPUT VOLTAGE (V )
pp
VO, OUTPUT VOLTAGE (V )
pp
±15 V Supplies
±12 V
±9.0 V
±6.0 V
VO, OUTPUT VOLTAGE SWING (Vpp)
Figure 6. Power Bandwidth
(Large Signal Swing versus Frequency) Figure 7. Open Loop Frequency Response
Figure 8. Positive Output Voltage Swing
versus Load Resistance Figure 9. Negative Output Voltage Swing
versus Load Resistance
Figure 10. Output Voltage Swing versus
Load Resistance (Single Supply Operation) Figure 11. Single Supply Inverting Amplifier
f, FREQUENCY (Hz)
10 100 1.0 k 100 k10 k
28
24
20
16
8.0
4.0
0
12
(Voltage Follower)
THD < 5%
f, FREQUENCY (Hz)
0
-20
20
40
60
80
100
120
1.0 100 1.0 k 10 k 100 k 1.0 M 10 M10
VOLTAGE GAIN (dB)Avol,
RL, LOAD RESISTANCE (Ω)
±15 V Supplies
±12 V
15
13
11
9.0
7.0
5.0
3.0
1.0 100 200 500 700 1.0 k 2.0 k 5.0 k 7.0 k 10 k
±9.0 V
±6.0 V
RL, LOAD RESISTANCE (Ω)
-15
-13
-11
-9.0
-7.0
-5.0
-3.0
-1.0 100 200 500 700 1.0 k 2.0 k 5.0 k 7.0 k 10
27 V
24 V
21 V
18 V
15 V
12 V
9.0 V
6.0 V
5.0 V
30 V Supply
28
26
24
22
20
18
16
14
12
10
8.0
6.0
4.0
2.0
00 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10
RL, LOAD RESISTANCE (kΩ)
100 µF
RL
VCC
200 k
50 k +
Vin
7
4
2
3
10 k
-
MC1741
1.0 k
200 k 50 k 100 µF
MC1741C
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5
Figure 12. Noninverting Pulse Response
Figure 13. Transient Response Test Circuit
Figure 14. Open Loop Voltage Gain
versus Supply Voltage
5.0 V/DIV
10 µs/DIV
Input
+
RLCL
To Scope
(Input)
To Scope
(Output)
-
70
75
80
90
95
100
105
85
0 2.0 4.0 6.0 8.0 10 12 14 16 18 20
VCC, |VEE|, SUPPLY VOLTAGES (V)
AV, VOLTAGE GAIN (dB)
Output
MC1741C
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6
PACKAGE DIMENSIONS
PDIP–8
P1 SUFFIX
CASE 626–05
ISSUE K
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
58
F
NOTE 2 –A–
–B–
–T–
SEATING
PLANE
H
J
GDK
N
C
L
M
M
A
M
0.13 (0.005) B M
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.40 10.16 0.370 0.400
B6.10 6.60 0.240 0.260
C3.94 4.45 0.155 0.175
D0.38 0.51 0.015 0.020
F1.02 1.78 0.040 0.070
G2.54 BSC 0.100 BSC
H0.76 1.27 0.030 0.050
J0.20 0.30 0.008 0.012
K2.92 3.43 0.115 0.135
L7.62 BSC 0.300 BSC
M--- 10 --- 10
N0.76 1.01 0.030 0.040

SO–8
D SUFFIX
CASE 751–06
ISSUE T
SEATING
PLANE
1
4
58
A0.25 MCB SS
0.25 MBM
h
C
X 45
L
DIM MIN MAX
MILLIMETERS
A1.35 1.75
A1 0.10 0.25
B0.35 0.49
C0.19 0.25
D4.80 5.00
E
1.27 BSCe
3.80 4.00
H5.80 6.20
h
0 7
L0.40 1.25
0.25 0.50
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETER.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
D
EH
A
Be
B
A1
CA
0.10
MC1741C
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7
Notes
MC1741C
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8
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without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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MC1741C/D
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