This document is a general product descriptio n and is subject to change wit hout noti ce. Hyni x does no t assume an y respon sibilit y for
use of circuits described. No patent licenses are implied.
Rev 0.0 / Sep. 2006 1
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
2Gb NAND FLASH
HY27UG162G5A
Rev 0.0 / Sep. 2006 2
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
Document Title
2Gbit (128Mx16bit) NAND Flash Memory
Revision History
Revision
No. History Draft Date Remark
0.1 Initial Draft. Sep. 15. 2006 Preliminary
Rev 0.0 / Sep. 2006 3
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES
- Cost effective solutions for mass storage applications
NAND INTERFACE
- x16 bus width.
- Multiplexed Address/ Data
- Pinout compatibility for all densities
SUPPLY VOLTAGE
- VCC = 2.7 to 3.6V : HY27UG162G5A
Memory Cell Array
= (1K+32) Bytes x 64 Pages x 2,048 Blocks
PAGE SIZE
- x16 device : (1K+32 spare) Bytes
: HY27UF161G5A
BLOCK SIZE
- x16 device: (64K + 2K spare) Words
PAGE READ / PROGRAM
- Random access: 25us (max.)
- Sequential access: 30ns (min.)
- Page program time: 200us (typ.)
COPY BACK PROGRAM MODE
- Fast page copy without external buffering
CACHE PROGRAM
- Internal (2048+64) By te buffer to improv e the program
throughput
FAST BLOCK ERASE
- Block erase time: 2ms (Typ.)
STATUS REGISTER
ELECTRONIC SIGNATURE
- 1st cycle: Manufacturer Code
- 2nd cycle: Device Code
- 3rd cycle: Internal chip number, Cell Type, Number of
Simultaneously Programmed Pages.
- 4th cycle: Page size, Block size, Organization, Spare
size
SERIAL NUMBER OPTION
CHIP ENABLE DON’T CARE
- Simple interface sith microcontroller
DATA RETENTION
- 100,000 Program/Erase cycles (with 1bit/528byte ECC)
- 10 years Data Retention
PACKAGE
- HY27UG162G5A-F(P)
: 63-ball FBGA (9 x 11 x 0.86 mm)
- HY27UG162G5A-F (Lead)
- HY27UG162G5A-FP (Lead Free)
Rev 0.0 / Sep. 2006 4
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
1. SUMMARY DESCRIPTION
The Hynix HY27UG162G5A series is a 128Mx16bit with spare 4Mx8 bit capacity. The device is offered in 3.3V Vcc
Power Supply.
Its NAND cell provides the most cost-e ff ective solution for the solid state mass stor age mark et. The memory is divided
into blocks that can be erased independently so it is possible to preserve valid data while old data is erased.
The device contains 2048 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected
Flash cells.
A program operation allows to write the 2112-byte page in typical 200us and an erase operation can be performed in
typical 2ms on a 128K-byte block.
Data in the page can be read out at 30ns cycle time per byte. The I/O pins serve as the ports for address and data
input/output as well as command input. This interface allows a reduced pin count and easy migration towards diff erent
densities, without any rearrangement of footprint.
Commands, Data and Addresses ar e synchronously introduced using CE, WE, ALE a nd CLE input pin. The on-chip Pro -
gram/Er ase Cont roller automates all progr am and er ase f unctions including pulse repetiti on, where required, and inter-
nal verification and margining of data.
The modify operations can be locked using the WP input pin or using the extended lock block feature described later.
The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multi-
ple memories the R/B pins can be connected all together to provide a global status signal.
Even the write-intensive systems can take advantage of the HY27UG162G2A extended reliability of 100K program/
erase cycles by providing ECC (E rror Correcting Code) with real time mapping-out algorithm.
The chip could be offered with the CE don’t care function. This function allows the direct download of the code from
the NAND Flash memory device by a microcontroller, since the CE transitions do not stop the read operation.
The copy back function allows the optimization of defective blocks management: whe n a page progr am operat ion fails
the data can be directly programmed in another page inside the same arr ay section without the time consuming serial
data insertion phase.
The cache program feature allows the data insertion in the cache register while the data register is copied into the
flash array. This pipelined program operation improves the program throughput when long files are written inside the
memory. A cache read feature is also implemented. This feature allows to dramatically improve the read throughput
when consecutive pa ges have t o be strea med out.
The HYNIX HY27UG162G5A series is available in FBGA 9 x 11 mm.
1.1 Product List
PART NUMBER ORIZATION VCC RANGE PACKAGE
HY27UG162G5A x16 2.7V - 3.6 Volt 63FBGA
Rev 0.0 / Sep. 2006 5
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
9&&
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Figure1: Logic Diagram
IO15 - IO8 Data Input / Outputs (x16 only)
IO7 - IO0 Data Inputs / Outputs
CLE Command latch enable
ALE Address latch enable
CE Chip Enable
RE Read Enable
WE Write Enable
WP Write Protect
R/B Ready / Busy
Vcc Power Supply
Vss Ground
NC No Connection
Table 1: Signal Names
Rev 0.0 / Sep. 2006 6
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
1&
1&
1& 1&1&
1& 1&
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Figure 2. 63FBGA Contactions, x16 Device (Top view through package)
Rev 0.0 / Sep. 2006 7
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
1.2 PIN DESCRIPTION
Pin Name Description
IO0-IO7
IO8-IO15(1)
DATA INPUTS/OUTPUTS
The IO pins allow to input command, address and data and to output data during read / program
operations. The inputs are latched on the rising edge of Write Enable (WE). The I/O buffer float to
High-Z when the device is deselected or the outputs are disabled.
CLE COMMAND LATCH ENABLE
This input activates the latching of the IO inputs inside the Command Register on the Rising edge of
Wri te Enable (WE).
ALE ADDRESS LATCH ENABLE
This input activates the latching of the IO inputs inside the Address Register on the Rising edge of
Wri te Enable (WE).
CE1, CE2CHIP ENABLE
This input controls the selection of the device. When the device is busy CE1, CE2 low does not
deselect the memory.
WE WRITE ENABLE
This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise
edge of WE.
RE
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is
valid tREA after the falling edge of RE which also increments the internal column address counter by
one.
WP WRITE PROTECT
The WP pin, when Low, provides an Hardw are pr otection against undesir ed modify (prog ram / er ase)
operations.
R/B1, R/B2READY BUSY
The Ready/Busy output is an Open Drain pin that signals the state of the memory.
VCC SUPPLY VOLTAGE
The VCC supplies the power for all the oper a tions (Read, W rite, Erase).
VSS GROUND
NC NO CONNECTION
Table 2: Pin Description
NOTE:
1. A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple
the current surges from the power s upply. The PCB track widths must be sufficient to carry the currents required
during program and erase operations.
Rev 0.0 / Sep. 2006 8
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8-IO15
1st Cycle A0 A1 A2 A3 A4 A5 A6 A7 L(1)
2nd Cycle A8 A9 A10 L(1) L(1) L(1) L(1) L(1) L(1)
3rd Cycle A11 A12 A13 A14 A15 A16 A17 A18 L(1)
4th Cycle A19 A20 A21 A22 A23 A24 A25 A26 L(1)
Table 3: Address Cycle Map(x16)
NOTE:
1. L must be set to Low.
FUNCTION 1st CYCLE 2nd CYCLE 3rd CYCLE 4th CYCLE Acceptable command
during busy
READ 1 00h 30h - -
READ FOR COPY-BACK 00h 35h - -
READ ID 90h---
RESET FFh - - - Yes
PAGE PROGRAM 80h 10h - -
COPY BACK PGM 85h 10h - -
BLOCK ERASE 60h D0h - -
READ STATUS REGISTER 70h--- Yes
CACHE PROGRAM 80h 15h - -
RANDOM DATA INPUT 85h---
RAMDOM DATA OUTPUT 05h E0h - -
CACHE READ START 00h 31h - -
CACHE READ EXIT 34h---
Table 4: Command Set
Rev 0.0 / Sep. 2006 9
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
CLE ALE CE WE RE WP MODE
H L L Rising H X Read Mode Command Input
L H L Rising H X Address Input(4 cycles)
H L L Rising H H Write Mode Command Input
L H L Rising H H Address Input(4 cycles)
LLLRisingHHData Input
LL
L(1) H Falling X Sequential Read and Data Output
L L L H H X During Read (Busy)
XXXXXHDuring Program (Busy)
XXXXXHDuring Erase (Busy)
XXXXXLWrite Protect
XXHXX0V/VccStand By
Table 5: Mode Selection
NOTE:
1. With the CE high during latency time does not stop the read operation
Rev 0.0 / Sep. 2006 10
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
2. BUS OPERATION
There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input,
Data Output, Write Protect, and Standby.
Typically glitches less than 5 ns on Chip Enab le, W rite Enab le and R ead E nable ar e ignore d by the me mory and do not
affect b us operations.
2.1 Command Input.
Command Input bus operation is used to give a command to the memory device. Command are accepted with Chip
Enable low, Command Latch Enable High, Address Latch Enable low and Read Enable High and latched on the rising
edge of Write Enable. Mor eover fo r comm ands that starts a modif y ope r ation (wr ite/er ase) the Write Protect pin must
be high. See figure 4 and table 12 for details of the timings requirements. Command codes are always applied on
IO7:0, disregarding the bus configuration (X16).
2.2 Address Input.
Address Input bus op er ation allows the ins ertion of the memory addr ess. To insert the 27 addresses needed to access
the 2Gbit 4 clock cycles (x8 version) are needed. Addresses are accepted with Chip Enable low, Address Latch Enable
High, Command Latch Enable low and R ead Enab le High and latched on the rising edge of W rite Enable. More ov er f or
commands that starts a modify operation (write/erase) the Write Protect pin must be high. See figure 5 and table 12
for details of the timings requirements. Addresses are always applied on IO7:0, disregarding the bus configuration
(X8/X16).
2.3 Data Input.
Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serially and
timed by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command
Latch Enable low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enab le. See figure
6 and table 12 for details of the timings requirements.
2.4 Data Output.
Data Output bus operation allows to read data from the memory array and to check the status register content, the
lock status and the ID data. Data can be serially shifted out toggling the Read Enable pin with Chip Enable low, Write
Enable High, Address Latch Enable low , and Command Latch Enable low. See figures 7 - 11 and table 12 for details of
the timings requirements.
2.5 Write Protect.
Hardware Write Protection is activated when the Write Protect pin is low. In this condition modify operation do not
start and the content of the memory is not altered. Write Protect pin is not latched by Write Enable to ensure the pro-
tection even during the power up.
2.6 Standby.
In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced.
Rev 0.0 / Sep. 2006 11
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
3. DEVICE OPERATION
3.1 Page Read.
Upon initial devi ce power up , the device de fault s to R ead mode. This oper ati on is also initi ated by writ ing 00h and 30h
to the command register along with four address cycles. In two consecutive read operations, the second one does
need 00h command, which four address cycles and 30h command initiates that operation. Second read operation
always requires setup command if first read operation was executed using also random data out command.
Two types of operations are available: random read. The random read mode is enabled when the page address is
changed. The 1056 words (X16 device) of data within the selected page are transferred to the data registers in less
than 25us(tR). The system contr oller may detect the completion of this data transfer (tR) by analyzing the output of R/
B pin. Once the data in a page is loaded into the data registers, they may be read out in 30ns cycle time (3.3V device)
by sequentially pulsing RE. The r epetitive high to low transitions of the RE clock make the de vice output the data start-
ing from the selected column address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random
data output command. The column address of next data, which is going to be out, may be changed to the address
which follows random data output command.
Random data output can be operated multiple times regardless of how many times it is done in a page.
Random data output is not available in cache read.
3.2 Page Program.
The device is progr ammed basically by pa ge, but it does allow multiple par tial page pr ogr amming of a word or consec -
utive words up to 1056 (X16 device), in a single page program cycle.
The number of consecutive partial page programming operation within the same page without an intervening erase
operation must not exceed 8; for example, 4 times for main array ( X16 device:1time 256word) and 4 times for spare
array (X16 device:1time/8word).
The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading
period in which up to 105 6 words (X16 dev ice) of da ta may be loaded into the data register, followed by a non- volatile
programming period where the loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the four cycle
address inputs and then serial data. The words other than those to be programmed do not need to be loaded. The
device supports random data input in a page. The column address of next data, which will be entered, may be
changed to the address which follows random data input command (85h). Random data input may be opera ted multi -
ple times regardless of how many times it is done in a page.
The Page Program confirm command (10h) initiates the programming process. Writing 10h alone without previously
entering the serial data will not initiate the programming process. The P/E/R controller automatically executes the
algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once
the progr am process starts, the Read Status R egister command may be entered to read the status re gister. The system
controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit (I/O 6) of the
Status Reg ister. Only the Read Status command and R eset command ar e valid while progr amming is in progress. When
the Page Program is complete, the Write Status Bit (I/O 0) may be checked. The internal write verify detects only
errors for "1"s that are not successfully progr ammed to "0"s. The command register remains in Read Status command
mode until another valid command is written to the command register. Figure 12 details the sequence.
Rev 0.0 / Sep. 2006 12
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
3.3 Block Erase.
The Erase oper ation is done on a block basis. Block addr ess loading is accomplished in two cycles initiated by an Erase
Setup command (60h). Only address A17 to A26 (X16) is v a lid while A11 to A16 (X16) are ig nored. The Er ase Confirm
command (D0h) following the block address loading initiates the internal erasing process. This two-step sequence of
setup followed by execution command ensures that memory contents are not accidentally erased due to external noise
conditions. At the rising edge of WE after the erase confirm command input, the P/E/R controller handles erase and
erase-verify.
Once the erase process starts, the Read Status Register command may be entered to read the status register.
The system controller can detect the completion of an erase by monitoring the R/B output, or the Status bit (I/O 6) of
the Status Register. Only the Read Status command and Reset command are valid while erasing is in progress. When
the erase operation is completed, the Write Status Bit (I/O 0) may be checked.
Figure 16 details the sequence.
3.4 Copy-Back Program.
The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an
external memory. Since the time-consuming cycles of seria l access and re-loading cy cles ar e removed, the sys tem per-
formance is improved. The bene fit is especially obvious when a portion of a block is updated and the rest of the block
also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a
sequential execution of page-read without serial access and copyingprogram with the address of destination page. A
read operation with "35h" command and the address of the source page moves the whole 2112byte (X8 device) or
1056word (X16 device) data into the internal data buffer.
As soon as the device returns to Ready state, Copy Back command (85h) with the address cycles of destination page
may be written. The Program Confirm command (10h) is required to actually begin the programming oper ation. Data
input cycle for modifying a portion or multiple distant portions of the source page is allowed as shown in Figure 15.
"When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But, if
Copy-Back operations are accumu lated over time, bit e rror due to charge loss is not checked by external
error detection/correction scheme. For this reason, two bit error correction is recommended for the u se
of Copy-Back operation."
Figure 14 shows the command sequence for the copy-back operation.
The Copy Back Program operation requires three steps:
1. The source page must be read using the Read A command (one bus write cycle to setup the command and then
4 bus write cy cles to input the source page a ddress). This oper ation copies all 2KBytes fr om the page into the Page
Buffer.
2. When the device returns to the ready state (Ready/Busy High), the second bus write cycle of the command is
given with the 4bus cycles to input the target page address. The v alue for A26 from second to the last page address
must be same as the value given to A26 in first address.
3. Then the confirm command is issued to start the P/E/R Controller.
Rev 0.0 / Sep. 2006 13
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
3.5 Read Status Register.
The device contains a Status Register which ma y be read to find out whether rea d, progra m or erase oper ation is com-
pleted, and whether the progr am or er as e oper a tion is c omple ted succ essfu lly. After writing 70h comman d to the co m-
mand register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE,
whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory
connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer
to Table 13 for specific Status Register definitions, and Figure 9 for specific tim ings requirements . The command reg-
ister remains in Status Read mode until further comma nds are issued to it. Theref ore, if the status regis ter is read dur-
ing a random read cycle, the read command (00h) should be given before starting read cycles.
3.6 Read ID.
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an
address input of 00h. Four read cycles sequentially output the 1st cycle (ADh), and 2nd cycle (the device code) and
3rd cycle ID, 4th cycle ID, respectively. The command register remains in Read ID mode until further commands are
issued to it. Figure 17 shows the operation sequence, while Tables 14, 15 explain the byte meaning.
3.7 Reset.
The device offers a reset feature, executed by writing FFh to the command re gis ter. When the device is in Busy state
during random read, pr ogr am or er ase mode, the res et operation will abort these operations. The contents of memory
cells being altered are no longer valid, as the data will be partially programmed or erased.
The command register is cleared to wait for the next command, and the Status Register is cleared to value E0h when
WP is high. Refer to table 14 for device status after reset operation. If the device is already in reset state a new reset
command will not be accepted by the command register. The R/B pin transitions to low for tRST after the Reset com-
mand is written.
Rev 0.0 / Sep. 2006 14
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
3.8 Cache program
Cache Progr am is an extension of Page Pr ogram, which is ex ecuted with 1 056word (X16 devi ce) data r egisters, and is
available only within a block. Since the device has 1 page of cache memory, serial data input may be executed while
data stored in data register a re pr ogra mmed into memory cell. Af ter writing the first se t of data up to 1056word (X16
device) into the selected cache registers, Cache Program command (15h) instead of actual Page Program (10h) is
input to make cache registers free and to start internal program operation. To transfer data from cache registers to
data registers, the device remains in Busy state for a short period of time (tCBSY) and has its cache registers ready
for the next data-input while the internal programming gets started with the data loaded into data registers. Read
Status command (70h) may be issued to find out when cache registers become ready by p olling the Ca che- Busy sta-
tus bit (I/O 6). Pass/fail status of only the previous page is available upon the return to Ready state.
When the next set of data is input with the Cache Program command, tCBSY is affected by the progress of pending
internal programming. The programming of the cache registers is initiated only when the pending program cycle is
finished and the data registers are available for the transfer of data from cache registers. The status bit (I/O5) for
internal Ready/Busy may be polled to identify the completion of internal programming.
If the system monitors the progress of progr amming only with R/B, the last page of the target progr amming sequence
must be programmed with actual Page Program command (10h). If the Cache Program command (15h) is used
instead, status bit (I/O5) must be polled to find out when the last programming is actually finished before starting
other operations such as read. Pass/fail status is available in two steps. I/O 1 returns with the status of the previous
page upon Ready or I/O6 status bit changing to "1", and later I/O 0 with the status of current page upon true Ready
(returning fro m intern al pr ogramming) or I/O 5 status bit changing to "1". I/O 1 may be read together when I/O 0 is
checked. See Fig. 15 for more details.
NO TE : Since progra mming the last page does not employ cach ing, the program time has to be that of Page Program.
However, if the previous program cy cle with the cache data has not finished, the actual progr am cycle of the last page
is initiated only after completion of the previous cycle, which can be expressed as the following formula.
tPROG=Program time for the last page + Program time for the (last-1)page
- (Program command cycle time + Last page data loading time)
Rev 0.0 / Sep. 2006 15
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
3.9 Cache Read
Cache read operation allows automatic download of consecut ive pages, up to the whole device. Immediately after 1st
latency end, while user can start reading out data, device internally starts reading following page.
Start address of 1st page must be at page start (A<10:0>=00h) : in this way after 1st latency time (tr) , automatic
data download will be uninterrupted. In fact latency time is 25us, while download of a page require at least 50us for
x16 device.
Cache read operation command is like standard read, except for confirm code (30h for standard read, 31h for cache
read) user can check operation status using :
- R/B ( ‘0’ means latency ongoing, download not possible, ‘1’ means download of n page possible, even if device in
ternally is active on n+1 page
- Status register (SR<6> behave like R/B, SR<5> is ‘0’ when device is internally reading and ‘1’ when device is idle)
To exit cache read operation, a cache read exit command (34h) must be issued. This command can be given any time
(both device idle and reading).
If device is active (SR<5>=0) it will go idle within 5us, while if it is not active, device itself will go busy for a time
shorter then tCBSY before becoming again idle and ready to accept any further commands. Figure 16 describes how
to handle Cache Read through Status register .
If user reads last byte/word of the memory array, then he has to stop by giving a cache read exit command. In general,
if user wants to terminate a cache read, then he must give a cache read exit command (or reset command) before
starting any new operation.
Random data output is not available in cache read.
Cache read operation must be done only block by block if system needs to avoid reading also from invalid blocks.
Rev 0.0 / Sep. 2006 16
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
4. OTHER FEATURES
4.1 Data Protection for Power on/off Sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal
voltage detector disables all functions whenever Vcc is below about 2.0V (3.3V version). WP pin provides hardware
protection and is recommended to be kept at VIL during power -up and power-down. A recovery time of minimum 10us
is required before internal circuit gets ready for any command sequences as shown in Figure 22. The two-step com-
mand sequence for program/erase provides additional software protection.
If the power is dropped during the ready read/write/erase operation, Power protection function may not guaranteed
the data. Power protection function is only available during the power on/off sequence.
4.2 Ready/Busy.
The device has a Ready/Busy output that provides method of indicating the completion of a page program, erase,
copy-back, cache progr am and random read completion. The R/B pin is normally high and goes to low when the device
is busy (after a reset, read, program, erase operation). It returns to high when the P/E/R controller has finished the
operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up
resistor value is related to tr(R/B) and current drain during busy (Ibusy), an appropriate value can be obtained with
the following reference chart (Figure 23). Its value can be determined by the following guidance.
Rev 0.0 / Sep. 2006 17
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
Parameter Symbol Min Typ Max Unit
Valid Block Number NVB 2008 2048 Blocks
Table 6: Valid Blocks Number
NOTE:
1. The 1st block is guaranteed to be a valid block up to 1K cycles with ECC. (1bit/528bytes)
Symbol Parameter Value Unit
3.3V
TAAmbient Operating Temperature (Temperature Range Option 1) 0 to 70 ℃
Ambient Operating Temperature (Industrial Temperature Range) -40 to 85 ℃
TBIAS Temperature Under Bias -50 to 125 ℃
TSTG Storage Temperature -65 to 150 ℃
VIO(2) Input or Output Voltage -0.6 to 4.6 V
Vcc Supply Voltage -0.6 to 4.6 V
Table 7: Absolute maximum ratings
NOTE:
1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute
Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of
the device at the se or an y other conditions abov e those indicat ed in t he Ope rat ing se ctions o f this specifi cation is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
2. Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions.
Rev 0.0 / Sep. 2006 18
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
Figure 3: Block Diagram
$''5(66
5(*,67(5
&2817(5
352*5$0
(5$6(
&21752//(5
+9*(1(5$7,21
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,2
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;
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(
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2
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(
5
0ELW0ELW
1$1')ODVK
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:3
&(
:(
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$a$
Rev 0.0 / Sep. 2006 19
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
Parameter Symbol Test Conditions 3.3Volt Unit
Min Typ Max
Operating
Current
Sequential
Read ICC1 tRC=30ns
CE=VIL,
IOUT=0mA -15 30 mA
Program ICC2 - - 15 30 mA
Erase ICC3 - - 15 30 mA
Stand-by Current (TTL) ICC4 CE=VIH,
WP=0V/Vcc - 1 mA
Stand-by Current (CMOS) ICC5 CE=Vcc-0.2,
WP=0V/Vcc - 20 100uA
Input Leakage Current ILI VIN=0 to Vcc (max) - - ±20 uA
Output Leakage Current ILO VOUT =0 to Vcc (max) - - ±20 uA
Input High Voltage VIH -Vccx0.8 -Vcc+0.3 V
Input Low Voltage VIL --0.3 -Vccx0.2 V
Output High Voltage Level VOH IOH=-400uA 2.4 - - V
Output Low Voltage Leve VOL IOL=2.1mA - - 0.4 V
Output Low Current (R/B) IOL
(R/B) VOL=0.4V 810 -mA
Table 8: DC and Operating Characteristics
Parameter Value
3.3Volt
Input Pulse Levels 0V to Vcc
Input Rise and Fall Times 5ns
Input and Output Timing Levels Vcc / 2
Output Load (2.7V - 3.6V) 1 TTL GATE and CL=50pF
Table 9: AC Conditions
Rev 0.0 / Sep. 2006 20
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
Item Symbol Test Condition Min Max Unit
Input / Output Capacitance CI/O VIL=0V - 20 pF
Input Capacitance CIN VIN=0V - 20 pF
Table 10: Pin Capacitance (TA=25C, F=1.0MHz)
Parameter Symbol Min Typ Max Unit
Program Time tPROG -200 700us
Dummy Busy Time for Cache Program tCBSY - 3 700us
Number of partial Program Cycles in the same page Main Array NOP - - 4 Cycles
Spare Array NOP - - 4 Cycles
Block Erase Time tBERS - 2 3 ms
Table 11: Program / Erase Characteristics
Rev 0.0 / Sep. 2006 21
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
Parameter Symbol 3.3Volt Unit
Min Max
CLE Setup time tCLS 15 ns
CLE Hold time tCLH 5ns
CE setup time tCS 20 ns
CE hold time tCH 5ns
WE puls e width tWP 15 ns
ALE setup time tALS 15 ns
ALE hold time tALH 5ns
Address to Data Loading tADL(4) 100 ns
Data setup time tDS 5ns
Data hold time tDH 5ns
Write C y cle tim e tWC 30 ns
WE High hold time tWH 10 ns
Data Transfer from Cell to register tR25 us
ALE to RE Delay tAR 15 ns
CLE to RE Delay tCLR 15 ns
Ready to RE Low tRR 20 ns
RE Pulse Width tRP 15 ns
WE High to Busy tWB 100 ns
Read Cycle Time tRC 30 ns
RE Access Time tREA 20 ns
RE High to Output High Z tRHZ 50 ns
CE High to Output High Z tCHZ 50 ns
RE High Hold Time tREH 10 ns
Output High Z to RE low tIR 0ns
CE Access Time tCEA 25 ns
WE High to RE low tWHR 60 ns
RE or CE High to Output Hold tOH 10 ns
Device Resetting Time (Read / Program / Erase) tRST 5/10/500(1) us
Write Protecti on time tWW(3) 100 ns
Table 12: AC Timing Characteristics
NOTE:
1. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us
2. The time to Ready depends on the value of the pull-up resistor tied R/B pin.ting time.
3. Program / Erase Enable Operation : WP high to WE High.
Program / Erase Disable Operation : WP Low to WE High.
4. tADL is the time from the WE rising edge of final address cycle to the WE rising of first data cycle.
Rev 0.0 / Sep. 2006 22
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
IO Pagae
Program Block
Erase Cache
Program Read Cache
Read CODING
0Pass / Fail Pass / Fail Pass / Fail (N) NA Pass: ‘0’ Fail: ‘1’
1NA NA Pass / Fail (N-1) NA Don’t care
2NA NA NA NA -
3NA NA NA NA -
4NA NA NA NA -
5Ready/Busy Ready/Busy P/E/R
Controller Bit Ready/Busy P/E/R
Controller Bit Active: ‘0’ Idle: ‘1’
6Ready/Busy Ready/Busy Cache Register
Free Ready/Busy Ready/Busy Busy: ‘0’ Ready’: ‘1’
7Write Protect Write Protect Write Protect Write Protect Protected: ‘0’ Not
Protected: ‘1’
Table 13: Status Register Coding
DEVIIDENTIFIER CYCLE DESCRIPTION
1st Manufacturer Code
2nd Device Identifier
3rd Internal chip number, cell Type, Number of Simultaneously Programmed
pages.
4th Page size, spare size, Block size, Organization
Table 14: Device Identifier Coding
Part Number Voltage Bus Width 1st cycle
(Manufacture Code) 2nd cycle
(Device Code) 3rd Code 4th Code
HY27UG162G5A 3.3V x16 ADh C1h 80h 5Dh
Table 15: Read ID Data Table
Rev 0.0 / Sep. 2006 23
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
Description IO7 IO6 IO5-4 IO3 IO2 IO1-0
Page Size
(Without Spare Area)
1KB
2KB
4KB
Reserved
0 0
0 1
1 0
1 1
Spare Area Size
(Byte / 512 Byte) 8
16 0
1
Serial Access Time
50ns
30ns
25ns
Reserved
0
0
1
1
0
1
0
1
Block Size (Without
Spare Area)
64KB
128KB
256KB
512KB
0 0
0 1
1 0
1 1
Organization X8
X16 0
1
Table 17: 4th Byte of Device Identifier Description
Description IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0
Die / Package
1
2
4
Reserved
0 0
0 1
1 0
1 1
String Type
Single Level
2x Multi-level
Reserved
Reservedl
0 0
0 1
1 0
1 1
Number of
Simultaneously
Programmed Pages
1
2
3
4
0 0
0 1
1 0
1 1
Interl eave Program
Between different dice Not Support
Support 0
1
Wri te Cache Not Support
Support 0
1
Table 16: 3rd Byte of Device Idendifier Description
Rev 0.0 / Sep. 2006 24
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
Figure 4: Command Latch Cycle
W&/
6
W&6
W:3
&RPPDQG
&/(
&(
:(
$/(
,2[
W'+W'6
W$/6 W$/+
W&/+
W&+
W&/6
W&6
W:3
W:& W:& W:&
W:3 W:3 W:3
W$/6
W:+W:+W:+W:+
W$/+ W$/6W$/6W$/6W$/6
&RO$GG
W$/+ W$/+ W$/+ W$/+
W'+
&RO$GG 5RZ$GG 5RZ$GG 5RZ$GG
W:&
W'+ W'+ W'+ W'+
W'6 W'6 W'6 W'6
W'6
&/(
&(
:(
$/(
,2[
Figure 5: Address Latch Cycle
Rev 0.0 / Sep. 2006 25
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
W:&
W$/6
W&/+
W&+
W:3
W:+
',1 ',1 ',1ILQDO
W'+ W'+ W'+
W'6 W'6 W'6
W:3 W:3
&/(
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1RWHV',1ILQDOPHDQV
t
CEA
t
REA
t
RP
t
REA
t
RHZ
t
RHZ*
Dout Dout Dout
t
CHZ*
t
OH
t
OH
t
REA
t
REH
t
RC
t
RR
Notes : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
CE
RE
R/B
I/Ox
Figure 6. Input Data Latch Cycle
Figure 7: Sequential Out Cycle after Read (CLE=L, WE=H, ALE=L)
Rev 0.0 / Sep. 2006 26
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
Figure 8: Status Read Cycle
tCLS
tCLR
tCLH
tCS
tCH
tWP
tWHR
tCEA
tDS tREA
tCHZ
tRH=
t2H
t2H
70h Status Output
tDH tIR
CE
WE
I/O
x
CLE
RE
&/(
$/(
&(
,2[
:(
5(
5'
W
:&
W
&/5
W
55
K K
&RO$GG
&ROXPQ$GGUHVV 5RZ$GGUHVV
&RO$GG
5RZ$GG 5RZ$GG 5RZ$GG
%XV\
'RXW1 'RXW1 'RXW0
W
:%
W
$5
W
5
W
5&
W
5+=
Figure 9: Read1 Operation (Read One Page)
Rev 0.0 / Sep. 2006 27
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
W:%
W$5
W&+=
W&2+
W5&
W5
W55
%XV\
K K 'RXW
1'RXW
1 'RXW
1
&RO
$GG &RO
$GG 5RZ
$GG 5RZ
$GG 5RZ
$GG
&ROXPQ$GGUHVV 5RZ$GGUHVV
&/(
&(
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$/(
5(
,2[
5%
Figure 10: Read1 Operation intercepted by CE
Rev 0.0 / Sep. 2006 28
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
&/(
$/(
&(
5(
5%
,2[
:(
W&/5
K
&ROXPQ$GGUHVV 5RZ$GGUHVV
%XV\
K K (K
'RXW1 'RXW0
'RXW1 'RXW0
&RO$GG 5RZ$GG 5RZ$GG 5RZ$GG
&RO$GG
&ROXPQ$GGUHVV
&RO$GG &RO$GG
W5 W5&
W:%
W$5
W55
W:+5
W5($
W5+:
Figure 11 : Random Data output
Rev 0.0 / Sep. 2006 29
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
Figure 12: Page Program Operation
&/(
$/(
&(
5(
5%
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:(
W:&
K &RO
$GG
6HULDO'DWD
,QSXW&RPPDQG &ROXPQ$GGUHVV 5RZ$GGUHVV 5HDG6WDWXV
&RPPDQG
3URJUDP
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,2R 6XFFHVVIXO3URJUDP
,2R (UURULQ3URJUDP
XSWRP%\WH
6HULDO,QSXW
&RO
$GG 5RZ
$GG 5RZ
$GG 5RZ
$GG 'LQ
1'LQ
0K K ,2R
W:&
W:% W352*
W:&
W$'/
Rev 0.0 / Sep. 2006 30
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
&/(
$/(
&(
5(
5%
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:(
W:&
K 'LQ
1'LQ
0'LQ
-'LQ
.
K K K
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W:&
W:%
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,QSXW&RPPDQG
&ROXPQ$GGUHVV &ROXPQ$GGUHVV5RZ$GGUHVV 6HULDO,QSXW 6HULDO,QSXW 3URJUDP
&RPPDQG
5HDG6WDWXV
&RPPDQG
W:&
W$'/ W$'/
Figure 13 : Random Data In
Rev 0.0 / Sep. 2006 31
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
%XV\
W:%
W:%
W$'/
W352*
W:&
&/(
&(
:(
5(
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5%
$/(
&ROXPQ$GGUHVV
K K K 'DWD 'DWD1 K ,2[%KK
&RO
$GG &RO
$GG 5RZ
$GG 5RZ
$GG 5RZ
$GG &RO
$GG &RO
$GG 5RZ
$GG 5RZ
$GG 5RZ
$GG
5RZ$GGUHVV &ROXPQ$GGUHVV 5RZ$GGUHVV
W5
%XV\
&RS\%DFN'DWD
,QSXW&RPPDQG
Figure 14 : Copy Back Program
Rev 0.0 / Sep. 2006 32
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
&/(
$/(
&(
5(
5%
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:(
5%
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([&DFKH3URJUDP
W:&
K K ,2
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6HULDO'DWD
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&RPPDQG
'XPP\
K K
$GGUHVV
'DWD,QSXW $GGUHVV
'DWD,QSXW $GGUHVV
'DWD,QSXW $GGUHVV
'DWD,QSXW
K K K KK K K
K K
'LQ
1'LQ
0'LQ
1'LQ
0
&RO
$GG
K &RO
$GG
5RZ
$GG
5RZ
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5RZ
$GG
W:% W352*
W:% W&%6<
&RO
$GG &RO
$GG
5RZ
$GG
5RZ
$GG
5RZ
$GG
Figure 15 : Cache Program
Rev 0.0 / Sep. 2006 33
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
W:&
&/(
&(
:(
$/(
5(
,2[
5%
W:% W%(56
%86<
K ,2'K
5RZ
$GG 5RZ
$GG 5RZ
$GG
K
$XWR%ORFN(UDVH
6HWXS&RPPDQG
(UDVH&RPPDQG 5HDG6WDWXV
&RPPDQG
,2 6XFFHVVIXO(UDVH
,2 (UURULQ(UDVH
5RZ$GGUHVV
Figure 16: Block Erase Operation (Erase One Block)
K
&/(
&(
:(
$/(
5(
,2[ K
W5($
5HDG,'&RPPDQG $GGUHVVF\FOH VWF\FOH QGF\FOH
$'K &K K
'K
W$5
UGF\FOH WKF\FOH
Figure 17: Read ID Operation
Rev 0.0 / Sep. 2006 34
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
'K
'
5HDGVWSDJH
5HDGQGSDJH
5HDGUGSDJH 5HDGWKSDJH
,GOH ,GOH
' ' ' ' ' ' ' ' ' '' '
$GG $GG $GG $GG $GG K
V V V
V
V V V
&/(
$/(
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5(
,QWHUQDORSHUDWLRQ
6WDWXV5HJLVWHU
65!
Figure 18: start address at page start :after 1st latency uninterrupted data flow
Rev 0.0 / Sep. 2006 35
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
System Interface Using CE don’t care
To simplify system interface, CE may be deasserted during data loading or sequential data-reading as shown below.
So, it is possible to conn ect NAND Flash t o a microporc essor. The only function that was removed from standard NAND
Flash to make CE don’t care read operation was disabling of the automatic sequential read function.
&(GRQ¶WFDUH
K 6WDUW$GG&\FOH 'DWD,QSXW K'DWD,QSXW
&/(
&(
:(
$/(
,2[
Figure 19: Program Operation with CE don’t-care.
,IVHTXHQWLDOURZUHDGHQDEOHG
&(PXVWEHKHOGORZGXULQJW5 &(GRQ¶WFDUH
K K
&/(
&(
5(
$/(
5%
:(
,2[
6WDUW$GG&\FOH 'DWD2XWSXWVHTXHQWLDO
W5
Figure 20: Read Operation with CE don’t-care.
Rev 0.0 / Sep. 2006 36
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
Figure 21: Reset Operation
))K
W567
:(
$/(
&/(
5(
,2[
5%
:3
:(
9FF
XV
W
97+
Figure 22: Power On and Data Protection Timing
VTH = 2.5 Volt for 3.3 Volt Supply devices
Rev 0.0 / Sep. 2006 37
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
5SYDOXHJXLGHQFH
5SPLQ9SDUW
ZKHUH,/LVWKHVXPRIWKHLQSXWFXUUQWVRIDOOGHYLFHVWLHGWRWKH5%SLQ
5SPD[LVGHWHUPLQHGE\PD[LPXPSHUPLVVLEOHOLPLWRIWU
#9FF 97D &&
/
S)
9FF0D[9
2/0D[ 9
P$,/,2/,/
5S LEXV\
&
/
5SRKP
LEXV\
LEXV\>$@
WUWI>V@
WI
%XV\
5HDG\ 9FF
92+
WUWI
92/
9FF
Q P
N N N N
Q P
Q P
*1'
'HYLFH
RSHQGUDLQRXWSXW
5%
Figure 23: Ready/Busy Pin electrical specifications
Rev 0.0 / Sep. 2006 38
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
Bad Block Management
Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the
blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and
common source line by a select transistor. The devices are supplied with all the locations inside valid blocks
erased(FFh).
The Bad Block Information is written prior to shipping. Any block where the 1st Byte/ 1st Word in the spare area of the
1st or 2nd page (if th e 1s t pag e is Ba d) does not contain FFh is a Bad Block. The Bad Block Information must be read
before any erase is attempted as the Bad Block Information may be erased. For the system to be able to recognize the
Bad Blocks based on the original information it is recommended to create a Bad Block table following the flowchart
shown in Figure 24. The 1st block, which is placed on 00h block address is guaranteed to be a valid block.
Block Replacement
Over the lifetime of the device additional Bad Blocks may develop. In this case the block has to be replaced by copying
the data to a valid block. These ad ditional Bad Blocks can be identified as attempts to program or era se them will give
errors in the Status Register.
As the failure of a page program operation doe s not affect the data in other pages in the same block, the block can b e
replaced by re-programming the current data and copying the rest of the replaced block to an available valid block.
The Copy Back Program command can be used to copy the data to a valid block.
See the “Copy Back Program” section for more details.
Refer to Table 18 for the recommended procedure to follow if an error occurs during an operation.
Operation Recommended Procedure
Erase Block Replacement
Program Block Replacement or ECC (with 1bit/528byte)
Read ECC (with 1bit/528byte)
Figure 24: Bad Block Management Flowchart
<HV
<HV
1R
1R
67$57
%ORFN$GGUHVV
%ORFN
'DWD
))K"
/DVW
EORFN"
(1'
,QFUHPHQW
%ORFN$GGUHVV
8SGDWH
%DG%ORFNWDEOH
Table 18: Block Failure
Rev 0.0 / Sep. 2006 39
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
Write Protect Operation
The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations
are enabled and disabled as follows (Figure 26~29)
::
W
K K
:(
,2[
:3
5%
K K
W::
:(
,2[
:3
5%
Figure 25: Enable Programming
Figure 26: Disable Programming
Rev 0.0 / Sep. 2006 40
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
K
W
'K
::
:(
,2[
:3
5%
K
W::
'K
:(
,2[
:3
5%
Figure 27: Enable Erasing
Figure 28: Disable Erasing
Rev 0.0 / Sep. 2006 41
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
Symbol Millimeters
Min Typ Max
A 0.80 0.86
A1 0.20
A2 0.60
b 0.25 0.30 0.35
D 8.90 9.00 9.10
D1 4.00
D2 7.20
E 10.90 11.00 11.10
E1 5.60
E2 8.80
e0.80
FD 2.50
FD1 0.90
FE 2.70
FE1 1.10
SD 0.40
SE 0.40
Figure 29. 63-ball FBGA, 9 x 11 ball array 0.8 mm pitch, Package Outline
Table 19: 63-ball FBGA - 9 x 11 ball array 0.8mm pitch, Pakage Mechanical Data
$
$
$
6(
)(
)(
H
((
%$//³FS´
(
H
HE
'
'
6'
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'
Rev 0.0 / Sep. 2006 42
Preliminary
HY27UG162G5A Series
2Gbit (128Mx16bit) NAND Flash
MARKING INFORMATION - FBGA
Packag M arking Exam ple
FBGA
K O R
H Y 2 7 U G 1 6 2 G 5 A
x x x x Y W W x x
- hynix
- K O R
- H Y27UG162G5A xxxx
HY : Hynix
2 7 : NAND Flash
U: Pow er Supply
G: Classification
16: Bit Organization
2G: Density
5: Mode
A: Version
x: Package Type
x : Package M aterial
x : O perating T em perature
x : Bad Block
- Y : Year (ex: 5= year 20 05, 06= year 2006)
- w w: Work W eek (ex: 12= w ork w eek 12)
- xx : Process C od e
Note
- C ap ital Lette r
- Sma ll Letter
: H yn ix S ymb ol
: Or ig in Co u n tr y
: U(2.7V~3.6V)
: S in g le L e v e l C e ll+Do u b le Die + L a rg e B lo ck
: 1 6(x 16 )
: 2G b it
: 2 n C E & 2 R /n B ; Se q u e ntia l R o w Re a d D isa b le
: 2n d G e ne ration
: F (63 -FB G A )
: Blank(Norm al), P(Lead Free)
: C (0 ℃~70℃), I(-40 ℃~85℃)
: B(Included Bad Block), S(1~5 Bad Block),
P (A ll G o o d B loc k )
: Fixe d Item
: N o n-fixe d Item
: Part N umb er
