SST39SF010-90-4C-U4 - Silicon Storage Technology, Inc.

S71149-03-000 4/01 394

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Data Sheet

512 Kbit / 1 Mbit (x8) Multi-Purpose Flash

SST39SF512 / SST39SF010

FEATURES:

• Organized as 64K x8 / 128K x8

• Single 5.0V Read and Write Operations

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

•Low Power Consumption:

–Active Current: 20 mA (typical)

–Standby Current: 10 µA (typical)

•Sector-Erase Capability

–Unif orm 4 KByte sectors

•Fast Read Access Time:

–70 ns

–90 ns

•Latched Address and Data

•Fast Erase and Byte-Program:

–Sec tor-Erase Time : 7 ms (typical)

–Chip-Erase Time: 15 ms (typical)

–Byte-Program Time: 20 µs (typical)

–Chip Rewrite Time:

2 seconds (typical) for SST39SF512

3 seconds (typical) for SST39SF010

•Automatic Wri te Timing

–Internal VPP Generation

•End-of-Write Detection

–Toggle Bit

–Data# Polling

•TTL I/O Compatibility

•JEDEC Standard

–Flash EEPROM Pinouts and command sets

•Packages A vailable

–32-pin PLCC

–32-pin TSOP (8mm x 14mm)

–32-pin PDIP

PRODUCT DESCRIPTION

The SST39SF512/010 are CMOS Multi-Purpose Flash

(MPF) manufactured with SST’s proprietary, high perfor-

mance CMOS SuperFlash technology. The split-gate cell

design and thick oxide tunneling injector attain better reli-

ability and manufacturability compared with alternate

approaches. The SST39SF512/010 devices write (Pro-

gram or Erase) with a 5.0V-only power supply. The

SST39SF512/010 device conforms to JEDEC standard

pinouts f or x8 memories.

Featuring high performance Byte-Program, the

SST39SF512/010 devices provide a maximum Byte-Pro-

gram time of 30 µsec. These devices use Toggle Bit or

Data# P olling to indicate the completion of Program opera-

tion. To pr otect against inadv ertent write , they have on-chip

hardware and Software Data Protection schemes.

Designed, manufactured, and tested for a wide spectrum of

applications, these devices are offered with a guaranteed

endurance of 10,000 cycles. Data retention is rated at

gr eat er t han 10 0 y e ar s.

The SST39SF512/010 devices are suited for applications

that require convenient and economical updating of pro-

gram, configuration, or data memory. For all system appli-

cations, they significantly improve performance and

reliability, while lowering power consumption. They inher-

ently use less energy during erase and program than alter-

native flash te chnologies. Th e total energy consumed is a

function of the applied v oltage , current, and time of applica-

tion. Since for any given voltage range, the SuperFlash

technology uses less current to program and has a shorter

erase time, the total energy consumed during any Erase or

Program operation is less than alternative flash technolo-

gies. These devices also improve flexibility while lowering

the cost for program, data, and configuration storage appli-

cations.

The S upe r Flas h te ch no logy pr ovid es fi xed Erase an d P r o-

gram times, in depen dent o f the num ber of Erase/ Pro gram

cycles that have occurred. Therefore the system software

or hardware does not ha v e to be modified or de-rated as is

necessary with alternative flash technologies, whose Er ase

and Pr ogram tim es inc rease with accumul ated Erase/P ro-

gr am cycles .

To meet high density, surface mount requirements, the

SST39SF512/010 are offered in 32-pin PLCC packages,

32- pin TSOP, and a 600 mil, 32-pin PDIP is also available.

See Figures 1, 2, and 3 f or pinouts.

Device Operation

Commands are used to initiate the memory operation func-

tions of the device. Commands are written to the device

using standard microprocessor write sequences. A com-

mand is written by asse rtin g WE# low while keepi ng CE#

SST39SF512 / 0105.0V 512Kb / 1Mb (x8) MPF memories

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

low. The address b us is latched on the f alling edge of WE#

or CE#, whichever oc curs l ast. The data bus is latc hed o n

the rising edge of WE# or CE#, whichev er occurs first.

Read

The Read operation of the S ST39SF51 2/010 is con trolled

by CE# and OE#, both have to be low for the system to

obtain data from the outputs. CE# is used for device selec-

tion. When CE# is high, the chip is deselected and only

standb y po wer is consumed. OE# is the output control and

is used to gate data from the output pins . The data bus is in

high impedance state when either CE# or OE# is high.

Refer to the Read cycle timing diagram for fur ther details

(Figure 4).

Byte-P rogram Opera ti on

The SST39SF512/010 are programmed on a byte-by-byte

basis. The Program operati on consists of thr e e s te ps. Th e

fir st st ep i s the th ree-b y te- loa d se quence f o r S oftw ar e Da ta

Protection. The second step is to load byte address and

byte data. During the Byte-Program operation, the

addres ses are latched on the fallin g edg e of either CE# or

WE#, whiche ver occurs last. The data is latched on the ris-

ing edge of either CE# or WE#, whic hev er occurs first. The

third step is the internal Program operation which is initi-

ated after the rising edge of the fourth WE# or CE#, which-

ev er occurs first. The Program operation, once initiated, will

be compl eted, within 30 µs. Se e Figures 5 and 6 fo r WE#

and CE# controlled Program operation timing diagrams

and Figure 15 for flowcharts. During the Program opera-

tion, the only valid reads a re Dat a# Polling and Toggl e Bit.

During the internal Program operation, the host is free to

perform additional tasks . An y commands written during the

internal Prog ram operation will be ignored.

Sector-Erase Operation

The Sector-Erase operation allows the system to erase the

device on a sector-by-sector ba sis. The sector architecture

is based on uniform sector size of 4 KByte. The Sector-

Erase operation is initiated by executing a six-byte-com-

mand load sequence for Software Data Protection with

Sector -Erase com mand (30 H) and s ector addr ess (S A) in

the last b us cycle. The sector address is latched on the fall-

ing edge of the sixth WE# pulse, while the command (30H)

is latched on the rising edge of the sixth WE# pulse. The

inter nal Erase ope ration begin s afte r the sixt h WE# pul se.

The end of Erase can be determined using either Data#

Polling or Toggle Bit methods. See Figure 9 for timing

waveforms. Any commands written during the Sector-

Erase operation will be ignored.

Chip-Erase Operation

The SST39SF512/010 provide Chip-Erase operation,

which al lows the user to erase the entire mem or y array to

the “1s” state. This is useful when the entire device must be

quickly er ased.

The Chip-Erase operation is initiated by executing a six-

byte Software Data Protection command sequence with

Chip-Erase command (10H) with address 5555H in the last

byte sequence. The Erase ope ration begi ns wi th the ri sin g

edge of the sixth WE# or CE#, whiche ver occurs first. Dur-

ing the Erase operation, the only valid read is Toggle Bit or

Data# Polling. See Table 4 for the command sequence,

Figure 10 for timing diagram, and Figure 18 for the flow-

chart. Any commands written during the Chip-Erase opera-

tion will be ignor ed.

Write Opera ti on Status De te ct ion

The SST39SF512/010 provide two software means to

detect the completion of a Write (Program or Erase) cycle,

in order to op timize the syste m Write cycle time. The soft-

ware detection includes two status bits: Data# Polling

(DQ7) and Toggle Bit (DQ6). The End-of-Write detection

mode is enabled after the rising edge of WE#, which ini-

tiates the program or erase cycle.

The act ual co mple tion of the nonvolatile wr ite is asyn chr o-

nous with the system; therefore, either a Data# Polling or

Toggle Bit read may be simultaneous with the co mpletion

of the Write cycle. If this occurs, the system may possibly

get an erroneous result, i.e., valid data ma y appear to con-

flict with either DQ7 or DQ6. In order to prevent spurious

rejection, if an erroneous result occurs, the software routine

should include a loop to read the accessed location an

additional two (2) times. If both reads are valid, then the

device has completed the Write cycle, otherwise the rejec-

tion is valid.

Data# Polling (DQ7)

When the SST39SF512/010 are in the internal Program

operatio n, any attempt to r ead DQ7 will pro duce the co m-

plement of the true data. Once the Program operation is

comp lete d, D Q7 will produc e true data. T he device is the n

ready for the next operation. During inter nal Erase opera-

tion, any a ttempt to read DQ7 will pro duce a ‘0’. Once the

inter nal Erase operati on is completed, DQ 7 will produce a

‘1’. The Data# Polling is valid after the rising edge of fourth

WE# (or CE #) pulse for Program Ope ration. For sect or or

Chip-E rase, the Data# Pollin g is valid after the r isi ng edge

of sixth WE# (or CE#) pulse. See Figure 7 for Data# P olling

timing diagram and Figure 16 f or a flowchart.

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

Toggle Bit (DQ6)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ6 will produce alter nating 0s

and 1s, i.e., tog gling betwe en 0 and 1. The To ggle Bit will

begin with “1”. When the internal Program or Erase opera-

tion is c om pl ete d, the to ggl in g will stop. The device i s then

ready f or the ne xt operation. The Toggle Bit is valid after the

rising edge of f ourth WE# (or CE#) pulse f or Program oper-

ation. For Sector or Chip-Erase, the Toggle Bit is valid after

the rising edge of sixth WE# (or CE#) pulse. See Figure 8

for Toggle Bit timing diagram and Figure 16 f or a flo wchart.

Data Protection

The SST39SF512/010 provide both hardware and soft-

ware features to protect nonvolatile data from inadver tent

writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pu lse of less th an 5

ns will not ini tiate a Wri te cycle .

VDD Power Up/Down Detection: The write operation is

inhibited when VDD is less than 2.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE#

high will in hi bit t he Write operation . T hi s prevents inadvert-

ent w rites durin g pow er-u p or po wer- dow n.

Software Data Protection (SDP)

The SS T39 SF 5 12 /01 0 p rovi de th e JE DEC approved Soft-

ware Data P rote ction s cheme for all data altera tion opera-

tions, i.e., Program and Erase. Any Program operation

requires the inclusion of a series of three byte sequence.

The three byte-load sequence is used to initiate the Pro-

gram operation, providing optimal protection from inadvert-

ent write operations, e.g., during the system power-up or

power -down. Any Erase operation requires the inclusion of

six byte load sequence. The SST39SF512 device is

shipped with the Software Data Protection permanently

enabled. See Table 4 for the specific software command

codes. During SDP command sequence, invalid com-

mands will abort the device to read mode, within TRC.

Product Identifica tion

The produc t identification mode identifies the device as the

SST39SF512 and SST39SF010 and manufacturer as

SST. This mode may be accessed by software operations.

Users ma y use the softw are product identification operation

to identify the part (i.e., using the device ID) when using

multiple manufacturers in the same sock et. For detail s, see

Tabl e 3 for hardware operation or Table 4 for software oper-

ation, Figure 11 for the software ID entry and read timing

diagram and Figure 17 for the ID entry command

sequence flowchart.

Product Identification Mode Exit/Reset

In order to return to the standard Read mode, the Software

Produc t Ident ificati on mode must be exited. Exit is acco m-

plished by issuing the Software ID Exit command

sequence , which returns the device to the Read operation.

Please note that the software reset command is ignored

during an internal Program or Erase operation. See Table 4

for software command codes, Figure 12 for timing wave-

f orm and Fi gure 17 f or a flowchart.

TABLE 1: PRODUCT IDENTIFICATION

Address Data

Manufacturer’s ID 0000H BFH

Device ID

SST39LF/VF512 0001H B4H

SST39LF/VF010 0001H B5H

T1.1 394

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN PLCC

Y-Decoder

I/O Buffers and Data Latches

394 ILL B1.1

Address Buffers & Latches

X-Decoder

DQ7 - DQ0

Memory Address

OE#

CE#

WE#

SuperFlash

Memory

Control Logic

FUNCTIONAL BLOCK DIAGRAM

SST39SF512SST39SF010

SST39SF512 SST39SF010

SST39SF512SST39SF010

SST39SF512 SST39SF010

DQ0

A14

A13

A11

OE#

A10

CE#

DQ7

A14

A13

A11

OE#

A10

CE#

DQ7

4 3 2 1 32 31 30

A12

A15

VDD

WE#

A12

A15

A16

VDD

WE#

32-pin PLCC

Top View

394 ILL F02b.4

14 15 16 17 18 19 20

DQ1

DQ2

VSS

DQ3

DQ4

DQ5

DQ6

DQ1

DQ2

VSS

DQ3

DQ4

DQ5

DQ6

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN TSOP (8MM X 14MM)

FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP

A11

A13

A14

WE#

VDD

A15

A12

A11

A13

A14

WE#

VDD

A16

A15

A12

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

394 ILL F01.2

Standard Pinout

Top View

Die Up

SST39SF512SST39SF010 SST39SF512 SST39SF010

32-pin

PDIP

Top View

394 ILL F02a.3

A15

A12

DQ0

DQ1

DQ2

VSS

A16

A15

A12

DQ0

DQ1

DQ2

VSS

SST39SF512SST39SF010 SST39SF512 SST39SF010

VDD

WE#

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VDD

WE#

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

TABLE 2: PIN DESCRIPTION

Symbol Pin Name Functions

AMS1-A0Address Inputs To provide memory addresses.

During Sector-Eras e AMS-A12 address lines will select the sector.

DQ7-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high.

CE# Chip Enable To activate the device when CE# is low.

OE# Output Enable To gate the data output buffers.

WE# Write Enable To control the Write operations.

VDD Power Supply To provide 5.0V supply (±10%)

VSS Ground

NC No Connection Unconnected pins.

T2.3 394

1. AMS = Most significant address

AMS = A15 for SST39SF512 and A16 for SST39SF010

TABLE 3: OPERATION MODES SELECTION

Mode CE# OE# WE# DQ Address

Read VIL VIL VIH DOUT AIN

Program VIL VIH VIL DIN AIN

Erase VIL VIH VIL X1

1. X can be VIL or VIH, but no other value.

Sector address,

XXH for Chip-Erase

Standby VIH X X High Z X

Write Inhibit X VIL X High Z/ DOUT X

XXV

IH High Z/ DOUT X

Product Identification

Softw are Mode VIL VIL VIH See Table 4

T3.4 394

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command

Sequence 1st Bus

Write Cycle 2nd Bus

Write Cycle 3rd Bus

Write Cycle 4th Bus

Write Cycle 5th Bus

Write Cycle 6th Bus

Write Cycle

Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data

Byte-Program 5555H AAH 2AAAH 55H 5555H A0H BA2Data

Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SAX330H

Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Softw are ID Entry4,5 5555H AAH 2AAAH 55H 5555H 90H

Softw are ID Exit6XXH F0H

Softw are ID Exit65555H AAH 2AAAH 55H 5555H F0H

T4.3 394

1. Address format A14-A0 (Hex), Address A15 can be VIL or VIH, but no other value, for the Command sequence for SST39SF512.

Addresses A15 - A16 can be VIL or VIH, but no other value, for the Command sequence for

SST39SF010.

2. BA = Program By te address

3. SAX for Sector-Erase; uses AMS-A12 address lines

AMS = Most significant address

AMS = A15 for SST39SF512 and A16 for SST39SF010

4. The device does not remain in Software Product ID Mode if powered down.

5. With AMS-A1 =0; SST Manufacturer’s ID= BFH, is read with A0 = 0,

SST39LF/VF512 Device ID = B4H, is read with A0 = 1

SST39LF/VF010 Device ID = B5H, is read with A0 = 1

6. Both Software ID Exit operations are equivalent

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause pe r manent da mage to the device. This is a stres s rating only and funct ional operatio n

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on An y Pin to G round Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD + 0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to VDD + 1.0V

Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 14.0V

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

Output Short Circuit Cur rent1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

1. Outputs shor ted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE

Range Ambient Temp VDD

Commercial 0°C to +70°C5.0V±10%

Industrial -40°C to +85°C5.0V±10%

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . 10 ns

Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF for 70 ns

Output Load . . . . . . . . . . . . . . . . . . . . . CL = 100 pF for 90 ns

See Figures 13 and 14

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

TABLE 5: DC OPERATING CHARACTERISTICS VDD = 5.0V±10%

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Power Supply Current Address input=VIL/VIH, at f=1/TRC Min

VDD=VDD Max

Read 30 mA CE#=OE#=VIL, WE#=VIH, all I/Os open

Write 50 mA CE#=WE#=VIL, OE#=VIH

ISB1 Standby VDD Current

(TTL input) 3µACE#=V

IH, VDD=VDD Max

ISB2 Standby VDD Current

(CMOS input) 50 µA CE#=VDD -0.3V, VDD=VDD Max

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VIH Input High Voltage 2.0 V VDD=VDD Max

VOL Output Low Voltage 0.4 V IOL=2.1 mA, VDD=VDD Min

VOH Output High Vol tage 2 .4 V IOH=-400 µA, VDD=VDD Min

VHSupervoltage for A9 pin 11.4 12.6 V CE#=OE#=VIL, WE#=VIH

IHSupervoltag e Current for A9 pin 200 µA CE#=OE#=VIL, WE#=VIH, A9=VH Max

T5.3 394

TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could aff ect this parameter.

Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Program/Erase Operation 100 µs

T6.1 394

TABLE 7: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could aff ect this parameter.

I/O Pin Capacitance VI/O = 0V 12 pF

CIN1Input Capacitance VIN = 0V 6 pF

T7.0 394

TABLE 8: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

NEND1

1. This parameter is measured only for initial qualification and after a design or process change that could aff ect this parameter.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

T8.1 394

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

AC CHARACTERISTICS

TABLE 9: READ CYCLE TIMING PARAMETERS VDD = 5.0V±10%

Symbol Parameter

SST39SF512/010-70 SST39SF512/010-90

UnitsMinMaxMinMax

TRC Read Cyc le Tim e 70 90 ns

TCE Chip Enable Access Time 70 90 ns

TAA Address Access Time 70 90 ns

TOE Output Enable Access Time 35 45 ns

TCLZ1

1. This parameter is measured only for initial qualification and after a design or process change that could aff ect this parameter.

CE# Low to Active Output 0 0 ns

TOLZ1OE# Low to Active Output 0 0 ns

TCHZ1CE# High to High-Z Output 25 30 ns

TOHZ1OE# High to High-Z Output 25 30 ns

TOH1Output Hold from Address Change 0 0 ns

T9.2 394

TABLE 10: PROGRAM/ERASE CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units

TBP Byte-Program Time 20 µs

TAS Address Setup Time 0 ns

TAH Address Hold Time 30 ns

TCS WE# and CE# Setup Time 0 ns

TCH WE# and CE# Hold Time 0 ns

TOES OE# Hi gh Setup Ti me 0 ns

TOEH OE# High Hold Time 10 ns

TCP CE# Pulse Width 40 ns

TWP WE# Pulse Width 40 ns

TWPH1

1. This parameter is measured only for initial qualification and after a design or process change that could aff ect this parameter.

WE# Pulse Width High 30 ns

TCPH1CE# Pulse Width High 30 ns

TDS Data Setup Time 30 ns

TDH1Data Hold Time 0 ns

TIDA1Software ID Access and Exit Time 150 ns

TSE Sector-Erase 10 ms

TSCE Chip-Erase 20 ms

T10.0 394

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

FIGURE 4: READ CYCLE TIMING DIAGRAM

FIGURE 5: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

394 ILL F03.1

ADDRESS AMS-0

DQ7-0

WE#

OE#

CE# TCE

TRC TAA

TOE

TOLZVIH

HIGH-Z TCLZ TOH TCHZ HIGH-Z

D ATA VALIDD ATA VALID

TOHZ

Note: AMS = Most significant address

AMS = A15 for SST39SF512 and A16 for SST39SF010

394 ILL F04.1

ADDRESS AMS-0

Note: AMS = Most significant address

AMS = A15 for SST39SF512 and A16 for SST39SF010

DQ7-0

TDH

TWPH

TDS

TWP

TAH

TAS

TCH

TCS

CE#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

AA 55 A0 DATA

INTERNAL PROGRAM OPERATION STARTS

BYTE

(ADDR/DATA)

OE#

WE#

TBP

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

FIGURE 6: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

FIGURE 7: DATA# POLLING TIMING DIAGRAM

394 ILL F05.1

ADDRESS AMS-0

DQ7-0

TDH

TCPH

TDS

TCP

TAH

TAS

TCH

TCS

WE#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

AA 55 A0 DATA

INTERNAL PROGRAM OPERATION STARTS

BYTE

(ADDR/DATA)

OE#

CE#

TBP

Note: AMS = Most significant address

AMS = A15 for SST39SF512 and A16 for SST39SF010

394 ILL F06.1

ADDRESS AMS-0

Note: AMS = Most significant address

AMS = A15 for SST39SF512 and A16 for SST39SF010

DQ7DD# D# D

WE#

OE#

CE#

TOEH

TOE

TCE

TOES

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

FIGURE 8: TOGGLE BIT TIMING DIAGRAM

FIGURE 9: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM

394 ILL F07.1

ADDRESS AMS-0

DQ6

WE#

OE#

CE#

TOETOEH

TCE

TOES

TWO READ CYCLES

WITH SAME OUTPUTS

Note

Note: Toggle bit output is always high first.

AMS = Most significant address

AMS = A15 for SST39SF512 and A16 for SST39SF010

394 ILL F08.2

Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 10)

SAX = Sector Address

AMS = Most significant address

AMS = A15 for SST39SF512 and A16 for SST39SF010

ADDRESS AMS-0

DQ7-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

55 3055AA 80 AA

SAX

OE#

CE#

SIX-BYTE CODE FOR SECTOR-ERASE

TSE

TWP

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

FIGURE 10: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM

FIGURE 11: SOFTWARE ID ENTRY AND READ

394 ILL F17.1

ADDRESS AMS-0

Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 10)

SAX = Sector Address

AMS = Most significant address

AMS = A15 for SST39SF512 and A16 for SST39SF010

DQ7-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

55 1055AA 80 AA

5555

OE#

CE#

SIX-BYTE CODE FOR CHIP-ERASE

TSCE

TWP

394 ILL F09.2

ADDRESS A14-0

TIDA

DQ7-0

WE#

SW0 SW1 SW2

5555 2AAA 5555 0000 0001

OE#

CE#

Three-byte sequence for

Software ID Entry

TWP

TWPH TAA

Device ID

55AA 90

Device ID = B5H for SST39SF010 and B6H for SST39SF020

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

FIGURE 12: SOFTWARE ID EXIT AND RESET

394 ILL F10.0

ADDRESS A14-0

DQ7-0

TIDA

TWP

T WHP

WE#

SW0 SW1 SW2

5555 2AAA 5555

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

OE#

CE#

AA 55 F0

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

FIGURE 13: AC INPUT/OUTPUT REFERENCE WAVEFORMS

FIGURE 14: A TEST LOAD EXAMPLE

394 ILL F11.0

REFERENCE POINTS OUTPUTINPUT

VHT

VLT

VHT

VLT

VIHT

VILT

AC test inpu ts ar e dri ven at VIHT (2.4V) fo r a logic “1” and VILT (0.4 V) for a logic “0”. Me asure ment r eference point s for

inputs and outputs are VHT (2.0 V) and VLT (0.8 V). Input rise and f all times (10% ↔ 90%) are <10 ns .

Note: VHT - VHIGH Test

VLT - VLOW Test

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

394 ILL F12.1

TEST LOAD EXAMPLE

T O TESTER

TO DUT

CLRL LOW

RL HIGH

VDD

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

FIGURE 15: BYTE-PROGRAM ALGORITHM

394 ILL F13.1

Start

Load data: AAH

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: A0H

Address: 5555H

Byte

Address/Byte

Data

Wait for end of

Program (TBP'

Data# Polling

bit or Toggle bit

operation)

Program

Completed

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

FIGURE 16: WAIT OPTIONS

394 ILL F14.0

W ait TBP,

TSCE, or TSE

Program/Erase

Initiated

Internal Timer Toggle Bit

Yes

Program/Erase

Completed

Does DQ6

match?

Read same

byte

Data# Polling

Write

Completed

Write

Completed

Read byte

Is DQ7 =

true data?

Read DQ7

Byte-Program

Initiated

Byte-Program/

Sector Erase

Initiated

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

FIGURE 17: SOFTWARE PRODUCT COMMAND FLOWCHARTS

394 ILL F15.1

Load data: AAH

Address: 5555H

Software Product ID Entry

Command Sequence

Load data: 55H

Address: 2AAAH

Load data: 90H

Address: 5555H

W ait TIDA

Read Software ID

Load data: AAH

Address: 5555H

Software Product ID Exit &

Reset Command Sequence

Load data: 55H

Address: 2AAAH

Load data: F0H

Address: 5555H

Load data: F0H

Address: XXH

Return to normal

operation

W ait TIDA

Return to normal

operation

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

FIGURE 18: ERASE COMMAND SEQUENCE

394 ILL F16.1

Load data: AAH

Address: 5555H

Chip-Erase

Command Sequence

Load data: 55H

Address: 2AAAH

Load data: 80H

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 10H

Address: 5555H

Load data: AAH

Address: 5555H

W ait TSCE

Chip-Erase

to FFH

Load data: AAH

Address: 5555H

Sector-Erase

Command Sequence

Load data: 55H

Address: 2AAAH

Load data: 80H

Address: 5555H

Load data: 55H

Address: 2AAAH

Load data: 30H

Address: SAX

Load data: AAH

Address: 5555H

W ait TSE

Sector-Erase

to FFH

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

SST39SF512 Valid combinations

SST39SF512-70-4C-NH SST39SF512-70-4C-WH SST39SF512-70-4C-PH

SST39SF512-90-4C-NH SST39SF512-90-4C-WH SST39SF512-90-4C-PH

SST39SF512-90-4C-U3

SST39SF512-70-4I-NH SST39SF512-70-4I-WH

SST39SF512-90-4I-NH SST39SF512-90-4I-WH

SST39SF010 Valid combinations

SST39SF010-70-4C-NH SST39SF010-70-4C-WH SST39SF010-70-4C-PH

SST39SF010-90-4C-NH SST39SF010-90-4C-WH SST39SF010-90-4C-PH

SST39SF010-90-4C-U4

SST39SF010-90-4I-NH SST39SF010-90-4I-WH

Example: Va lid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

Device Speed Suffix1 Suffix2

SST39SFxxx -XX -XX-XX

Package Mo d ifie r

H = 32 pins

Numeric = Die modifier

Package Ty pe

N = PLCC

W = TSOP (die up) (8mm x 14mm)

P = PDIP

U = Unenca ps ula ted die

Temperature Range

C = Commercial = 0°C to +70°C

I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

70 = 70 ns

90 = 90 ns

Device Density

512 = 512 Kilobit

010 = 1 Mega bi t

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

PACKAGING DIAGRAMS

32-PIN PLASTIC LEAD CHIP CARRIER (PLCC)

SST PACKAGE CODE: NH

32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM

SST PACKAGE CODE: WH

.030

.040

.013

.021 .490

.530

.075

.095

.015 Min.

.125

.140

T OP VIEW SIDE VIEW BO TT OM VIEW

1232

.026

.032

.400

BSC

32.PLCC.NH-ILL.2

Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (min/max).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.

4. Coplanarity: 4 mils.

.050

BSC.

.050

BSC.

.026

.032

.023

.029

.447

.453

.042

.048

.042

.048

Optional

Pin #1 Identifier

.547

.553

.585

.595

.485

.495

.020 R.

MAX.

.106

.112

x 30˚

32.TSOP-WH-ILL.4

Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (min/max).

3. Coplanarity: 0.1 (±.05) mm.

4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.

8.10

7.90

.270

.170

1.05

0.95

.50

BSC

0.15

0.05

12.50

12.30

Pin # 1 Identifier

14.20

13.80

0.70

0.50

Data Sheet

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

32-PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP)

SST PACKAGE CODE: PH

32.pdipPH-ILL.2

Pin #1 Identifier

Base Plane

Seating Plane

Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (min/max).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.

.170

.200

7˚

4 PLCS.

.600 BSC

.100 BSC

.120

.150

.016

.022

.045

.065

.070

.080

.015

.050

.065

.075 1.645

1.655

.008

.012

0˚

15˚

.600

.625

.530

.550

Silicon Storage Technology, Inc. • 117 1 Sonora Court • Sunnyvale , CA 940 86 • Telephone 408-735-9110 • Fax 408-735-90 36