LM4859
LM4859  Stereo 1.2W Audio Sub-system with 3D Enhancement
Literature Number: SNAS256D
LM4859
Stereo 1.2W Audio Sub-system with 3D Enhancement
General Description
The LM4859 is an integrated audio sub-system designed for
stereo cell phone applications. Operating on a 3.3V supply, it
combines a stereo speaker amplifier delivering 495mW per
channel into an 8Ωload and a stereo headphone amplifier
delivering 33mW per channel into a 32Ωload. It integrates
the audio amplifiers, volume control, mixer, power manage-
ment control, and National 3D enhancement all into a single
package. In addition, the LM4859 routes and mixes the
stereo and mono inputs into 10 distinct output modes. The
LM4859 is controlled through an I
2
C compatible interface.
Other features include an ultra-low current shutdown mode
and thermal shutdown protection.
Boomer audio power amplifiers are designed specifically to
provide high quality output power with a minimal amount of
external components.
The LM4859 is available in a 30–bump TL package and a
28–lead LLP package.
Key Specifications
jP
OUT
, Stereo Loudspeakers, 4Ω, 5V,
1% THD+N (LM4859SP) 1.6W (typ)
jP
OUT
, Stereo Loudspeakers, 8Ω, 5V,
1% THD+N 1.2W (typ)
jP
OUT
, Stereo Headphones, 32Ω, 5V,
1% THD+N 75mW (typ)
jP
OUT
, Stereo Loudspeakers, 8Ω, 3.3V,
1% THD+N 495mW (typ)
jP
OUT
, Stereo Headphones, 32Ω, 3.3V,
1% THD+N 33mW (typ)
jShutdown Current 0.06µA (typ)
Features
nStereo speaker amplifier
nStereo headphone amplifier
nIndependent Left, Right, and Mono volume controls
nNational 3D enhancement
nI
2
C compatible interface
nUltra low shutdown current
nClick and Pop Suppression circuit
n10 distinct output modes
nThermal Shutdown Protection
nAvailable in micro SMD and LLP packages
Applications
nCell Phones
nPDAs
nPortable Gaming Devices
nInternet Appliances
nPortable DVD/CD/AAC/MP3 players
Boomer®is a registered trademark of National Semiconductor Corporation.
June 2005
LM4859 Stereo 1.2W Audio Sub-system with 3D Enhancement
© 2006 National Semiconductor Corporation DS201061 www.national.com
Typical Application
20106101
FIGURE 1. Typical Audio Amplifier Application Circuit
LM4859
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Connection Diagrams
30 Bump TL Package micro SMD Marking
20106108
Top View
(Bump-side down)
Order Number LM4859TL
See NS Package Number TLA30CZA
20106163
Top View
XY - 2 Digit date code
TT - Die run traceability
G - Boomer Family
F1 - LM4859TL
Pin Connections (TL)
Pin Name Pin Description
A1 RLS+ Right Loudspeaker Positive Output
A2 V
DD
Power Supply
A3 SDA Data
A4 RHP3D Right Headphone 3D
A5 RHP Right Headphone Output
B1 GND Ground
B2 I
2
CV
DD
I
2
C Interface Power Supply
B3 ADR I
2
C Address Select
B4 LHP3D Left Headphone 3D
B5 V
DD
Power Supply
C1 RLS- Right Loudspeaker Negative Output
C2 NC No Connect
C3 SCL Clock
C4 NC No Connect
C5 GND Ground
D1 LLS- Left Loudspeaker Negative Output
D2 V
DD
Power Supply
D3 M
IN
Mono Input
D4 NC No Connect
D5 NC No Connect
E1 GND Ground
E2 BYPASS Half-supply bypass
E3 LLS3D Left Loudspeaker 3D
E4 R
IN
Right Stereo Input
E5 NC No Connect
F1 LLS+ Left Loudspeaker Positive Output
F2 V
DD
Power Supply
F3 RLS3D Right Loudspeaker 3D
F4 L
IN
Left Stereo Input
F5 LHP Left Headphone Output
LM4859
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Connection Diagram
28 – Lead SP Package
20106199
Top View
Order Number LM4859SP
See NS Package Number SPA28A
LM4859
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Pin Connections (SP)
Pin Name Pin Description
1 RHP Right Headphone Output
2V
DD
Power Supply
3 NC No Connect
4 GND Ground
5 NC No Connect
6 NC No Connect
7 LHP Left Headphone Output
8 RIN Right Stereo Input
9 LIN Left Stereo Input
10 MIN Mono Input
11 LLS3D Left Loudspeaker 3D
12 RLS3D Right Loudspeaker 3D
13 BYPASS Half-supply bypass
14 V
DD
Power Supply
15 LLS+ Left Loudspeaker Positive Output
16 GND Ground
17 LLS- Left Loudspeaker Negative Output
18 V
DD
Power Supply
19 RLS- Right Loudspeaker Negative Output
20 GND Ground
21 RLS+ Right Loudspeaker Positive Output
22 V
DD
Power Supply
23 I
2
CV
DD
I
2
C Interface Power Supply
24 SDA Data
25 ADR I
2
C Address Select
26 SCL Clock
27 RHP3D Right Headphone 3D
28 LHP3D Left Headphone 3D
LM4859
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Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage 6.0V
Storage Temperature −65˚C to +150˚C
Input Voltage −0.3V to V
DD
+0.3V
Power Dissipation (Note 3) Internally Limited
ESD Susceptibility (Note 4) 2000V
ESD Susceptibility (Note 5) 200V
Junction Temperature (T
J
) 150˚C
Thermal Resistance
θ
JA
(SPA28A) (Note 10) 42˚C/W
θ
JC
(SPA28A) 3˚C/W
θ
JA
(TLA30CZA) (Note 12) 62˚C/W
Operating Ratings
Temperature Range
T
MIN
≤T
A
≤T
MAX
−40˚C ≤T
A
≤+85˚C
Supply Voltage
2.7V ≤V
DD
≤5.5V
2.5V ≤I
2
CV
DD
≤5.5V
Audio Amplifier Electrical Characteristics V
DD
= 5.0V (Notes 1, 2)
The following specifications apply for V
DD
= 5.0V, unless otherwise specified. Limits apply for T
A
= 25˚C.
Symbol Parameter Conditions LM4859 Units
(Limits)
Typical
(Note 6)
Limits (Notes
7, 8)
I
DD
Supply Current
V
IN
= 0V, No load;
LD5 = RD5 = 0 (Note 9)
Mode 4, 9, 14 5 8 mA (max)
Mode 2, 3, 7, 8, 12, 13 13 21 mA (max)
I
SD
Shutdown Current Output mode 0 (Note 9) 0.2 3 µA (max)
P
O
Output Power
LM4859SP
Speaker; THD+N = 1%;
f = 1kHz; 4ΩBTL
1.6 W
Speaker; THD+N = 1%;
f = 1kHz; 8ΩBTL 1.2 0.9 W (min)
Headphone; THD+N = 1%;
f = 1kHz; 32ΩSE 75 60 mW (min)
THD+N Total Harmonic Distortion Plus
Noise
LD5=RD5=0
Speaker; P
O
= 400mW;
f = 1kHz; 8ΩBTL 0.05 %
Headphone; P
O
= 15mW;
f = 1kHz; 32ΩSE 0.04 %
V
OS
Offset Voltage Speaker; LD5 = RD5 = 0 5 40 mV (max)
N
OUT
Output Noise
A-weighted, 0dB gain; (Note 11)
LD5 = RD5 = 0; Audio Inputs Terminated
Speaker; Mode 2, 3, 7, 8 27 µV
Speaker; Mode 12, 13 38 µV
Headphone; Mode 3, 4, 8, 9 10 µV
Headphone; Mode 13, 14 14 µV
PSRR Power Supply Rejection Ratio
f = 217Hz; V
rip
= 200mV
pp
;C
B
= 2.2µF;
0dB gain; (Note 11)
LD5 = RD5 = 0; Audio Inputs Terminated
Speaker; Mode 2, 3, 7, 8 70 dB
Speaker; Mode 12, 13, 64 54 dB (min)
Headphone; Mode 3, 4, 8, 9 86 dB
Headphone; Mode 13, 14 73 60 dB (min)
LM4859
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Audio Amplifier Electrical Characteristics V
DD
= 5.0V (Notes 1, 2) (Continued)
The following specifications apply for V
DD
= 5.0V, unless otherwise specified. Limits apply for T
A
= 25˚C.
Symbol Parameter Conditions LM4859 Units
(Limits)
Typical
(Note 6)
Limits (Notes
7, 8)
Xtalk Crosstalk
LD5=RD5=0
Loudspeaker; P
O
= 400mW;
f = 1kHz 85 dB
Headphone; P
O
= 15mW;
f = 1kHz 85 dB
T
WU
Wake-up Time CD5=0;C
B
= 2.2µF 120 ms
CD5=1;C
B
= 2.2µF 230 ms
Audio Amplifier Electrical Characteristics V
DD
= 3.0V (Notes 1, 2)
The following specifications apply for V
DD
= 3.0V, unless otherwise specified. Limits apply for T
A
= 25˚C.
Symbol Parameter Conditions LM4859 Units
(Limits)
Typical
(Note 6)
Limits (Notes
7, 8)
I
DD
Supply Current
V
IN
= 0V, No load;
LD5 = RD5 = 0 (Note 9)
Mode 4, 9, 14 4.5 7.5 mA (max)
Mode 2, 3, 7, 8, 12, 13 11.2 19 mA (max)
I
SD
Shutdown Current Mode 0 (Note 9) 0.06 2.5 µA (max)
P
O
Output Power
LM4859SP
Speaker; THD+N = 1%;
f = 1kHz; 4ΩBTL
530 mW
P
O
Output Power
Speaker; THD+N = 1%;
f = 1kHz; 8ΩBTL 400 320 mW (min)
Headphone; THD+N = 1%;
f = 1kHz; 32ΩSE 25 20 mW (min)
THD+N Total Harmonic Distortion Plus
Noise
LD5=RD5=0
Speaker; P
O
= 200mW;
f = 1kHz; 8ΩBTL 0.05 %
Headphone; P
O
= 10mW;
f = 1kHz; 32ΩSE 0.04 %
V
OS
Offset Voltage Speaker; LD5 = RD5 = 0 5 40 mV (max)
N
OUT
Output Noise
A-weighted; 0dB gain; (Note 11)
LD5 = RD5 = 0; All Inputs Terminated
Speaker; Mode 2, 3, 7, 8 27 µV
Speaker; Mode 12, 13 38 µV
Headphone; Mode 3, 4, 8, 9 10 µV
Headphone; Mode 13, 14 14 µV
PSRR Power Supply Rejection Ratio
f = 217Hz, V
rip
= 200mV
pp
;C
B
= 2.2µF;
0dB gain; (Note 11)
LD5 = RD5 = 0; All Audio Inputs
Terminated
Speaker; Mode 2, 3, 7, 8 70 dB
Speaker; Mode 12, 13, 65 55 dB (min)
Headphone; Mode 3, 4, 8, 9 87 dB
Headphone; Mode 13, 14 75 62 dB (min)
LM4859
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Audio Amplifier Electrical Characteristics V
DD
= 3.0V (Notes 1, 2) (Continued)
The following specifications apply for V
DD
= 3.0V, unless otherwise specified. Limits apply for T
A
= 25˚C.
Symbol Parameter Conditions LM4859 Units
(Limits)
Typical
(Note 6)
Limits (Notes
7, 8)
Xtalk Crosstalk
LD5=RD5=0
Loudspeaker; P
O
= 200mW;
f = 1kHz 82 dB
Headphone; P
O
= 10mW;
f = 1kHz 82 dB
T
WU
Wake-up Time CD5=0;C
B
= 2.2µF 80 ms
CD5=1;C
B
= 2.2µF 140 ms
Volume Control Electrical Characteristics (Notes 1, 2)
The following specifications apply for V
DD
= 5.0V and V
DD
= 3.0V, unless otherwise specified. Limits apply for T
A
= 25˚C.
Symbol Parameter Conditions LM4859 Units
(Limits)
Typical
(Note 6)
Limits (Notes
7, 8)
Stereo Volume Control Range
maximum gain setting 6 5.5
6.5
dB (min)
dB (max)
minimum gain setting -40.5 -41
-40
dB (min)
dB (max)
Mono Volume Control Range
maximum gain setting 12 11.5
12.5
dB (min)
dB (max)
minimum gain setting -34.5 -35
-34
dB (min)
dB (max)
Volume Control Step Size 1.5 dB
Volume Control Step Size
Error
+/-0.2 +/-0.5 dB (max)
Stereo Channel to Channel
Gain Mismatch 0.3 dB
Mute Attenuation Mode 12, V
in
=1V
RMS
Headphone 85 dB
L
IN
and R
IN
Input Impedance
maximum gain setting 33.5 25
42
kΩ(min)
kΩ(max)
minimum gain setting 100 75
125
kΩ(min)
kΩ(max)
M
IN
Input Impedance
maximum gain setting 20 15
25
kΩ(min)
kΩ(max)
minimum gain setting 98 73
123
kΩ(min)
kΩ(max)
Control Interface Electrical Characteristics (Notes 1, 2)
The following specifications apply for V
DD
= 5V and V
DD
= 3V and 2.5V ≤I
2
CV
DD
≤5.5V, unless otherwise specified. Limits
apply for T
A
= 25˚C.
Symbol Parameter Conditions LM4859 Units
(Limits)
Typical
(Note 6)
Limits (Notes
7, 8)
t
1
SCL period 2.5 µs (min)
t
2
SDA Set-up Time 100 ns (min)
t
3
SDA Stable Time 0 ns (min)
t
4
Start Condition Time 100 ns (min)
t
5
Stop Condition time 100 ns (min)
LM4859
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Control Interface Electrical Characteristics (Notes 1, 2) (Continued)
The following specifications apply for V
DD
= 5V and V
DD
= 3V and 2.5V ≤I
2
CV
DD
≤5.5V, unless otherwise specified. Limits
apply for T
A
= 25˚C.
Symbol Parameter Conditions LM4859 Units
(Limits)
Typical
(Note 6)
Limits (Notes
7, 8)
V
IH
Digital Input High Voltage 0.7 x I
2
CVDD V (min)
V
IL
Digital Input Low Voltage 0.3 x I
2
CV
DD
V (max)
Note 1: All voltages are measured with respect to the GND pin unless otherwise specified.
Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which
guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit
is given, however, the typical value is a good indication of device performance.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX,θJA, and the ambient temperature, TA. The maximum
allowable power dissipation is PDMAX =(T
JMAX -T
A)/θJA or the number given in Absolute Maximum Ratings, whichever is lower. For the LM4859 operating in Mode
3, 8, or 13 with VDD =5V,8Ωstereo loudspeakers and 32Ωstereo headphones, the total power dissipation is 1.348W. θJA = 62˚C/W.
Note 4: Human body model, 100pF discharged through a 1.5kΩresistor.
Note 5: Machine Model, 220pF-240pF discharged through all pins.
Note 6: Typicals are measured at +25˚C and represent the parametric norm.
Note 7: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Note 9: Shutdown current and supply current are measured in a normal room environment. All digital input pins are connected to I2CVDD.
Note 10: The given θJA is for an LM4859SP mounted on a PCB with a 2in2area of 10oz printed circuit board ground plane.
Note 11: “0dB gain” refers to the volume control gain setting of MIN,L
IN, and RIN set at 0dB.
Note 12: The given θJA is for an LM4859TL mounted on a PCB with a 2in2area of 10oz printed circuit board ground plane.
External Components Description
Components Functional Description
1. C
IN
This is the input coupling capacitor. It blocks the DC voltage and couples the input signal to the
amplifier’s input terminals. C
IN
also creates a high pass filter with the internal resistor R
i
(Input
Impedance) at f
C
= 1/(2πR
i
C
IN
).
2. C
S
This is the supply bypass capacitor. It filters the supply voltage applied to the V
DD
pin and helps
reduce the noise at the V
DD
pin.
3. C
B
This is the BYPASS pin capacitor. It filters the V
DD
/ 2 voltage and helps maintain the LM4859’s
PSRR.
4. C
OUT
This is the output coupling capacitor. It blocks the DC voltage and couples the output signal to the
speaker load R
L
.C
OUT
also creates a high pass filter with R
L
at f
O
= 1/(2πR
L
C
OUT
).
5. R
3D
This resistor sets the gain of the National 3D effect. Please refer to the National 3D Enhancement
section for information on selecting the value of R
3D
.
6. C
3D
This capacitor sets the frequency at which the National 3D effect starts to occur. Please refer to the
National 3D Enhancement section for information on selecting the value of C
3D
.
LM4859
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Typical Performance Characteristics (Note 11)
LM4859SP THD+N vs Frequency LM4859SP THD+N vs Frequency
20106155
V
DD
= 5V; LLS, RLS; P
O
= 400mW;
R
L
=4Ω; Mode 7; 0dB Gain
20106156
V
DD
= 3V; LLS, RLS; P
O
= 200mW;
R
L
=4Ω; Mode 7; 0dB Gain
LM4859SP THD+N vs Output Power LM4859SP THD+N vs Output Power
20106157
V
DD
= 5V; LLS, RLS; f = 1kHz;
R
L
=4Ω; Mode 7; 0dB Gain
20106158
V
DD
= 3V; LLS, RLS; f = 1kHz;
R
L
=4Ω; Mode 7; 0dB Gain
LM4859
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Typical Performance Characteristics (Note 11) (Continued)
THD+N vs Frequency THD+N vs Frequency
20106110
V
DD
= 5V; LLS, RLS; P
O
= 400mW;
R
L
=8Ω; Mode 7; 0dB Gain
20106111
V
DD
= 3V; LLS, RLS; P
O
= 200mW;
R
L
=8Ω; Mode 7; 0dB Gain
THD+N vs Frequency THD+N vs Frequency
20106112
V
DD
= 5V; LHP, RHP; P
O
= 15mW;
R
L
=32Ω; Mode 9; 0dB Gain
20106113
V
DD
= 3V; LHP, RHP; P
O
= 10mW;
R
L
=32Ω; Mode 9; 0dB Gain
LM4859
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Typical Performance Characteristics (Note 11) (Continued)
THD+N vs Output Power THD+N vs Output Power
20106120
V
DD
= 5V; LLS, RLS; f = 1kHz;
R
L
=8Ω; Mode 7; 0dB Gain
20106121
V
DD
= 3V; LLS, RLS; f = 1kHz;
R
L
=8Ω; Mode 7; 0dB Gain
THD+N vs Output Power THD+N vs Output Power
20106122
V
DD
= 5V; LHP, RHP; f = 1kHz;
R
L
=32Ω; Mode 9; 0dB Gain
20106123
V
DD
= 3V; LHP, RHP; f = 1kHz;
R
L
=32Ω; Mode 9; 0dB Gain
LM4859
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Typical Performance Characteristics (Note 11) (Continued)
PSRR vs Frequency PSRR vs Frequency
20106126
V
DD
= 5V; LLS, RLS; R
L
=8Ω; 0db Gain;
All audio inputs terminated
Top-Mode 12, 13; Mid-Mode 2, 3; Bot-Mode 7, 8
20106127
V
DD
= 3V; LLS, RLS; R
L
=8Ω; 0db Gain;
All audio inputs terminated
Top-Mode 12, 13; Mid-Mode 2, 3; Bot-Mode 7, 8
PSRR vs Frequency PSRR vs Frequency
20106128
V
DD
= 5V; LHP, RHP; R
L
=32Ω; 0db Gain;
All audio inputs terminated
Top-Mode 13, 14; Mid-Mode 3, 4; Bot-Mode 8, 9
20106129
V
DD
= 3V; LHP, RHP; R
L
=32Ω; 0db Gain;
All audio inputs terminated
Top-Mode 13, 14; Mid-Mode 3, 4; Bot-Mode 8, 9
LM4859
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Typical Performance Characteristics (Note 11) (Continued)
Crosstalk vs Frequency Crosstalk vs Frequency
20106134
V
DD
= 5V; LLS, RLS; P
O
= 400mW; R
L
=8Ω;
Mode 7; 0db Gain; 3D off
Top-Left to Right; Bot-Right to Left
20106135
V
DD
= 3V; LLS, RLS; P
O
= 200mW; R
L
=8Ω;
Mode 7; 0db Gain; 3D off
Top-Left to Right; Bot-Right to Left
Crosstalk vs Frequency Crosstalk vs Frequency
20106136
V
DD
= 5V; LHP, RHP; P
O
= 15mW; R
L
=32Ω;
Mode 9; 0db Gain; 3D off
Top-Left to Right; Bot-Right to Left
20106137
V
DD
= 3V; LHP, RHP; P
O
= 10mW; R
L
=32Ω;
Mode 9; 0db Gain; 3D off
Top-Left to Right; Bot-Right to Left
LM4859
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Typical Performance Characteristics (Note 11) (Continued)
Frequency vs Response Frequency vs Response
20106138
LLS, RLS; R
L
=8Ω;
Mode 2; Full Gain
20106139
LLS, RLS; R
L
=8Ω;
Mode 7; Full Gain
Frequency vs Response Frequency vs Response
20106140
LHP, RHP; R
L
=32Ω;C
O
= 100µF
Mode 4; Full Gain
20106141
LHP, RHP; R
L
=32Ω;C
O
= 100µF
Mode 9; Full Gain
LM4859
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Typical Performance Characteristics (Note 11) (Continued)
Power Dissipation vs Output Power Power Dissipation vs Output Power
20106145
LLS, RLS; R
L
=8Ω; THD+N ≤1%
Top-V
DD
= 5V; Bot-V
DD
=3V
per channel
20106146
LHP, RHP; R
L
=32Ω; THD+N ≤1%
Top-V
DD
= 5V; Bot-V
DD
=3V
per channel
Output Power vs Load Resistance Output Power vs Load Resistance
20106148
LLS, RLS; R
L
=8Ω;
Top-V
DD
= 5V, 10% THD+N; Topmid-V
DD
= 5V, 1% THD+N;
Botmid-V
DD
= 3V, 10% THD+N; Bot-V
DD
= 3V, 1% THD+N
20106149
LHP, RHP; R
L
=32Ω;
Top-V
DD
= 5V, 10% THD+N; Topmid-V
DD
= 5V, 1% THD+N;
Botmid-V
DD
= 3V, 10% THD+N; Bot-V
DD
= 3V, 1% THD+N
LM4859
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Typical Performance Characteristics (Note 11) (Continued)
Output Power vs Supply Voltage Output Power vs Supply Voltage
20106152
LLS, RLS; R
L
=8Ω;
Top–10% THD+N; Bot–1% THD+N
20106153
LHP, RHP; R
L
=32Ω;
Top–10% THD+N; Bot–1% THD+N
LM4859
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Application Information
TABLE 1. Chip Address
A7 A6 A5 A4 A3 A2 A1 A0
Chip Address 111110EC0
ADR=011111000
ADR=111111010
EC - externally configured by ADR pin
TABLE 2. Control Registers
D7 D6 D5 D4 D3 D2 D1 D0
Mono Volume control 0 0 0 MD4 MD3 MD2 MD1 MD0
Left Volume control 0 1 LD5 LD4 LD3 LD2 LD1 LD0
Right Volume control 1 0 RD5 RD4 RD3 RD2 RD1 RD0
Mode control 1 1 CD5 0 CD3 CD2 CD1 CD0
201061F5
FIGURE 2. I
2
C Bus Format
201061F4
FIGURE 3. I
2
C Timing Diagram
LM4859
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Application Information (Continued)
TABLE 3. Mono Volume Control
MD4 MD3 MD2 MD1 MD0 Gain (dB)
00000 -34.5
00001 -33.0
00010 -31.5
00011 -30.0
00100 -28.5
00101 -27.0
00110 -25.5
00111 -24.0
01000 -22.5
01001 -21.0
01010 -19.5
01011 -18.0
01100 -16.5
01101 -15.0
01110 -13.5
01111 -12.0
10000 -10.5
10001 -9.0
10010 -7.5
10011 -6.0
10100 -4.5
10101 -3.0
10110 -1.5
10111 0.0
11000 1.5
11001 3.0
11010 4.5
11011 6.0
11100 7.5
11101 9.0
11110 10.5
11111 12.0
LM4859
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Application Information (Continued)
TABLE 4. Stereo Volume Control
LD4//RD4 LD3//RD3 LD2//RD2 LD1//RD1 LD0//RD0 Gain (dB)
00000-40.5
00001-39.0
00010-37.5
00011-36.0
00100-34.5
00101-33.0
00110-31.5
00111-30.0
01000-28.5
01001-27.0
01010-25.5
01011-24.0
01100-22.5
01101-21.0
01110-19.5
01111-18.0
10000-16.5
10001-15.0
10010-13.5
10011-12.0
10100-10.5
10101-9.0
10110-7.5
10111-6.0
11000-4.5
11001-3.0
11010-1.5
110110.0
111001.5
111013.0
111104.5
111116.0
LM4859
www.national.com 20
Application Information (Continued)
TABLE 5. Mixer and Output Mode
Mode CD3 CD2 CD1 CD0 Loudspeaker L Loudspeaker R Headphone L Headphone R
00000 SD SD SD SD
1 0 0 0 1 RESERVED
200102(G
M
x M) 2(G
M
x M) MUTE MUTE
300112(G
M
x M) 2(G
M
xM) (G
M
xM) (G
M
xM)
40100 SD SD (G
M
xM) (G
M
xM)
5 0 1 0 1 RESERVED
6 0 1 1 0 RESERVED
701112(G
L
x L) 2(G
R
x R) MUTE MUTE
810002(G
L
x L) 2(G
R
xR) (G
L
xL) (G
R
xR)
91001 SD SD (G
L
xL) (G
R
xR)
10 1 0 1 0 RESERVED
11 1 0 1 1 RESERVED
12 1 1 0 0 2(G
L
xL)+
2(GMxM)
2(G
R
xR)+
2(GMxM)
MUTE MUTE
13 1 1 0 1 2(G
L
xL)+
2(GMxM)
2(G
R
xR)+
2(GMxM)
(G
L
xL)+
(G
M
xM)
(G
R
xR)+
(G
M
xM)
141110 SD SD (G
L
xL)+
(G
M
xM)
(G
R
xR)+
(G
M
xM)
15 1 1 1 1 RESERVED
M-M
IN
Input Level
L-L
IN
Input Level
R-R
IN
Input Level
G
M
- Mono Volume Control Gain
G
L
- Left Stereo Volume Control Gain
G
R
- Right Stereo Volume Control Gain
SD - Shutdown
MUTE - Mute
TABLE 6. National 3D Enhancement
LD5 0 Loudspeaker National 3D Off
1 Loudspeaker National 3D On
RD5 0 Headphone National 3D Off
1 Headphone National 3D On
TABLE 7. Wake-up Time Select
CD5 0 Fast Wake-up Setting
1 Slow Wake-up Setting
LM4859
www.national.com21
Application Information (Continued)
I
2
C COMPATIBLE INTERFACE
The LM4859 uses a serial bus, which conforms to the I
2
C
protocol, to control the chip’s functions with two wires: clock
(SCL) and data (SDA). The clock line is uni-directional. The
data line is bi-directional (open-collector). The maximum
clock frequency specified by the I
2
C standard is 400kHz. In
this discussion, the master is the controlling microcontroller
and the slave is the LM4859.
The I
2
C address for the LM4859 is determined using the
ADR pin. The LM4859’s two possible I
2
C chip addresses are
of the form 111110X
1
0 (binary), where X
1
= 0, if ADR is logic
low; and X
1
= 1, if ADR is logic high. If the I
2
C interface is
used to address a number of chips in a system, the
LM4859’s chip address can be changed to avoid any pos-
sible address conflicts.
The bus format for the I
2
C interface is shown in Figure 2. The
bus format diagram is broken up into six major sections:
The "start" signal is generated by lowering the data signal
while the clock signal is high. The start signal will alert all
devices attached to the I
2
C bus to check the incoming ad-
dress against their own address.
The 8-bit chip address is sent next, most significant bit first.
The data is latched in on the rising edge of the clock. Each
address bit must be stable while the clock level is high.
After the last bit of the address bit is sent, the master
releases the data line high (through a pull-up resistor). Then
the master sends an acknowledge clock pulse. If the
LM4859 has received the address correctly, then it holds the
data line low during the clock pulse. If the data line is not
held low during the acknowledge clock pulse, then the mas-
ter should abort the rest of the data transfer to the LM4859.
The 8 bits of data are sent next, most significant bit first.
Each data bit should be valid while the clock level is stable
high.
After the data byte is sent, the master must check for another
acknowledge to see if the LM4859 received the data.
If the master has more data bytes to send to the LM4859,
then the master can repeat the previous two steps until all
data bytes have been sent.
The "stop" signal ends the transfer. To signal "stop", the data
signal goes high while the clock signal is high. The data line
should be held high when not in use.
I
2
C INTERFACE POWER SUPPLY PIN (I
2
CV
DD
)
The LM4859’s I
2
C interface is powered up through the
I
2
CV
DD
pin. The LM4859’s I
2
C interface operates at a volt-
age level set by the I
2
CV
DD
pin which can be set indepen-
dent to that of the main power supply pin V
DD
. This is ideal
whenever logic levels for the I
2
C interface are dictated by a
microcontroller or microprocessor that is operating at a lower
supply voltage than the main battery of a portable system.
NATIONAL 3D ENHANCEMENT
The LM4859 features a 3D audio enhancement effect that
widens the perceived soundstage from a stereo audio signal.
The 3D audio enhancement improves the apparent stereo
channel separation whenever the left and right speakers are
too close to one another, due to system size constraints or
equipment limitations.
An external RC network, shown in Figure 1, is required to
enable the 3D effect. There are separate RC networks for
both the stereo loudspeaker outputs as well as the stereo
headphone outputs, so the 3D effect can be set indepen-
dently for each set of stereo outputs.
The amount of the 3D effect is set by the R
3D
resistor.
Decreasing the value of R
3D
will increase the 3D effect. The
C
3D
capacitor sets the low cutoff frequency of the 3D effect.
Increasing the value of C
3D
will decrease the low cutoff
frequency at which the 3D effect starts to occur, as shown by
Equation 1.
f
3D(-3dB)
=1/2π(R
3D
)(C
3D
) (1)
Activating the 3D effect will cause an increase in gain by a
multiplication factor of (1 + 9kΩ/R
3D
). Setting R
3D
to 9kΩwill
result in a gain increase by a multiplication factor of (1+
9kΩ/9kΩ)=2or6dBwhenever the 3D effect is activated.
The volume control can be programmed through the I
2
C
compatible interface to compensate for the extra 6dB in-
crease in gain. For example, if the stereo volume control is
set at 0dB (11011 from Table 4) before the 3D effect is
activated, the volume control should be programmed to
–6dB (10111 from Table 4) immediately after the 3D effect
has been activated. Setting R
3D
= 20kΩand C
3D
= 0.22µF
allows the LM4859 to produce a pronounced 3D effect with a
minimal increase in output noise.
EXPOSED-DAP MOUNTING CONSIDERATIONS
The LM4859’s exposed-DAP (die attach paddle) package
(SP) provides a low thermal resistance between the die and
the PCB to which the part is mounted and soldered. This
allows rapid heat transfer from the die to the surrounding
PCB copper area heatsink, copper traces, ground plane, and
finally, surrounding air. The result is a low voltage audio
power amplifier that produces 1.6W dissipation in a 4Ωload
at ≤1% THD+N and over 1.8W in a 3Ωload at 10% THD+N.
This high power is achieved through careful consideration of
necessary thermal design. Failing to optimize thermal design
may compromise the LM4859’s high power performance and
activate unwanted, though necessary, thermal shutdown
protection.
The SP package must have its DAP soldered to a copper
pad on the PCB. The DAP’s PCB copper pad is then, ideally,
connected to a large plane of continuous unbroken copper.
This plane forms a thermal mass, heat sink, and radiation
area. Place the heat sink area on either outside plane in the
case of a two-sided or multi-layer PCB. (The heat sink area
can also be placed on an inner layer of a multi-layer board.
The thermal resistance, however, will be higher.) Connect
the DAP copper pad to the inner layer or backside copper
heat sink area with 9 (3 X 3) (SP) vias. The via diameter
should be 0.012in - 0.013in with a 1.27mm pitch. Ensure
efficient thermal conductivity by plugging and tenting the vias
with plating and solder mask, respectively.
Best thermal performance is achieved with the largest prac-
tical copper heat sink area. If the heatsink and amplifier
share the same PCB layer, a nominal 2in
2
area is necessary
for 5V operation with a 4Ωload. Heatsink areas not placed
on the same PCB layer as the LM4859 should be 4in
2
for the
same supply voltage and load resistance. The last two area
recommendations apply for 25˚C ambient temperature. In-
crease the area to compensate for ambient temperatures
above 25˚C. In all circumstances and under all conditions,
the junction temperature must be held below 150˚C to pre-
vent activating the LM4859’s thermal shutdown protection.
An example PCB layout for the exposed-DAP SP package is
LM4859
www.national.com 22
Application Information (Continued)
shown in the Demonstration Board Layout section. Further
detailed and specific information concerning PCB layout and
fabrication and mounting an SP (LLP) is found in National
Semiconductor’s AN1187.
PCB LAYOUT AND SUPPLY REGULATION
CONSIDERATIONS FOR DRIVING 3ΩAND 4ΩLOADS
Power dissipated by a load is a function of the voltage swing
across the load and the load’s impedance. As load imped-
ance decreases, load dissipation becomes increasingly de-
pendent on the interconnect (PCB trace and wire) resistance
between the amplifier output pins and the load’s connec-
tions. Residual trace resistance causes a voltage drop,
which results in power dissipated in the trace and not in the
load as desired. For example, 0.1Ωtrace resistance reduces
the output power dissipated by a 4Ωload from 1.6W to 1.5W.
The problem of decreased load dissipation is exacerbated
as load impedance decreases. Therefore, to maintain the
highest load dissipation and widest output voltage swing,
PCB traces that connect the output pins to a load must be as
wide as possible.
Poor power supply regulation adversely affects maximum
output power. A poorly regulated supply’s output voltage
decreases with increasing load current. Reduced supply
voltage causes decreased headroom, output signal clipping,
and reduced output power. Even with tightly regulated sup-
plies, trace resistance creates the same effects as poor
supply regulation. Therefore, making the power supply
traces as wide as possible helps maintain full output voltage
swing.
BRIDGE CONFIGURATION EXPLANATION
The LM4859 consists of two sets of bridged-tied amplifier
pairs that drive the left loudspeaker (LLS) and the right
loudspeaker (RLS). For this discussion, only the LLS bridge-
tied amplifier pair will be referred to. The LM4859 drives a
load, such as a speaker, connected between outputs, LLS+
and LLS-. In the LLS amplifier block, the output of the
amplifier that drives LLS- serves as the input to the unity gain
inverting amplifier that drives LLS+.
This results in both amplifiers producing signals identical in
magnitude, but 180˚ out of phase. Taking advantage of this
phase difference, a load is placed between LLS- and LLS+
and driven differentially (commonly referred to as ’bridge
mode’). This results in a differential or BTL gain of:
A
VD
= 2(R
f
/R
i
)=2 (2)
Both the feedback resistor, R
f
, and the input resistor, R
i
, are
internally set.
Bridge mode amplifiers are different from single-ended am-
plifiers that drive loads connected between a single amplifi-
er’s output and ground. For a given supply voltage, bridge
mode has a distinct advantage over the single-ended con-
figuration: its differential output doubles the voltage swing
across the load. Theoretically, this produces four times the
output power when compared to a single-ended amplifier
under the same conditions. This increase in attainable output
power assumes that the amplifier is not current limited and
that the output signal is not clipped.
Another advantage of the differential bridge output is no net
DC voltage across the load. This is accomplished by biasing
LLS- and LLS+ outputs at half-supply. This eliminates the
coupling capacitor that single supply, single-ended amplifiers
require. Eliminating an output coupling capacitor in a typical
single-ended configuration forces a single-supply amplifier’s
half-supply bias voltage across the load. This increases
internal IC power dissipation and may permanently damage
loads such as speakers.
POWER DISSIPATION
Power dissipation is a major concern when designing a
successful single-ended or bridged amplifier.
A direct consequence of the increased power delivered to
the load by a bridge amplifier is higher internal power dissi-
pation. The LM4859 has 2 sets of bridged-tied amplifier pairs
driving LLS and RLS. The maximum internal power dissipa-
tion operating in the bridge mode is twice that of a single-
ended amplifier. From Equation (3) and (4), assuming a 5V
power supply and an 8Ωload, the maximum power dissipa-
tion for LLS and RLS is 634mW per channel.
P
DMAX-LLS
= 4(V
DD
)
2
/(2π
2
R
L
): Bridged (3)
P
DMAX-RLS
= 4(V
DD
)
2
/(2π
2
R
L
): Bridged (4)
The LM4859 also has a pair of single-ended amplifiers driv-
ing LHP and RHP. The maximum internal power dissipation
for ROUT and LOUT is given by equation (5) and (6). From
Equations (5) and (6), assuming a 5V power supply and a
32Ωload, the maximum power dissipation for LOUT and
ROUT is 40mW per channel.
P
DMAX-LHP
=(V
DD
)
2
/(2π
2
R
L
): Single-ended (5)
P
DMAX-RHP
=(V
DD
)
2
/(2π
2
R
L
): Single-ended (6)
The maximum internal power dissipation of the LM4859
occurs during output modes 3, 8, and 13 when both loud-
speaker and headphone amplifiers are simultaneously on;
and is given by Equation (7).
P
DMAX-TOTAL
=
P
DMAX-LLS
+P
DMAX-RLS
+P
DMAX-LHP
+P
DMAX-RHP
(7)
The maximum power dissipation point given by Equation (7)
must not exceed the power dissipation given by Equation
(8):
P
DMAX
’=(T
JMAX
-T
A
)/θ
JA
(8)
The LM4859’s T
JMAX
= 150˚C. In the SP package, the
LM4859’s θ
JA
is 42˚C/W. At any given ambient temperature
T
A
, use Equation (8) to find the maximum internal power
dissipation supported by the IC packaging. Rearranging
Equation (8) and substituting P
DMAX-TOTAL
for P
DMAX
’ results
in Equation (9). This equation gives the maximum ambient
temperature that still allows maximum stereo power dissipa-
tion without violating the LM4859’s maximum junction tem-
perature.
T
A
=T
JMAX
-P
DMAX-TOTAL
θ
JA
(9)
LM4859
www.national.com23
Application Information (Continued)
For a typical application with a 5V power supply, stereo 8Ω
loudspeaker load, and the stereo 32Ωheadphone load, the
maximum ambient temperature that allows maximum stereo
power dissipation without exceeding the maximum junction
temperature is approximately 93.4˚C for the SP package.
T
JMAX
=P
DMAX-TOTAL
θ
JA
+T
A
(10)
Equation (10) gives the maximum junction temperature T
J-
MAX
. If the result violates the LM4859’s 150˚C, reduce the
maximum junction temperature by reducing the power sup-
ply voltage or increasing the load resistance. Further allow-
ance should be made for increased ambient temperatures.
The above examples assume that a device is a surface
mount part operating around the maximum power dissipation
point. Since internal power dissipation is a function of output
power, higher ambient temperatures are allowed as output
power or duty cycle decreases. If the result of Equation (7) is
greater than that of Equation (8), then decrease the supply
voltage, increase the load impedance, or reduce the ambient
temperature. If these measures are insufficient, a heat sink
can be added to reduce θ
JA
. The heat sink can be created
using additional copper area around the package, with con-
nections to the ground pin(s), supply pin and amplifier output
pins. External, solder attached SMT heatsinks such as the
Thermalloy 7106D can also improve power dissipation.
When adding a heat sink, the θ
JA
is the sum of θ
JC
,θ
CS
, and
θ
SA
.(θ
JC
is the junction-to-case thermal impedance, θ
CS
is
the case-to-sink thermal impedance, and θ
SA
is the sink-to-
ambient thermal impedance.) Refer to the Typical Perfor-
mance Characteristics curves for power dissipation informa-
tion at lower output power levels.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is
critical for low noise performance and high power supply
rejection. Applications that employ a 5V regulator typically
use a 10µF in parallel with a 0.1µF filter capacitors to stabi-
lize the regulator’s output, reduce noise on the supply line,
and improve the supply’s transient response. However, their
presence does not eliminate the need for a local 1.0µF
tantalum bypass capacitance connected between the
LM4859’s supply pins and ground. Keep the length of leads
and traces that connect capacitors between the LM4859’s
power supply pin and ground as short as possible.
SELECTING EXTERNAL COMPONENTS
Input Capacitor Value Selection
Amplifying the lowest audio frequencies requires a high
value input coupling capacitor (C
i
in Figure 1). In many
cases, however, the speakers used in portable systems,
whether internal or external, have little ability to reproduce
signals below 50Hz. Applications using speakers with this
limited frequency response reap little improvement; by using
a large input capacitor.
The internal input resistor (R
i
) and the input capacitor (C
i
)
produce a high pass filter cutoff frequency that is found using
Equation (13).
f
c
=1/(2πR
i
C
i
)(11)
As an example when using a speaker with a low frequency
limit of 50Hz and R
i
= 20kΩ,C
i
, using Equation (13) is
0.19µF. The 0.22µF C
i
shown in Figure 4 allows the LM4859
to drive high efficiency, full range speaker whose response
extends below 40Hz.
Output Capacitor Value Selection
Amplifying the lowest audio frequencies also requires the
use of a high value output coupling capacitor (C
O
in Figure
1). A high value output capacitor can be expensive and may
compromise space efficiency in portable design.
The speaker load (R
L
) and the output capacitor (C
O
) form a
high pass filter with a low cutoff frequency determined using
Equation (14).
f
c
=1/(2πR
L
C
O
) (12)
When using a typical headphone load of R
L
=32Ωwith a low
frequency limit of 50Hz, C
O
is 99µF.
The 100µF C
O
shown in Figure 4 allows the LM4859 to drive
a headphone whose frequency response extends below
50Hz.
Bypass Capacitor Value Selection
Besides minimizing the input capacitor size, careful consid-
eration should be paid to value of C
B
, the capacitor con-
nected to the BYPASS pin. Since C
B
determines how fast
the LM4859 settles to quiescent operation, its value is critical
when minimizing turn-on pops. The slower the LM4859’s
outputs ramp to their quiescent DC voltage (nominally V
DD
/
2), the smaller the turn-on pop. Choosing C
B
equal to 2.2µF
along with a small value of C
i
(in the range of 0.1µF to
0.39µF), produces a click-less and pop-less shutdown func-
tion. As discussed above, choosing C
i
no larger than neces-
sary for the desired bandwidth helps minimize clicks and
pops. C
B
’s value should be in the range of 5 times to 10
times the value of C
i
. This ensures that output transients are
eliminated when the LM4859 transitions in and out of shut-
down mode. Connecting a 2.2µF capacitor, C
B
, between the
BYPASS pin and ground improves the internal bias voltage’s
stability and improves the amplifier’s PSRR. The PSRR im-
provements increase as the bypass pin capacitor value in-
creases. However, increasing the value of C
B
will increase
wake-up time. The selection of bypass capacitor value, C
B
,
depends on desired PSRR requirements, click and pop per-
formance, wake-up time, system cost, and size constraints.
LM4859
www.national.com 24
Application Information (Continued)
20106102
FIGURE 4. Reference Design Board Schematic
LM4859
www.national.com25
Demonstration Board Layout
20106162
Recommended SP PCB Layout:
Silkscreen Layer
20106159
Recommended SP PCB Layout:
Top Layer
20106161
Recommended SP PCB Layout:
Mid Layer
20106160
Recommended SP PCB Layout:
Bottom Layer
LM4859
www.national.com 26
Revision History
Rev Date Description
1.1 6/02/05 Added Modes 9 and 14 into Mode 4
(Conditions) for the Idd under Elect.Char
tables 5V and 3V, then re-released D/S to the
WEB (per Alvin Fok). (MC)
1.2 06/06/06 Edited the micro SMD markings (per Alvin F.),
then re-released D/S to the WEB.
LM4859
www.national.com27
Physical Dimensions inches (millimeters) unless otherwise noted
30 Bump TL Package
Order Number LM4859TL
NS Package Number TLA30CZA
LM4859
www.national.com 28
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
28 – Lead SP Package
Order Number LM4859SP
NS Package Number SPA28A
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor follows the provisions of the Product Stewardship Guide for Customers (CSP-9-111C2) and Banned Substances
and Materials of Interest Specification (CSP-9-111S2) for regulatory environmental compliance. Details may be found at:
www.national.com/quality/green.
Lead free products are RoHS compliant.
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Support Center
Email: new.feedback@nsc.com
Tel: 1-800-272-9959
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Fax: +49 (0) 180-530 85 86
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Tel: 81-3-5639-7560
www.national.com
LM4859 Stereo 1.2W Audio Sub-system with 3D Enhancement
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Products Applications
Audio www.ti.com/audio Communications and Telecom www.ti.com/communications
Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers
Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps
DLP®Products www.dlp.com Energy and Lighting www.ti.com/energy
DSP dsp.ti.com Industrial www.ti.com/industrial
Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical
Interface interface.ti.com Security www.ti.com/security
Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Power Mgmt power.ti.com Transportation and Automotive www.ti.com/automotive
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
TI E2E Community Home Page e2e.ti.com
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