Rev. 1.1 9/08 Copyright © 2008 by Silicon Laboratories Si570/Si571
Si570/Si571
ANY-RATE I2C PROGRAMMABLE XO/VCXO
Features
Applications
Description
The Si570 XO/Si571 VCXO utilizes Silicon Laboratories’ advanced DSPLL
®
circuitry to provide a low-jitter clock at any frequency. The Si570/Si571 are
user-programmable to any output frequency from 10 to 945 MHz and select
frequencies to 1400 MHz with <1 ppb resolution. The device is programmed
via an I
2
C serial interface. Unlike traditional XO/VCXOs where a different
crystal is required for each output frequency, the Si57x uses one fixed-
frequency crystal and a DSPLL clock synthesis IC to provide any-rate
frequency operation. This IC-based approach allows the crystal resonator to
provide exceptional frequency stability and reliability. In addition, DSPLL
clock synthesis provides superior supply noise rejection, simplifying the task
of generating low-jitter clocks in noisy environments typically found in
communication systems.
Functional Block Diagram
Any-rate programmable output
frequencies from 10 to 945 MHz and
select frequencies to 1.4 GHz
I2C serial interface
3rd generation DSPLL® with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available LVPECL, CMOS,
LVDS, and CML outputs
Industry-standard 5x7 mm
package
Pb-free/RoHS-compliant
1.8, 2.5, or 3.3 V supply
SONET / SDH
xDSL
10 GbE LAN / WAN
Low-jitter clock generation
Optical modules
Clock and data recovery
Fixed
Frequency
XO
Any-rate
10-1400 MHz
DSPLL®Clock
Synthesis
CLK- CLK+
SCL
GND
OE
VDD
SDA
VC
ADC
Si571 only
Ordering Information:
See page 24.
Pin Assignments:
See page 23.
(Top View)
Si5602
Si570
Si571
1
2
3
6
5
4
NC
GND
OE
VDD
CLK+
CLK–
SDA
SCL
8
7
1
2
3
6
5
4
VC
GND
OE
VDD
CLK+
CLK–
SDA
SCL
8
7
Si570/Si571
2 Rev. 1.1
Si570/Si571
Rev. 1.1 3
TABLE OF CONTENTS
Section Page
1. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.1. Programming a New Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.2. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4. Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
5. Si570 (XO) Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
6. Si571 (VCXO) Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
7. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
8. Si57x Mark Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
9. Outline Diagram and Suggested Pad Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
10. 8-Pin PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Si570/Si571
4 Rev. 1.1
1. Detailed Block Diagrams
Figure 1. Si570 Detailed Block Diagram
Figure 2. Si571 Detailed Block Diagram
Frequency
Control
Control
Interface
NVM
÷HS_DIV ÷N1
+DCO
RFREQ
CLKOUT+
CLKOUT–
VDD GND
fXTAL
fosc
M
SDA
OE
SCL
RAM
Frequency
Control
Control
Interface
NVM
÷HS_DIV ÷N1
+DCOADC
RFREQ
VCADC
VC
CLKOUT+
CLKOUT–
VDD GND
fXTAL
fosc
M
SDA
OE
SCL
RAM
Si570/Si571
Rev. 1.1 5
2. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Symbol Test Condition Min Typ Max Units
Supply Voltage1VDD
3.3 V option 2.97 3.3 3.63
V2.5 V option 2.25 2.5 2.75
1.8 V option 1.71 1.8 1.89
Supply Current IDD
Output enabled
LVPECL
CML
LVDS
CMOS
—
—
—
—
120
108
99
90
130
117
108
98
mA
TriState mode — 60 75
Output Enable (OE)2,
Serial Data (SDA),
Serial Clock (SCL)
VIH 0.75 x VDD ——
V
VIL ——0.5
Operating Temperature Range TA–40 — 85 ºC
Notes:
1. Selectable parameter specified by part number. See Section "7. Ordering Information" on page 24 for further details.
2. OE pin includes a 17 kΩ pullup resistor to VDD. See “7.Ordering Information”.
Table 2. VC Control Voltage Input
Parameter Symbol Test Condition Min Typ Max Units
Control Voltage Tuning Slope1,2,3 KVVC 10 to 90% of VDD —
33
45
90
135
180
356
— ppm/V
Control Voltage Linearity4LVC
BSL –5 ±1 +5 %
Incremental –10 ±5 +10
Modulation Bandwidth BW 9.3 10.0 10.7 kHz
VC Input Impedance ZVC 500 — — kΩ
Nominal Control Voltage VCNOM @ fO—V
DD/2 — V
Control Voltage Tuning Range VC0V
DD V
Notes:
1. Positive slope; selectable option by part number. See "7. Ordering Information" on page 24.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. KV variation is ±10% of typical values.
4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope is
determined with VC ranging from 10 to 90% of VDD.
Si570/Si571
6 Rev. 1.1
Table 3. CLK± Output Frequency Characteristics
Parameter Symbol Test Condition Min Typ Max Units
Programmable Frequency
Range1,2,3 fO
LVPECL/LVDS/CML 10 — 1417.5
MHz
CMOS 10 — 160
Temperature Stability1,4 TA= –40 to +85 ºC
–20
–50
–100
—
—
—
+20
+50
+100
ppm
Initial Accuracy —1.5—
ppm
Aging fa
Frequency drift over first year — — ±3 ppm
Frequency drift over 15 year life — — ±10 ppm
Total Stability
Temp stability = ±20 ppm — — ±31.5 ppm
Temp stability = ±50 ppm — — ±61.5 ppm
Absolute Pull Range1,4 APR ±25 — ±375 ppm
Power up Time5tOSC ——10ms
Notes:
1. See Section "7. Ordering Information" on page 24 for further details.
2. Specified at time of order by part number. Three speed grades available:
Grade A covers 10 to 945 MHz, 970 to 1134 MHz, and 1213 to 1417.5 MHz.
Grade B covers 10 to 810 MHz.
Grade C covers 10 to 280 MHz.
3. Nominal output frequency set by VCNOM =1/2xV
DD.
4. Selectable parameter specified by part number.
5. Time from power up or tristate mode to fO.
Si570/Si571
Rev. 1.1 7
Table 4. CLK± Output Levels and Symmetry
Parameter Symbol Test Condition Min Typ Max Units
LVPECL Output Option1
VOmid-level VDD – 1.42 — VDD – 1.25 V
VOD swing (diff) 1.1 —1.9 VPP
VSE swing (single-ended) 0.55 —0.95 VPP
LVDS Output Option2
VOmid-level 1.125 1.20 1.275 V
VOD swing (diff) 0.5 0.7 0.9 VPP
CML Output Option2
VO
2.5/3.3 V option mid-level — VDD – 1.30 — V
1.8 V option mid-level — VDD – 0.36 — VPP
VOD
2.5/3.3 V option swing (diff) 1.10 1.50 1.90 V
1.8 V option swing (diff) 0.35 0.425 0.50 VPP
CMOS Output Option3VOH IOH =32mA 0.8 x VDD —VDD V
VOL IOL =32mA — — 0.4
Rise/Fall time (20/80%) tR, tF
LVPECL/LVDS/CML — — 350 ps
CMOS with CL=15pF — 1 — ns
Symmetry (duty cycle) SYM
LVPECL: VDD – 1.3 V (diff)
LVDS: 1.25 V (diff)
CMOS: VDD/2
45 — 55 %
Notes:
1. 50 Ω to VDD – 2.0 V.
2. Rterm =100Ω (differential).
3. CL=15pF
Table 5. CLK± Output Phase Jitter (Si570)
Parameter Symbol Test Condition Min Typ Max Units
Phase Jitter (RMS)*
for FOUT > 500 MHz
φJ12 kHz to 20 MHz (OC-48) — 0.25 0.40 ps
50 kHz to 80 MHz (OC-192) — 0.26 0.37
Phase Jitter (RMS)*
for FOUT of 125 to
500 MHz
φJ12 kHz to 20 MHz (OC-48) — 0.36 0.50 ps
50 kHz to 20 MHz (OC-192) — 0.34 0.42
Phase Jitter (RMS)
for FOUT of 10 to 160 MHz
CMOS Output Only
φJ12 kHz to 20 MHz (OC-48) — 0.62 — ps
50 kHz to 80 MHz (OC-192) — 0.61 —
*Note: Refer to AN256 for further information.
Si570/Si571
8 Rev. 1.1
Table 6. CLK± Output Phase Jitter (Si571)
Parameter Symbol Test Condition Min Typ Max Units
Phase Jitter (RMS)1,2,3
for FOUT > 500 MHz
φJKv = 33 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.26
0.26
—
—
ps
Kv = 45 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.27
0.26
—
—
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.32
0.26
—
—
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.40
0.27
—
—
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.49
0.28
—
—
Kv = 356 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.87
0.33
—
—
Notes:
1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
4. Single ended mode: CMOS. Refer to the following application notes for further information:
“AN255: Replacing 622 MHz VCSO Device with the Si55x VCXO”
“AN256: Integrated Phase Noise”
“AN266: VCXO Tuning Slope (Kv), Stability, and Absolute Pull Range (APR)”
Si570/Si571
Rev. 1.1 9
Phase Jitter (RMS)2,4
for FOUT 10 to 160 MHz
CMOS Output Only
φJKv = 33 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.63
0.62
—
—
ps
Kv = 45 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.63
0.62
—
—
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.67
0.66
—
—
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.74
0.72
—
—
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.83
0.8
—
—
Kv = 356 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
1.26
1.2
—
—
Table 6. CLK± Output Phase Jitter (Si571) (Continued)
Parameter Symbol Test Condition Min Typ Max Units
Notes:
1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
4. Single ended mode: CMOS. Refer to the following application notes for further information:
“AN255: Replacing 622 MHz VCSO Device with the Si55x VCXO”
“AN256: Integrated Phase Noise”
“AN266: VCXO Tuning Slope (Kv), Stability, and Absolute Pull Range (APR)”
Si570/Si571
10 Rev. 1.1
Phase Jitter (RMS)1,2,3
for FOUT of 125 to
500 MHz
φJKv = 33 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.37
0.33
—
—
ps
Kv = 45 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.37
0.33
—
—
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.43
0.34
—
—
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.50
0.34
—
—
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
0.59
0.35
—
—
Kv = 356 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
—
1.00
0.39
—
—
Table 7. CLK± Output Period Jitter
Parameter Symbol Test Condition Min Typ Max Units
Period Jitter* JPER
RMS — 2 —
ps
Peak-to-Peak — 14 —
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to “AN279: Estimating Period Jitter
from Phase Noise” for further information.
Table 6. CLK± Output Phase Jitter (Si571) (Continued)
Parameter Symbol Test Condition Min Typ Max Units
Notes:
1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
4. Single ended mode: CMOS. Refer to the following application notes for further information:
“AN255: Replacing 622 MHz VCSO Device with the Si55x VCXO”
“AN256: Integrated Phase Noise”
“AN266: VCXO Tuning Slope (Kv), Stability, and Absolute Pull Range (APR)”
Si570/Si571
Rev. 1.1 11
Table 8. Typical CLK± Output Phase Noise (Si570)
Offset Frequency (f) 120.00 MHz
LVDS
156.25 MHz
LVPECL
622.08 MHz
LVPECL
Units
100 Hz
1kHz
10 kHz
100 kHz
1MHz
10 MHz
100 MHz
–112
–122
–132
–137
–144
–150
n/a
–105
–122
–128
–135
–144
–147
n/a
–97
–107
–116
–121
–134
–146
–148
dBc/Hz
Table 9. Typical CLK± Output Phase Noise (Si571)
Offset Frequency (f) 74.25 MHz
90 ppm/V
LVPECL
491.52 MHz
45 ppm/V
LVPECL
622.08 MHz
135 ppm/V
LVPECL
Units
100 Hz
1kHz
10 kHz
100 kHz
1MHz
10 MHz
100 MHz
–87
–114
–132
–142
–148
–150
n/a
–75
–100
–116
–124
–135
–146
–147
–65
–90
–109
–121
–134
–146
–147
dBc/Hz
Table 10. Absolute Maximum Ratings
Parameter Symbol Rating Units
Supply Voltage, 1.8 V Option VDD –0.5 to +1.9 V
Supply Voltage, 2.5/3.3 V Option VDD –0.5 to +3.8 V
Input Voltage VI–0.5 to VDD + 0.3 V
Storage Temperature TS–55 to +125 ºC
ESD Sensitivity (HBM, per JESD22-A114) ESD >2500 V
Soldering Temperature (lead-free profile) TPEAK 260 ºC
Soldering Temperature Time @ TPEAK (lead-free profile) tP20–40 seconds
Notes:
1. Stresses beyond the absolute maximum ratings may cause permanent damage to the device. Functional operation or
specification compliance is not implied at these conditions.
2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at
www.silabs.com/VCXO for further information, including soldering profiles.
Si570/Si571
12 Rev. 1.1
Table 11. Environmental Compliance
The Si570/571 meets the following qualification test requirements.
Parameter Conditions/Test Method
Mechanical Shock MIL-STD-883F, Method 2002.3 B
Mechanical Vibration MIL-STD-883F, Method 2007.3 A
Solderability MIL-STD-883F, Method 203.8
Gross & Fine Leak MIL-STD-883F, Method 1014.7
Resistance to Solvents MIL-STD-883F, Method 2016
Table 12. Programming Constraints and Timing
(VDD = 3.3 V ±10%, TA= –40 to 85 ºC)
Parameter Symbol Test Condition Min Typ Max Unit
Output Frequency Range CKOF
HS_DIV x N1 > = 6 10 — 945 MHz
HS_DIV x N1 = 5
N1 = 1
970 — 1134 MHz
HS_DIV = 4
N1 = 1
1.2125 — 1.4175 GHz
Frequency Reprogramming
Resolution
MRES 114.285 MHz — 0.09 — ppb
Internal Oscillator Frequency fOSC 4850 — 5670 MHz
Internal Crystal Frequency
Accuracy
fXTAL Maximum variation is
±2000 ppm
— 114.285 — MHz
Delta Frequency for Continu-
ous Output
From center frequency –3500 — +3500 ppm
Unfreeze to NewFreq Delay 10 ms
Settling time for small
frequency change
<±3500 ppm from
center frequency
——100µs
Settling time for large
frequency change
>±3500 ppm from
center frequency after
setting NewFreq bit
——10 ms
Si570/Si571
Rev. 1.1 13
3. Functional Description
The Si570 XO and the Si571 VCXO are low-jitter
oscillators ideally suited for applications requiring
programmable frequencies. The Si57x can be
programmed to generate virtually any output clock in
the range of 10 MHz to 1.4 GHz. Output jitter
performance exceeds the strict requirements of high-
speed communication systems including OC-192/STM-
64 and 10 Gigabit Ethernet (10 GbE).
The Si57x consists of a digitally-controlled oscillator
(DCO) based on Silicon Laboratories' third-generation
DSPLL technology, which is driven by an internal fixed-
frequency crystal reference.
The device's default output frequency is set at the
factory and can be reprogrammed through the two-wire
I2C serial port. Once the device is powered down, it will
return to its factory-set default output frequency.
While the Si570 outputs a fixed frequency, the Si571
has a pullable output frequency using the voltage
control input pin. This makes the Si571 an ideal choice
for high-performance, low-jitter, phase-locked loops.
3.1. Programming a New Output
Frequency
The output frequency (fout) is determined by
programming the DCO frequency (fDCO) and the
device's output dividers (HS_DIV, N1). The output
frequency is calculated using the following equation:
The DCO frequency is adjustable in the range of 4.85 to
5.67 GHz by setting the high-resolution 38-bit fractional
multiplier (RFREQ). The DCO frequency is the product
of the internal fixed-frequency crystal (fXTAL) and
RFREQ.
The 38-bit resolution of RFREQ allows the DCO
frequency to have a programmable frequency resolution
of 0.09 ppb.
As shown in Figure 3, the device allows reprogramming
of the DCO frequency up to ±3500 ppm from the center
frequency configuration without interruption to the
output clock. Changes greater than the ±3500 ppm
window will cause the device to recalibrate its internal
tuning circuitry, forcing the output clock to momentarily
stop and start at any arbitrary point during a clock cycle.
This re-calibration process establishes a new center
frequency and can take up to 10 ms. Circuitry receiving
a clock from the Si57x device that is sensitive to glitches
or runt pulses may have to be reset once the
recalibration process is complete.
3.1.1. Reconfiguring the Output Clock for a Small
Change in Frequency
For output changes less than ±3500 ppm from the
center frequency configuration, the DCO frequency is
the only value that needs reprogramming. Since
fDCO =f
XTAL x RFREQ, and that fXTAL is fixed, changing
the DCO frequency is as simple as reconfiguring the
RFREQ value as outlined below:
1. Using the serial port, read the current RFREQ value
(registers 0x08–0x12).
2. Calculate the new value of RFREQ given the change
in frequency.
3. Using the serial port, write the new RFREQ value
(registers 0x08—0x12).
Example:
An Si570 generating a 148.35 MHz clock must be
reconfigured "on-the-fly" to generate a 148.5 MHz clock.
This represents a change of +1011.122 ppm, which is
well within the ±3500 ppm window.
Figure 3. DCO Frequency Range
fout
fDCO
Output Dividers
-----------------------------------------fXTAL RFREQ×
HSDIV N1×
-------------------------------------------
==
RFREQnew RFREQcurrent
fout_new
fout_current
-------------------------
×=
4.85 GHz 5.67 GHz
Center
Frequency
Configuration
-3500 ppm +3500 ppm
small frequency changes can be made
“on-the-fly” without interruption to the
output clock
Si570/Si571
14 Rev. 1.1
A typical frequency configuration for this example:
RFREQcurrent = 0x2EBB04CE0
Fout_current =148.35MHz
Fout_new =148.50MHz
Calculate RFREQnew to change the output frequency
from 148.35 MHz to 148.5 MHz:
Note that performing calculations with RFREQ requires
a minimum of 38-bit arithmetic precision.
3.1.2. Reconfiguring the Output Clock for Large
Changes in Output Frequency
For output frequency changes outside of ±3500 ppm
from the center frequency, it is likely that both the DCO
frequency and the output dividers need to be
reprogrammed. Note that changing the DCO frequency
outside of the ±3500 ppm window will cause the output
to momentarily stop and restart at any arbitrary point in
a clock cycle. Devices sensitive to glitches or runt
pulses may have to be reset once reconfiguration is
complete.
The process for reconfiguring the output frequency
outside of a ±3500 ppm window is shown below:
1. Using the serial port, read the current values for
RFREQ, HSDIV, and N1.
2. Calculate fXTAL for the device. Note that because of
slight variations of the internal crystal frequency from
one device to another, each device may have a
different RFREQ value or possibly even different
HSDIV or N1 values to maintain the same output
frequency. It is necessary to calculate fXTAL for each
device.
Once fXTAL has been determined, new values for
RFREQ, HSDIV, and N1 are calculated to generate a
new output frequency (fout_new). New values can be
calculated manually or with the Si57x-EVB software,
which provides a user-friendly application to help find
the optimum values.
The first step in manually calculating the frequency
configuration is to determine new frequency divider
values (HSDIV, N1). Given the desired output frequency
(fout_new), find the frequency divider values that will
keep the DCO oscillation frequency in the range of 4.85
to 5.67 GHz.
Valid values of HSDIV are 4, 5, 6, 7, 9 or 11. N1 can be
selected as 1 or any even number up to 128 (i.e. 1, 2, 4,
6, 8, 10 … 128). To help minimize the device's power
consumption, the divider values should be selected to
keep the DCO's oscillation frequency as low as
possible. The lowest value of N1 with the highest value
of HS_DIV also results in the best power savings.
Once HS_DIV and N1 have been determined, the next
step is to calculate the reference frequency multiplier
(RFREQ).
RFREQ is programmable as a 38-bit binary fractional
frequency multiplier with the first 10 most significant bits
(MSBs) representing the integer portion of the multiplier,
and the 28 least significant bits (LSBs) representing the
fractional portion.
Before entering a fractional number into the RFREQ
register, it must be converted to a 38-bit integer using a
bitwise left shift operation by 28 bits, which effectively
multiplies RFREQ by 228.
Example:
RFREQ = 46.043042064d
Multiply RFREQ by 228 = 12359584992.1
Discard the fractional portion = 12359584992
Convert to hexadecimal = 02E0B04CE0h
In the example above, the multiplication operation
requires 38-bit precision. If 38-bit arithmetic precision is
not available, then the fractional portion can be
separated from the integer and shifted to the left by 28-
bits. The result is concatenated with the integer portion
to form a full 38-bit word. An example of this operation is
shown in Figure 4.
RFREQnew 0x2EBB04CE0 148.50 MHz
148.35 MHz
--------------------------------
×
0x2EC71D666
=
=
fXTAL
Fout HSDIV×N1×
RFREQ
---------------------------------------------------
=
fDCO_new fout_new HSDIVnew
×N1new
×=
RFREQnew
fDCO_new
fXTAL
-----------------------
=
Si570/Si571
Rev. 1.1 15
Figure 4. Example of RFREQ Decimal to Hexadecimal Conversion
Once the new values for RFREQ, HSDIV, and N1 are
determined, they can be written directly into the device
from the serial port using the following procedure:
1. Freeze the DCO (bit 4 of Register 137)
2. Write the new frequency configuration (RFREQ,
HS_DIV, N1)
3. Unfreeze the DCO and assert the NewFreq bit (bit 6
of Register 135) within the maximum delay specified
in Table 12, “Programming Constraints and Timing,”
on page 12.
The process of freezing and unfreezing the DCO will
cause the output clock to momentarily stop and start at
any arbitrary point during a clock cycle. This process
can take up to 10 ms. Circuitry that is sensitive to
glitches or runt pulses may have to be reset after the
new frequency configuration is written.
Example:
An Si570 generating 156.25 MHz must be re-configured
to generate a 161.1328125 MHz clock (156.25 MHz x
66/64). This frequency change is greater than
±3500 ppm.
fout =156.25MHz
Read the current values for RFREQ, HS_DIV, N1:
RFREQcurrent = 0x2BC011EB8h = 11744124600d,
11744124600d x 228 = 43.7502734363d
HS_DIV = 4
N1 = 8
Calculate fXTAL, fDCO_current
Given fout_new = 161.1328125 MHz, choose output
dividers that will keep fDCO within the range of 4.85 to
5.67 GHz. In this case, keeping the same output
dividers will still keep fDCO within its range limits:
Calculate the new value of RFREQ given the new DCO
frequency:
46.043042064
Convert integer portion to a 10-bit binary number
46 = 00 0010 1110b
Concatenate the two results
00 0010 1110 0000 1011 0000 0100 1100 1110 0000b
Convert to Hex
02E0B04CE0h
Multiply the fractional portion by 228
.043042064 x 228 = 11554016.077
Truncate the remaining fractional portion
= 11554016
Convert to a 28-bit binary number (pad 0s on the left)
0000 1011 0000 0100 1100 1110 0000
fDCO_current fout HSDV×N1×5.000000000 GHz==
fXTAL
fDCO_current
RFREQcurrent
---------------------------------------114.285 MHz==
fDCO_new fout_new HSDVnew
×N1new
×
161.1328125 MHz 4×8×5.156250000 GHz
=
==
RFREQnew
fDCO_new
fXTAL
-----------------------45.11746934
0x2D1E12788
=
==
Si570/Si571
16 Rev. 1.1
3.2. I2C Interface
The control interface to the Si570 is an I2C-compatible
2-wire bus for bidirectional communication. The bus
consists of a bidirectional serial data line (SDA) and a
serial clock input (SCL). Both lines must be connected
to the positive supply via an external pullup.Fast mode
operation is supported for transfer rates up to 400 kbps
as specified in the I2C-Bus Specification standard.
Figure 5 shows the command format for both read and
write access. Data is always sent MSB. Data length is 1
byte. Read and write commands support 1 or more data
bytes as illustrated. The master must send a Not
Acknowledge and a Stop after the last read data byte to
terminate the read command. The timing specifications
and timing diagram for the I2C bus can be found in the
I2C-Bus Specification standard (fast mode operation).
The device I2C address is specified in the part number.
Figure 5. I2C Command Format
From master to slave From slave to master
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH).
Required after the last data byte to signal the end of the read comand to the slave.
S – START condition
P – STOP condition
P
A
A
Byte AddressA
S Slave Address 0 Data
Write Command
(Optional 2nd data byte and acknowledge illustrated)
A
Byte AddressA
S Slave Address 0 SSlave Address 1 A
AData
A
Data Data NP
Read Command
(Optional data byte and acknowledge before the last data byte and not acknowledge illustrated)
Si570/Si571
Rev. 1.1 17
4. Serial Port Registers
Note: Any register not listed here is reserved and must not be written. All bits are R/W unless otherwise noted.
Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
7 High Speed/
N1 Dividers
HS_DIV[2:0] N1[6:2]
8 Reference
Frequency
N1[1:0] RFREQ[37:32]
9 Reference
Frequency
RFREQ[31:24]
10 Reference
Frequency
RFREQ[23:16]
11 Reference
Frequency
RFREQ[15:8]
12 Reference
Frequency
RFREQ[7:0]
135 Reset/Memory
Control
RST_REG NewFreq RECALL
137 Freeze DCO Freeze
DCO
Si570/Si571
18 Rev. 1.1
Register 7. High Speed/N1 Dividers
BitD7D6D5D4D3D2D1D0
Name HS_DIV[2:0] N1[6:2]
Type R/W R/W
Bit Name Function
7:5 HS_DIV[2:0] DCO High Speed Divider.
Sets value for high speed divider that takes the DCO output fOSC as its clock input.
000 = 4
001 = 5
010 = 6
011 = 7
100 = Not used.
101 = 9
110 = Not used.
111 = 11
4:0 N1[6:2] CLKOUT Output Divider.
Sets value for CLKOUT output divider. Allowed values are [1] and [2, 4, 6, ..., 27]. Illegal
odd divider values will be rounded up to the nearest even value. The value for the N1 reg-
ister can be calculated by taking the divider ratio minus one. For example, to divide by 10,
write 0001001 (9 decimal) to the N1 registers.
0000000 = 1
1111111 = 27
Register 8. Reference Frequency
BitD7D6D5D4D3D2D1D0
Name N1[1:0] RFREQ[37:32]
Type R/W R/W
Bit Name Function
7:6 N1[1:0] CLKOUT Output Divider.
Sets value for CLKOUT output divider. Allowed values are [1, 2, 4, 6, ..., 27]. Illegal odd
divider values will be rounded up to the nearest even value. The value for the N1 regis-
ter can be calculated by taking the divider ratio minus one. For example, to divide by
10, write 0001001 (9 decimal) to the N1 registers.
0000000 = 1
1111111 = 27
5:0 RFREQ[37:32] Reference Frequency.
Frequency control input to DCO.
Si570/Si571
Rev. 1.1 19
Register 9. Reference Frequency
BitD7D6D5D4D3D2D1D0
Name RFREQ[31:24]
Type R/W
Bit Name Function
7:0 RFREQ[31:24] Reference Frequency.
Frequency control input to DCO.
Register 10. Reference Frequency
BitD7D6D5D4D3D2D1D0
Name RFREQ[23:16]
Type R/W
Bit Name Function
7:0 RFREQ[23:16] Reference Frequency.
Frequency control input to DCO.
Register 11. Reference Frequency
BitD7D6D5D4D3D2D1D0
Name RFREQ[15:8]
Type R/W
Bit Name Function
7:0 RFREQ[15:8] Reference Frequency.
Frequency control input to DCO.
Si570/Si571
20 Rev. 1.1
Reset settings = 00xx xx00
Register 12. Reference Frequency
BitD7D6D5D4D3D2D1D0
Name RFREQ[7:0]
Type R/W
Bit Name Function
7:0 RFREQ[7:0] Reference Frequency.
Frequency control input to DCO.
Register 135. Reset/Memory Control
BitD7D6D5D4D3D2D1D0
Name RST_REG NewFreq N/A RECALL
Type R/W R/W R/W R/W
Bit Name Function
7 RST_REG Internal Reset.
0 = Normal operation.
1 = Reset of all internal logic. Output tristated during reset.
Upon completion of internal logic reset, RST_REG is internally reset to zero.
6 NewFreq New frequency applied.
Alerts the DSPLL that a new frequency configuration has been applied. This bit will
clear itself when the new frequency is applied.
5:1 N/A Always zero.
0 RECALL Recall NVM into RAM.
0 = No operation.
1 = Write NVM bits into RAM. Bit is internally reset following completion of operation.
Si570/Si571
Rev. 1.1 21
Reset settings = 00xx xx00
Register 137. Freeze DCO
BitD7D6D5D4D3D2D1D0
Name Freeze
DCO
Type R/W
Bit Name Function
7:5 Reserved
4 Freeze DCO Freeze DCO.
Freezes the DSPLL so the frequency configuration can be modified.
3:0 Reserved
Si570/Si571
22 Rev. 1.1
5. Si570 (XO) Pin Descriptions
Table 13. Si570 Pin Descriptions
Pin Name Type Function
1NC N/A No Connect. Make no external connection to this pin.
2OE Input Output Enable:
See "7. Ordering Information" on page 24.
3GND Ground Electrical and Case Ground.
4CLK+ Output Oscillator Output.
5CLK–
(NC for CMOS*)
Output
(N/A for CMOS*)
Complementary Output.
(NC for CMOS*).
6 VDD Power Power Supply Voltage.
7SDA Bidirectional
Open Drain
I2C Serial Data.
8SCL Input I2C Serial Clock.
*Note: CMOS output option only: make no external connection to this pin.
(Top View)
1
2
3
6
5
4
NC
GND
OE
VDD
CLK+
CLK–
SDA
SCL
8
7
Si570/Si571
Rev. 1.1 23
6. Si571 (VCXO) Pin Descriptions
Table 14. Si571 Pin Descriptions
Pin Name Type Function
1 VCAnalog Input Control Voltage
2OE Input Output Enable:
See "7. Ordering Information" on page 24.
3GND Ground Electrical and Case Ground
4CLK+ Output Oscillator Output
5CLK–
(NC for CMOS*)
Output
(N/A for CMOS*)
Complementary Output.
(NC for CMOS*).
6 VDD Power Power Supply Voltage
7SDA Bidirectional
Open Drain
I2C Serial Data
8SCL Input I2C Serial Clock
*Note: CMOS output option only: make no external connection to this pin.
(Top View)
1
2
3
6
5
4
VC
GND
OE
VDD
CLK+
CLK–
SDA
SCL
8
7
Si570/Si571
24 Rev. 1.1
7. Ordering Information
The Si570/Si571 supports a wide variety of options including frequency range, start-up frequency, temperature
stability, tuning slope, output format, and VDD. Specific device configurations are programmed into the Si570/Si571
at time of shipment. Configurations are specified using the Part Number Configuration chart shown below. Silicon
Labs provides a web browser-based part number configuration utility to simplify this process. Refer to
www.silabs.com/VCXOPartNumber to access this tool and for further ordering instructions. The Si570/Si571 XO/
VCXO series is supplied in an industry-standard, RoHS compliant, 8-pad, 5 x 7 mm package. Tape and reel
packaging is an ordering option.
Figure 6. Part Number Convention
570 Programmable
XO Product Family
57x X
1st Option Code
VDD Output Format Output Enable Polarity
A 3.3 LVPECL High
B 3.3 LVDS High
C 3.3 CMOS High
D3.3CML High
E 2.5 LVPECL High
F 2.5 LVDS High
G 2.5 CMOS High
H2.5CML High
J 1.8 CMOS High
K1.8CML High
M 3.3 LVPECL Low
N 3.3 LVDS Low
P 3.3 CMOS Low
Q 3.3 CML Low
R 2.5 LVPECL Low
S 2.5 LVDS Low
T 2.5 CMOS Low
U 2.5 CML Low
V 1.8 CMOS Low
W 1.8 CML Low
Note:
CMOS available to 160 MHz.
571 Programmable
VCXO Product Family
R = Tape & Reel
Blank = Trays
Operating Temp Range (°C)
G –40 to +85 °C
Device Revision Letter
X D G R
Six-Digit Start-up Frequency/I2C Address Designator
The Si57x supports a user-defined start-up frequency within the following
bands of frequencies: 10–945 MHz, 970–1134 MHz, and 1213–1417 MHz.
The start-up frequency must be in the same frequency range as that
specified by the Frequency Grade 3rd option code.
The Si57x supports a user-defined I2C 7-bit address. Each unique start-up
frequency/I2C address combination is assigned a six-digit numerical code.
This code can be requested during the part number request process. Refer
to www.silabs.com/VCXOPartNumber to request an Si57x part number.
XXXX XXX
3rd Option Code
Frequency Grade
Code Frequency Range Supported (MHz)
A 10-945, 970-1134, 1213-1417.5
B 10-810
C 10-280 (CMOS available to 160 MHz)
2nd Option Code
Temperature Tuning Slope Minimum APR
Stability Kv (±ppm) for VDD @
Code ± ppm (max) ppm/V (typ) 3.3 V 2.5 V 1.8 V
A 100 180 100 75 25
B 100 90 30 Note 6 Note 6
C 50 180 150 125 75
D50 90 803025
E 20 45 25 Note 6 Note 6
F 50 135 100 75 50
G 20 356 375 300 235
H 20 180 185 145 105
J 20 135 130 104 70
K 100 356 295 220 155
M 20 33 12 Note 6 Note 6
Notes:
1. For best jitter and phase noise performance, always choose the smallest Kv that meets
the application’s minimum APR requirements. Unlike SAW-based solutions which
require higher higher Kv values to account for their higher temperature dependence,
the Si55x series provides lower Kv options to minimize noise coupling and jitter in real-
world PLL designs. See AN255 and AN266 for more information.
2. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an
APR of ±25 ppm is able to lock to a clock with a ±25 ppm stability over 15 years over all
operating conditions.
3. Nominal Pull range (±) = 0.5 x VDD x tuning slope.
4. Nominal Absolute Pull Range (±APR) = Pull range – stability – lifetime aging
= 0.5 x VDD x tuning slope – stability – 10 ppm
5. Minimum APR values noted above include worst case values for all parameters.
6. Combination not available.
Si570
Si571
2nd Option Code
Code Temperature Stability (ppm, max, ±) Total Stablility (ppm, max, ±)
A 50 61.5
B 20 31.5
Si570/Si571
Rev. 1.1 25
8. Si57x Mark Specification
Figure 7 illustrates the mark specification for the Si57x. Table 15 lists the line information.
Figure 7. Mark Specification
Table 15. Si57x Top Mark Description
Line Position Description
1 1–10 “SiLabs”+ Part Family Number, 5xx (First 3 characters in part number)
2 1–10 Si570, Si571: Option1 + Option2 + Option3 + ConfigNum(6) + Temp
3 Trace Code
Position 1 Pin 1 orientation mark (dot)
Position 2 Product Revision (D)
Position 3–6 Tiny Trace Code (4 alphanumeric characters per assembly release instructions)
Position 7 Year (least significant year digit), to be assigned by assembly site (ex: 2007 = 7)
Position 8–9 Calendar Work Week number (1–53), to be assigned by assembly site
Position 10 “+” to indicate Pb-Free and RoHS-compliant
SiLabs 123
123
4
5
6
R T T T T Y W W +
1 2 3 4 5 6 7 8 9 0
Si570/Si571
26 Rev. 1.1
9. Outline Diagram and Suggested Pad Layout
Figure 8 illustrates the package details for the Si570/Si571. Table 16 lists the values for the dimensions shown in
the illustration.
Figure 8. Si570/Si571 Outline Diagram
Table 16. Package Diagram Dimensions (mm)
Dimension Min Nom Max
A 1.45 1.65 1.85
b1.21.41.6
c0.60 TYP
d 0.97 1.17 1.37
D 7.00 BSC
D1 6.10 6.2 6.30
e 2.54 BSC
E 5.00 BSC
E1 4.30 4.40 4.50
L 1.07 1.27 1.47
M0.81.01.2
S 1.815 BSC
R 0.7 REF
aaa — — 0.15
bbb — — 0.15
ccc — — 0.10
ddd — — 0.10
Si570/Si571
Rev. 1.1 27
10. 8-Pin PCB Land Pattern
Figure 9 illustrates the 8-pin PCB land pattern for the Si570/Si571. Table 17 lists the values for the dimensions
shown in the illustration.
Figure 9. Si570/Si571 PCB Land Pattern
Table 17. PCB Land Pattern Dimensions (mm)
Dimension Min Max
D2 5.08 REF
D3 5.705 REF
e 2.54 BSC
E2 4.20 REF
GD 0.84 —
GE 2.00 —
VD 8.20 REF
VE 7.30 REF
X1 1.70 TYP
X2 1.545 TYP
Y1 2.15 REF
Y2 1.3 REF
ZD — 6.78
ZE — 6.30
Note:
1. Dimensioning and tolerancing per the ANSI Y14.5M-1994
specification.
2. Land pattern design follows IPC-7351 guidelines.
3. All dimensions shown are at maximum material condition
(MMC).
4. Controlling dimension is in millimeters (mm).
Si570/Si571
28 Rev. 1.1
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Updated " Description" on page 1.
Updated "1. Detailed Block Diagrams" on page 4 for
both XO and VCXO.
Updated the Nominal Control Voltage in Table 2, “VC
Control Voltage Input,” on page 5.
Updated tables to reflect slight performance
differences between Si570 and Si571.
Added detail to the "3.2. I2C Interface" on page 16.
Revised "3.2.3. Programming Procedure" on page
12.
Procedure now requires use of two frequency
configuration register sets.
Procedure now recommends disabling output at
powerup to protect equipment not expecting the
default output frequency.
Added second frequency configuration register set
to the register tables.
Added frequency configuration select register.
Updated "7. Ordering Information" on page 24 to be
consistent with the Si55x series devices.
Revision 0.2 to Revision 0.3
Updated Table 1, “Recommended Operating
Conditions,” on page 5.
Device maintains stable operation over –40 to +85 ºC
operating temperature range.
Supply current specifications updated.
Updated Table 4, “CLK± Output Levels and
Symmetry,” on page 7.
Updated LVDS differential peak-peak swing
specifications.
Updated Table 5, “CLK± Output Phase Jitter
(Si570),” on page 7.
Updated Table 6, “CLK± Output Phase Jitter
(Si571),” on page 8.
Updated Table 7, “CLK± Output Period Jitter,” on
page 10.
Revised period jitter specifications.
Updated Table 10, “Absolute Maximum Ratings,” on
page 11 to reflect the soldering temperature time at
260 ºC is 20–40 sec per JEDEC J-STD-020C.
Updated device programming procedure in Section
"3.2.3. Programming Procedure" on page 12.
Updated "7. Ordering Information" on page 24.
Changed ordering instructions to revision D.
Added "8. Si57x Mark Specification" on page 25.
Revision 0.3 to Revision 0.31
Updated "3.2.3. Programming Procedure" on page
12.
Corrected Step 6 to read “bit 4”.
Corrected Freeze DCO bit location in Register 137 to
bit 4 on pages 14 and 18.
Revision 0.31 to Revision 1.0
Updated " Functional Block Diagram" on page 1.
Updated Figure 1, “Si570 Detailed Block Diagram,”
on page 4.
Updated Figure 2, “Si571 Detailed Block Diagram,”
on page 4.
Updated Figure 6, “Part Number Convention,” on
page 24.
Updated Table 1, “Recommended Operating
Conditions,” on page 5.
Updated Table 3, “CLK± Output Frequency
Characteristics,” on page 6.
Updated Table 6, “CLK± Output Phase Jitter
(Si571),” on page 8.
Updated Table 12, “Programming Constraints and
Timing,” on page 12.
Updated Table 12, “Programming Constraints and
Timing,” on page 12.
Updated "3. Functional Description" on page 13.
Updated "3.1. Programming a New Output
Frequency" on page 13.
Updated "3.1.1. Reconfiguring the Output Clock for a
Small Change in Frequency" on page 13.
Updated "3.1.2. Reconfiguring the Output Clock for
Large Changes in Output Frequency" on page 14.
Updated “7.Ordering Information”.
Updated Figure 6, “Part Number Convention,” on page
24.
Revision 1.0 to Revision 1.1
Restored programming constraint information on
page 15 and in Table 12, page 12.
Clarified NC (No Connect) pin designations in Tables
13–14 on pages 22–23.
Si570/Si571
Rev. 1.1 29
NOTES:
Si570/Si571
30 Rev. 1.1
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: VCXOinfo@silabs.com
Internet: www.silabs.com
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the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
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