ECP5™ Evaluation Board
User Guide
FPGA-EB-02017-1.0
July 2018
ECP5™ Evaluation Board
User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2 FPGA-EB-02017-1.0
Contents
Acronyms in This Document ................................................................................................................................................. 5
1. Introduction .................................................................................................................................................................. 6
1.1. ECP5 Evaluation Board ........................................................................................................................................ 6
1.2. Features ............................................................................................................................................................... 8
1.3. ECP5 Device ......................................................................................................................................................... 8
2. Applying Power to the Board ........................................................................................................................................ 9
3. Programming and I2C .................................................................................................................................................. 10
3.1. JTAG Download Interface .................................................................................................................................. 10
3.2. Alternate JTAG Download Interface .................................................................................................................. 10
3.3. JTAG to MSPI Pass-through Interface ................................................................................................................ 11
3.4. Other JTAG Configuration Pins .......................................................................................................................... 11
3.5. Configuration Modes ......................................................................................................................................... 11
4. ECP5 Clock Sources ..................................................................................................................................................... 12
5. Headers and Test Connections ................................................................................................................................... 13
5.1. Versa Headers ................................................................................................................................................... 13
5.2. Arduino Board GPIO Headers ............................................................................................................................ 15
5.3. Raspberry Pi Board GPIO Header ...................................................................................................................... 17
5.4. GPIO Headers .................................................................................................................................................... 18
5.5. Microphone Expansion Header ......................................................................................................................... 21
5.6. PMOD Header ................................................................................................................................................... 21
5.7. JTAG Header ...................................................................................................................................................... 22
5.8. Parallel Configuration Header ........................................................................................................................... 22
6. Control Buses - I2C, I3C, UART, and SPI ........................................................................................................................ 23
6.1. I2C and I3C Topology .......................................................................................................................................... 23
6.2. UART Topology .................................................................................................................................................. 24
6.3. SPI Topology ...................................................................................................................................................... 24
6.3.1. SPI Configuration .......................................................................................................................................... 24
6.3.2. SPI Flash Access ............................................................................................................................................. 25
7. LEDs and Switches ...................................................................................................................................................... 26
7.1. DIP Switch .......................................................................................................................................................... 26
7.2. Configuration Mode Switch............................................................................................................................... 26
7.3. General Purpose Push Buttons.......................................................................................................................... 26
7.4. General Purpose LEDs ....................................................................................................................................... 27
7.5. Indicator LEDs .................................................................................................................................................... 27
8. Software Requirements .............................................................................................................................................. 28
9. Storage and Handling.................................................................................................................................................. 28
10. Ordering Information .............................................................................................................................................. 28
References .......................................................................................................................................................................... 29
Lattice Semiconductor Documents ................................................................................................................................. 29
Technical Support Assistance............................................................................................................................................... 30
Appendix A. ECP5 Evaluation Board Schematics ................................................................................................................ 31
Appendix B. ECP5 Evaluation Board Bill of Materials ......................................................................................................... 43
Revision History ................................................................................................................................................................... 49
ECP5™ Evaluation Board
User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02017-1.0 3
Figures
Figure 1.1. Top View of ECP5 Evaluation Board.................................................................................................................... 6
Figure 1.2. Bottom View of ECP5 Evaluation Board ............................................................................................................. 7
Figure 1.3. Top View of ECP5 Evaluation Board – Jumper Locations .................................................................................... 7
Figure 2.1. Board Power Supply............................................................................................................................................ 9
Figure 3.1. Configuration and I2C Architecture ................................................................................................................... 10
Figure 6.1. I2C Architecture, I3C, and UART Options ........................................................................................................... 24
Figure 6.2. SPI Interface ...................................................................................................................................................... 25
Figure A. 1. Title Page ......................................................................................................................................................... 31
Figure A. 2. Block Diagram .................................................................................................................................................. 32
Figure A. 3. USB Interface ................................................................................................................................................... 33
Figure A. 4 Arduino Header (BANK2) .................................................................................................................................. 34
Figure A. 5. Raspberry Pi Header (BANK3) .......................................................................................................................... 35
Figure A. 6. SERDES SMA .................................................................................................................................................... 36
Figure A. 7. IO Breakout (BANK0, BANK1, BANK6) ............................................................................................................. 37
Figure A. 8. IO Breakout (BANK7, Differential Pairs) .......................................................................................................... 38
Figure A. 9. Configuration ................................................................................................................................................... 39
Figure A. 10. Power Decoupling and LEDs .......................................................................................................................... 40
Figure A. 11.Power Hookup ................................................................................................................................................ 41
Figure A. 12. Power Regulators .......................................................................................................................................... 42
Tables
Table 2.1. ECP5 VCCIO Supply Options ................................................................................................................................. 9
Table 3.1. JTAG Connections .............................................................................................................................................. 10
Table 3.2. Other JTAG Signals ............................................................................................................................................. 11
Table 3.3. CFGMDN Mode Settings .................................................................................................................................... 11
Table 4.1. Clock Sources ..................................................................................................................................................... 12
Table 5.1. Versa J39 Header Pin Connections..................................................................................................................... 13
Table 5.2. Versa J40 Header Pin Connections..................................................................................................................... 14
Table 5.3. Arduino J6 Pin Connections ............................................................................................................................... 15
Table 5.4. Arduino J3 Pin Connections ............................................................................................................................... 15
Table 5.5. Arduino J7 Pin Connections ............................................................................................................................... 16
Table 5.6. Arduino J4 Pin Connections ............................................................................................................................... 16
Table 5.7. Raspberry Pi JP8 Header Pin Connections ......................................................................................................... 17
Table 5.8. J5 Header Pin Connections................................................................................................................................. 18
Table 5.9. J8 Header Pin Connections................................................................................................................................. 19
Table 5.10. J32 Header Pin Connections ............................................................................................................................ 19
Table 5.11. J33 Header Pin Connections ............................................................................................................................ 20
Table 5.12. J30 Header Pin Connections ............................................................................................................................ 21
Table 5.13. J31 Header Pin Connections ............................................................................................................................ 21
Table 5.14. J1 Header Pin Connections............................................................................................................................... 22
Table 5.15. J38 Header Pin Connections ............................................................................................................................ 22
Table 6.1. I2C Global Bus Connections ................................................................................................................................ 23
Table 6.2. ECP5 SPI Connections ......................................................................................................................................... 25
Table 7.1. Eight-Position DIP Switch Signals ....................................................................................................................... 26
Table 7.2. CFGMDN Switch Signals ..................................................................................................................................... 26
Table 7.3. Push Button Switch Signals ................................................................................................................................ 26
Table 7.4. General Purpose LED Signals .............................................................................................................................. 27
ECP5™ Evaluation Board
User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
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4 FPGA-EB-02017-1.0
Table 7.5. Various LED Signals ............................................................................................................................................ 27
Table 10.1. Ordering Information ....................................................................................................................................... 28
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© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
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FPGA-EB-02017-1.0 5
Acronyms in This Document
A list of acronyms used in this document.
Acronym
Definition
ASC
Analog Sense and Control
caBGA
Chip Array Ball Grid Array
CMOS
Complementary Metal-Oxide Semiconductor
DIP
Dual Inline Package
DNI
Do Not Install
ESD
Electro Static Discharge
FPGA
Field Programmable Logic Array
FTDI
Future Technology Devices International
GDDR
Graphics Double Data Rate
GPIO
General Purpose Input/Output
I2C
Inter-Integrated Circuit
I3C
Improved Inter-Integrated Circuit
JTAG
Joint Test Action Group
LVDS
Low-Voltage Differential Signaling
MDP
Mobile Development Platform
PMOD
Peripheral Module
SCM
Serial Configuration Mode
SPCM
Slave Parallel Configuration Mode
SPI
Serial Peripheral Interface
UART
Universal Asynchronous Receiver Transmitter
USB
Universal Serial Bus
ECP5™ Evaluation Board
User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6 FPGA-EB-02017-1.0
1. Introduction
The Lattice Semiconductor ECP5™ Evaluation Board allows designers to investigate and experiment with the features of
the ECP5-5G Field Programmable Gate Array (FPGA). The features of the ECP5 Evaluation Board can assist engineers
with the rapid prototyping and testing of their specific designs.
The ECP5 Evaluation Board is part of the ECP5 Evaluation Kit, which includes the following:
ECP5 Evaluation Board pre-loaded with the demo design
Mini USB cable
Quick Start Guide
The contents of this user guide include top-level functional descriptions of the various portions of the development
board, descriptions of the on-board headers, diodes and switches and a complete set of schematics.
1.1. ECP5 Evaluation Board
The ECP5 Evaluation Board features the ECP5-5G FPGA in the 381-ball caBGA package (LFE5UM5G-85F-8BG381) and
the ability to expand the usability of the ECP5 with Arduino, Raspberry Pi, PMOD, MCD, and Versa headers, along with
access to all SERDES channels. Over 170 I/Os and 20 differential pairs are available for user-defined applications.
Figure 1.1 shows the top view of the ECP5 Evaluation Board. Figure 1.2 shows the bottom view of the board. Figure 1.3
shows the jumper locations.
12 V DC Power
Input (J37)
SPI Flash
Configuration
Memory (U4)
Versa Expansion
Connectors (J39, J40)
SERDES Test SMA
Connectors (J9-J26)
mini USB
Programming (J2)
JTAG Interface (J1)
ECP5-5G Device
(U3)
GPIO Headers
(J5, J8)
Prototype Area Microphone Board/
GPIO Header (J30)
PMOD/GPIO
Header (J31)
GPIO Headers
(J32, J33)
Input Switches
(SW5)
Output LEDs
(D5-D12)
Input Push Buttons
(SW2, SW3, SW4)
Parallel Config
Header (J38)
CFG Switches (SW1)
Figure 1.1. Top View of ECP5 Evaluation Board
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FPGA-EB-02017-1.0 7
Raspberry
Pi Header
(JP8)
FTDI Interface
Chip (U1)
Arduino Header
(J3, J4, J6, J7)
Figure 1.2. Bottom View of ECP5 Evaluation Board
FTDI Reset
(JP1)
FTDI Osc
Connect (JP2)
SERDES Osc
Reset (JP9)
Arduino Supplies
(JP3, JP4, JP5)
Raspberry Pi
Supplies (JP6, JP7)
VCCIO0 Supply
Selection
(JP10)
VCCIO7 Supply
Selection
(JP11)
Flash Chip
Selection (JP18)
Figure 1.3. Top View of ECP5 Evaluation Board – Jumper Locations
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8 FPGA-EB-02017-1.0
1.2. Features
ECP5-5G FPGA (LFE5UM5G-85F-8BG381)
General Purpose Input/Output (GPIO) breakout with Arduino, Raspberry Pi, Versa, PMOD, and MDC board
interconnect
178 General purpose I/Os, 20 differential pair I/Os with on board termination, 4 5G SERDES channels
USB-B connection for device programming and Inter-Integrated Circuit (I2C) utility and ability to support Improved
Inter-Integrated Circuit (I3C)
On-board Boot Flash – 128 Mbit Serial Peripheral Interface (SPI) Flash, with Quad read feature
8 input DIP switches, 3 push buttons and 8 LEDs for demo purposes
Lattice Diamond® programming support
Multiple reference clock sources
Caution:
The ECP5 Evaluation Board contains ESD-sensitive components. ESD safe practices
should be followed while handling and using the development board.
1.3. ECP5 Device
The ECP5 Evaluation Board features the ECP5-5G in a 381-ball caBGA package. This ECP5-5G device, also referred to as
LFE5UM5G-85F-8BG381, features 84,000 LUTs and 3744 kbits of embedded block RAM. This device offers a variety of
features and programmability. For more information on the capabilities of ECP5™, see ECP5 and ECP5-5G Family Data
Sheet (FPGA-DS-02012).
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© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02017-1.0 9
2. Applying Power to the Board
The ECP5 Evaluation Board has most of its power supplied by onboard regulators powered by an external 12 V power.
In addition, the USB connection supplies 5 V to some components, and off board supplies can be used to supply the
Raspberry Pi and Arduino headers. Jumpers or resistor installation/removal can be used to achieve several different
power supply configurations. Refer to Appendix A. ECP5 Evaluation Board Schematics to see the details of these power
supply options. Figure 2.1 shows the high-level power supply architecture of the board. Table 2.1 shows the voltage
options available for the various VCCIO supplies.
Figure 2.1. Board Power Supply
Table 2.1. ECP5 VCCIO Supply Options
VCCIO Bank
Selection
+3.3V
+2.5V
+3.3V_AR
+3.3V_RASP
+1.5V
VCC_CORE(+1.2V)
VCCIO0
Jumper
(JP 10)
Default
Selectable
N/A
N/A
Selectable
Selectable
VCCIO1
Resistors
Selectable
Default
N/A
N/A
N/A
N/A
VCCIO2
Resistors
Default
Selectable
Selectable
N/A
N/A
N/A
VCCIO3
Resistors
Default
Selectable
N/A
Selectable
N/A
N/A
VCCIO6
Resistors
Default
Selectable
N/A
N/A
N/A
N/A
VCCIO7
Jumper
(JP 11)
Default
Selectable
N/A
N/A
Selectable
Selectable
VCCIO8
Resistors
Default
Selectable
N/A
N/A
N/A
N/A
Warning: Only one option should be enabled for each ECP5 device I/O Bank. The implementation of these options can be found in
Figure A. 11.
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10 FPGA-EB-02017-1.0
3. Programming and I2C
The JTAG/SPI programming architecture and I2C interface of the ECP5 Evaluation Board is shown in Figure 3.1.
Figure 3.1. Configuration and I2C Architecture
3.1. JTAG Download Interface
The ECP5 Evaluation Board has a built-in download controller for programming the ECP5-5G device. It uses an FT2232H
Future Technology Devices International (FTDI) part to convert USB to JTAG. To use the built-in download cable,
connect the USB cable from the mini USB to your PC, that is, with Diamond programming software installed. A mini USB
to USB-A cable is included in the ECP5 Evaluation Kit. The USB hub on the PC detects the cable of the USB function on
Port 0, making the built-in cable available for use with the Diamond programming software.
3.2. Alternate JTAG Download Interface
J1 is an 8-pin standalone JTAG header used with an external Lattice download cable that is available separately, when
the FTDI part is disabled from the JTAG chain after setting the JP1 jumper. A USB download cable can be attached to
the board using J1 to interface with the ECP5-5G. For details on the connection between the USB download cable and
J1, refer to Programming Cable User’s Guide (FPGA-UG-02042).
J1 can also be used as test point when USB to JTAG is working. Additionally, you can enable the JTAG access path
through the Raspberry Pi header (JP8) for customer applications. This is done by connecting the JP8 header to the J1
header through some onboard resistors. The JTAG connections between J1 and JP8 are listed in Table 3.1.
Table 3.1. JTAG Connections
J1 Pin
Number
JTAG Signal
Name
ECP5-5G Ball Location
for JTAG
Raspberry Pi Header
(JP8) Pin Number
J1 to JP8 Isolation
(Assembly)
Raspberry Pi GPIO
1
VCCIO8
—
—
—
—
2
TDO
V4
10
R39 (DNI)
IO15
3
TDI
R5
11
R40 (DNI)
IO17
4
—
—
—
—
—
5
—
—
—
—
—
6
TMS
U5
12
R41 (DNI)
IO18
7
GND
—
—
—
—
8
TCK
T5
8
R38 (DNI)
IO14
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FPGA-EB-02017-1.0 11
3.3. JTAG to MSPI Pass-through Interface
The download controller can also access the JTAG to MSPI pass-through circuit that allows the slave SPI Flash to be
erased, programmed, and read with Diamond Programmer.
3.4. Other JTAG Configuration Pins
The ECP5 Evaluation Board provides test points for other JTAG configuration pins as shown in Table 3.2.
Table 3.2. Other JTAG Signals
Signal Name
ECP5-5G Ball Location
Test Point
PROGRAMN
W3
TP21
INITN
V3
TP20
DONE
Y3
TP22
For more information on ECP5 JTAG and SPI programming, refer to ECP5 and ECP5-5G sysCONFIG Usage Guide (FPGA-
TN-02039).
3.5. Configuration Modes
The ECP5 can be configured in Master SPI, Slave SPI, SCM, JTAG, and SPCM modes. These modes can be selected using
the CFGMDN switches provided on the board (detailed in the DIP Switch section and ECP5 and ECP5-5G sysCONFIG
Usage Guide (FPGA-TN-02039). Table 3.3 below details the CFGMDN settings that are used to select individual
configuration modes.
Table 3.3. CFGMDN Mode Settings
Configuration Mode
Bus Size
Options
Clock
CFGMDN2
CFGMDN1
CFGMDN0
SSPI
1
—
CCLK
0
0
1
MSPI
1
Serial (SPI_Serial
MCLK
0
1
0
2
Dual (SPI_Dual)
4
Quad (SPI_Quad)
1, 2, 4
Dual-Boot
1, 2, 4
Multi-Boot
SCM (Slave_Serial)
1
—
CCLK
1
0
1
SPCM (Slave_Parallel)
8
—
CCLK
1
1
1
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12 FPGA-EB-02017-1.0
4. ECP5 Clock Sources
The ECP5 Evaluation Board has three options for the ECP5-5G clock sources:
12 MHz from U1 FTDI Chip
200 MHz SERDES clock from X2 Differential Oscillator. For different user applications, the X2 footprint accepts
commonly-available devices of different frequencies.
X5 oscillator for LVDS source sync clock. X5 is not populated by default. For convenience, a 50 MHz device is
specified in the ECP5 Evaluation Board Bill of Materials section, Item 127. Other frequency devices may be
mounted as desired.
The 12 MHz clock from the FT2232H FTDI device requires JP2 to be installed to connect the 12 MHz clock signal to the
ECP5 device I/O. JP1 should not be installed to enable U1.
Table 4.1. Clock Sources
Clock Frequency
Signal Name
ECP5 Ball Location
Clock Source
Comments
12 MHz
12 MHz
A10
U1
JP2 installed. JP1 removed.
200 MHz
200 MHz/200 MHz_n
Y19/ W20
X2
JP9 added to disable.
50 MHz
50 MHz_OSC
B11
X5 (DNI)
50 MHz_OSC_EN (C11) to enable/disable.
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FPGA-EB-02017-1.0 13
5. Headers and Test Connections
This section describes the ECP5 Evaluation Board headers and test connections.
5.1. Versa Headers
The board provides two headers – J39 and J40 which can be used for expansion or as general purpose I/O connections.
Table 5.1. Versa J39 Header Pin Connections
J39 Pin Number
Signal Name
ECP5-5G-85 Ball
1
GND
—
2
NC
—
3
EXPCON_2V5*
—
4
D15
D15
5
B15
B15
6
C15
C15
7
B13
B13
8
B20
B20
9
D11
D11
10
E11
E11
11
B12
B12
12
C12
C12
13
D12
D12
14
E12
E12
15
C13
C13
16
D13
D13
17
E13
E13
18
A14
A14
19
A9
A9
20
B10
B10
21
5VIN
—
22
GND
—
23
EXPCON_2V5*
—
24
GND
—
25
+3.3V
—
26
GND
—
27
+3.3V
—
28
GND
—
29
E7
—
30
GND
—
31
A11
A11
32
GND
—
33
A19
A19
34
GND
—
35
EXPCON_3V3*
—
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14 FPGA-EB-02017-1.0
J39 Pin Number
Signal Name
ECP5-5G-85 Ball
36
GND
—
37
EXPCON_3V3*
—
38
GND
—
39
EXPCON_3V3*
—
40
GND
—
*Note: Signal is connected to power source through removable resistor.
Table 5.2. Versa J40 Header Pin Connections
J40 Pin Number
Signal Name
ECP5-5G-85 Ball
1
K2
K2
2
GND
—
3
A15
A15
4
F1
F1
5
H2
H2
6
G1
G1
7
J4
J4
8
J5
J5
9
J3
J3
10
K3
K3
11
L4
L4
12
L5
L5
13
M4
M4
14
N5
N5
15
N4
N4
16
P5
P5
17
N3
N3
18
M3
M3
19
GND
—
20
EXPCON_3V3*
—
21
K5
K5
22
GND
—
23
M5
M5
24
GND
—
25
L3
L3
26
GND
—
27
N2
N2
28
M1
M1
29
L2
L2
30
GND
—
31
L1
L1
32
N1
N1
33
C14
C14
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FPGA-EB-02017-1.0 15
J40 Pin Number
Signal Name
ECP5-5G-85 Ball
34
GND
—
35
P1
P1
36
E14
E14
37
D14
D14
38
CARDSEL#*
—
39
K4
K4
40
GND
—
*Note: Signal is connected to power source through removable resistor.
5.2. Arduino Board GPIO Headers
The board provides four headers – J3, J4, J6 and J7 for Arduino Zero board adaption or as general purpose I/O
connections.
Table 5.3. Arduino J6 Pin Connections
J6 Pin
Number
Signal Name
Arduino ZERO Board Signal
ECP5-5G-85 Ball
Comments
1
AR_IO8
~8
K16
—
2
AR_IO9
~9
J16
—
3
AR_SS_IO10
~10
H17
—
4
AR_MOSI_IO11
~11
J17
—
5
AR_MISO_IO12
~12
H18
—
6
AR_SCK_IO13
~13
H16
—
7
GND
GND
—
—
8
AR_AREF
AREF
G18
AR_AREF connection to AREF
through R27, DNI by default.
9
AR_SDA
SDA
G16
Optional connection to SDA0
through R26, DNI by default.
10
AR_SCL
SCL
F17
Optional connection to SCL0
through R25, DNI by default.
Table 5.4. Arduino J3 Pin Connections
J3 Pin
Number
Signal Name
Arduino ZERO Board Signal
ECP5-5G-85 Ball
Comments
1
AR_IO0
RX <- 0
F19
—
2
AR_IO1
TX -> 1
F20
—
3
AR_IO2
2
E20
—
4
AR_IO3
~3
E19
—
5
AR_IO4
~4
D19
—
6
AR_IO5
~5
D20
—
7
AR_IO6
~6
C20
—
8
AR_IO7
7
K17
—
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16 FPGA-EB-02017-1.0
Table 5.5. Arduino J7 Pin Connections
J7 Pin
Number
Signal Name
Arduino ZERO Board
Signal
ECP5-5G-85 Ball
Comments
1
AR_IO14
ATN
C18
—
2
NC
IOREF
—
—
3
AR_RESET
RESET
D17
Pin D17 should be set high by default. Avoid
Arduino ZERO board in Reset status when
connected.
4
+3.3V_AR
3.3 V
—
Jumper to 3.3 V power supply from Arduino
ZERO board
5
VBUS_5V
5 V
—
Jumper to 5 V USB power
6
GND
GND
—
—
7
GND
GND
—
—
8
+12.0V
VIN
—
Jumper to +12.0V power supply from Arduino
ZERO board
Table 5.6. Arduino J4 Pin Connections
J4 Pin
Number
Signal Name
Arduino ZERO
Board Signal
ECP5-5G-85 Ball
Comments
1
AR_AD0
A0
F18
Used as GPIO in digital mode
2
AR_AD1
A1
E17
Used as GPIO in digital mode
3
AR_AD2
A2
E18
Used as GPIO in digital mode
4
AR_AD3
A3
D18
Used as GPIO in digital mode
5
AR_AD4
A4
F16
Used as GPIO in digital mode
6
AR_AD5
A5
E16
Used as GPIO in digital mode
Note: For Table 5.3, Table 5.4, Table 5.5, and Table 5.6, if jumper to VBUS_5V is installed, 5 V power can be supplied
from either the Arduino board or the ECP5 Evaluation Board. With jumper removed, both boards need their own 5 V
power.
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FPGA-EB-02017-1.0 17
5.3. Raspberry Pi Board GPIO Header
The ECP5 Evaluation Board provides a 40-pin receptacle which is compatible with the GPIO header of Raspberry Pi 2/3
serial models, or can be used for general purpose I/Os.
Table 5.7. Raspberry Pi JP8 Header Pin Connections
JP8 Pin Number
Signal Name
ECP5-5G-85 Ball
1
+3.3V_RASP 1
—
2
RASP_5V 2
—
3
RASP_IO02
T17
4
RASP_5V 2
—
5
RASP_IO03
U16
6
GND
—
7
RASP_IO04
U17
8
RASP_IO14
P18
9
GND
—
10
RASP_IO15
N20
11
RASP_IO17
N19
12
RASP_IO18
T16
13
RASP_IO27
M18
14
GND
—
15
RASP_IO22
N17
16
RASP_IO23
P17
17
3.3V_RASP 1
—
18
RASP_IO24
M17
19
RASP_IO10
U20
20
GND
—
21
RASP_IO09
T19
22
RASP_IO25
N18
23
RASP_IO11
R20
24
RASP_IO08
U19
25
GND
—
26
RASP_IO07
R18
27
RASP_ID_SD
L18
28
RASP_ID_SC
L17
29
RASP_IO05
U18
30
GND
—
31
RASP_IO06
T18
32
RASP_IO12
T20
33
RASP_IO13
P20
34
GND
—
35
RASP_IO19
R17
36
RASP_IO16
P19
37
RASP_IO26
N16
38
RASP_IO20
P16
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18 FPGA-EB-02017-1.0
JP8 Pin Number
Signal Name
ECP5-5G-85 Ball
39
GND
—
40
RASP_IO21
R16
Notes:
1. 3.3 V power is supplied from Raspberry Pi board.
2. 5 V power can come from either the Raspberry Pi board or the ECP Evaluation Board (via USB) when jumper JP7 is installed.
When jumper JP7 is not installed, both boards need their own 5 V power.
5.4. GPIO Headers
There are two types of general purpose I/O headers: simple general purpose headers, and differential general purpose
headers. The differential headers have associated termination resistors for each differential I/O pair.
Table 5.8. J5 Header Pin Connections
J5 Pin Number
Signal Name
ECP5-5G-85 Ball
Differential Pair
1
VCCIO2
—
—
2
VCCIO2
—
—
3
H20
H20
H20/G19
4
G19
G19
H20/G19
5
GND
—
—
6
GND
—
—
7
K18
K18
K18/J18
8
J18
J18
K18/J18
9
GND
—
—
10
GND
—
—
11
K19
K19
K19/J19
12
J19
J19
K19/J19
13
GND
—
—
14
GND
—
—
15
K20
K20
K20/J20
16
J20
J20
K20/J20
17
GND
—
—
18
GND
—
—
19
G20
G20
—
20
GND
—
—
21
GND
—
—
22
GND
—
—
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FPGA-EB-02017-1.0 19
Table 5.9. J8 Header Pin Connections
J8 Pin Number
Signal Name
ECP5-5G-85 Ball
1
VCCIO3
—
2
VCCIO3
—
3
L19
L19
4
M19
M19
5
L20
L20
6
M20
M20
7
L16
L16
8
GND
—
Table 5.10. J32 Header Pin Connections
J32 Pin Number
Signal Name
ECP5-5G-85 Ball
Differential Pair
1
NC
—
—
2
VCCIO7
—
—
3
GND
—
—
4
GND
—
—
5
A5
A5
A5/A4
6
A4
A4
A5/A4
7
GND
—
—
8
GND
—
—
9
C5
C5
C5/B5
10
B5
B5
C5/B5
11
GND
—
—
12
GND
—
—
13
B4
B4
B4/C4
14
C4
C4
B4/C4
15
GND
—
—
16
GND
—
—
17
B3
B3
B3/A3
18
A3
A3
B3/A3
19
GND
—
—
20
GND
—
—
21
D5
D5
D5/E4
22
E4
E4
D5/E4
23
GND
—
—
24
GND
—
—
25
D3
D3
D3/C3
26
C3
C3
D3/C3
27
GND
—
—
28
GND
—
—
29
E3
E3
E3/F4
30
F4
F4
E3/F4
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20 FPGA-EB-02017-1.0
J32 Pin Number
Signal Name
ECP5-5G-85 Ball
Differential Pair
31
GND
—
—
32
GND
—
—
33
F5
F5
F5/E5
34
E5
E5
F5/E5
35
GND
—
—
36
GND
—
—
37
B1
B1
B1/A2
38
A2
A2
B1/A2
39
GND
—
—
40
GND
—
—
Table 5.11. J33 Header Pin Connections
J33 Pin Number
Signal Name
ECP5-5G-85 Ball
Differential Pair
1
NC
—
—
2
VCCIO7
—
—
3
GND
—
—
4
GND
—
—
5
C2
C2
C2/B2
6
B2
B2
C2/B2
7
GND
—
—
8
GND
—
—
9
D1
D1
D1/C1
10
C1
C1
D1/C1
11
GND
—
—
12
GND
—
—
13
E1
E1
E1/D2
14
D2
D2
E1/D2
15
GND
—
—
16
GND
—
—
17
G5
G5
G5/H4
18
H4
H4
G5/H4
19
GND
—
—
20
GND
—
—
21
H3
H3
H3/H5
22
H5
H5
H3/H5
23
GND
—
—
24
GND
—
—
25
F3
F3
F3/G3
26
G3
G3
F3/G3
27
GND
—
—
28
GND
—
—
29
E2
E2
E2/F2
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FPGA-EB-02017-1.0 21
J33 Pin Number
Signal Name
ECP5-5G-85 Ball
Differential Pair
30
F2
F2
E2/F2
31
GND
—
—
32
GND
—
—
5.5. Microphone Expansion Header
The J30 header can be used as GPIO, or can mate to the 8:1 Microphone Aggregator Board. It is placed with a non-
connected header in close proximity to allow the physical pairing of the boards.
Table 5.12. J30 Header Pin Connections
J30 Pin Number
Signal Name
ECP5-5G-85 Ball
1
VCCIO0
—
2
I2S_SD_mic1_mic2_card_B6
B6
3
I2S_SCK_mic_D9
D9
4
I2S_SD_mic3_mic4_C9
C9
5
I2S_WS_mic_E9
E9
6
I2S_SD_mic5_mic6_D10
D10
7
GPIO_amp_A6
A6
8
I2S_SD_mic7_E10
E10
9
GND
—
10
GND
—
5.6. PMOD Header
The J31 header can be used as GPIO or as a connector to a PMOD interface.
Table 5.13. J31 Header Pin Connections
J31 Pin Number
Signal Name
ECP5-5G-85 Ball
1
C6
C6
2
C7
C7
3
E8
E8
4
D8
D8
5
GND
—
6
VCCIO0
—
7
C8
C8
8
B8
B8
9
A7
A7
10
A8
A8
11
GND
—
12
VCCIO0
—
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22 FPGA-EB-02017-1.0
5.7. JTAG Header
The J1 header is used to access the JTAG port of the ECP5 or the Raspberry Pi interface.
Table 5.14. J1 Header Pin Connections
J1 Pin Number
Signal Name
ECP5-5G-85 Ball
1
VCCIO8
—
2
TDO
V4
3
TDI
R5
4
NC
—
5
NC
—
6
TMS
U5
7
GND
—
8
TCK
T5
5.8. Parallel Configuration Header
The J38 header is used to access the SPI port of the ECP5 or the Raspberry Pi interface.
Table 5.15. J38 Header Pin Connections
J38 Pin Number
Signal Name
ECP5-5G-85 Ball
1
PROGRAMN
W3
2
FLASH_CS
R2 (with jumper)
3
WRITEN
T3
4
DONE
Y3
5
DQ7
R1
6
INITN
V3
7
DQ6
T1
8
DQ1_MISO
V2
9
DQ5_MISO2
U1
10
DQ0_MOSI
W2
11
DQ4_MOSI2
V1
12
CSN
T2
13
DQ3
W1
14
CS1N
U2
15
DQ2
Y2
16
BUSY_CSSPIN
R2
17
CCLK_MCLK_SCK
U3
18
DOUT_CSON
R3
19
GND
—
20
VCCIO8
—
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6. Control Buses - I2C, I3C, UART, and SPI
This section describes the topology of the various configuration and communication buses.
6.1. I2C and I3C Topology
The ECP5 Evaluation Board uses the I2C bus to support ECP5 configuration, and optionally to support Arduino and
Raspberry Pi communication. The global I2C bus has the signal names SDA0 and SCL0 and they are routed close to the
devices and headers as shown in Figure 3.1 and in more detail in Figure 6.1.
To support the Arduino and Raspberry Pi, each header or device is connected to a dedicated ECP5 GPIO bank with a
direct local I2C bus. Each local I2C bus can optionally connect to the global I2C bus through resistors. The local I2C
connections are summarized in Table 6.1.
Table 6.1. I2C Global Bus Connections
ECP5 Bank
Component
(Reference)
Header Pin
ECP5-5G-85 Ball
Local Signal Name
(Global I2C Signal)
Resistor
2
Arduino header (J6)
9
G16
AR_SDA (SDA0)
R26 (DNI)
10
F17
AR_SCL (SCL0)
R25 (DNI)
3
Raspberry Pi header
(JP8)
27
L18
RASP_ID_SD (SDA0)
R33 (DNI)
28
L17
RASP_ID_SC (SCL0)
R32 (DNI)
The board also has the option to switch to an I3C interface by removing the installed 2.2 kΩ I2C pull-up resistors (R18
and R19) and installing I3C resistors (R52 at 2.2 kΩ, R53 at 100 kΩ, or R54 at 100 kΩ) as shown in Figure 6.1.
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24 FPGA-EB-02017-1.0
rst
FTDI 2232H (U1)
SCL0
SDA0
rst
Bank2 (U3)
AR_SDA
AR_SCL
rst
Bank3 (U3)
RASP_ID_SC
RASP_ID_SD
rst
Bank0 (U3)
SDA0_WPU
SDA0_SPU
SDA0
SCL0_WPU
SCL0
Uninstantiated I3C
Resistors (R52, R53, R54)
rst
Bank6 (U3)
RXD_UART
TXD_UART
BDBUS1/2
BDBUS0
Instantiated I2C Resistors
(R18, R19)
Figure 6.1. I2C Architecture, I3C, and UART Options
6.2. UART Topology
The board provides support for UART configuration by providing an uninstalled connection between the FTDI and ECP5.
Two 0 Ω resistors (R34 and R35) can be installed to connect Port 1 to two general purpose I/Os (PL92A/P2 and
PL92C/P3) in Bank 6 as shown in Figure 6.1.
6.3. SPI Topology
6.3.1. SPI Configuration
One of the major functions of SPI connections on the board is to support ECP5 configuration from the SPI Flash or the
Parallel Configuration Header. The ECP5 Evaluation Board can support both Master SPI (MSPI) and Slave SPI (SSPI)
modes for ECP5 configuration. Figure 6.2 from the schematics show the connections between the header, Flash chip,
and FPGA.
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FPGA-EB-02017-1.0 25
Table 6.2. ECP5 SPI Connections
Signal Name
ECP5-5G-85 Ball
Parallel Configuration
Header Pin
MSPI Mode Direction
SSPI Mode Direction
CCLK_MCLK_SCK
U3
17
Output
Input
DQ0_MOSI
W2
10
Output
Input
DQ1_MISO
V2
8
Input
Output
BUSY_CSSPIN
R2
16
Output
Not used
DQ2
Y2
15
Input
Not used
DQ3
W1
13
Input
Not used
6.3.2. SPI Flash Access
Onboard SPI Flash memory can be used to store the ECP5 configuration data in either External or Dual Boot mode. It
can also store customer data in certain applications. The ECP5 device includes the JTAG to MSPI pass-through circuit
that allows the slave SPI Flash to be erased, programmed, and read with Diamond Programmer. For detailed
information on JTAG to MSPI pass-through for slave SPI Flash access, refer to ECP5 and ECP5-5G sysCONFIG Usage
Guide (FPGA-TN-02039).
Quad
SPI
Flash
(U4)
FLASH_CS
DQ1_MISO
DQ2
DQ3
MCLK
DQ0_MOSI
ECP5
(U3)
Jumper
JP18
BUSY_CSSPIN
Parallel
Config
Header
(J38)
PROGRAMN
DQ7
DQ6
DQ5
DONE
INITN
DOUT_CSON
DQ4
Note: See schematics for complete INITN, PROGRAMN, and DONE connections.
WRITEN
CSN
CS1N
Figure 6.2. SPI Interface
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26 FPGA-EB-02017-1.0
7. LEDs and Switches
This section describes the ECP5 Evaluation Board LEDs and switches that can be used in demo and customer designs.
7.1. DIP Switch
Eight ECP5 pins are connected to the SW5 DIP switch to allow for manually actuated inputs to the FPGA. One side of
each switch is connected to GPIOs within the VCCIO6 and VCCIO1 bank and pulled up through 4.7 kΩ resistors. The
other side is grounded. The designated pins are connected as shown in Table 7.1.
Table 7.1. Eight-Position DIP Switch Signals
Signal Name
ECP5-5G-85 Ball
ECP5-5G-85 Bank
SW5 DIP Switch Position
SWITCH1
J1
6
1
SWITCH2
H1
6
2
SWITCH3
K1
6
3
SWITCH4
E15
1
4
SWITCH5
D16
1
5
SWITCH6
B16
1
6
SWITCH7
C16
1
7
SWITCH8
A16
1
8
7.2. Configuration Mode Switch
A DIP switch is provided to allow the selection of the configuration mode between SSPI, MSPI, SCM, and SPCM as
specified in ECP5 and ECP5-5G sysCONFIG Usage Guide (FPGA-TN-02039). Table 7.2 lists the connectivity of this switch
(SW1).
Table 7.2. CFGMDN Switch Signals
Signal Name
Functional Name
ECP5-5G-85 Ball
ECP5-5G-85 Bank
SW1 DIP Switch Position
CFG0
CFGMDN0
U4
6
2
CFG1
CFGMDN1
T4
6
3
CFG2
CFGMDN2
R4
6
4
7.3. General Purpose Push Buttons
The ECP5 Evaluation Board provides three push button switches – SW2, SW3 and SW4 for demos and user applications.
Two of the buttons control pre-defined functional pins, and the third is generic. Pressing these buttons drives a logic
level “0” to the corresponding I/O pins.
Table 7.3. Push Button Switch Signals
Signal Name
ECP5-5G-85 Ball
Push Button Reference
Logic Level at Button Pressed
GSRN
G2
SW2
0
PROGRAMN
W3
SW3
0
BUTTON_1
P4
SW4
0
SW3 is used as a PROGRAMN push button to trigger the configuration process without power cycle. For detailed
information on PROGRAMN, refer to ECP5 and ECP5-5G sysCONFIG Usage Guide (FPGA-TN-02039). SW2 is intended to
be used as a global set/reset pin when active low, but can be substituted for another function if the user desires. SW3
can be used as a generic input.
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7.4. General Purpose LEDs
The ECP5 Evaluation Board provides eight red LEDs that are connected to I/Os within Bank 1. The LEDs are lighted when
the output is driven LOW.
Table 7.4. General Purpose LED Signals
Signal Name
ECP5-5G-85 Ball
ECP5-5G-85 Bank
LED0
A13
1
LED1
A12
1
LED2
B19
1
LED3
A18
1
LED4
B18
1
LED5
C17
1
LED6
A17
1
LED7
B17
1
7.5. Indicator LEDs
Table 7.5 lists various LEDs and describes their purpose.
Table 7.5. Various LED Signals
LEDs
Signal Name
ECP5-5G-85 Ball
Color
Purpose
D1
UART_ACT
P3
Green
If installed, lights in UART mode
D3
INITN
V3
Red
Lights if configuration error
D4
DONE
Y3
Green
Lights if successful configuration
D22
VCCA0
—
Green
Lights if voltage present
D23
+1.5V
—
Green
Lights if voltage present
D24
+1.2V/VCC_CORE
—
Green
Lights if voltage present
D25
+3.3V
—
Green
Lights if voltage present
D26
+12.0V
—
Blue
Lights if voltage present (external
connection)
D31
+2.5V
—
Green
Lights if voltage present
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28 FPGA-EB-02017-1.0
8. Software Requirements
The following software versions are required to develop designs for the ECP5 Evaluation Board:
Diamond 3.10
Diamond Programmer 3.10
LatticeMico System Development Tools
9. Storage and Handling
Static electricity can shorten the life span of electronic components. Observe these tips to prevent damage that can
occur from electrostatic discharge:
Use antistatic precautions such as operating on an antistatic mat and wearing an antistatic wristband.
Store the development board in the provided packaging.
Touch a metal USB housing to equalize voltage potential between you and the board.
10. Ordering Information
Table 10.1. Ordering Information
Description
Ordering Part Number
China RoHS Environment-Friendly Use Period
(EFUP)
ECP5 Evaluation Board
LFE5UM5G-85F-EVN
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References
Lattice Semiconductor Documents
Related documents available from your Lattice Semiconductor sales representative are listed on the table below.
Document
Title
FPGA-UG-02042
Programming Cables
FPGA-DS-02012
ECP5 and ECP5-5G Family Data Sheet
FPGA-TN-02039
ECP5 and ECP5-5G sysCONFIG Usage Guide
EB103
ECP5-5G Versa Development Board User Guide
FPGA-EB-02004
MachXO3-9400 Development Board User Guide
ECP5™ Evaluation Board
User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
30 FPGA-EB-02017-1.0
Technical Support Assistance
Submit a technical support case through www.latticesemi.com/techsupport.
ECP5™ Evaluation Board
User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02017-1.0 31
Appendix A. ECP5 Evaluation Board Schematics
Figure A. 1. Title Page
ECP5™ Evaluation Board
User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
32 FPGA-EB-02017-1.0
Figure A. 2. Block Diagram
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Page 3 Page 9 Page 6
Page 5
Page 4
Page 9-10
Page 7
Page 7
Unless otherwise noted, blocks are on Page7
ALL MEASURMENT UNITS ARE IN MILS
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
Project
0.1
ECP5-5G Evaluation Board
B
2 12Wednesday, May 16, 2018 B
Block Diagram
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
Project
0.1
ECP5-5G Evaluation Board
B
2 12Wednesday, May 16, 2018 B
Block Diagram
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
Project
0.1
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2 12Wednesday, May 16, 2018 B
Block Diagram
ECP5™ Evaluation Board
User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02017-1.0 33
Figure A. 3. USB Interface
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+3.3V
+3.3V
VCC1_8FT +3.3V
VCC1_8FT +3.3V
+3.3V
+3.3V
VCCIO8
VCCIO0
VBUS_5V
VBUS_5V
+3.3V
VCCIO0
12MHz[7]
TCK [5,9]
TDI [5,9]
TDO [5,9]
TMS [5,9]
RXD_UART [7]
TXD_UART [7]
SCL0 [4,5,7]
SDA0 [4,5,7]
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
Project
0.1
ECP5-5G Evaluation Board
B
3 12Wednesday, May 16, 2018 B
USB Interface
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
Project
0.1
ECP5-5G Evaluation Board
B
3 12Wednesday, May 16, 2018 B
USB Interface
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
Project
0.1
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B
3 12Wednesday, May 16, 2018 B
USB Interface
R13
10K
R2
4.7K
L3
600ohm 500m A
12
C11
0.01uF
R4 0
C141
0.1uF
R240
R21
0R-0603SMT-DNI
DNI
R3
4.7K
TP2
1
C1
0.1uF
R1
4.7K
C9
4.7uF
12
TP1
1
R80
93LC56C-I/SN
U2
CS 1
CLK 2
DI 3
DO 4
VSS
5ORG
6NU
7VCC
8
R10 100K
C4
0.1uF
J2 USB_MINI_AB
VCC 1
D- 2
D+ 3
GND 5
NC 4
CASE 7
CASE 8
CASE 9
CASE 6
X1
7M-12.000MAAJ
1
133
G1
2G2 4
C142
0.1uF
R12 2.2K
R90
R18
2_2K-0603SMT
C6
4.7uF
12
D2
ESDR0502N-UDFN6
GND
1
NC2
2
NC3
3D- 4
VBUS 6
D+ 5
R5
2.2K
R15
10K
C8
0.1uF
G
D1
LED_GREEN_0603
C16
18pF
R70
C14
0.1uF
L1
600ohm 500m A
12
R340 DNI
R110
FTDI High-Speed USB
FT2232H
FT2232HL
U1
VREGIN
50
VREGOUT
49
DM
7
DP
8
REF
6
RESET#
14
EECS
63
EECLK
62
EEDATA
61
OSCI
2
OSCO
3
TEST
13
ADBUS0 16
ADBUS1 17
ADBUS2 18
ADBUS3 19
VPHY 4
VPLL 9
VCORE 12
VCORE 37
VCORE 64
VCCIO 20
VCCIO 31
VCCIO 42
VCCIO 56
AGND
10
GND
1
GND
5
GND
11
GND
15
GND
25
GND
35
GND
47
GND
51
PWREN# 60
SUSPEND# 36
ADBUS4 21
ADBUS5 22
ADBUS6 23
ADBUS7 24
ACBUS0 26
ACBUS1 27
ACBUS2 28
ACBUS3 29
ACBUS4 30
ACBUS5 32
ACBUS6 33
ACBUS7 34
BDBUS0 38
BDBUS1 39
BDBUS2 40
BDBUS3 41
BDBUS4 43
BDBUS5 44
BDBUS6 45
BDBUS7 46
BCBUS0 48
BCBUS1 52
BCBUS2 53
BCBUS3 54
BCBUS4 55
BCBUS5 57
BCBUS6 58
BCBUS7 59
L2
600ohm 500m A
12
R350 DNI
C15
18pF
C2
0.1uF
R14
10K
R17
2_2K-0603SMT
C7
0.1uF
R19
2_2K-0603SMT
JP2 JUMPER
12
R220
C12
10uF
C5
10uF
C13
0.1uF
R2012K
J1
Header 1x8
DNI
11
22
33
44
55
66
77
88
R6 0
C10
0.1uF
R230
R16 12K
JP1
JUMPER
12
C3
0.1uF
FT_VPLL
FT_VPHY
DM
DP
FT_RSTb
FT_REF
FT_EECS
FT_EECLK
FT_EEDATA
FT_OSCI
FT_OSCO
ADBUS3
ADBUS0
ADBUS1
ADBUS2
UART_ACT
SHLD
D-
VBUS
D+
DM
DP DP
DM
FT_RSTb
ECP5™ Evaluation Board
User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
34 FPGA-EB-02017-1.0
Figure A. 4 Arduino Header (BANK2)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ARDUINO Connector
Bank2
Through Hole Prototype Area
Spacing between J3/J6 column and J4/J7 column: 47.96 mils
LVDS RX TERMINATION
RESISTORS
NOTE : PLACE ALL THE TERMINATION
RESISTORS ON TOP SIDE AND CLOSE
TO THE U3C
Note :
1) Match length within pair as well as other pairs with +/- 5% tolerence
2)Differential impedance should be 100 Ohms and 50 Ohms as a single ended signals
3)All the power rails should be capable of carrying 1A current
Warning Note Needed on Silkscreen:
3V3 ARDUINO ONLY
+3.3V_AR +12.0VVBUS_5V
VCCIO2
+3.3V
+2.5V
VCCIO2
VCCIO2
VCCIO2
SDA0 [3,5,7]
SCL0 [3,5,7]
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
Project
0.1
ECP5-5G Evaluation Board
B
4 12Wednesday, May 16, 2018 B
Arduino Interface
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
Project
0.1
ECP5-5G Evaluation Board
B
4 12Wednesday, May 16, 2018 B
Arduino Interface
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
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4 12Wednesday, May 16, 2018 B
Arduino Interface
AF8
AB3
AA11
AC9
AE5
AE10
AC2AF2
AC1
AF7
C84
0.1uF
AB5
AA8
JP4 JUMPER
12
AD5
R250 DNI
AE4
AF10
AC7
C82
0.1uF
R28 100DNI
AG2
AB1
AE8 AB9
AG8
J3
Header 1x8
IO0/RXD
1
IO1/TXD
2
IO3/PWM
4
IO4
5
IO5/PWM
6
IO6/PWM
7
IO7
8
IO2
3
AD4AG4
R31 100DNI
AA4
LFE5G-85F-BG381
U3C
VCCIO2
H14
VCCIO2
H15
VCCIO2
J15 PR11A/URC_GPLL0T_IN C18
PR11B/URC_GPLL0C_IN D17
PR11C E16
PR11D F16
PR14A D18
PR14B E17
PR14C E18
PR14D F18
PR17A F17
PR17B G18
PR17C G16
PR17D H16
PR20A H18
PR20B H17
PR20C J17
PR20D J16
PR29A K16
PR29B K17
PR35A C20
PR35B D19
PR35C/VREF1_2 D20
PR35D E19
PR38A E20
PR38B F19
PR38C F20
PR38D G20
PR41A/GR_PCLK2_1 G19
PR41B H20
PR41C/GR_PCLK2_0 J18
PR41D K18
PR44A/PCLKT2_1 J19
PR44B/PCLKC2_1 K19
PR44C/PCLKT2_0 J20
PR44D/PCLKC2_0 K20
AC5
AD11
AD1
AG7 AB8
AA10
AD3
AF5
AA3
AC4
J7
Header 1x8
N/A
1IOREF
23V3
45V0
5GND1
6GND2
7VIN
8
RESET
3
AE2
AG1
Header_2x11
J5
DNI
11
33
55
77
99
11 11
13 13
15 15
17 17
19 19
21 21
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
AF6
C81
10uF
AB7
AE11
AD7
AG5
AA7
AC8
AG3
J6
Header 1x10
IO8
1
IO9/PWM
2
MOSI/PWM
4
MISO
5
SCK
6
GND
7
AREF
8
SS/PWM
3
AD4/SDA
9
AD5/SCL
10
AE1
JP5 JUMPER
12
AF9
AB11
AG9
AB2
AD6
R29 100DNI
AE7 AA6
R270 DNI
AC11
AF4
AF1
AA2
AB10
AB4
AG11 AD10
AE6 AA5
AD2
J4
Header 1x6
AD0
1AD1
2AD3
4AD4/SDA
5AD5/SCL
6
AD2
3
C83
0.1uF
AF3
AA1
AE9
AC6
AG10
JP3 JUMPER
12
AD9
AG6 AB6
AA9
AC10
AE3
AF11
R30 100DNI
AC3
R260 DNI
AD8
AR_RESET
AR_IO14
AR_IO1
AR_SCL
AR_SDA
AR_IO6
AR_IO5
AR_IO4
AR_IO3
AR_IO2
AR_IO8
AR_IO9
AR_AD5
AR_AD4
AR_AD3
AR_AD1
AR_AD0
AR_AD2
AR_MISO_IO12
AR_IO7
AR_IO0
AR_SS_IO10
AR_AREF
AR_MOSI_IO11
AR_SCK_IO13
AR_IO1
AR_IO6
AR_IO5
AR_IO4
AR_IO2
AR_IO7
AR_IO0
AR_IO3
AR_IO8
AR_IO9
AR_MISO_IO12
AR_SS_IO10
AR_MOSI_IO11
AR_SCK_IO13
AR_SCL
AR_SDA
AR_AREF
AR_AD5
AR_AD4
AR_AD3
AR_AD2
AR_AD1
AR_AD0
AR_RESET
AR_IO14
K20
K19
H20
J18
G19
G20
K18
J19
J20
K19
K20
G20
H20
K18
G19
H20
J18
K18
J19
K19
J20
K20
G19
J18
J19
J20
ECP5™ Evaluation Board
User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02017-1.0 35
Figure A. 5. Raspberry Pi Header (BANK3)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Raspberry PI Connector
Bank3
VBUS_5V
+3.3V_RASP
VCCIO3
VCCIO3
VCCIO3
SCL0 [3,4,7]
SDA0 [3,4,7]
TCK [3,9]
TDI [3,9]
TDO [3,9]
TMS [3,9]
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
Project
0.1
ECP5-5G Evaluation Board
B
5 12Wednesday, May 16, 2018 B
Raspberry Pi Interface
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
Project
0.1
ECP5-5G Evaluation Board
B
5 12Wednesday, May 16, 2018 B
Raspberry Pi Interface
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
Project
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B
5 12Wednesday, May 16, 2018 B
Raspberry Pi Interface
R40 0DNI
JP8
Receptacle 20X2
1
122
3
344
5
566
7
788
9
910 10
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
12 12
14 14
16 16
18 18
20 20
22 22
24 24
26 26
28 28
30 30
32 32
34 34
36 36
38 38
40 40
C18
0.1uF
JP6
JUMPER
12
C92
0.1uF
Header_2x4
J8
DNI
1
1
3
3
5
5
7
7
22
44
66
88
JP7
JUMPER
12
C90
0.1uF
R41 0DNI
LFE5G-85F-BG381
U3D
VCCIO3
L14
VCCIO3
L15
VCCIO3
M15 PR47A/PCLKT3_1 L20
PR47B/PCLKC3_1 M20
PR47C/PCLKT3_0 L19
PR47D/PCLKC3_0 M19
PR50A/GR_PCLK3_0 L16
PR50B L17
PR50C/GR_PCLK3_1 L18
PR50D M18
PR53A N16
PR53B M17
PR53C N18
PR53D P17
PR56A N17
PR56B/VREF1_3 P16
PR56C R16
PR56D R17
PR77A T16
PR83A N19
PR83B N20
PR83C P19
PR83D P18
PR86A P20
PR86B R20
PR86C T20
PR86D U20
PR89A T19
PR89B R18
PR89C U19
PR89D T18
PR92A U18
PR92B U17
PR92C/LRC_GPLL0T_IN U16
PR92D/LRC_GPLL0C_IN T17
C89
10uF
R38 0DNI
R320 DNI
R39 0DNI
C91
0.1uF
C17
0.1uF
R330 DNI
RASP_5V
RASP_IO22
RASP_IO26
RASP_IO27
RASP_ID_SC
RASP_IO09
RASP_IO10 RASP_IO25
RASP_IO23
RASP_IO24
RASP_IO11 RASP_IO07
RASP_IO08
RASP_IO13
RASP_IO05
RASP_IO06
RASP_IO04
RASP_IO12
RASP_IO03
RASP_IO21
RASP_IO20
RASP_IO16RASP_IO19
RASP_ID_SD
RASP_IO18RASP_IO17
RASP_IO02
RASP_IO14
RASP_IO15
RASP_IO04
RASP_IO03
RASP_IO02
RASP_IO09
RASP_IO10
RASP_IO07
RASP_IO11
RASP_IO08
RASP_IO05
RASP_IO06
RASP_IO13
RASP_IO12
RASP_IO16
RASP_IO20
RASP_IO18
RASP_IO19
RASP_IO17
RASP_IO14
RASP_IO15
RASP_IO26
RASP_IO22
RASP_IO27
RASP_IO23
RASP_IO25
RASP_IO24
RASP_IO21
RASP_ID_SC
RASP_ID_SD
L16
M19
M20
L19
L20
L19
L20
L16
M19
M20
ECP5™ Evaluation Board
User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
36 FPGA-EB-02017-1.0
Figure A. 6. SERDES SMA
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SERDES Bank
VCCA_SERDES1
VCCA_SERDES0
VCCHTX1
VCCHTX0
+3.3V
VCCHTX0
VCCHTX1
VCCA_SERDES0
VCCA_SERDES1
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
Project
0.1
ECP5-5G Evaluation Board
B
6 12Wednesday, May 16, 2018 B
SERDES SMAs
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
Project
0.1
ECP5-5G Evaluation Board
B
6 12Wednesday, May 16, 2018 B
SERDES SMAs
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
Project
0.1
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6 12Wednesday, May 16, 2018 B
SERDES SMAs
R44
10K-0402SMT
C26
100NF-0402SMT
C21
100NF-0201SMT
J25
SMA
DNI
12
3
4
5
J24
SMA
DNI
12
3
4
5
J15
SMA
DNI
12
3
4
5
J21
SMA
DNI
12
3
4
5
LFE5G-85F-BG381
U3I
VCCHTX0_D0CH0
T7
VCCHRX0_D0CH0
T8
VCCHTX1_D0CH1
T10
VCCHRX1_D0CH1
T9
VCCHTX0_D1CH0
T11
VCCHRX0_D1CH0
T12
VCCHTX1_D1CH1
T14
VCCHRX1_D1CH1
T13
HDTXP0_D0CH0 W4
HDTXN0_D0CH0 W5
HDTXP0_D0CH1 W8
HDTXN0_D0CH1 W9
HDRXP0_D0CH0 Y5
HDRXN0_D0CH0 Y6
HDRXP0_D0CH1 Y7
HDRXN0_D0CH1 Y8
REFCLKP_D0 Y11
REFCLKN_D0 Y12
HDTXP0_D1CH0 W13
HDTXN0_D1CH0 W14
HDTXP0_D1CH1 W17
HDTXN0_D1CH1 W18
HDRXP0_D1CH0 Y14
HDRXN0_D1CH0 Y15
HDRXP0_D1CH1 Y16
HDRXN0_D1CH1 Y17
REFCLKP_D1 Y19
REFCLKN_D1 W20
X2
200_00MHz_LVDS
Q_N 5
Q4
VCC 6
GND
3
DIS#
1
NC
2
EPAD
7
J20
SMA
DNI
12
3
4
5
R45 10
J11
SMA
DNI
12
3
4
5
C145
1UF-16V-0402SMT
C20
100NF-0402SMT
C30
100NF-0201SMT
J17
SMA
DNI
12
3
4
5
J18
SMA
DNI
12
3
4
5
JP9
JUMPER
1 2
R180 100
C19
100NF-0402SMT
C29
100NF-0402SMT
C24
100NF-0201SMT
J16
SMA
DNI
12
3
4
5
J14
SMA
DNI
12
3
4
5
C32
100NF-0402SMT
J13
SMA
DNI
12
3
4
5
J10
SMA
DNI
12
3
4
5
C25
100NF-0402SMT
J12
SMA
DNI
12
3
4
5
C28
100NF-0402SMT
C31
1UF-16V-0805SMT
C23
100NF-0201SMT
J26
SMA
DNI
12
3
4
5
C146
1UF-16V-0402SMT
J22
SMA
DNI
12
3
4
5
R46 10
L8
600ohm 500m A
12
J9
SMA
DNI
12
3
4
5
C144
1UF-10V-0201SMT
J23
SMA
DNI
12
3
4
5
C143
1UF-16V-0402SMT
J19
SMA
DNI
12
3
4
5
C22
100NF-0201SMT
C27
100NF-0201SMT
HDTXP_D0C0
HDTXN_D0C0
HDTXP_D0C1
HDTXN_D0C1
HDRXP_D0C0
HDRXN_D0C0
HDRXP_D0C1
HDRXN_D0C1
HDTXP_D1C0
HDTXN_D1C0
HDTXP_D1C1
HDTXN_D1C1
HDRXP_D1C0
HDRXN_D1C0
HDRXP_D1C1
HDRXN_D1C1
HDTXP_D0C0
HDTXN_D0C0
HDRXP_D0C0
HDRXN_D0C0
HDTXP_D0C1
HDTXN_D0C1
HDRXP_D0C1
HDRXN_D0C1
HDTXP_D1C0
HDTXN_D1C0
HDRXP_D1C0
HDRXN_D1C0
HDTXP_D1C1
HDTXN_D1C1
HDRXP_D1C1
HDRXN_D1C1
REFCLKP_D0
REFCLKN_D0
REFCLKN_D0REFCLKP_D0
200MHz
200MHz_N
200MHz
200MHz_N
ECP5™ Evaluation Board
User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02017-1.0 37
Figure A. 7. IO Breakout (BANK0, BANK1, BANK6)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Bank0
Bank1 Bank6
Rotate on PCB - Keep a 90
degree orientation
difference between J29 / J30
Microphone Daughter
Board Expansion Connectors
(Through Hole)
5VIN
GND
Pin 2 removed for coding
of expansion board
VERSA Expansion
Headers
PMOD
Header
Distance between jumpers should be the
same as in the ice40 UltraPlus MDP board
VCCIO0
VCCIO1 VCCIO6
VCCIO0
VCCIO0
+3.3V
+2.5V
VCCIO6
VCCIO0
VCCIO1
VCCIO6
LED[0:7] [10]
SWITCH[1:8] [10]
GSRN[9]
BUTTON_1[9]
12MHz [3]
TXD_UART[3] RXD_UART[3]
SCL0 [3,4,5]
SDA0 [3,4,5]
50MHz_OSC_EN [8]
50MHz_OSC [8]
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
Project
0.1
ECP5-5G Evaluation Board
B
7 12Wednesday, May 16, 2018 B
IO Breakout
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
Project
0.1
ECP5-5G Evaluation Board
B
7 12Wednesday, May 16, 2018 B
IO Breakout
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
Project
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B
7 12Wednesday, May 16, 2018 B
IO Breakout
TP4
C75
0.1uF
LFE5G-85F-BG381
U3A
VCCIO0
F10
VCCIO0
F9 PT11A C6
PT11B C7
PT13A E8
PT13B D8
PT15A C8
PT15B B8
PT18A A7
PT18B A8
PT20A D9
PT20B E9
PT4A/ULC_GPLL1T_IN A6
PT4B/ULC_GPLL1C_IN B6
PT54A C9
PT56A D10
PT56B E10
PT58A B9
PT58B C10
PT60A/GR_PCLK0_1 A9
PT60B/GR_PCLK0_0 B10
PT63A/PCLKT0_1 A10
PT63B/PCLKC0_1 A11
PT65A/PCLKT0_0 B11
PT65B/PCLKC0_0 C11
PT6A E6
PT6B D6
PT9A E7
PT9B D7
J40
HDR40
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
C66
0.1uF
R50
0R-0603SMT- DNI
C71
0.1uF
TP3
R54
100K-DNI
C65
10uF
LFE5G-85F-BG381
U3B
VCCIO1
F11
VCCIO1
F12 PT103A A15
PT105A B15
PT105B C15
PT107A D15
PT107B E15
PT110A A16
PT110B B16
PT112A C16
PT112B D16
PT114A B17
PT114B C17
PT116A A17
PT116B B18
PT119A A18
PT119B B19
PT121A/URC_GPLL1T_IN A19
PT121B/URC_GPLL1C_IN B20
PT69A/PCLKT1_1 D11
PT69B/PCLKC1_1 E11
PT71A/PCLKT1_0 B12
PT71B/PCLKC1_0 C12
PT74A/GR_PCLK1_0 D12
PT74B/GR_PCLK1_1 E12
PT76A A12
PT76B A13
PT78A B13
PT78B C13
PT80A D13
PT80B E13
PT83A A14
PT83B C14
PT85A D14
PT85B E14
C74
0.1uF
C72
0.1uF
C70
0.1uF
R49
0R-0603SMT
C67
0.1uF
J30
2x5 HEADER
Wurth
61301021121
2
4
6
8
109
7
5
3
1
R52
2.2K-DNI
C73
10uF
J39
HDR40
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
J29
2x5 HEADER
Wurth
DNI
61301021121
2
4
6
8
109
7
5
3
1
C33
0.1uF
J31
PMOD 2x6
DNI
82
4
6
7
5
3
1
10
9
12
11
LFE5G-85F-BG381
U3E
VCCIO6 L6
VCCIO6 L7
VCCIO6 M6
PL47A/PCLKT6_1
G2
PL47B/PCLKC6_1
F1
PL47C/PCLKT6_0
H2
PL47D/PCLKC6_0
G1
PL50A/GR_PCLK6_0
J4
PL50B
J5
PL50C/GR_PCLK6_1
J3
PL50D
K3
PL53A
K2
PL53B
J1
PL53C
H1
PL53D
K1
PL56A
K4
PL56B/VREF1_6
K5
PL56C
L4
PL56D
L5
PL77A
M5
PL83A
M4
PL83B
N5
PL83C
N4
PL83D
P5
PL86A
N3
PL86B
M3
PL86C
L3
PL86D
L2
PL89A
N2
PL89B
M1
PL89C
L1
PL89D
N1
PL92A
P1
PL92B
P2
PL92C/LLC_GPLL0T_IN
P3
PL92D/LLC_GPLL0C_IN
P4
C69
10uF
R51
0R-0603SMT
R53
100K-DNI
GPIO_amp_A6
I2S_SD_mic1_mic2_card_B6
C6
C7
E8
C8
D8
B8
A7
I2S_SCK_mic_D9
A8
I2S_WS_mic_E9
B10
F1
J4
J3
SWITCH3
K4
L4
K5
L5
M5
M4
N4
N5
P5
N3
L3
M3
L2
N2
L1
M1
N1
LED3
LED6
LED2
LED7
LED5
LED4 SWITCH8
SWITCH7
SWITCH4
SWITCH1
SWITCH[1..8]
SWITCH2
SWITCH3
SWITCH5
SWITCH6
SWITCH5
SWITCH6
SWITCH7
SWITCH8
H2
G1
J5
K3
B15
C15
D15
SWITCH4
D11
E11
B12
C12
D12
E12
B13
C13
D13
E13
A14 P1
A11
LED1
LED0
B20
A19
SWITCH1
K2
C6
C7
E8
D8
C8
B8
A7
A8
I2S_SCK_mic_D9
I2S_WS_mic_E9
I2S_SD_mic1_mic2_card_B6
I2S_SD_mic3_mic4_C9
I2S_SD_mic5_mic6_D10
I2S_SD_mic7_E10GPIO_amp_A6
EXPCON_2V5
EXPCON_2V5
E7
EXPCON_3V3
EXPCON_3V3
CARDSEL#
A15 F1
H2 G1
J4 J5
J3 K3
K2
SWITCH2
L4 L5
M4 N5
N4 P5
N3 M3
K5
M5
L3
L2
N2
L1
M1
N1
C14
D14
P1 E14
K4
A11
A19
A9
B15 C15
D15
D11 E11
B12 C12
D12 E12
B20B13
C13 D13
E13 A14
A9 B10
SDA0_WPU
SDA0_SPU
SCL0_WPU
E7
SDA0
SCL0
I2S_SD_mic3_mic4_C9
I2S_SD_mic5_mic6_D10
I2S_SD_mic7_E10
A15
C14
D14
E14
ECP5™ Evaluation Board
User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
38 FPGA-EB-02017-1.0
Figure A. 8. IO Breakout (BANK7, Differential Pairs)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Bank7
50MHz OSC
This is optional
to enable or
disable the
crystal.
LVDS RX TERMINATION RESISTORS
NOTE : PLACE ALL THE TERMINATION
RESISTORS ON TOP SIDE AND CLOSE
TO THE U3F
Note :
1) Match length within pair as well as other pairs with +/- 5% tolerence
2)Differential impedance should be 100 Ohms and 50 Ohms as a single ended signals
3)All the power rails should be capable of carrying 1A current
(3.3 V)
(3.3V)
VCCIO7
VCCIO7 VCCIO7
VCCIO0 VCCIO7
50MHz_OSC_EN[7]
50MHz_OSC [7]
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
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B
8 12Wednesday, May 16, 2018 B
IO Breakout (Diff)
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
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8 12Wednesday, May 16, 2018 B
IO Breakout (Diff)
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
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8 12Wednesday, May 16, 2018 B
IO Breakout (Diff)
R58 100DNI
R64 100DNI
X5
LFSPXO01998
DNI
EN
1
GND
2Output 3
Vcc 4
C79
0.1uF
LFE5G-85F-BG381
U3F
VCCIO7 H6
VCCIO7 H7
VCCIO7 J6
PL11A/ULC_GPLL0T_IN
A4
PL11B/ULC_GPLL0C_IN
A5
PL11C
B5
PL11D
C5
PL14A
C4
PL14B
B4
PL14C
A3
PL14D
B3
PL17A
E4
PL17B
D5
PL17C
C3
PL17D
D3
PL20A
F4
PL20B
E3
PL20C
E5
PL20D
F5
PL35A
A2
PL35B
B1
PL35C/VREF1_7
B2
PL35D
C2
PL38A
C1
PL38B
D1
PL38C
D2
PL38D
E1
PL41A/GR_PCLK7_1
H4
PL41B
G5
PL41C/GR_PCLK7_0
H5
PL41D
H3
PL44A/PCLKT7_1
G3
PL44B/PCLKC7_1
F3
PL44C/PCLKT7_0
F2
PL44D/PCLKC7_0
E2
R59 100DNI
C34
0.1uF
Header_2x16
J33
DNI
11
33
55
77
99
11 11
13 13
15 15
17 17
19 19
21 21
23 23
25 25
27 27
29 29
31 31
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
R70 100DNI
R66 100DNI
C80
0.1uF
R55
0
R56 100DNI
R69 100DNI
C78
0.1uF
R72 100DNI
R68 100DNIR67 100DNI
R62 100DNI
J32
Header2x20
DNI
2
4
6
8
10
12
14
16
18
20
24
22
26
28
30
32
34
36
38
40 39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
R60
22
R71 100DNI
C77
10uF
R65 100DNI
R63 100DNI
R57 100DNI
R61 100DNI
A4
A5
C5
C4
A3
B4
B3
E4
C3
D5
D3
B5
F4
E5
E3
F5
A2
B2
B1
C1
D2
D1
E1
H4
H5
G5
H3
G3
C2
F2
F3
E2
A4
A5
A4
C4
A3
E4
C3
B5
F4
E5
A2
B2
C1
D2
H4
H5
G3
F2
B5
C5
C4
B4
A3
B3
E4
D5
C3
D3
F4
E3
E5
F5
A2
B1
B2
C2
C1
D1
D2
E1
H4
G5
H5
H3
G3
F3
F2
E2
A5
C5
B4
B3
D5
D3
E3
F5
B1
D1
E1
G5
H3
C2
F3
E2
ECP5™ Evaluation Board
User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02017-1.0 39
Figure A. 9. Configuration
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
128Mb SPI Flash
DONE indicator will light when
configuration is successfully
completed
INITN indicator will light
if an error occurs during
configuration programming
DONE
INITN
CONFIG Status LEDs
GP BUTTON
18pF = 12pF + Ground Plane ( 6pF )
FPGA GSRN
PROGRAMN
Parallel Config Header
Place as close to Flash as possible
VCCIO8
VCCIO8
VCCIO8
VCCIO8
VCCIO8
VCCIO8 VCCIO8
VCCIO8
VCCIO8 VCCIO6
VCCIO6
VCCIO8
VCCIO8
TCK [3,5]
TDI [3,5]
TDO [3,5]
TMS [3,5]
GSRN [7]
BUTTON_1 [7]
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
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B
9 12Wednesday, May 16, 2018 B
Configuration
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
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9 12Wednesday, May 16, 2018 B
Configuration
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
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9 12Wednesday, May 16, 2018 B
Configuration
430182043816
SW4
A1
1
A2
3B1 2
B2 4
R83
4_7K-0603SMT
RLP-101
SW1
SW DIP-4
R93
10K-0402SMT
TP16
R80
4_7K-0603SMT
RLP-101
JP18JUMPER
1 2
C85
10uF
R81
4_7K-0603SMT
RLP-101
TP10
C39
20pF-0603SMT
DNI
TP19
C86
0.1uF
R78
1K-0603SMT
R75
4_7K-0603SMT
R85 0R-0402SMT
TP13
R88 0R-0402SMT
TP5
R77
1K-0603SMT
R86 0R-0402SMT
R76
1K-0603SMT
R73
4_7K-0603SMT
C37
20pF-0603SMT
DNI TP14
R74
4_7K-0603SMT
Header_2x10
J38
DNI
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
22
44
66
88
10 10
12 12
14 14
16 16
18 18
20 20
R91
10K-0402SMT
TP54
TP9
430182043816
SW2
A1
1
A2
3B1 2
B2 4
TP11
R87 0R-0402SMT
430182043816
SW3
A1
1
A2
3B1 2
B2 4
R
D3
LED_RED_0603
R94
2_2K-0603SMT
R79
50R-0603SMT
R82
1K-0603SMT
RLP-101
C40
100NF-0402SMT
C38
20pF-0603SMT
DNI
TP18
G
D4
LED_GREEN_0603
TP20
TP7
C36
100NFX5R-0402SMT
LFE5G-85F-BG381
U3G
VCCIO8
P10
VCCIO8
P9 CCLK/MCLK/SCK U3
CFG_0 U4
CFG_1 T4
CFG_2 R4
DONE Y3
INITN V3
PB11A/D1/MISO/IO1 V2
PB11B/D0/MOSI/IO0 W2
PB13A/SN/CSN T2
PB13B/CS1N U2
PB15A/HOLDN/DI/BUSY/CSSPIN/CEN R2
PB15B/DOUT/CSON R3
PB18A/WRITEN T3
PB4A/D7/IO7 R1
PB4B/D6/IO6 T1
PB6A/D5/MISO2/IO5 U1
PB6B/D4/MOSI2/IO4 V1
PB9A/D3/IO3 W1
PB9B/D2/IO2 Y2
PROGRAMN W3
TP12
LFE5G-85F-BG381
U3H
TCK T5
TDI R5
TDO V4
TMS U5
U4
MX25L12833FMI-10G
CS#
7
SO/SIO1
8
WP#/SIO2
9
GND
10 SI/SIO0 15
SCLK 16
DNU/SIO3 1
VCC 2
RESET#/NC_3
3
NC_4
4
NC_5
5
NC_6
6
NC_14 14
NC_13 13
NC_12 12
NC_11 11
TP8
TP23
TP17
C42
100NF-0402SMT
R92
10K-0402SMT
R89
10K-0402SMT
C41
100NF-0402SMT
R95
2_2K-0603SMT
C35
10NF-0402SMT
R96
10K-0603SMT
TP21
C43
100NF-0402SMT
Q1
2N2222/SOT23
3
1
2
TP22
TP53
TP15
TP6
R90
10K-0402SMT
C87
0.1uF
CFG1
CFG0
CFG2
DQ2
FLASH_CS
DQ1_MISO
INITN
DONE
BUTTON_1
GSRN
PROGRAMN
DONE
INITN
PROGRAMN
DQ1_MISO
DQ0_MOSI
CSN
CS1N
DOUT_CSON
BUSY_CSSPIN
DQ7
WRITEN
DQ5_MISO2
DQ6
DQ3
DQ4_MOSI2
DQ2
DONE
INITN
CCLK_MCLK_SCK
DONE
INITN
DQ1_MISO
DQ0_MOSI
CSN
CS1N
DOUT_CSON
BUSY_CSSPIN
DQ7
WRITEN
DQ5_MISO2
DQ6
DQ3
DQ4_MOSI2
DQ2
CCLK_MCLK_SCK
CCLK_MCLK_SCK
DQ3
BUSY_CSSPIN
PROGRAMN FLASH_CS
DQ0_MOSI
ECP5™ Evaluation Board
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© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
40 FPGA-EB-02017-1.0
Figure A. 10. Power Decoupling and LEDs
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LEDs
D5
D6
D7
D8
D9
D10
D11
D12
LEDs Signal Map
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
A13
A12
B19
A18
B18
C17
A17
B17
U1 pin Signal LED
DIP SWITCH
Switch Signal Map
8
1
2
3
4
5
6
7
J1
H1
K1
E15
D16
B16
C16
A16
U1 pin SWITCHSignal
SWITCH8
SWITCH1
SWITCH2
SWITCH3
SWITCH4
SWITCH5
SWITCH6
SWITCH7
VCCIO1
VCCIO6
VCCIO1
+2.5V
VCCA0
VCCA1
VCC_CORE
LED[0:7] [7]
SWITCH[1:8] [7]
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
Project
0.1
ECP5-5G Evaluation Board
B
10 12Wednesday, May 16, 2018 B
Power Decoupling and LEDs
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
Project
0.1
ECP5-5G Evaluation Board
B
10 12Wednesday, May 16, 2018 B
Power Decoupling and LEDs
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
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Power Decoupling and LEDs
RN2B
EXB2HV472JV
4_7K
2 15
C59
100NF-0201SMT
RN2F
EXB2HV472JV
4_7K
6 11
FB2
BLM31KN121SN1L
RN1F
EXB-2HV102JV
1K
6 11
G
D10LED_GREEN_0603
RN1C
EXB-2HV102JV
1K
3 14
G
D12LED_GREEN_0603
C46
100NF-0402SMT
RN2C
EXB2HV472JV
4_7K
3 14
SW5
TDA DIP-8
RN2G
EXB2HV472JV
4_7K
7 10
C56
100NF-0201SMT
G
D5LED_GREEN_0603
RN1D
EXB-2HV102JV
1K
4 13
C53
100NF-0201SMT
LFE5G-85F-BG381
U3K
VCCA0 U6
VCCA0 T6
VCCA1 U15
VCCA1 T15
VCCAUX P6
VCCAUX P15
VCCAUX F6
VCCAUX F15
VCCAUXA0 V11
VCCAUXA0 V10
VCCAUXA1 V18
VCCAUXA1 V17
RESERVED1 W11
RESERVED2 W10
GNDA
U10
GNDA
U11
GNDA
U12
GNDA
U13
GNDA
U14
GNDA
U7
GNDA
U8
GNDA
U9
GNDA
V12
GNDA
V13
GNDA
V14
GNDA
V15
GNDA
V16
GNDA
V19
GNDA
V20
GNDA
V5
GNDA
V6
GNDA
V7
GNDA
V8
GNDA
V9
GNDA
W12
GNDA
W15
GNDA
W16
GNDA
W19
GNDA
W6
GNDA
W7
RN1E
EXB-2HV102JV
1K
5 12
C61
100NF-0201SMT
C62
100NF-0402SMT
G
D7LED_GREEN_0603
RN2H
EXB2HV472JV
4_7K
8 9
RN2D
EXB2HV472JV
4_7K
4 13
C50
100NF-0201SMT
RN1H
EXB-2HV102JV
1K
8 9
G
D8LED_GREEN_0603
C57
100NF-0201SMT
RN1G
EXB-2HV102JV
1K
7 10
G
D11LED_GREEN_0603
LFE5G-85F-BG381
U3J
VCC H10
VCC H11
VCC H12
VCC H13
VCC H8
VCC H9
VCC J13
VCC J8
VCC K13
VCC K8
VCC L13
VCC L8
VCC M13
VCC M8
VCC N10
VCC N11
VCC N12
VCC N13
VCC N8
VCC N9
GND
B14
GND
B7
GND
C19
GND
D4
GND
F13
GND
F14
GND
F7
GND
F8
GND
G10
GND
G11
GND
G12
GND
G13
GND
G14
GND
G15
GND
G17
GND
G4
GND
G6
GND
G7
GND
G8
GND
G9
GND
H19
GND
J10
GND
J11
GND
J12
GND
J14
GND
J2
GND
J7
GND
J9
GND
K10
GND
K11
GND
K12
GND
K14
GND
K15
GND
K6
GND
K7
GND
K9
GND
L10
GND
L11
GND
L12
GND
L9
GND
M10
GND
M11
GND
M12
GND
M14
GND
M16
GND
M2
GND
M7
GND
M9
GND
N14
GND
N15
GND
N6
GND
N7
GND
P11
GND
P12
GND
P13
GND
P14
GND
P7
GND
P8
GND
R19
C60
100NF-0402SMT
C76
10uF
G
D9LED_GREEN_0603
C147
22uF-6.3V-0805SMT
RLP-133
C58
100NF-0201SMT
C49
1UF-0402SMT
C55
100NF-0201SMT
C44
100NF-0201SMT
C51
100NF-0201SMT
C68
10uF
C47
100NF-0201SMT
RN2A
EXB2HV472JV
4_7K
1 16
RN2E
EXB2HV472JV
4_7K
5 12
RN1B
EXB-2HV102JV
1K
2 15
C63
1UF-16V-0805SMT
C45
1UF-0402SMT
RN1A
EXB-2HV102JV
1K
1 16
C52
100NF-0201SMT
C48
100NF-0402SMT
G
D6LED_GREEN_0603
C54
100NF-0201SMT
LED0
LED2
LED3
LED1
LED6
LED7
LED4
LED5
USR0_PU
USR3_PU
POLL_PU
DL_UP_PU
USR1_PU
USR2_PU
PLL_LK_PU
L0_PU
LED[0:7]
SWITCH4
SWITCH3
SWITCH2
SWITCH1
SWITCH6
SWITCH7
SWITCH5
SWITCH8
SWITCH[1..8]
SWITCH4
SWITCH3
SWITCH2
SWITCH1
SWITCH6
SWITCH7
SWITCH5
SWITCH8
VCCA0
VCCA1
VCCAUX
ECP5™ Evaluation Board
User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02017-1.0 41
Figure A. 11.Power Hookup
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
spread across board, easy access
This can be configured in a +
configuration with VCCIO0 in the
middle to reduce space used
2.5 V
1.2 V
VCC_CORE 1.5 V 3.3 V
1.1 V
Analog
12VIN GOOD
This can be configured in a +
configuration with VCCIO0 in the
middle to reduce space used
Default : Pin 1 & 2
Default : Pin 1 & 2
+3.3V_AR
+3.3V VCCIO2
+3.3V_RASP
+3.3V VCCIO3 +3.3V VCCIO6
+2.5V
+3.3V +3.3V VCCIO8 +3.3V
+1.5V
+2.5V
+2.5V +2.5V
+2.5V
VCC_CORE
+2.5V
+12.0V
+12.0V
+12.0V
+12.0V
VCC_CORE +1.5v
VCCA0
+2.5V +3.3V
VCCIO1
+3.3V
VCC_CORE
+2.5V
VCCIO0
+1.5V
+3.3V
VCC_CORE
+2.5V
+1.5V
VCCIO7
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
Project
0.1
ECP5-5G Evaluation Board
B
11 12Wednesday, May 16, 2018 B
Power Hookup
Date:
Size Schematic Rev
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Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
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11 12Wednesday, May 16, 2018 B
Power Hookup
Date:
Size Schematic Rev
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Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
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11 12Wednesday, May 16, 2018 B
Power Hookup
R179
470R-0603SMT
R136
24K-1206SMT
TP34
1
R138
4.7K-0603SMT
TP27
1
G
D25
LED_GREEN_0603
R104 0
DNI
R101 0
TP24
1
R106 0
DNI
Q2
2N2222/SOT23
3
1
2
R107 0
DNI
R105 0
DNI
TP28
1
TP35
1
JP11
HEADER_5PIN
5
4
3
2
1
Q3
2N2222/SOT23
3
1
2
R139
24K-1206SMT
TP33
1
R103 0
DNI
R99 0
JP10
HEADER_5PIN
5
4
3
2
1
TP36
1
R140
4.7K-0603SMT
R142
1_8K-1206SMT
Q4
2N2222/SOT23
3
1
2
TP29
1
G
D22
LED_GREEN_0603
TP55
1
G
D31
LED_GREEN_0603
R100 0
R108 0
DNI TP39
1
TP56
1
TP25
1
R135
2_2K-0603SMT
B
D26
LED_BLUE_0603
R137
24K-1206SMT
TP30
1
G
D23
LED_GREEN_0603
TP37
1
R102 0
DNI
TP32
1
TP31
1
R97 0
TP57
1
R141
4.7K-0603SMT
TP40
1
TP26
1
G
D24
LED_GREEN_0603
TP38
1
R98 0
ECP5™ Evaluation Board
User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
42 FPGA-EB-02017-1.0
Figure A. 12. Power Regulators
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCCA
current
VCCHTX
current
0.45 v drop at 500 mA max
SERDES VCCHTX
1.2 V Power
+1.2 V
500 mA
SERDES VCCA
1.2 V Power
+1.2 V
500 mA
2.5 V Current 3.3 V Current
1.2v/ms
+3.3 V
1.35 A
Vout = 0.8*(R119/R124+1) = 3.32 V
3.3 V
1.2v/ms
+2.5 V
1.1 A
Vout = 0.8*(R118/R120+1) = 2.52 V
2.5 V
Right angle
mount, cable
to board edge
POWER INPUT
+11v to +16v
+1.5 V
1.1 A
1.2v/ms
1.2v/ms
+1.2 V
1.35 A
Vout = 0.8*(R128/R133+1) = 1.21 V Vout = 0.8*(R129/R134+1) = 1.51 V
Core Power 1.5 V Current 1.5 V
1.2 V Current
Place current measuring
resistor R115 topside
Place current measuring
resistor R117 topside
Place current measuring
resistor R127 topside
Place current measuring
resistor R126 topside
1 2
K
+3.3V +3.3V VCCA
VCCHTX VCCHTX0
VCCHTX1
VCCA0
VCCA1
+3.3V +3.3V
+3.3V+2.5V
+12.0V +12.0V
+12.0V
+3.3V +3.3V
+1.5V
VCC_CORE
VCCA_SERDES0
VCCA_SERDES1
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
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B
12 12Wednesday, May 16, 2018 B
Power Regulators
Date:
Size Schematic Rev
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Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
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B
12 12Wednesday, May 16, 2018 B
Power Regulators
Date:
Size Schematic Rev
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Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Board Rev
Project
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B
12 12Wednesday, May 16, 2018 B
Power Regulators
C106
1UF-16V-0805SMT
TP43
C133
330pF-0402SMT
C1281000pF-0402SMT
R112
121K-0603SMT
R121
51K-0402SMT
D18
1N4448W
21
C94
1UF-16V-0805SMT
C124
22uF,6.3V-0805SMT
RLP-133
C118
10pF-0402SMT
C116
330pF-0402SMT
L5
4.7uH-SPD62R-472M
D20
DFLS220L
12
C96
10uF-6.3V-0805SMT
RLP-133
C151
22uF-6.3V-0805SMT
RLP-133
R132
20K-0402SMT
TP45
TP44
C136
22uF,6.3V-0805SMT
RLP-133
U7
LT3508EUF
FB2 18
VC2 19
PG2 20
RT/SYNC
22
SHDN 21
FB1
1
TRACK/SS1
2
BOOST1
7
SW1
8
VIN1 9
VC1
24
VIN2 10
PG1
23
SW2 11
BOOST2 12
TRACK/SS2 17
GND5
25
GND6
13
GND7
14
GND4
6GND3
5GND2
4GND1
3
GND8
15
GND9
16
C111
1UF-16V-0805SMT
C120
22uF,6.3V-0805SMT
RLP-133
R120
10K-0603SMT
1%
R133
10K-0603SMT
1%
C138
22uF,6.3V-0805SMT
RLP-133
C125
10uF,25V-1206SMT
RLP-134
D16
DFLS220L
12
R122
34K-0402SMT
1%
Freq = 1.0 MHz
C119
330pF-0402SMT
C137
10pF-0402SMT
C123
22uF,6.3V-0805SMT
RLP-133
C132
10pF-0402SMT
DNI
R119
10_7K-0603SMT
1%
C95
1UF-16V-0805SMT
RLP-133
TP46
TP50
TP41
C152
22uF-6.3V-0805SMT
RLP-133
C102
10NFX5R-0402SMT
R109
0.01 cr2512_alt11%
L7
4.7uH-SPD62R-472M
D13
SCHOTTKY/VISHAY-V12P10
R130
30_1K-0402SMT
C122
22uF,6.3V-0805SMT
RLP-133
C108
1UF-16V-0805SMT
C139
22uF,6.3V-0805SMT
RLP-133
C140
22uF,6.3V-0805SMT
RLP-133
R114
121K-0603SMT
FB5
BLM31KN121SN1L
R117
0.1
cr2010_alt1
1%
C113
220NF-0402SMT
16V
C1151000pF-0402SMT
R126
0.1
cr2010_alt1
1%
U5
LT3085
OUT_1 1
OUT_2 2
OUT_3 3
SET 4
IN_7
7IN_8
8
IN_6
6
VCtrl
5
Pad 9
R118
21_5K-0603SMT
1%
FB6
BLM31KN121SN1L
D14
1N4448W
21
TP42
C97
1UF-16V-0805SMT
RLP-133
R113
1K
C131
10pF-0402SMT
DNI
C153
22uF-6.3V-0805SMT
RLP-133
R116
51K-0402SMT
J37
PJ-002A
Male Power Jack 2.1mm
1
3
2
R134
16_9K-0603SMT
1%
D19
1N4448W
21
C100
1UF-16V-0805SMT
C117
10pF-0402SMT
C148
22uF-6.3V-0805SMT
RLP-133
R127
0.1
cr2010_alt1
1%
C109
10uF,25V-1206SMT
RLP-134
TP49
R125
51K-0402SMT
D21
DFLS220L
12
FB8
BLM31KN121SN1L
TP47
C127
220NF-0402SMT
16V
C98
10uF-6.3V-0805SMT
RLP-133
FB3
BLM31KN121SN1L
C112
220NF-0402SMT
16V
R110
0.1
cr2010_alt1
1%
R129
15K-0603SMT
1%
C1291000pF-0402SMT
D15
1N4448W
21
C121
22uF,6.3V-0805SMT
RLP-133
C104
1UF-16V-0805SMT
R131
63_4K-0402SMT
1%
Freq = 625 KHz
U8
LT3508EUF
FB2 18
VC2 19
PG2 20
RT/SYNC
22
SHDN 21
FB1
1
TRACK/SS1
2
BOOST1
7
SW1
8
VIN1 9
VC1
24
VIN2 10
PG1
23
SW2 11
BOOST2 12
TRACK/SS2 17
GND5
25
GND6
13
GND7
14
GND4
6GND3
5GND2
4GND1
3
GND8
15
GND9
16
C135
22uF,6.3V-0805SMT
RLP-133
C149
22uF-6.3V-0805SMT
RLP-133
TP48
FB7
BLM31KN121SN1L
R124
3_4K-0603SMT
1%
L6
4.7uH-SPD62R-472M
R128
5_11K-0603SMT
1%
C126
220NF-0402SMT
16V
F1
F1251CT-ND
5A Fast-Blo SMT Socketed Fuse
R115
0.1
cr2010_alt1
1%
U6
LT3085
OUT_1 1
OUT_2 2
OUT_3 3
SET 4
IN_7
7IN_8
8
IN_6
6
VCtrl
5
Pad 9
TP51
C114 1000pF-0402SMT
FB4
BLM31KN121SN1L
R123
51K-0402SMT
L4
4.7uH-SPD62R-472M
C134
10pF-0402SMT
C101
10NFX5R-0402SMT
R111
1K
C150
22uF-6.3V-0805SMT
RLP-133
C130
330pF-0402SMT
D17
DFLS220L
12
TP52
ECP5™ Evaluation Board
User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02017-1.0 43
Appendix B. ECP5 Evaluation Board Bill of Materials
Item
Reference
Qty
Part
PCB
Footprint
Comments
Part Number
Manufacturer
Description
1
AG1,AF1,AE1,AD1,AC1,
AB1,AA1,AG2,AF2,AE2,
AD2,AC2,AB2,AA2,AG3,
AF3,AE3,AD3,AC3,AB3,A
A3,AG4,AF4,AE4,AD4,A
C4,AB4,AA4,AG5,AF5,A
E5,AD5,AC5,AB5,AA5,A
G6,AF6,AE6,AD6,AC6,A
B6,AA6,AG7,AF7,AE7,A
D7,AC7,AB7,AA7,AG8,A
F8,AE8,AD8,AC8,AB8,AA
8,AG9,AF9,AE9,AD9,AC
9,AB9,AA9,AG10,AF10,
AE10,AD10,AC10,AB10,
AA10,AG11,AF11,AE11,
AD11,AC11,AB11,AA11
77
T POINT R
TP
DNL
—
—
—
2
C1,C2,C3,C4,C7,C8,C10,
C13,C14,C141,C142
11
0.1uF
C0402
—
CL05B104KA5NNNC
Samsung
CAP CER 0.1UF 25V
10% X7R 0402
3
C5
1
10uF
C0402
—
CL05A106MP8NUB8
Samsung
CAP CER 10UF 10V
X5R 0402
4
C6,C9
2
4.7uF
C0603
—
CL10A475KA8NQNC
Samsung
CAP CER 4.7UF 25V
X5R 0603
5
C11
1
0.01uF
C0402
—
CL05B103KA5NNNC
Samsung
CAP CER 10000PF
25V X7R 0402
6
C12
1
10uF
C0603
—
CL10A106KO8NNNC
Samsung
CAP CER 10UF 10V
X5R 0603
7
C15,C16
2
18pF
C0402
—
CL05C180JA5NNNC
Samsung
CAP CER 18PF 25V
10% NP0 0402
8
C17,C18
2
0.1uF
C0402
—
CL05B104KA5NNNC
Samsung
CAP CER 0.1UF 25V
10% X7R 0402
9
C19,C20,C25,C26,C28,C
29,C32,C40,C41,C42,C4
3,C46,C48,C60,C62
15
100NF-
0402SMT
RLP-130-A
—
CL05B104KA5NNNC
Samsung
CAP CER 0.1UF 25V
10% X7R 0402
10
C21,C22,C23,C24,C27,C
30,C44,C47,C50,C51,C5
2,C53,C54,C55,C56,C57,
C58,C59,C61
19
100NF-
0201SMT
C0201
—
C0603X5R1C104K030
BC
TDK
CAP CER 0.1UF 16V
10% X5R 0201
11
C31,C63,C94,C95,C97,C
100,C104,C106,C108,C1
11
10
1UF-16V-
0805SMT
RLP-133
—
CL21B105KOFNNNG
Samsung
CAP CER 1UF 16V
X7R 0805
12
C33
1
0.1uF
cc0402
—
CL05B104KA5NNNC
Samsung
CAP CER 0.1UF 25V
10% X7R 0402
13
C34
1
0.1uF
cc0402
—
CL05B104KA5NNNC
Samsung
CAP CER 0.1UF 25V
10% X7R 0402
14
C35
1
10NF-0402SMT
RLP-130-A
—
CL05B103KA5NNNC
Samsung
CAP CER 10000PF
25V X7R 0402
15
C36
1
100NFX5R-
0402SMT
RLP-130-A
—
CL05A104MP5NNNC
Samsung
CAP CER 0.1UF 10V
X5R 0402
16
C37,C38,C39
3
20pF-0603SMT
RLP-132
DNL
—
—
—
17
C45,C49
2
1UF-0402SMT
RLP-130-A
—
GRM152R60J105ME
15D
Murata
CAP CER 1UF 6.3V
X5R 0402
18
C65,C68,C69,C73,C76,C
77,C81,C85,C89
9
10uF
C0603
—
LMK107BJ106MALTD
Taiyo Yuden
CAP CER 10UF 10V
X5R 20% 0603
ECP5™ Evaluation Board
User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
44 FPGA-EB-02017-1.0
Item
Reference
Qty
Part
PCB
Footprint
Comments
Part Number
Manufacturer
Description
19
C66,C67,C70,C71,C72,C
74,C75,C78,C79,C80,C8
2,C83,C84,C86,C87,C90,
C91,C92
18
0.1uF
C0201
—
C0603X5R1C104K030
BC
TDK
CAP CER 0.1UF 16V
10% X5R 0201
20
C96,C98
2
10uF-6.3V-
0805SMT
RLP-133
—
CL21A106KPFNNNE
Samsung
CAP CER 10UF 10V
X5R 0805
21
C101,C102
2
10NFX5R-
0402SMT
RLP-130-A
—
GRM155R61C103KA0
1D
Murata
CAP CER 10000PF
16V X5R 0402
22
C109,C125
2
10uF,25V-
1206SMT
RLP-134
—
TMK316B7106KL-TD
Taiyo Yuden
CAP CER 10UF 25V
X7R 1206
23
C112,C113,C126,C127
4
220NF-
0402SMT
RLP-130-A
—
CL05A224KO5NNNC
Samsung
CAP CER 0.22UF 16V
X5R 0402
24
C114,C115,C128,C129
4
1000pF-
0402SMT
RLP-130-A
—
CL05B102KB5NFNC
Samsung
CAP CER 1000PF 50V
X7R 0402
25
C116,C119,C130,C133
4
330pF-
0402SMT
RLP-130-A
—
CL05B331KB5NNNC
Samsung
CAP CER 330PF 50V
X7R 0402
26
C117,C118,C134,C137
4
10pF-0402SMT
RLP-130-A
—
CL05C100CB5NNNC
Samsung
CAP CER 10PF 50V
C0G/NP0 0402
27
C120,C121,C122,C123,C
124,C135,C136,C138,C1
39,C140
10
22uF,6.3V-
0805SMT
RLP-133
—
CL21A226MQQNNNE
Samsung
CAP CER 22UF 6.3V
X5R 0805
28
C131,C132
2
10pF-0402SMT
RLP-130-A
DNL
—
—
—
29
C143,C145,C146
3
1UF-16V-
0805SMT
RLP-130-A
—
CL21B105KOFNNNG
Samsung
CAP CER 1UF 16V
X7R 0805
30
C144
1
1UF-10V-
0201SMT
C0201
—
GRM033R61A105ME
15D
Murata
CAP CER 1UF 10V
X5R 0201
31
C147,C148,C149,C150,C
151,C152,C153
7
22uF-6.3V-
0805SMT
RLP-133
—
CL21A226MQQNNNE
Samsung
CAP CER 22UF 6.3V
X5R 0805
32
D1,D4,D5,D6,D7,D8,D9,
D10,D11,D12,D22,D23,
D24,D25,D31
15
LED_GREEN_0
603
APT1608
—
150060GS75000
Wurth
LED GREEN CLEAR
0603 SMD
33
D2
1
ESDR0502N-
UDFN6
UDFN6_04
0
—
ESDR0502NMUTBG
ON semi
TVS DIODE 5.5VWM
6UDFN
34
D3
1
LED_RED_0603
APT1608
—
150060RS75000
Wurth
LED RED CLEAR 0603
SMD
35
D13
1
SCHOTTKY/VIS
HAY-V12P10
V12P10
—
V12P10-M3/86A
Vishay
DIODE SCHOTTKY
100V 12A TO277A
36
D14,D15,D18,D19
4
1N4448W
1N4448W
—
1N4448WS
On Semi
DIODE GEN PURP
75V 150MA SOD323F
37
D16,D17,D20,D21
4
DFLS220L
DFLS220L
—
DFLS220L-7
Diodes
Incorporated
DIODE SCHOTTKY
20V 2A POWERDI123
38
D26
1
LED_BLUE_060
3
APT1608
—
150060BS75000
Wurth
LED BLUE CLEAR
0603 SMD
39
FB2,FB3,FB4,FB5,FB6,FB
7,FB8
7
BLM31KN121S
N1L
BLM41P
—
BLM31KN121SN1L
Murata
FERRITE BEAD 120
OHM IMPEDANCE
ECP5™ Evaluation Board
User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02017-1.0 45
Item
Reference
Qty
Part
PCB
Footprint
Comments
Part Number
Manufacturer
Description
40
F1
1
F1251CT-ND
154010
—
0154010.DR
Littelfuse Inc.
FUSE BRD MNT 10A
125VAC/VDC SMD
41
JP1,JP2,JP3,JP4,JP5,JP6,J
P7,JP9,JP18
9
JUMPER
Header_1x
2
—
61300211121
Wurth
CONN HEADER 2 POS
2.54
42
JP8
1
Receptacle
20X2
HDR254-
2X20_sock
et
—
PPTC202LFBN-RC
Sullins
CONN HEADER FEM
40POS .1" DL TIN
43
JP10,JP11
2
HEADER_5PIN
HEADER_5
—
61300511121
Wurth
CONN HEADER 5 POS
2.54
44
J1
1
Header 1x8
hdr_amp_
87220_8_
1x8_100
DNL
22284081
Molex
CONN HEADER 8POS
.100 VERT TIN
45
J2
1
USB_MINI_AB
usb2-0-
rec-240-
0001-9
—
651305142821
Wurth
CONN RCPT USB
MINI AB R/A SMT
46
J3,J7
2
Header 1x8
CONF1X8-
254P_210
4X240X85
0H_TH
—
61300811121
Wurth
CONN HEADER 8 POS
2.54
47
J4
1
Header 1x6
CONF1X6-
254P_159
6X240X85
0H_TH
—
61300611121
Wurth
CONN HEADER 6 POS
2.54
48
J5
1
Header_2x11
Header_2x
11
DNL
61302221121
Wurth
CONN HEADER VERT
DUAL 22POS 2.54
49
J6
1
Header 1x10
CONF1X10
-
254P_261
2X240X85
0H_TH
—
61301011121
Wurth
CONN HEADER
10POS PIN 2.54MM
50
J8
1
Header_2x4
Header_2x
4
DNL
61300821121
Wurth
CONN HEADER VERT
DUAL 8POS 2.54
51
J9,J10,J11,J12,J13,J14,J1
5,J16,J17,J18,J19,J20,J2
1,J22,J23,J24,J25,J26
18
SMA
73391-
0060
DNL
73391-0060
Molex
CONN SMA RCPT STR
50 OHM PCB
52
J29
1
2x5 HEADER
61301021
121
DNL
61301021121
Wurth
CONN HEADER
10POS DL PIN
2.54MM
53
J30
1
2x5 HEADER
61301021
121
—
61301021121
Wurth
CONN HEADER
10POS DL PIN
2.54MM
54
J31
1
PMOD 2x6
skt_sullins
_pppc062
_2x6_100
DNL
PPPC062LFBN-RC
Sullins
CONN HEADER FMAL
12PS.1" DL GOLD
55
J32
1
Header2x20
hdr_samte
c_mtsw_2
x20_100
DNL
61304021121
Wurth
CONN HEADER VERT
40POS 2.54
56
J33
1
Header_2x16
Header_2x
16
DNL
61303221121
Wurth
CONN HEADER VERT
DUAL 32POS 2.54
57
J37
1
PJ-002A
pj_002a_3
p
—
694106301002
Wurth
CONN PWR JACK
2X5.5MM SOLDER
58
J38
1
Header_2x10
Header_2x
10
DNL
61302021121
Wurth
CONN HEADER VERT
DUAL 20POS 2.54
59
J39,J40
2
HDR40
HDR-20x2
—
61304021121
Wurth
CONN HEADER VERT
40POS 2.54
ECP5™ Evaluation Board
User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
46 FPGA-EB-02017-1.0
Item
Reference
Qty
Part
PCB
Footprint
Comments
Part Number
Manufacturer
Description
60
L1,L2,L3,L8
4
600ohm
500mA
fb0603
—
BLM18AG601SN1D
Murata
FERRITE CHIP 600
OHM 500MA 0603
61
L4,L5,L6,L7
4
4.7uH-SPD62R-
472M
SPD62R
—
SPD62R-472M
API Delevan
Inc.
FIXED IND 4.7UH 2A
150 MOHM SMD
62
Q1,Q2,Q3,Q4
4
2N2222/SOT23
MMBT222
2ALT-1
—
MMBT2222ALT1G
ON
Semiconductor
TRANS NPN 40V 0.6A
SOT23
63
RN1
1
EXB-2HV102JV
EXB-2HV
—
EXB-2HV102JV
Panasonic
RES ARRAY 8 RES 1K
OHM 1506
64
RN2
1
EXB2HV472JV
EXB-2HV
—
EXB2HV472JV
Panasonic
RES ARRAY 8 RES
4.7K OHM 1506
65
R1,R2,R3
3
4.7K
R0603
—
RC0603FR-074K7L
yageo
RES 4.70K OHM
1/10W 1% 0603 SMD
66
R4,R6
2
0
R0402
—
RC0402FR-070RL
yageo
RES SMD 0 OHM
JUMPER 1/16W 0402
67
R5,R12
2
2.2K
R0603
—
RC0603FR-072K2L
yageo
RES SMD 2.2K OHM
1% 1/10W 0603
68
R7,R8,R9,R11,R22,R23,R
24
7
0
R0603
—
RC0603FR-070RL
yageo
RES SMD 0 OHM
JUMPER 1/10W 0603
69
R10
1
100K
R0603
—
RC0603FR-07100KL
yageo
RES SMD 100K OHM
1% 1/10W 0603
70
R13,R14,R15
3
10K
R0603
—
RC0603FR-0710KL
Yageo
RES SMD 10K OHM
1% 1/10W 0603
71
R16,R20
2
12K
R0603
—
RC0603FR-0712KL
yageo
RES SMD 12K OHM
1/10W 1% 0603
72
R17,R18,R19,R94,R95,R
135
6
2_2K-0603SMT
RLP-101
—
RC0603FR-072K2L
yageo
RES SMD 2.2K OHM
1% 1/10W 0603
73
R21
1
0R-0603SMT-
DNI
RLP-101
DNL
—
—
—
74
R25,R26,R27,R34,R35
5
0
R0603
DNL
RC0603FR-070RL
yageo
RES SMD 0 OHM
JUMPER 1/10W 0603
75
R28,R29,R30,R31,R56,R
57,R58,R59,R61,R62,R6
3,R64,R65,R66,R67,R68,
R69,R70,R71,R72
20
100
cr0201
DNL
RC0201JR-07100RL
Yageo
RES SMD 100 OHM
5% 1/20W 0201
76
R32,R33,R38,R39,R40,R
41
6
0
R0603
DNL
RC0603JR-070RL
Yageo
RES 0.0 OHM 1/10W
JUMP 0603 SMD
77
R44,R89,R90,R91,R92,R
93
6
10K-0402SMT
RLP-100
—
RC0402FR-0710KL
Yageo
RES SMD 10K OHM
1% 1/16W 0402
78
R45,R46
2
10
R0603
—
RC0603FR-0710RL
yageo
RES SMD 10 OHM 1%
1/10W 0603
79
R60
1
22
R0603
—
RC0603FR-0722RL
yageo
RES SMD 22 OHM 1%
1/10W 0603
80
R49,R51
2
0R-0603SMT
RLP-101
—
RC0603FR-070RL
yageo
RES SMD 0 OHM
JUMPER 1/10W 0603
81
R50
1
0R-0603SMT-
DNI
RLP-101
DNL
—
—
—
82
R52
1
2.2K-DNI
R0603
DNL
RC0603FR-072K2L
yageo
RES SMD 2.2K OHM
1% 1/10W 0603
83
R53,R54
2
100K-DNI
R0603
DNL
RC0603FR-07100KL
yageo
RES SMD 100K OHM
1% 1/10W 0603
84
R55
1
0
cr0603
—
RC0603FR-070RL
yageo
RES SMD 0 OHM
JUMPER 1/10W 0603
85
R73,R74,R75,R80,R81,R
83
6
4_7K-0603SMT
RLP-101
—
RC0603FR-074K7L
yageo
RES 4.70K OHM
1/10W 1% 0603 SMD
ECP5™ Evaluation Board
User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02017-1.0 47
Item
Reference
Qty
Part
PCB
Footprint
Comments
Part Number
Manufacturer
Description
86
R76,R77,R78,R82
4
1K-0603SMT
RLP-101
—
RC0603FR-071KL
yageo
RES SMD 1K OHM
1/10W 1% 0603
87
R79
1
50R-0603SMT
RLP-101
—
RC0603FR-0749R9L
yageo
RES SMD 49.9 OHM
1% 1/10W 0603
88
R85,R86,R87,R88
4
0R-0402SMT
RLP-100
—
RC0402FR-070RL
yageo
RES SMD 0 OHM
JUMPER 1/16W 0402
89
R94
1
2_2K-0603SMT
RLP-101
—
RC0603FR-072K2L
yageo
RES SMD 2.2K OHM
1% 1/10W 0603
90
R95,R135
2
2_2K-0603SMT
RLP-101
—
RC0603FR-072K2L
yageo
RES SMD 2.2K OHM
1% 1/10W 0603
91
R96,R120,R133
3
10K-0603SMT
RLP-101
—
RC0603FR-0710KL
Yageo
RES SMD 10K OHM
1% 1/10W 0603
92
R97,R98,R99,R100,R101
5
0
R0603
—
RC0603JR-070RL
Yageo
RES SMD 0 OHM
JUMPER 1/10W 0603
93
R102,R103,R104,R105,R
106,R107,R108
7
0
R0603
DNL
RC0603JR-070RL
Yageo
RES SMD 0 OHM
JUMPER 1/10W 0603
94
R109
1
0.01
cr2512_alt
1
—
PE2512FKE7W0R01L
Yageo
RES 0.01 OHM 1%
2W 2512
95
R110,R115,R117,R126,R
127
5
0.1
cr2010_alt
1
—
WSL2010R1000FEA
Vishay Dale
RES 0.1 OHM 1%
1/2W 2010
96
R111,R113
2
1K
R0603
—
RC0603FR-071KL
yageo
RES SMD 1K OHM
1/10W 1% 0603
97
R112,R114
2
121K-0603SMT
RLP-101
—
RC0603FR-07121KL
yageo
RES SMD 121K OHM
1% 1/10W 0603
98
R116,R121,R123,R125
4
51K-0402SMT
RLP-100
—
RC0402FR-0751KL
yageo
RES SMD 51K OHM
1% 1/16W 0402
99
R118
1
21_5K-
0603SMT
RLP-101
—
RC0603FR-0721K5L
yageo
RES SMD 21.5K OHM
1% 1/10W 0603
100
R119
1
10_7K-
0603SMT
RLP-101
—
RC0603FR-0710K7L
yageo
RES SMD 10.7K OHM
1% 1/10W 0603
101
R122
1
34K-0402SMT
RLP-100
—
RC0402FR-0734KL
yageo
RES SMD 34K OHM
1% 1/16W 0402
102
R124
1
3_4K-0603SMT
RLP-101
—
RC0603FR-073K4L
yageo
RES SMD 3.4K OHM
1% 1/10W 0603
103
R128
1
5_11K-
0603SMT
RLP-101
—
RC0603FR-075K11L
yageo
RES SMD 5.11K OHM
1% 1/10W 0603
104
R129
1
15K-0603SMT
RLP-101
—
RC0603FR-0715KL
yageo
RES SMD 15K OHM
1% 1/10W 0603
105
R130
1
30_1K-
0402SMT
RLP-100
—
ERJ-2RKF3012X
Panasonic
RES SMD 30.1K OHM
1% 1/10W 0402
106
R131
1
63_4K-
0402SMT
RLP-100
—
ERJ-2RKF6342X
Panasonic
RES SMD 63.4K OHM
1% 1/10W 0402
107
R132
1
20K-0402SMT
RLP-100
—
ERJ-2RKF2002X
Panasonic
RES SMD 20K OHM
1% 1/10W 0402
108
R134
1
16_9K-
0603SMT
RLP-101
—
RC0603FR-0716K9L
yageo
RES SMD 16.9K OHM
1% 1/10W 0603
109
R136,R137,R139
3
24K-1206SMT
RLP-103
-
RC1206JR-0724KL
Panasonic
RES SMD 24K OHM
5% 1/4W 1206
110
R138,R140,R141
3
4.7K-0603SMT
RLP-101
—
RC0603FR-074K7L
yageo
RES SMD 4.7K OHM
1% 1/10W 0603
111
R142
1
1_8K-1206SMT
RLP-103
-
RC1206JR-071K8L
Yageo
RES SMD 1.8K OHM
5% 1/4W 1206
112
R179
1
470R-0603SMT
RLP-101
-
RC0603FR-07470RL
yageo
RES SMD 470 OHM
1% 1/10W 0603
113
R180
1
100
R0402
—
ERJ-2RKF1000X
Panasonic
RES SMD 100 OHM
1% 1/10W 0402
114
SW1
1
SW DIP-4
41812127
0804
—
418121270804
Wurth
SWITCH SLIDE DIP
SPST 25MA 24V
ECP5™ Evaluation Board
User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
48 FPGA-EB-02017-1.0
Item
Reference
Qty
Part
PCB
Footprint
Comments
Part Number
Manufacturer
Description
115
SW2,SW3,SW4
3
430182043816
sw_sp_st_
ck_pts645
_sm
—
430182043816
Wurth
SWITCH TACTILE
SPST-NO 0.05A 12V
116
SW5
1
TDA DIP-8
TDA08H0S
B1
—
416131160808
Wurth
SWITCH SLIDE DIP
SPST 25MA 24V
117
TP1,TP2,TP24,TP25,TP2
6,TP27,TP28,TP29,TP30,
TP31,TP32,TP33,TP34,T
P35,TP36,TP37,TP38,TP
39,TP40,TP55,TP56,TP5
7
22
TP_S_40_63
TP
DNL
—
—
Square test point,
40mil inner
diameter, 63mil
outer diameter
118
TP3,TP4,TP5,TP6,TP7,TP
8,TP9,TP10,TP11,TP12,T
P13,TP14,TP15,TP16,TP
17,TP18,TP19,TP20,TP2
1,TP22,TP23,TP41,TP42,
TP43,TP44,TP45,TP46,T
P47,TP48,TP49,TP50,TP
51,TP52,TP53,TP54
35
TestPoint
TP50
DNL
—
—
—
119
U1
1
FT2232HL
tqfp64_0p
5_12p2x1
2p2_h1p6
—
FT2232HL-REEL
FTDI
IC USB HS DUAL
UART/FIFO 64-LQFP
120
U2
1
93LC56C-I/SN
so8_50_24
4
—
93LC56C-I/SN
Microchip
Technology
IC EEPROM 2KBIT
3MHZ 8SOIC
121
U3
1
LFE5G-85F-
BG381
LFE5G-
85F-BG381
—
LFE5UM5G-85F-
8BG381
Lattice
83.6K LUTS, 205 /O,
1.1V, -8 SPE
122
U4
1
MX25L12833F
MI-10G
SO16W
—
MX25L12833FMI-
10G
Macronix
International
IC FLASH 128MBIT
133MHZ 16SOIC
123
U5,U6
2
LT3085
msop8_26
_198_ep
—
LT3085IMS8E#PBF
Linear
Technology/An
alog Devices
IC REG LIN POS ADJ
500MA 8MSOP
124
U7,U8
2
LT3508EUF
LT3508EU
F
—
LT3508EUF#PBF
Linear
Technology/An
alog Devices
IC REG BUCK ADJ
1.4A DL 24QFN
125
X1
1
7M-
12.000MAAJ
xtal_4p_7
m
—
7M-12.000MAAJ-T
TXC
CRYSTAL 12MHZ
18PF SMD
126
X2
1
200_00MHz_L
VDS
DSC1123A
E2
—
DSC1123AE2-
200.0000
Microchip
Technology
OSC MEMS
200.000MHZ LVDS
SMD
127
X5
1
LFSPXO01998
osc_4p_cb
3lv
DNL
LFSPXO019987Reel
IQD
OSC XO 50.000MHZ
HCMOS TTL SMD
128
Shorting-Jumper
4
Shorting-
Jumper
—
—
929957-08
3M
SHORTING JUMPERS
GOLD PLATED GRY
129
ECP5 EVALUATION
BOARD REV A PCB
1
—
—
—
305-PD-18-0078
PACTRON
—
ECP5™ Evaluation Board
User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02017-1.0 49
Revision History
Revision 1.0, July 2018
Initial release.
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