UT54ACS190/UT54ACTS190 Radiation-Hardened Synchronous 4-Bit Up-Down BCD Counters FEATURES PINOUTS Single down/up count control line Look-ahead circuitry enhances speed of cascaded counters Fully synchronous in count modes Asynchronously presettable with load control radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 16-pin DIP - 16-lead flatpack 16-Pin DIP Top View The outputs of the four flip-flops are triggered on a low-to-highlevel transition of the clock input if the enable input (CTEN) is low. A logic one applied to CTEN inhibits counting. The direction of the count is determined by the level of the down/up (D/U) input. When D/U is low, the counter counts up and when D/U is high, it counts down. The counters feature a fully independent clock circuit. Changes at control inputs (CTEN and D/U) that will modify the operating mode have no effect on the contents of the counter until clocking occurs. The counters are fully programmable. The outputs may be preset to either logic level by placing a low on the load input and entering the desired data at the data inputs. The output will change to agree with the data inputs independently of the level of the clock input. The asynchronous load allows counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. If preset to an illegal state, the counter returns to a normal sequence in one or two counts. 125 1 16 VDD QB 2 15 A QA 3 14 CLK CTEN D/U 4 5 13 12 RCO MAX/MIN QC QD 6 7 11 10 LOAD C VSS 8 9 D 16-Lead Flatpack Top View DESCRIPTION The UT54ACS190 and the UT54ACTS190 are synchronous 4bit reversible up-down BCD decade counters. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed. Synchronous operation eliminates the output counting spikes associated with asynchronous counters. B B 1 16 VDD QB 2 15 A QA 3 14 CLK CTEN D/U 4 5 13 12 RCO MAX/MIN QC 6 11 LOAD QD VSS 7 8 10 9 C D Two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum (MAX/MIN) count. The MAX/MIN output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock while the count is zero (all outputs low) counting down or maximum (9) counting up. The ripple clock output (RCO) produces a low-level output pulse under those same conditions but only while the clock input is low. The counters easily cascade by feeding the RCO to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. Use the MAX/MIN count output to accomplish look-ahead for highspeed operation. The devices are characterized over full military temperature range of -55 C to +125 C. RadHard MSI Logic UT54ACS190/UT54ACTS190 FUNCTION TABLE LOGIC SYMBOL Function LOAD CTEN D/U Count up H L L Count down H L H Asynchronous L X CLK CTRDIV 10 G M2 (DOWN) (4) CTEN D/U X CLK H X (13) G4 (11) No change (12) MAX/MIN RCO LOAD (15) 5D (1) B C (1) 7 (2) (6) (9) QA Q (4) Q (8) QD Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. LOGIC DIAGRAM (14) CLK (13) (5) D/U RCO (12) MAX/MIN (15) A CTEN B (4) J S Q (3) Q A C K Q R (1) J S Q (2) Q B C KR Q C (10) J S Q (6) Q C C K Q R D (9) J S Q (7) Q D C K Q R LOAD RadHard MSI Logic (11) 126 UT54ACS190/UT54ACTS190 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS 127 SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic UT54ACS190/UT54ACTS190 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; V SS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100 A Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 2.2 mW/MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic 128 UT54ACS190/UT54ACTS190 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 129 RadHard MSI Logic UT54ACS190/UT54ACTS190 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; V SS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH LOAD to Qn 2 19 ns tPHL LOAD to Qn 2 22 ns tPLH Data In to Qn 2 19 ns tPHL Data In to Qn 2 21 ns tPLH CLK to Qn 2 18 ns tPHL CLK to Qn 2 20 ns tPLH CLK to RCO 2 16 ns tPHL CLK to RCO 2 16 ns tPLH CLK to MAX/MIN 2 18 ns tPHL CLK to MAX/MIN 2 23 ns tPLH D/U to RCO 2 16 ns tPHL D/U to RCO 2 18 ns tPLH D/U to MAX/MIN 1 14 ns tPHL D/U to MAX/MIN 2 18 ns tPLH CTEN to RCO 2 12 ns tPHL CTEN to RCO 2 16 ns fMAX Maximum clock frequency 71 MHz tSU1 CTEN, D/U Setup time before CLK 13 ns tSU2 LOAD Setup time before CLK 2 ns tSU3 A, B, C, D setup time before LOAD 7 ns tH1 CTEN and D/U hold time after CLK 2 ns tH23 A, B, C, D hold time after LOAD 2 ns Minimum pulse width CLK high CLK low LOAD low 7 ns tW Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). 3. Based on characterization, hold time (t H2) of 0ns can be assumed if data setup time (tSU3) is >10ns. This is guaranteed, but not tested. RadHard MSI Logic 130