THC7984-17 - CEL - Datasheet.Directory

THC7984_Rev.2.0_E

1 / 45 THine Electronics, Inc.

THC7984

10-bit 3-channel Video Signal Digitizer

General Description

The THC7984 integrates all the functions to digitize

analog video signals on a single chip.

Acceptable Signals

PC Graphics (RGB) : VGA-UXGA

- Separate Sync

- Composite Sync

- Sync on Green

Component Video (YPbPr) :

- SDTV (480i / 480p) 2-level Sync

- HDTV (1080i / 720p / 1080p) 3-level Sync

- Protection Signal

Applications

LCD TV / PDP TV

Rear-Projection TV

LCD Display / PDP Display

Front Projector etc.

Features

170 MSPS 10-bit ADC

- Internal 14-bit ADCs

- Oversampling functions (2x, 4x, and 8x)

Line-locked PLL with low jitter

- Phase adjustment: 64 steps

Fine clamp / preamp

- Pedestal / center clamp

- Clamp level auto adjust

- Very low gain mismatch

- Gain adjustment: 2048 steps

Video Filter (LPF)

- Bandwidth adjustment: 28 steps (6MHz - 310MHz)

Sync Processor

- 2-level / 3-level sync slicer

- Advanced sync detection / measurement

- Automatic sync processing mode

- IRQ Output

2-wire serial interface

LQFP 80-pin package

PGA

Clamp ADC 10-bit

Auto Clamp

Level Adjust

PGA

Clamp ADC

Output

Formatter

10-bit RED0-9

GREEN0-9

BLUE0-9

HSYNC0

VSYNC0

Serial I/F

Control

SOGOUT

O/E FIELD

DATACK

SCL

SDA

SYNC

Processing

RAIN0

GAIN0

BAIN0

SOGIN0 SOG

Slicer

HSOUT

2:1

Switch

Auto Clamp

Level Adjust

PGA

Clamp ADC 10-bit

Auto Clamp

Level Adjust

FILT

Clock

Generation

Block Diagram

CLAMP

EXTCLK/COAST

VSOUT/A0

Voltage

Reference

REFHI

REFCM

REFLO

RST

2:1

RAIN1

GAIN1

BAIN1

Decimation

Filter

LPF

Switch

SOGIN1

VSYNC1

HSYNC1

THC7984_Rev.2.0_E

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Specifications

VD=1.8V, VDD=3.3V, PVD=1.8V, DAVDD=1.8V, ADC Clock=Maximum Conversion Rate, Full Temperature Range=0° C to 70° C

Analog Input Voltage=0.5 to 1.0Vpp

Min Typ Max

Number of Bits 10 Bits

LSB Size 0.098 %FS

25° C I ± 0.75 ± 1 LSB

Full VI -1.0/+1.25 LSB

25°C I ±1.5 ±3 LSB

Full VI ±4 LSB

No Missing Code 25° C I Guaranteed

Minimum Input Voltage Full VI 0.5 V p-p

Maximum Input Voltage Full VI 1.0 V p-p

Gain Tempco 25° C V 100 ppm/° C

25° C IV 1 µA

Full IV 1 µA

Input O ffset Voltage Full VI ± 1 LSB

Input Full-Scale Matching

Between Channels Full VI 0.2 0.8 %

Offset Adjustment Range Full VI 50 %FS

Maximum Conversion Rate Full VI 170 MSPS

Minimum Conversion Rate Full IV 10 MSPS

Data Setu

Time to Clock *2 Full IV 0.48Tpixel-2.1 ns

Data Hold Time to Clock *2 Full IV 0.48Tpixel-0.4 ns

Dut

cle, DATACK *2 Full IV 40 50 60 %

HSYNC Input Frequency Full IV 15 110 kHz

Maximum PLL Clock Rate Full VI 170 MHz

Minimum PLL Clock Rate Full IV 10 MHz

PLL Jitter *3 25° C V 500 ps p-p

Sampling Phase Tempco Full IV 15 ps/° C

SCL Clock Frequency ( fSCL ) Full IV 100 kHz

tBUFF Full IV 4.7 µs

tSTAH Full IV 4.0 µs

tDHO Full IV 0 3.45 µs

tDAL Full IV 4.7 µs

tDAH Full IV 4.0 µs

tDSU Full IV 250 ns

tSTASU Full IV 4.7 µs

tSTOSU Full IV 4.0 µs

Tr Full IV 1000 ns

Tf Full IV 150 ns

Capacitive Load ( Cb ) Full IV 400 pF

Noise m argin at the LOW level ( VnL ) Full IV 0.2 V

Noise m argin at the HIGH level ( VnH ) Full IV 0.25 V

Input Voltage, High (VIH) Full VI 1.4 V

Input Voltage, Low (VIL) Full VI 0.8 V

Input Current, High (IIH) Full V 10 µA

Input Current, Low (IIL) Full V 10 µA

Input Capacitance 25° C V 2 pF

Output Voltage, High (VOH) Full VI VDD-0.2 V

Output Voltage, Low (VO L) Full VI 0.2 V

Output Coding Binary

VD Supply Voltage Full IV 1.7 1.8 1.9 V

VDD Supply Voltage Full IV 2.3 3.3 3.45 V

PVD Supply Voltage Full IV 1.7 1.8 1.9 V

DAVDD Supply Voltage Full IV 1.7 1.8 1.9 V

ID Supply Current (VD) 25° C V 295 mA

IDD Su

Current (VDD) *4 25° C V 180 mA

IPVD Supply Current (PVD) 25° C V 30 mA

IDAVDD Supply Current (DAVDD) 25°C V 65 mA

Total Power Dissipation Full VI 1350 mW

Power-Down Supply Current Full VI 10 20 mA

Power-Down Dissipation Full VI 20 40 mW

Operating Ambient Temperature IV 0 70 °C

θ JC Junction-to-Case

Thermal Resistance 25° C V 4 ° C/W

θJA Junction-to-Ambient

Thermal Resistance 25° C V 37 ° C/W

*1 Input Bias Voltage: 0.05V to VD-0.05V

*2 See "Data/Clock Output Test Condition".

*3 THC7984-17: UXGA@60Hz

*4 Output Load Capacitance per Pin: 15pF

Temp

Integral N onlinearity

2-WIRE SERIAL

INTERFACE

DC ACCURACY Differential Nonlinearity

RESOLUTION

Parameter

THERMAL

CHARACTERISTICS

THC7984-17 Unit

DIGITAL INPUTS

POWER SUPPLY

ANALOG INPUT

Input Bias Current*1

DIGITAL OUTPUTS

SWITCHING

PERFORMANCE

Test

Level

EXPLANATION OF TEST LEVELS

Test Level

I. 100% production tested.

II. 100% production tested at +25°C and sample tested at specified temperatures.

III. Sample tested only.

IV. Parameter is guaranteed by design and characterization testing.

V. Parameter is a typical value only.

VI. 100% production tested at +25°C; guaranteed by design and characterization testing.

THC7984_Rev.2.0_E

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Absolute Maximum Ratings

Pin Configuration

50％

80％

20％

VDD

GND

Data Setup Time

DATA

DATACK

< Data Setup/Hold Time to Clock >

10pF

33ohm

THC7984 Probe

< Data /Clock Output Test Condition >

Output Drive Strength (VDD=3.3V) : Medium

DATACK: Pixel Clock

DATACK Phase: 4

Output Format: Normal (not DDR)

*DATACK output phase is register programmable.

Data Hold Time

Tpixel

Parameter Min Max Unit

VD 2.1 V

VDD 3.8 V

PVD 2.1 V

DAVDD 2.1 V

Analog Inputs -0.2 VD+0.2 or 2.1 *1 V

Digital Inputs -0.3 PVD+3.6 or 5.5

*1 V

Storage Temperature -55 150 °C

Maximum Junction Temperature 125 °C

*1 Smaller Value is adopted.

BAIN0

RAIN0

SOGIN0

GAIN1

SOGIN1

GND

SOGOUT

RAIN1

O/E FIELD

HSOUT

DATACK

VSOUT/A0

RED<9>

GAIN0

VDD

GND

REFCM

BLUE<2>

38 64

BAIN1

GND

RST

REFLO

REFHI

GND

DAVDD

THC7984

Top View

RED<8>

RED<7>

RED<6>

RED<5>

RED<4>

RED<3>

RED<2>

RED<1>

RED<0>

VDD

GND

GREEN<9>

GREEN<8>

GREEN<7>

GREEN<6>

GREEN<5>

GREEN<4>

GREEN<3>

GREEN<2>

GREEN<1>

GREEN<0>

VDD

GND

BLUE<9>

BLUE<8>

BLUE<7>

BLUE<6>

BLUE<5>

BLUE<4>

BLUE<3>

BLUE<1>

BLUE<0>

VDD

GND

SDA

SCL

HSYNC1

VSYNC1

HSYNC0

CLAMP

EXTCLK/COAST

PVD

GND

FILT

PVD

GND

VSYNC0

PVD

GND

THC7984_Rev.2.0_E

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Pin List

Pin Name Type Function

VD P Analog Power Supply

VDD P Output Power Supply

PVD P PLL Power Supply

DAVDD P Digital Core Power Supply

GND P Ground

BAIN0 AI B-ch Analog Input, Port 0

BAIN1 AI B-ch Analog Input, Port 1

GAIN0 AI G-ch Analog Input, Port 0

SOGIN0 AI Sync on Green Input, Port 0

GAIN1 AI G-ch Analog Input, Port 1

SOGIN1 AI Sync on Green Input, Port 1

RAIN0 AI R-ch Analog Input, Port 0

RAIN1 AI R-ch Analog Input, Port 1

RST DI Reset Input

Low: Normal Operation

High: Power Down (Stand-by)

High -> Low: Chip Reset

REFLO - Connection for External Capacitor

REFCM - Connection for External Capacitor

REFHI - Connection for External Capacitor

O/E FIELD DO Field Parity Output for Interlaced Video

Data Enable (DE) Output

Sync Processor IRQ Output

VSOUT/A0 DIO VSYNC Output / Serial Interface Device Address bit 0 (A0)

HSOUT DO HSYNC Output

SOGOUT DO SOG Slicer Output

DATACK DO Data Clock Output

RED<9:0> DO R-ch Data Output

GREEN<9:0> DO G-ch Data Output

BLUE<9:0> DO B-ch Data Output

SCL DI Serial Port Data Clock Input

SDA DIO Serial Port Data I/O

HSYNC1 DI HSYNC Input, Port 1

VSYNC1 DI VSYNC Input, Port 1

HSYNC0 DI HSYNC Input, Port 0

VSYNC0 DI VSYNC Input, Port 0

EXTCLK/COAST DI External Clock Input / Coast Signal Input

CLAMP DI External Clamp Pulse Input

Reference Clock Input for HSYNC Period Measure

FILT - Connection for PLL Loop Filter

P:Power AI:Analog Input DI:Digital Input DO:Digital Output DIO:Digital Input/Output

THC7984_Rev.2.0_E

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Functional Description

Digital Input

- All digital inputs are 5V tolerant during power-on.

Analog Input

- The THC7984 has two ports that each include three analog inputs for RGB or YPbPr . The input port can be selected by

- In case input signals are YPbPr, Y may b e inp ut into GAIN0 (or GAIN1) and SOG IN0 (or SOGIN1) , Pr into RAIN0

(or RAIN1) , and Pb into BAIN0 (or BAIN1) .

- The THC7984 accommodates analog signals ranging from 0.5 Vpp to 1.0 Vpp.

Video Filter (LPF)

The THC7984 has 2 kinds of lo w-pass filters.

- 5th-order LPF for YPbPr, whose bandwidth is adjustable from 6 MHz to 92 MHz in 24 steps.

- 2nd-order LPF for RGB, whose bandwidth is adjustable in 4 steps (40 MHz, 90 MHz, 170 MHz, and 310 MHz) .

Serial Interface

- The THC7984 is controlled by 2-wire serial interface.

- Serial clock SCL supports up to 100 kHz.

Sync Input

- The THC7984 has two ports that each include two digital inputs for the separa te sync (HSYNC and VSYNC) . The

input port can be selected by register.

- The THC7984 can process composite sync (CSYNC) . CSYNC may be input into HSYNC0 or HSYNC1.

Digital Output

- The digital outputs can operate from 2.5 V to 3.3 V (VDD) .

- The output drive strength is programmable by 2-bit registers (except SDA) .

Clamp

- Pedestal clamp for RGB and Y (luminance) clamps black level to 0 with automatic offset cancel.

- Midscale clamp for PbPr clamps to 512 with automatic offset cancel.

- 256-level clamp for Y (luminance) clamps to 256 with automatic offset cancel. It can be used for A/D conversion of Y

including sync signal . In this case, inp ut signal needs to be attenuated to put it within the input rang of A/D converter.

- Clamp pulses can be input from CLAMP pin when external clamp is selected.

Gain, Offset

- Gain is programmable by 11-bit registers (2048 steps) .

- Offset from -256 to +255 can be added to the output code.

- Gain and offset can be adjusted independently.

Reference Voltage

- The THC7984 has Band Gap Reference inside and doesn’t require external voltage reference.

- The internal reference voltages (REFHI, REFCM, and REFLO) must be bypassed to stabilize. Each pin (REFHI,

REFCM, and REFLO) is connected to ground through a 10 μF capacitor.

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Sampling Clock Generation

- The THC7984 has PLL to generate the sampling clock from HSYNC. The sampling clock frequency range is from

10MHz to 170 MHz.

- PLL divider ratio (the number of horizontal total pixels per line) can be set to the value between 200 to 8191.

- The sampling clock Phase can be adjusted in 64 steps of T/64.

- The external clock can be used as the sampling clock.

- It is required to set VCO Frequency Range and Charge Pump Current according to the input signal format (resolution) .

Oversampling

- Oversampling is the function that enables sampling analog signals with higher rate than the pixel clock and downsam-

pling to the pixel clock rate with decim a tion filter, which is effective for improving S/ N rati o.

- Oversampling ratio can be selected amon g 1x (normal operat ion) , 2x, 4x, and 8x. Even if any is selected, output fre-

quency of the output clock and data is same as normal operati on.

Output Clock (DATACK)

- The output clock phase can be selected in 8 steps for the data setup/hold adjustment.

- Divide-by-2 clock can be selected as the output clock for the dual edge data clocking at the subsequent stage. It can not

be selected when oversampling.

SOG Slicer

- Sync on Green (SOG) is sliced at the threshold level above the sy nc tip t o extract the sync signal. The thresho ld level

can be set by a register ranging from 15 mV to 240 mV in steps of 15mV.

- Low pass filer prior to the slicer can be used to reduce hi gh frequen c y noise, which can be disab led by a regi ster.

- The slicer also has hysteresis (about 30mV ) , wh ich can be disabled by a register.

- 3-level sync signal can be processed by slicing at the pedestal level.

Sync Processor

Sync Processor implement s VSYNC separation from CSYN C, vertical timing generation , and detection and measure-

ment of the sync signals. The various automatic sync-processing modes are realized by utilizing the sync detection and

measurement.

The THC7984 can process the copy protection signal.

(1) VSYNC Separation

Extracting VSYNC from Compo site sy nc (CSYNC) or Sync on Green (SOG) .

(2) Vertical Timing Generation

- VSYNC Output Generation

- PLL COAST Generation

- Clamp COAST Generation

- V-Blank of DE Generation

(3) Sync Detection/Measurement

- Input Sync Type Detection (Separate sync, Composite sync, Sync on Green, and No input signal)

- HSYNC, VSYNC Input Polarity Detection

- 3-level Sync Detection

- Interlace Detection

- Vertical Total Line Measurement

- VSYNC Input Pulse Width Measurement

- HSYNC Period Measurement (Reference clock needs to be input into CLAMP pin.)

- SYNC Change Detection

- HSYNC Edge Detection

- Sync Processor IRQ Output

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(4) Automatic Sync Processing Mode (Manual Setting M odes are also available)

- Auto Output Mode (All outputs are enabled when inpu t si gnal is active)

- Input Port Auto Select (Selects the port whose input signal is active)

- Input Sync Type Auto Select (HSYNC Input, VSYNC Input)

- HSYNC, VSYNC Input Polarity Auto Select

- HSYNC, VSYNC Output Polarity Auto Select

- VSYNC Output Timing Auto Setting

- PLL COAST Timing Auto Setting

Power Control

- The THC7984 can be set to stand-by mode by a register or RST-pin.

- In stand-by mode, most of the analog circuits are powered down for low power dissipation.

- In stand-by mode, the sync detection and measurement are available nonetheless because SOG Slicer, Sync Processor,

and 2-wire serial interface are still power-on.

- The THC7984 is set to stand-by mode when RST- pin is set to High. If unused, RST-pi n must be pull-down to ground

with a resistor.

Reset

- The logic circuit of the chip is reset when power is applied with RST-pin asserted Low (Power-on Reset) .

- The reset can be also triggered by RST-pin (Manual Reset) . The reset is triggered when RST-pin falls from High to

Low, that means the reset is triggered whenever the THC7984 gets out of stand-by mode by RST-pin.

- Reset after power-up is necessary to access the seria l interface. Please power-up with RST-pin asserted Low or make

RST-pin High then Low after power-up. If unused, RST-pin must be pull-down to ground with a resistor.

- The registers are set to the default values by the reset and the chip becomes stand-by mode and out put disable (Hi-Z) .

For normal operation, the registers must be set to power-on and output enable by the serial interface.

- For Manual Reset, keep RST-pin Low more than 20 us after the transition from High to Low.

Device Address

- The LSB of 7-bit device address of serial interface (A0) is obtained from VSOUT/A0-pin at the reset.

Pull-down to ground with a resistor (10 kΩ) , then Device Address is set to 1001100

Pull-up to VDD with a resistor (10 kΩ) , then Device Address is set to 1001101

- The pull-up resistor must be connected to VDD.

RST (Reset Signal) VIH

VIL

Min. 100ns

Min. 20us

* Reset Timing

THC7984_Rev.2.0_E

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Registers

The register is notated with “R” added to the head of the address in hexadecimal. e.g. R00: Regi ster of address 0x00

The bit position is notated with “[]”. e.g. R04[1:0]: Bit 1 and bit 0 of address 0x04

The register value in hexadecimal is notated with “h” added to the end. e.g. R01=18h

The register value in binary is notated with “b” added to the end. e.g. R04[1:0]=11b

The register value in decimal is notated without suffix. e.g. R15[7:0]=32

Default Valu e

All registers are set to the default values by the reset (Power-on Reset, Manual Reset) .

Minus Number Setting

Some registers can be configured by two's complement.

< Register Classification>

Sign Category Description Register

R/W Read/Write Registers for configuration and adjustment except below

R Read Only Registers which report the result of measurement and detection R00, R2C～R30, R32～R34

AAuto

Registers which can be auto-configured

- When auto-configuration is enabled, the registers become Read

Only and the value auto-configured can be read.

- When auto-configuration is disabled, the registers become

Read/Write and the value must be set manually.

R12[3], R12[1:0], R13[5],

R13[4], R13[2], R13[1],

R20[6:0], R21[5:0],

R22[6:0], R23[6:0]

EVRC Event

Recorder

Registers which record the event that has occurred in Sync

Processor.

- 1 is set when the event occurs.

- The value is cleared by writing 1 to the register.

R35

< Minus Number Setting >

Function Register Range

Clamp Level Offset R0C/R0D, R0E/R0F, R10/R11 -256 to +255

HSYNC Output Start Position R14 -128 to +127

VSYNC Output Start Position R20 -64 to +63

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Bit R/W Default

Value Fun ctio n D es cri ption

R 00 7 R 0 Revision Code Can be read 21h

6R 0

5R 1

4R 0

3R 0

2R 0

1R 0

0R 1

R01 7

4 R/W 0 Chip Power-On 0: Power-Down (Stand-by Mode) 1: Power-On (Normal O peration)

3 R/W 0 Auto Output Enable (All outputs become Enable when input sign al is active) 0: Disable 1: Enable

2 R/W 0 Output Enable (Except SOGOUT & IRQ) 0: Disable 1: Enable

1 R/W 0 SOGOUT Output Enable 0: Disable 1: Enable

0 R/W 0 Reserved Must be set to 0 (Default Value)

R02 7

6 R/W 0 Oversampli ng 00b: 1x(Normal Operation) 01b: 2x 10b: 4x 11b: 8x

5R/W 0

4 R/W 0 PLL Divider Ratio Set the number of hori zontal total pixels per line

3R/W 0

2R/W 1

1R/W 1

0R/W 0

R03 7 R/W 1

6R/W 0

5R/W 0

4R/W 1

3R/W 1

2R/W 0

1R/W 0

0R/W 0

R 04 7 R/W 1 Reserved Must be set to 1 (Default Value)

6 R/W 1 VCO Frequen cy Range 00b: 1/8 01b: 1/4 10b: 1/2 11b: 1/1

5R/W 1

4 R/W 1 Charge Pump Current 000b: 50uA 001b: 100u A 010b: 150uA 011b: 250uA

3R/W 0 100b: 350uA 101b: 500uA 110b: 750uA 111b: 1000uA

2R/W 0

1 R/W 0 Sampling Clock Source 00b: Internal Clock 01b: Reserved

0R/W 0 10b: External Clock (10-20MHz) 11b: External Clock (20-17 0MHz)

R05 7

5 R/W 0 Sampling Clock Phase Set in 64 steps of T/64

4R/W 0 *Bi gger values me an more delay.

3R/W 0

2R/W 0

1R/W 0

0R/W 0

R06 7

2 R/W 1 R-ch Gain Gain = (Register Value + 1024) / 2048

1R/W 0 2048 steps from x0.5 to x1.5

0R/W 0 *Bi gger values mean higher gai n.

R07 7 R/W 0

6R/W 0

5R/W 0

4R/W 0

3R/W 0

2R/W 0

1R/W 0

0R/W 0

Address

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R08 7

2 R/W 1 G-ch Gain Gain = (Register Value + 1024) / 2048

1R/W 0 2048 steps from x0.5 to x1.5

0R/W 0 *Bi gger values mean higher gai n.

R09 7 R/W 0

6R/W 0

5R/W 0

4R/W 0

3R/W 0

2R/W 0

1R/W 0

0R/W 0

R0A 7

2 R/W 1 B-ch Gain Gain = (Register Value + 1024) / 2048

1R/W 0 2048 steps from x0.5 to x1.5

0R/W 0 *Bi gger values mean higher gai n.

R0B 7 R/W 0

6R/W 0

5R/W 0

4R/W 0

3R/W 0

2R/W 0

1R/W 0

0R/W 0

R0C 7

0 R/W 0 R-ch Clamp Level Offset 1 LSB of offset corresponds to 1 LSB of output code.

R0D 7 R/W 0 -256 to +255

6R/W 0 *Set in two's complement.

5R/W 0

4R/W 0

3R/W 0

2R/W 0

1R/W 0

0R/W 0

R0E 7

0 R/W 0 G-ch Clamp Level Offse t 1 LSB of offset corresponds to 1 LSB of output code.

R0F 7 R/W 0 -256 to +255

6R/W 0 *Set in two's complement.

5R/W 0

4R/W 0

3R/W 0

2R/W 0

1R/W 0

0R/W 0

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R10 7

0 R/W 0 B-ch Clamp Level Offset 1 LSB of offset corresponds to 1 LSB of output code.

R11 7 R/W 0 -256 to +255

6R/W 0 *Set in two's complement.

5R/W 0

4R/W 0

3R/W 0

2R/W 0

1R/W 0

0R/W 0

R 12 7 R/W 0 Reserved Must be set to 0

6 R/W 0 Reserved Must be set to 0

5 R/W 1 Input Port Automatic Selection Enable 0: Disable 1: Enable

4 R/W 0 Reserved Must be set to 0

3 A 0 Input Port 0: Port-0 1: Port-1

2 R/W 1 Sync Type Automatic Select Enable 0: Disable 1: Enable

1 A 0 Sync Type Select 00b: Separate Sync 01b: Composite Sync

0A 0 10b: Sync on Video (2-lelvel) 11b: Sync on Video (3-lelvel)

R13 7

6 R/W 1 HSYNC Input, VSYNC Input Polarity Automatic Selection Enable 0: Disable 1: Enable

5 A 0 HSYNC Input Polarity 0: Active-Low 1: Active-High

4 A 0 VSYNC Input Polarity 0: Active-Low 1: Active-High

3 R/W 1 HSYNC Output, VSYNC Output Polarity Automatic Selection Enable 0: Disable 1: Enable (Output Polarity is conformed to Input Polarity)

2 A 0 HSYNC Output (HSOUT) Polarity 0: Active-Low 1: Active-High

1 A 0 VSYNC Output (VSOUT) Polarity 0: Active-Low 1: Active-High

0 R/W 1 VSYNC Output (VSOUT) Interlace Mode 0: Disable 1: Enable

R 14 7 R/W 0 HSYNC Output (HO) Start Position Set in 1 pixel steps with reference to the leading edge of HSYNC input

6R/W 0 -128 to +127

5R/W 0 *Set in two's complement.

4R/W 0

3R/W 0

2R/W 0

1R/W 0

0R/W 0

R 15 7 R/W 0 HSYNC Output (HO) Pulse Width Set in 1 pixel steps

6R/W 0 1 to 255

5R/W 1

4R/W 0

3R/W 0

2R/W 0

1R/W 0

0R/W 0

R16 7

4 R/W 0 PLL COAST Source 0: Internal PLL COAST 1: External PLL COAST

3 R/W 1 PLL/Clamp COAST Input Polarity (If COAST Source is External) 0: Active-Low 1: Active-High

2 R/W 0 Clamp Pulse Source 0: Internal Clamp Pulse 1: External Clamp Pulse

1 R/W 1 Clamp Pulse Input Polarity (If COAST Source is External) 0: Active-Low 1: Active-High

0 R/W 0 Clamp COAST Source 0: Internal Clamp COAST 1: External Clamp COAST

R17 7

6 R/W 1 Clamp Pulse Start Reference Edge (Pedestal Clamp, Midscale Clamp) 0: the leading edge of HSYNC Input 1: the trailing edge of HSYNC Input

5 R/W 0 R-ch Clamp Mode 00b: Pedestal Clamp 01b: Midscale Clamp

4R/W 0 10b: Reserved 11b: 256-level clamp

3 R/W 0 G-ch Clamp Mode 00b: Pedestal Clamp 01b: Midscale Clamp

2R/W 0 10b: Reserved 11b: 256-level clamp

1 R/W 0 B-ch Clamp Mode 00b: Pedestal Clamp 01b: Midscale Clamp

0R/W 0 10b: Reserved 11b: 256-level clamp

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12 / 45 THine Electronics, Inc.

R 18 7 R/W 0 Clamp Pulse Start Position Set in 1 pixel steps with the reference edge of HSYNC Input (R17[6]).

6R/W 0 0 to 255

5R/W 0

4R/W 0

3R/W 1

2R/W 0

1R/W 0

0R/W 0

R 19 7 R/W 0 Clamp Pulse Width Set in 1 pixel steps

6R/W 0 1 to 255

5R/W 0

4R/W 1

3R/W 0

2R/W 0

1R/W 0

0R/W 0

R1A 7 R/W

6 R/W 1 SOG Slicer Hysterisis Enable 0: Disable 1: Enable

5 R/W 1 SOG Input Filter 00b: Disable 01b: Enable

4R/W 0 10b, 11b: Reserved

3 R/W 0 SOG Slicer threshold Set in 15mV steps

2R/W 1 15mV to 240mV above the Sync Tip

1R/W 0

0R/W 0

R 1B 7 R/W 0 SOGOUT Output Polarity 0: Active-Low 1: Active-High

6 R/W 0 SOGOUT Output Signal 00b: Raw HSYNC 01b: Regenerated HSYNC

5R/W 0 10b: Filtered HSYNC 11b: Reserved

4 R/W 1 Preamp Bandwidth (Low Pass Filter)

3R/W 1

2R/W 0

1R/W 1

0R/W 0

R 1C 7 R/W 0 Output Format 00b: 4: 4: 4 Output 01b: 4: 4: 4 DDR Output

6R/W 0 10b: 4: 2: 2 Output 11b: 4: 2: 2 DDR Output

5 R/W 1 4:2:2 Decimation Filter Enable 0: Disable 1: Enable

4 R/W 0 Output Clock (DATACK) 00b: Pixel Clock 01b: 1/2x Pixel Clock

3R/W 0 10b: Internal Oscillator (40MHz) 11b: Reserved

2 R/W 1 Output Clock Phase Set in T/8 steps

1R/W 0 0 to 7/8T

0R/W 0 *Bigger values mean more delay.

R 1D 7 R/W 1 Reserved Must be set to 0

6 R/W 0 Reserved Must be set to 1

5 R/W 0 RGB DATA Output Drive Strength 00b: Weak 01b: Medium 10b: Strong 11b: Very Strong

4R/W 1

3 R/W 0 Sync (SOGOUT/HSOUT/VSOUT/OEFIELD) Output Drive Strength 00b: Weak 01b: Medium 10b: Str ong 11b: Very Strong

2R/W 1

1 R/W 0 Clock Output Drive Strength 00b: Weak 01b: Medium 10b: Strong 11b: Very Strong

0R/W 1

R 1E 7 R/W 0 HSOUT Output Signal 00b: HO 01b: Regenerated HSYNC 10b: Raw HSYNC 11b: Filtered HSYNC

6R/W 0

5 R/W 0 VSOUT Output Signal 00b: VO 01b: Regenerated VSYNC 10b: Raw VSYNC 11b: Filtered VSYNC

4R/W 1

3 R/W 0 O/E FIELD Output Signal 000b: FO 001b: Regenerated FIELD 010b: DE 011b: IRQ

2R/W 0 100b to 111b: Reserved

1R/W 1

0 R/W 0 O/E FIELD Output Polarity 0: Odd Field＝Low/Even Field=High 1: Odd Field＝High/Even Field=Low

R1F 7

6 R/W 0 Reserved Must be set to 0

5 R/W 0 Reserved Must be set to 0

4 R/W 1 PLL HSYNC Filter Enable 0: Disable (Raw HSYNC) 1: Enable (Filtered HSYNC)

3 R/W 0 HSYNC Filter Window Width Set in +/-100ns steps

2R/W 0 +/-100ns to +/-1600ns

1R/W 1 *Bigger values mean wider window.

0R/W 1

THC7984_Rev.2.0_E

13 / 45 THine Electronics, Inc.

R 20 7 R/W 1 VSYNC Output Timing Automatic Setting Enable (Except Raw VSYNC) 0: Disable 1: Enable

6 A 0 VSYNC Output (VO, Regenerated VSYNC) Start Position Set in 1 line steps

5A 0 -64 t o +63

4A 0 *Set in two's complement.

3A 0 *VSYNC Output Start Position with reference to the leading edge of VSYNC Input.

2A 0

1A 0

0A 0

R21 7

5 A 0 VSYNC Output (VO, Regenerated VSYNC) Pulse Width Set in 1 lin e steps

4A 0 1 to 63

3A 0

2A 0

1A 0

0A 0

R 22 7 R/W 1 PLL COAST Timing Automatic Setting Enable 0: Disable 1: Enable

6 A 0 PLL Pre-Coast (PLL COAST Start Position) Set in 1 line steps

5 A 0 *PLL free-r uns during PLL COAST 0 to 127

4A 0 *PLL COAST Start Position prior to the leading edge of VSYNC Input.

3A 0

2A 0

1A 0

0A 0

R23 7

6 A 0 PLL Post-Coast (PLL COAST End Position) Set in 1 line steps

5 A 0 *PLL free-r uns during PLL COAST 0 to 127

4A 0 *PLL COAST End Position after the leading edge of VSYNC Input.

3A 0

2A 0

1A 0

0A 1

R24 7

6 R/W 0 Clamp Pre-Coast (Clamp COAST Start Position) Set in 1 line steps

5 R/W 0 *Clamp stops during Clamp COAST 0 to 127

4R/W 0 *Clamp COAST Start Position prior to the lea ding edge of VSYNC Input.

3R/W 0

2R/W 1

1R/W 1

0R/W 0

R25 7

6 R/W 0 Clamp Post-Coast (Clamp COAST End Position) Set in 1 line steps

5 R/W 0 *Clamp stops during Clamp COAST 0 to 127

4R/W 1 *Clamp COAST End Position after the leading edge of VSYNC Input.

3R/W 0

2R/W 1

1R/W 0

0R/W 0

R26 7

3 R/W 0 DE Start Position Set in 1 pixel steps

2R/W 0 *DE Start Position after the leading edge of HSYNC Input.

1R/W 0

0R/W 1

R27 7 R/W 0

6R/W 1

5R/W 1

4R/W 1

3R/W 0

2R/W 0

1R/W 0

0R/W 0

THC7984_Rev.2.0_E

14 / 45 THine Electronics, Inc.

R28 7

3 R/W 0 DE Width Set in 1 pixel steps

2R/W 1

1R/W 0

0R/W 1

R29 7 R/W 0

6R/W 0

5R/W 0

4R/W 0

3R/W 0

2R/W 0

1R/W 0

0R/W 0

R2A 7

6 R/W 0 V-Blank Front Porch (DE Low Start Position) Set in 1 line steps

5R/W 0 0 to 127

4R/W 0 *V-Blank Start Position prior to the leading edge of VSYNC Output.

3R/W 0

2R/W 0

1R/W 0

0R/W 1

R2B 7

6 R/W 0 V-Blank Back Porch (DE Low Start Position) Set in 1 line steps

5R/W 1 0 to 127

4R/W 0 *V-Blank End Position after the trailing edge of VSYNC Output.

3R/W 0

2R/W 1

1R/W 1

0R/W 0

R2C 7 R 1 Reserved

6R 1

5R 1Reserved

4R 1

3 R 1 Port-1 Input Sync Type Detection 00b: Separate Sync 01b: Composite Sync

2R 1 10b: Sync on Video 11b: No Signal

1 R 1 Port-0 Input Sync Type Detection 00b: Separate Sync 01b: Composite Sync

0R 1 10b: Sync on Video 11b: No Signal

R2D 7

2 R 0 VSYNC Input Polarity Detection 0: Active-Low 1: Active-High

1 R 0 HSYNC Input Polarity Detection 0: Active-Low 1: Active-High

0 R 0 Sync on Video 2-level/3-level Detection 0: 2-level 1: 3-level

R 2E 7 R 0 Interlace Detection 0: Progressive 1: Interlace

6 R 0 Vertica l Total Line Measurement Reports the number of vertical total lines

5R 0 on the active input counted in 1/4 line unit.

4R 0

3R 0

2R 0

1R 0

0R 0

R2F 7 R 0

6R 0

5R 0

4R 0

3R 0

2R 0

1R 0

0R 0

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15 / 45 THine Electronics, Inc.

R 30 7 R 0 VSYNC Input Pulse Width Measurement Reports the number of VSYNC Pulse Width

6R 0 on the active input counted in 1/4 line unit.

5R 0

4R 0

3R 0

2R 0

1R 0

0R 0

R31 7

2 R/W 0 Reserved Must be set to 0

1 R/W 0 Reference Clock Enable from Clamp-pin for HSYNC Period Measurement 0: Disable 1: Enable

0 R/W 1 HSYNC Period Measurement Run (Must be stop before reading the result) 0: Stop 1: Run

R32 7

3 R 0 HSYNC Period Measurement Result

2R 0

1R 0

0R 0

R33 7 R 0

6R 0

5R 0

4R 0

3R 0

2R 0

1R 0

0R 0

R34 7 R 0

6R 0

5R 0

4R 0

3R 0

2R 0

1R 0

0R 0

R 35 7 EVRC 0 Sync Signal Valid Flag 0: Detect 1: Not Detect

6EVRC 0 Reserved

5EVRC 0 Reserved

4 EVRC 0 Port-1 Input Sync Type Change Detection 0: Detect 1: Not Detect

3 EVRC 0 Port-0 Input Sync Type Change Detection 0: Detect 1: Not Detect

2EVRC 0 In

ut Si

nal Format Chan

e Detection 0: Detect 1: Not Detec

1 EVRC 0 Input HSYNC Missing Edge Detection 0: Detect 1: Not Detect

0 EVRC 0 Input HSYNC Ext raneous Edge Detection 0: Detect 1: Not Detect

R 36 7 R/W 0 Sync Processor IRQ Output Enable by Event Recorder (R34[7]) 0: Disable 1: Enable

6 R/W 0 Reserved

5 R/W 0 Reserved

4 R/W 0 Sync Processor IRQ Output Enable by Event Recorder (R34[4])0: Disable 1: Enable

2 R/W 0 Sync Processor IRQ Output Enable by Event Recorder (R34[3])0: Disable 1: Enable

2 R/W 0 Sync Processor IRQ Output Enable by Event Recorder (R34[2])0: Disable 1: Enable

1 R/W 0 Sync Processor IRQ Output Enable by Event Recorder (R34[1])0: Disable 1: Enable

0 R/W 0 Sync Processor IRQ Output Enable by Event Recorder (R34[0])0: Disable 1: Enable

R 37 7 R/W 0 Input Signal Format Change Detection 000b: 0.5lines 001 b: 1line 010b: 2lines 011b: 4lines

6 R/W 0 - Threshold of Vertical Total Line Change 100b: 8lines 101b: 16lines 110b: 32lines 111b: Do not watching

5R/W 0

4 R/W 0 Input Signal Format Change Detection 00b: 0.5lines 01b: 1line 10b: 4lines 11b: Do not watching

2 R/W 0 - Threshold of VSYNC Input Pulse Width

2 R/W 0 Input Signal Format Change Detection 000b: 8 001b: 16 010b: 32 011b: 64

1 R/W 0 - Threshold of HSYNC Period 100b: 128 101b: 256 110b: 512 111b: Do not watching

0R/W 0

THC7984_Rev.2.0_E

16 / 45 THine Electronics, Inc.

Sync Signal Flow

< Sync Processing Block Diagram >

MUX HSYNC

Filter

POL MUX

PLL

MUX

SOG

Slicer

Sync

Processor

DEMUX

Internal

Oscillator

MUX

DEMUX POL

MUX

POL

MUX POL

POL

MUX

Internal Clamp Pulse

External Clamp Pulse

Clamp Pulse

External COAST

Internal PLL COAST

Internal Clamp COAST

Clamp COAST

PLL COAST

External Clock

External REFCLK FO

Regenerated FIELD

IRQ

Regenerated VSYNC

Raw VSYNC

Regenerated HSYNC

Raw HSYNC

Filtered HSYNC

Regenerated HSYNC

Internal Oscillator Clock

PLL COAST

External Clock

HSYNC0

HSYNC1

VSYNC0

VSYNC1

SOGIN1

SOGIN0

CLAMP

EXTCLK/COAST

DATACK

SOGOUT

HSOUT

VSOUT

O/E FIELD

2-level Sliced SOGIN0

2-level Sliced SOGIN1

3-level Sliced SOGIN

Pixel Clock

1/2 x Pixel Clock

POL

MUX

CSYNC

R12[3]+R12[1:0]

R13[5]

R1F[4] R1C[4:3]

R1B[6:5]

R1B[7]

R12[3]+R12[1:0]

R13[4]

R1E[7:6]

R1E[5:4]

R1E[3:1]

R13[2]

R13[1]

R1E[0]

R31[1]

R16[1]

R16[2]

R04[1:0] R16[3]

R16[4]

R16[0]

MUX

POL

DEMUX

Polarity Select

Multiplexer

Demultiplexer

MUX

POL

Filtered VSYNC

MUX

Raw HSYNC

Filtered HSYNC

THC7984_Rev.2.0_E

17 / 45 THine Electronics, Inc.

R00 Revision Code 21h can be read

R01[4] Chip Power-On

1: all the circuits power-on for normal operation.

0: the chip is set to stand-by mode. In stand-by mode, several circuits are active for sync monitoring.

Stan-by mode can be triggered by RST-pin.

* During the stand-by mode, all the output pins except SOGOUT and SDA are disable (Hi-Z) .

R01[3] Auto Output Enable

1: all the output pins are automatically enabled regardless of “Output Enable except SOGOUT (R01[2]) ” or “SOGOUT

Output Enable (R01[1]) ” while input sync is detected. Input sync detection is processed in Sync Processor.

* Output Pins are RED<9:0>, GREEN<9:0>, BLUE<9:0>, DATACK, SOGOUT, HSOUT, VSOUT, and O/E FIELD

R01[2] Outpu t Enable (Except SOGOUT)

1: Output pins except SOGOUT-pin are enabled.

R01[1] SOGOUT Output Enable

1: SOGOUT-pin is enabled.

* When disabled, output pins are Hi-Z.

* SDA-pin is always enabled.

R01[0] Reserved * Must be set to 0 (Default Value: 0)

< Power Control >

R01[4] RST-pin Status ADC/PLL Serial

Interface

SOG

Slicer

Sync

Processor

1 Low Normal Operation Power-On Power-On Power-On Power-On

1 High Stand-by Power-Down Power-On Power-On Power-On

0 Low Stand-by Power-Down Power-On Power-On Power-On

0 High Stand-by Power-Down Power-On Power-On Power-On

< Output Control >

R01[3] R01[2] R01[1] Input

Signal

Output Signal

except

SOGOUT

0 0 0 Inactive Disable Disable

000Active Disable Disable

0 0 1 Inactive Disable Enable

0 0 1 Active Disable Enable

0 1 0 Inactive Enable Disable

0 1 0 Active Enable Disable

0 1 1 Inactive Enable Enable

0 1 1 Active Enable Enable

1 0 0 Inactive Disable Disable

1 0 0 Active Enable Enable

1 0 1 Inactive Disable Enable

1 0 1 Active Enable Enable

1 1 0 Inactive Enable Disable

1 1 0 Active Enable Enable

1 1 1 Inactive Enable Enable

1 1 1 Active Enable Enable

THC7984_Rev.2.0_E

18 / 45 THine Electronics, Inc.

R02[6:5] Oversampling

Oversampling is the function th at enables sampling analog signals with higher rate than the pixel clock and

downsampling to the pixel clock rate with the decimation filter.

When setting it as oversampling, setting of the PLL Divider Ratio (R02 [4:0] /R03 [7:0]) and the Charge Pump Current

(R04 [4:2]) is unnecessary, but it's necessary to change the VCO frequency range (R04 [6:5]) .

Every time the oversampling setting is increased one step, VCO frequency range also must be increased one step.

00b: Normal operation

01b: 2x Oversampling

10b: 4x Oversampling

11b: 8x Oversampling

(ex) In case of 480i (HSYNC Frequency: 15.75kHz / Pixel Clock: 13.51MHz)

Oversampling(R02[6:5]) VCO Range(R04[6:5]) Charge Pump(R04[4:2])

1x(00b) 1/8(00b) 250uA(011b)

2x(01b) 1/4(01b) 250uA(011b)

4x(10b) 1/2(10b) 250uA(011b)

8x(11b) 1/1(11b) 250uA(011b)

* Under the output of 4:4:4 DDR (R1C[7:6]=01b ) or 4:2:2 DDR (R1C[7:6]=11b), the oversampling function can't be

used.

* “Internal PLL Divider Ratio” can’t be over 8191.

“Internal PLL Divider Ratio” = PLL Divider Ratio setting * Oversampli ng setting

* Sampling frequency can’t be over 170MHz

Sampling frequency = Input HSYNC frequency * PLL Divider Ratio * Oversampli ng setting

* Even if oversampling setting is changed, the output clock frequency and the output data rate don't change.

* The latency of the data output changes according to the oversampling setting.

R02[4:0]/R03[7:0] PLL Divider Ratio

The internal PLL generates sampling clock from HSYNC.

Set the number of horizontal total pixels per line according to the input signal.

*When the external clock input which is supplied through EXTCLK/COAST-pin is used as sampling clock

(R04[1:0]=10b or 11b), PLL Divider Ratio setti ng is unnecessary.

R04[7] Reserved *Must be set to 1 (Default value: 1)

R04[6:5] VCO Frequency Range *Set according to “Recommended PLL Settings”

R04[4:2] Charge Pump Current *Set according to “Recommended PLL Settings”

THC7984_Rev.2.0_E

19 / 45 THine Electronics, Inc.

R04[1:0] Sampling Clock Source

Set to 00b, when the internal PLL generates sampling clock (pixel clock) from the HSYNC input.

When an external clock input supplied th rough EXTCLK/COAST-pin is used and the clock frequency is from 10 to

20MHz, set to 10b.

When an external clock input supplied th rough EXTCLK/COAST-pin is used and the clock frequency is from 20 to

170MHz, set to 11b.

* Even though the external clock is used as samp ling clock(R04[1:0]=10b or 11b) , setting like a Recommended PLL

Settings are necessary.

* When the external clock is used as sampling clock(R04[1:0]=10b or 11b) , PLL COAST and Clamp COAST can not be

input (R16[4]=1, R16[0]=1) .

* Other than the settings above, please refer to the other document, “THC7984 PLL Setting Sheet”.

R05[5:0] Sampling Clock Phase

The sampling clock phase can be shifted in 64 steps of T/64. Bigger values mean more delay.

* Even the external clock is used as sampling clock(R04[1:0]=10b or 11b) , the clock phase can be shifted.

R06[2:0]/R07[7:0] R-ch (Pr-ch) Gain

R08[2:0]/R09[7:0] G-ch (Y-ch) Gain

R0A[2:0]/R0B[7:0] B-ch (Pb-ch) Gain

The gain can be adjusted from 0.5 to 1.5 in 2048 steps. Bigger value means higher gain.

Gain = (Register Value + 1024) / 2048

Because the full scale of ADC input is 0.7 Vpp (Typical Value) , the gain is set to [0.7 / Video Signal Level*].

* Signal Level without Sync on Video (Vpp)

Example.

Video Signal Level: 0.5 Vpp Gain = 0.7/0.5 =1.4 Register val ue=1843

Video Signal Level: 0.7 Vpp Gain = 0.7/0.7 =1.0 Register value=10 24

Video Signal Level: 1.0 Vpp Gain = 0.7/1.0 =0.7 Register value=410

* The setting method above is not always necessary for the purpose of contrast adjustment. Bigger gain means higher

contrast.

< Recommended PLL Settings >

R04[6:5] R04[4:2] R04[1:0] R04 R04[6:5] R04[4:2] R04[1:0] R04

480i 15.750 13.51 858 00 011 00 8C 00 000 10 82

480p 31.469 27.00 858 01 011 00 AC 01 000 11 A3

720p 45.000 74.25 1650 10 101 00 D4 10 000 11 C3

1080i 33.750 74.25 2200 10 100 00 D0 10 000 11 C3

1080p 67.500 148.50 2200 11 101 00 F4 11 000 11 E3

VGA-60 31.479 25.18 800 01 011 00 AC 01 000 11 A3

VGA-72 37.861 31.50 832 01 100 00 B0 01 000 11 A3

VGA-75 37.500 31.50 840 01 100 00 B0 01 000 11 A3

VGA-85 43.269 36.00 832 01 101 00 B4 01 000 11 A3

SVGA-56 35.156 36.00 1024 01 100 00 B0 01 000 11 A3

SVGA-60 37.879 40.00 1056 01 101 00 B4 01 000 11 A3

SVGA-72 48.077 50.00 1040 10 100 00 D0 10 000 11 C3

SVGA-75 46.875 49.50 1056 10 100 00 D0 10 000 11 C3

SVGA-85 53.674 56.25 1048 10 100 00 D0 10 000 11 C3

XGA-60 48.363 65.00 1344 10 100 00 D0 10 000 11 C3

XGA-70 56.476 75.00 1328 10 101 00 D4 10 000 11 C3

XGA-75 60.023 78.75 1312 10 101 00 D4 10 000 11 C3

XGA-80 64.000 85.50 1336 11 011 00 EC 11 000 11 E3

XGA-85 68.677 94.50 1376 11 100 00 F0 11 000 11 E3

SXGA-60 63.981 108.00 1688 11 100 00 F0 11 000 11 E3

SXGA-75 79.976 135.00 1688 11 101 00 F4 11 000 11 E3

SXGA-85 91.146 157.50 1728 11 101 00 F4 11 000 11 E3

UXGA-60 75.000 162.00 2160 11 101 00 F4 11 000 11 E3

Sampling Clock: Internal Sampling Clock: External

Hsync

[kHz]

Pixel

Rate

PLL

Divider

THC7984_Rev.2.0_E

20 / 45 THine Electronics, Inc.

R0C[0]/R0D[7:0] R-ch (P r-ch) Clamp Level Offset

R0E[0]/R0F[7:0] G-ch (Y-ch) Clamp Level Offset

R10[0]/R11[7:0] B-ch (Pb-ch) Clamp Level Offset

Clamping restores DC level of the video signals. Three clamp modes can be selected; Pedestal clamp, Center clamp

(Midscale clamp) , and Sync tip clamp (R17[5:4]/R17[3:2 ]/R17[1:0]) .

It's possible to give an offset to the clamp level by the 1LSB unit by a clamp level offset. The register value is configured

by two's complement from -256 to +255.

R12[7:6] Reserved *Must be set to 00b (Default value: 00b)

R12[5] Input Port Auto matic Selection Enable

1: Selection input port (R12[3 ]) is done automatically.

Under Automatic setting, wi th the judgement result of the input SYNC type by Sync Processor, An activated port is

selected with the following rules.

-When the selected port is activated, even if the other port becomes activated, selection of port doesn't change.

-Both ports are activate and one port which is selected became inactivate, selection of port changes to the other port.

Clamp Level Offset = 0

Output Code

< Clamp Level Offset >

Clamp Level Offset

Clamp Level Offs et > 0 Clamp Level Offset < 0

1023

(Pedestal Clamp)

Clamp Level Offset = 0

Output Code

Clamp Level Offset

Clamp Level Offs et > 0 Clamp Level Offset < 0

1023

(Center Clamp) 512

Clamp Level Offset = 0

Output Code

Clamp Level Offset

Clamp Level Offset > 0 Clamp Level Offset < 0

1023

(256-level Clamp)

256

THC7984_Rev.2.0_E

21 / 45 THine Electronics, Inc.

R12[4] Reserved * Must be set to 0 (Default Value: 0)

R12[3] Input Port Select

0: Port-0 is selected.

Port-0: HSYNC0, VSYNC0, RAIN0, GAIN0, SOGIN0, BAIN0

1: Port-1 is selected.

Port-1: HSYNC1, VSYNC1, RAIN1, GA IN1, SOGIN1, BAIN1

R12[2] Input Sync Type Automatic Select Enable

1: Input Sync Type Select (R12[1:0]) is automa tical ly set.

When Automatic Select is enabled, Input Sync Type Select is determined by sync processor based on the result of Input

Sync Type Detection(R2C[6:5]/R2C[4:3]/R2C[0]) .

R12[1:0] Input Sync Type Select

Select the input sync type .

The combination of Input Port Select (R12[3]) and Input Sync Type Select (R12[1:0]) determines the input pin for

HSYNC and VSYNC.

*3-level sliced (pedestal slice) .

R13[6] HSYNC Input, VSYNC Input Polarity Automatic Select Enable

1: HSYNC Input Polarity (R13[5] ) and VSYNC Input Polarity (R13[4]) are automatical ly set.

When Automatic Select is enabled, the sync input p olarity is determined by sync processor based on the result of

HSYNC Input Polarity Detection (R2C[1]) and VSYNC Input Polarity Detection (R2C[2]) .

R13[5] HSYNC Input Polarity

HSYNC Input Polarity must be correctly set for normal operation.

Set to 0 when the input polarity is Active-Low.

Set to 1 when the input polarity is Active-High.

* Set to 0 when Input Sync Type Select is set to “Sync on Video (3-level) ” (R12[1:0]=11b) .

R13[4] VSYNC Input Polarity

VSYNC Input Polarity must be correctly set for normal operation.

Set to 0 when the input polarity is Active-Low.

Set to 1 when the input polarity is Active-High.

< Input Port / Sync Type >

R12[3] Input Port R12[1:0] Sync Type HSYNC

Input Pin

VSYNC

Input Pin

0 Port-0 00b Separate Sync HSYNC0 VSYNC0

0 Port-0 01b Composite Sync HSYNC0 HSYNC0

0Port-010b

Sync on Video

(2-level) SOGIN0 SOGIN0

0Port-011b

Sync on Video

(3-level) SOGIN0* SOGIN0*

1 Port-1 00b Separate Sync HSYNC1 VSYNC1

1 Port-1 01b Composite Sync HSYNC1 HSYNC1

1Port-110b

Sync on Video

(2-level) SOGIN1 SOGIN1

1Port-111b

Sync on Video

(3-level) SOGIN1* SOGIN1*

THC7984_Rev.2.0_E

22 / 45 THine Electronics, Inc.

R13[3] HSYNC Output, VSYNC Output Polarity Automatic Select Enable

1: HSYNC Output Polarity (R13[2]) and VSYNC Out put Polarity (R13[1]) are automatically set to the same polarity

as the input.

When Automatic Select is enabled, the sync output polarity is determined by sync processor based on the result of

HSYNC Input Polarity Detection (R2D[1]) and VSYNC Input Polarity Detection (R2D[2]) .

R13[2] HSYNC Output (HSOUT) Polarity

Select the HSYNC output polarity of HSOUT-pin.

0: Output polarity is Active-Low.

1: Output polarity is Active-High.

* The polarity of HSYNC available from HSOUT-pin (HO, Regenerated HSYNC) is selected.

R13[1] VSYNC Output (VSOUT) Polarity

Select the VSYNC output polarity of VSOUT-pin.

0: Output polarity is Active-Low.

1: Output polarity is Active-High.

* The polarity of VSYNC availa ble from VSOUT-pin (VO, Regenerated VSYNC, Raw VSYNC) is selected.

R13[0] VSYNC Output (VSOUT) Interlace Mode

Select the output mode of VSYNC available from VSOUT-pin (VO, Regenerated VSYNC) for interlaced video input.

1: VSYNC Output (VO, Regenerated VSYNC) is produced at the center of horizontal period when video field of

interlaced video changes from ODD field to EVEN field.

0: VSYNC Output is produced only at the start position of horizontal period. Consequently, the vertical total line number

of interlaced video changes by 1 depending on video field.

* The output mode of VSYNC available from VSOUT-pin (VO, Regenerated VSYNC) is selected. Raw VSYNC is not

affected by this mode.

* The edge of VSYNC Output always occurs at the start position of horizontal period for non-interlaced video

(Detection result: R2E[7]=0) . Therefore, R13[0]=0 and R13[0]=1 produce the same result for non-interlaced video.

Input Sync

VSOUT (R13[0]=1)

VSOUT (R13[0]=0)

Horizontal Cycle

Input Sync

VSOUT (R13[0]=1)

VSOUT (R13[0]=0)

EVEN Field -> ODD Field

ODD Field -> EVEN Field

< VSOUT Interlace Mode >

Horizontal Cycle

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23 / 45 THine Electronics, Inc.

R14[7:0] HSYNC Output (HO) Start Position

Set the start position of HO available from HSOUT-pin in steps of 1 pixel with reference to the leading edge of the

HSYNC (It is the leading edge of the positive pulse when it is 3-level sync) . The register value is configured by two's

complement from -128 to +127.

* When the external clock input is used (R04[1:0]=10b or 11b) , minus number is prohibited.

R15[7:0] HSYNC Output (HO) Pulse Width

Set the pulse width of HO available from HSOUT-pin in steps of 1 pixel.

R16[4] PLL COAST Source

PLL should stop synchronization with the HSY NC inp ut during the vertical blank time inclu ding the pulses disturbing

PLL lock and the sampling clock generation such as equalization pulses and copy protection signal. PLL COAST signal

causes PLL to stop synchronization with the HSYNC input and free-run.

0: PLL COAST signal is internally generated in the device.

1: PLL COAST signal can be externally input from COAST-pin.

* When PLL COAST signal is internally generated, automatic setting mode (R22[7]) is available.

R16[3] PLL COAST Input Polarity

Select the input polarit y of PLL COAST signal when externally input (R16[4]=1) .

Set to 0 when the input polarity is Active-Low (PLL free-runs at C OAST-pin=Low) .

Set to 1 when the input polarity is Active-High (PL L free-runs at COAST-pin= High) .

R16[2] Clamp Pulse Source

Select the generation source of clamp pulse which is a timing signal of a clamp

0: The clamp pulse is generated internally.

1: Clamp pulse must be inputted thro ugh Clamp-pin.

R16[1] Clamp Pul s e Input Polarity

Select input polarit y when the external clamp pulse is used (R16[2]=1).

0: Input polarity becomes Active-Low.

1: Input polarity becomes Active-High.

Input HSYNC

HO (Start Position < 0)

HO (Start Position > 0)

Start Position

Pulse Width

< HO Start Position / Pulse Width >

Input HSYNC

HO (Start Position < 0)

HO (Start Position > 0)

Start Position

Pulse Width

HSYNC / CSYNC / Sync on Video (2-level)

Sync on Video (3-level)

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24 / 45 THine Electronics, Inc.

R16[0] Clamp COAST Source

It's sometimes necessary to make the clamp suspend while the period which is including the signals that disturb the

clamp such as a copy protection signal. The clamp COAST signal is the sign al which makes the clamp stop.

0: Internal Clamp COAST

1: External Clamp COAST

R17[6] Clamp Pulse Start Reference Edge

The timing of Clamp pulse is set based on the edge of the HSYNC input. Selecting the edge of the HSYNC input

0: the leading edge of the HSYNC input is referred.

1: the trailing edge of the HSYNC input is referred.

* In case of 3-level sync, the leading edge or trailing edge of the positive pulse is referred.

R17[5:4] R-ch (Pr-ch) Clamp Mode

R17[3:2] G-ch (Y-ch) Clamp Mode

R17[1:0] B-ch (Pb-ch) Clamp Mode

As a clamp method, pedestal clamp, midscale clamp, and 256-level clamp can be selected.

00b: Pedestal clamp for RGB and Y (luminance) clamps black level to 0 with automatic of fset cancel (if clamp level of f-

set is set to 0) . The Automatic offset cancel circuitry eliminates any offset errors.

01b: Midscale clamp for PbPr clamps to 512 with automatic offset cancel (if clamp level offset is set to 0) . The

Automatic offset cancel circuitry eliminates any offset errors.

10b: Reserved

11b: 256-level clamp clamps to 256 with automatic offset cancel (if clamp level offs et is set to 0). The Automatic offset

cancel circuitry eliminates any offset errors.

* It's possible to set a clamp pulse on sync part and realize sync tip clamp by a pedestal clamp (R17 [5:4], R17 [3:2] and

R17 [1:0] =00b) .

R18[7:0] Clamp Pulse Start Position

Set the clamp pulse start position in steps of 1 pixel with reference to clamp pulse start reference edge (selected by

R17[6]) .

R19[7:0] Clamp Pulse Width

Set the clamp pulse width in steps of 1 pixel.

* When the register is set to 0, clamp pulse is not generated.

* Set the end position of clamp pulse (R18[7:0] + R19[7:0]) more than 16 pixels front of active video period because

Clamp Offset Cancel is completed after 16 pixels from the clamp pulse.

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R1A[6] SOG Slicer Hysterisis Enable

1: SOG Slicer works with about 30mV hysteresi s.

R1A[5:4] SOG Input Filter

SOG Input Filter (low pass filter) can reduce the noise and the ringing, etc. of SOG input.

00b: OFF (Through)

01b: ON

10b,11b: Reserved

*The default value is 10b(Reserved) , so please change the setting to 00b (OFF) or 01b (ON) .

R1A[3:0] SOG Slicer threshold

When Input Sync Type Select is set to “Sync on Vi deo (2-level) ” (R12[1:0]=10b) , input signal from SOGIN0 or

SOGIN1 is sliced at the selected level by R1A[3:0] relative to the lowest leve l (sync tip) to extract the sync signal.

SOG slicer threshold can be adjusted from15 mV to 240 mV in steps of 15 mV.

*Set the value of SOG Slicer threshold to 3 and over.

Input HSYNC

Clamp Pulse (R17[6]=0) Star t Position

Start Position

Pulse Width

< Clamp Pulse Start Position / Pulse Width >

Input HSYNC

Star t Position

Pulse Width

HSYNC / CSYNC / Sync on Video (2-level)

Sync on Video (3-level)

Clamp Pulse (R17[6]=1)

Clamp Pulse (R17[6 ]=0)

Clamp Pulse (R17[6 ]=1)

SOG Slice Level (R1A[3:0])

Sync on Video

Extracted Sync

< SOG Slicer >

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*When setting the input sync signal as Sync on Video (2-level ) at the time of 3-level sync signal input, (R12 [1:0],

=10b) , it is sliced by the SOG slicer threshold.

R1B[7] SOGOUT Output Polarity

Select the output polarity of SOGOUT-pin.

0: Output polarity is Active-Low.

1: Output polarity is Active-High.

* The polarity of signals available from SOGOUT-pin (Raw HSYNC, Regenerated HSYNC, and Filtered HSYNC) is

selected.

R1B[6:5] SOGO UT Output Signal

Select the output signal from SOGOUT-pin. The source signal of th e output is HSYNC selected by the combination of

Input Port Select (R12[3]) and Input Sync Type Select (R12[1:0]) .

00b: Raw HSYNC --- Buffered signal of the HSYNC input.

01b: Regenerated HSYNC --- This HSYNC is generated by using the internal oscillator (about 40 MHz) from Raw

HSYNC. It has jitter of several internal oscillator clock cycles.

10b: Filtered HSYNC --- By the HSYNC Filter, the pulses which are not related to Horizontal period is eliminat ed.

11b: Reserved

Sync on Video (2-Level)

Sync on Video (3-Level)

Sync on Video

Extracted Sync

Sync on Video

Extracted Sync

Sliced at Pedestal Level

Sliced at SOG Slice Level (R1A[3:0])

<2-Level Slice / 3-Level Slice>

Input HSYNC

Raw HSYNC

Regenerated HSYNC

Filtered HSYNC

< Output Signal from SOGO UT>

Horizontal Period

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R1B[4:0] Pre-Amp Bandwidth (Low Pass Filter)

The THC7984 has the internal 5th-order Low Pass Filters as an ti-aliasing filter for component video inp ut (YPbPr) , and

it's possible to control cut-off frequency in 24 steps between 6 to 92MHz by set ting the register.

The THC7984 also has the internal 2 nd-order Low Pass Filters to filter the noise and glitch of PC input (RGB) , and it's

possible to control cut-off frequency in 4 st eps (40 MHz/90 MHz/ 170 MHz/310 MHz) by setting the register.

*Setting example

Component video input: About 0.5 times of the sampling frequency is used as cut-off frequency.

PC input: About 1.5 times of the sampling frequency is used as cutoff frequency.

*When R54[4] is set to 1, it's possible to control the cut-off frequency of a 5th-order lowpass filter

in steps of 1MHz between 25MHzto 39MHz by using regist er R54 [3:0]. In this case, R1B [4:0] is ignored.

< Preamp Bandwidth>

Analog Input Preamp Output (ADC Input)

< Cutoff Frequency >

Dec Dec

0 0 0 0 0 0 6MHz 16 1 0 0 0 0 39MHz

1 0 0 0 0 1 7MHz 17 1 0 0 0 1 42MHz

2 0 0 0 1 0 8MHz 18 1 0 0 1 0 46MHz

3 0 0 0 1 1 9MHz 19 1 0 0 1 1 52MHz

4 0 0 1 0 0 10MHz 20 1 0 1 0 0 58MHz

5 0 0 1 0 1 11MHz 21 1 0 1 0 1 66MHz

6 0 0 1 1 0 12MHz 22 1 0 1 1 0 78MHz

7 0 0 1 1 1 13.5MHz 23 1 0 1 1 1 92MHz

8 0 1 0 0 0 15MHz 24 1 1 0 0 0 40MHz

9 0 1 0 0 1 18MHz 25 1 1 0 0 1 90MHz

10 0 1 0 1 0 21MHz 26 1 1 0 1 0 170MHz

11 0 1 0 1 1 24MHz 27 1 1 0 1 1 310MHz

12 0 1 1 0 0 27MHz 28 1 1 1 0 0

13 0 1 1 0 1 30MHz 29 1 1 1 0 1

14 0 1 1 1 0 33MHz 30 1 1 1 1 0

15 0 1 1 1 1 36MHz 31 1 1 1 1 1

Notefc Note

Reserved

5th-order LPF

for Component Video

5th-order LPF

for Component Video

2nd-order LPF

for PC

Reserved

Binary

R1B[4:0]R1B[4:0] fc

Binary

< Cutoff Frequency >

Dec

0 0000 25MHz

1 0001 26MHz

2 0010 27MHz

3 0011 28MHz

4 0100 29MHz

5 0101 30MHz

6 0110 31MHz

7 0111 32MHz

8 1000 33MHz

9 1001 34MHz

10 1010 34MHz

11 1011 35MHz

12 1100 36MHz

13 1101 37MHz

14 1110 38MHz

15 1111 39MHz

R54[3:0]

Binary fc Note

5th-order LPF

for Component Video

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R1C[7:6] Output Format

4 output formats can be selected.

00b: 4:4:4 Output

01b: 4:4:4 DDR Output

10b: 4:2:2 Output

11b: 4:2:2 DDR Out put

* 4:4:4 DDR Output and 4:2:2 DDR Output are supported up to 85 MHz of sampling clock.

* The pins not assigned to output data are disabled (Hi-Z) .

< 4:4:4 Normal Output >

* DATACK can be shifted in 8 steps (R1C[2:0]) .

< 4:4:4 DDR Output >

* "M" indicates upper 5 bits in MSB side. "L" indicat es lower 5 bits in LSB side.

* DATACK can be shifted in 8 steps (R1C[2:0]) .

Edge987654321098765432109876543210

Normal

↑

↓

Normal

↑

↓

Cb/Cr

4:2:2

Cb/Cr Y

DDR

G[4:0] B[9:0]

R[9:0] G[9:5]

BLUE

Output Format

4:4:4

R[9:0] G[9:0] B[9:0]

DDR

RED GREEN

RED[9:0]

GREEN[9:0]

BLUE[9:0]

DATACK

R0 R1 R2 R3 R4 R5

G0 G1 G2 G3 G4 G5

B0 B1 B2 B3 B4 B5

HO, DE Start Position = Even

HO, DE

HO, DE Start Position = Odd

R1C[4:3]=00b

R1C[2:0]=000b

RED[9:5]

RED[4:0]

GREEN[9:5]

G0L R0M R2M R3M R4M R5M

R1M

B0L

R2L R3L R4L R5LR1L

G1L G2L G3L G4L G5L

G1M G2M G3M G4M G5MB1L B2L B3L B4L B5L

R0L

G0M

B0M B1M B2M B3M B4M B5M

DATACK

HO, DE Start Position = OddHO, DE Start Position = Even

HO, DE

R1C[4:3]=00b

R1C[2:0]=000b

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< 4:2:2 Normal Output >

* DATACK can be shifted in 8 steps (R1C[2:0]) .

< 4:2:2 DDR Output >

* DATACK can be shifted in 8 steps (R1C[2:0]) .

R1C[5] 4:2:2 Decimation Filter Enable

Set the way of downsamplin g (process of changing from 4:4:4 to 4:2:2) of CbCr in 4:2:2 output and 4:2:2 DDR output

0: CbCr is sampled every two pixel by pixel skipping.

1: CbCr is decimated by digital filter.

Cb0 Cr0 Cb2 Cr2 Cb4 Cr4

Y0 Y1 Y2 Y3 Y4 Y5

RED[9:0]

GREEN[9:0]

DATACK

HO, DE

HO, DE Start Position = Even HO, DE Start Position = Odd

R1C[4:3]=00b

R1C[2:0]=000b

Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 Cb4 Y4 Cr4 Y5

BLUE[9:0]

DATACK

HO, DE Start Position = Odd

HO, DE Start Position = Even

HO, DE

R1C[4:3]=00b

R1C[2:0]=000b

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30 / 45 THine Electronics, Inc.

R1C[4:3] Output Clock Select

Select a output signal from DATACK-pin.

00b: Pixel Clock: the same frequency as the sampling clock

01b: 1/2 x Pixel Clock: half the frequency of the sam pling clock

10b: Internal Oscillator (approximately 40 MHz)

11b: Reserved

R1C[2:0] Output Clock Phase

Since the output clock phase can be shifted in 8 steps, the setup and hold time of output data can be adjusted.

* If DATACLK is Pixel Clock(R1C[4:3]=00b) , Phase setteing 0-2 is not recommended to use (except for DDR outpu t)

because rising edge of output clock will be around the transition period of ou tput data.

* The phase of internal oscillator clock (R1C[4:3]=10b) can not be controlled.

* When oversampling setting is 8 times, the output clock pahse is possible to set in only 4 steps. (the value of 0 and 1 , 2

and 3, 4 and 5, 6 and 7 will be the same phase setting.)

HO, DE Start Position =Even

HO, DE Start Position =Odd

Output Data

(Normal Output)

HO, DE

R1C[2:0]=0

R1C[2:0]=1

R1C[2:0]=2

R1C[2:0]=3

R1C[2:0]=4

R1C[2:0]=5

R1C[2:0]=6

R1C[2:0]=7

R1C[2:0]=0

R1C[2:0]=1

R1C[2:0]=2

R1C[2:0]=3

R1C[2:0]=4

R1C[2:0]=5

R1C[2:0]=6

R1C[2:0]=7

DATACK: Pixel Clock

DATACK: 1/2 x Pixel Clock

Output Data

(DDR Output)

< DATACK Phase Shift>

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R1D[7:6] Reserved *Must be set to 01b for proper operation (Default value: 10b)

R1D[5:4] RGB DATA Output Driv e Strength

Output pins: RED<9:0>, GREEN<9:0>, BLUE<9:0>

R1D[3:2] Sync Output Drive Strength

Output pins: SOGOUT, HSOUT, VSOUT, O/E FIELD

R1D[1:0] Clock Output Drive Strength

Output pins: DATACK

Bigger values mean stronger ou tput dri ve strength.

* Output drive strength should be adjusted according to the load capacitance, the trance length on PCB, and the power

supply voltage of output buffer (VDD) .

* Clock output drive strength is stronger than others.

R1E[7:6] HSOUT Output Signal Select

Select a output signal from HSOUT-pin.

00: HO --- HSYNC generated from the HSYNC input, and synchronous with the PLL clock.

Output polarity (R13[2]) , Start Position (R14[7:0]) , and Pulse Width (R15[7:0]) can be selected by the register setting.

PLL parameter settings (R02 to R04) are necessary for normal output.

HO can be used as a reference of the image (RGB data) alignment.

01: Regenerated HSYNC --- HSYNC generated from the HSYNC input, and synchronous with the internal oscillator

clock (approximately 40 MHz) . The start position is delayed some internal oscillator clock cycles after the leading edge

of the HSYNC input, and the pulse width is approximately 1/16 of horizontal period. The polarity is selected by register

(R13[2]) . PLL parameter settings (R02 to R04) are unnecessary for normal output. It has jitter of several internal

oscillator clock cycles.

10b: Raw HSYNC --- Buffered signal of the HSYNC input.

11b: Filtered HSYNC --- The Raw Hsync’s pulse which is not relate to horizontal period is remov ed by the HSYNC

Filter (R1F[3:0].

Input VSYNC

Regenerated HSYNC

< Output Signal from HSOUT>

Horizontal Period

Raw HSYN C

Filtered HSYNC

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R1E[5:4] VSOUT Output Signal Select

Select a output signal from VSOUT-pin.

00b: VO --- VSYNC generated from the HSYNC and VSYNC input, and synchronous with the PLL clock.

Output polarity (R13[1]) , Start Position (R20[6:0]) , and Puls e Width (R21[5:0]) can be select by the register setting

(auto setting modes are available) . PLL parameter settings (R02 to R04) are necessary for normal output. It is

synchronous with HO.

01b: Regenerated VSYNC --- VSYNC generated from the HSYNC and VSYNC input, and synchronous with the

internal oscillator clock (approximately 40 MHz) . Output polarity (R13[1]) , Start Position (R20[6:0]) , and Pulse Width

(R21[5:0]) can be selected by the register setting (auto setting modes are available) . PLL parameter settings (R02 to

R04) are unnecessary for normal output. It has jitter of several internal oscillator clock cycles. It is synch ro nous wit h

Regenerated HSYNC.

10b: Raw VSYNC --- Buffered signal of the VSYNC input

11b: Filtered VSYNC --- VSYNC generated from the HSYNC and VSYNC input, and digitally filtered with the internal

oscillator clock (approximately 40 MHz). It's possible to set polarity (R13 [1]) by register. (An automatic setting mode is

available.) It's generated regardless of PLL setting (R02-R04). It has jitter of several internal oscillator clock cycles. The

output phase is delayed about 3/4 H to input VSYNC.

Input VSYNC

Regenerated VSYNC

< Output Signal from V SOUT>

Horizontal Period

Raw VSYNC

Filtered VSYNC

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R1E[3:1] O/E FIELD Output Signal Select

Select a output signal from O/E FIELD - pin.

000b: FO --- Odd / Even FIELD generated from the HSYNC and VSYNC input, and synchronous with the PLL clock.

Output polarity (R1E[0]) can be select by the register setti ng. PLL pa ram eter settings (R02 to R04) are necessary for

normal output. It is synchronous with VO.

001b: Regenerated FIELD --- Odd / Even FIELD generated from the HSYNC and VSYNC input, and synchronous with

the internal oscillator clock (app roximately 40 MH z) . Output polarity (R1E[0]) can be selected by the register setting.

PLL parameter settings (R02 to R04) are unnecessary for normal output. It has jitter of several internal oscillat or clock

cycles. It is synchronous with Regenerated VSYNC.

010b: DE --- Data Enable signal generated from the HSYNC and VSYNC in put, and synchronous with the PLL clock.

The polarity is Active-High. Start Position (R26[3:0]/R27[7:0]) , Pulse Width(R28[3:0]/R29[7:0]) , Vertical Blank Front

Porch (R2A[6:0]) and Back Porch (R2B[6:0]) are programmable by registers (auto sett ing modes are not available) .

011b: IRQ --- Interrupt Request Signal from Sync Processor.

100b - 111b: Reserved

R1E[0] O/E FIELD Output Polarity

Select the polarity of FO and Regenerated FIELD available from O/E FIELD-pin

0: O/E FIELD=Low in Odd FIELD, O/E FIELD=High in Even FIELD.

1: O/E FIELD=High in Odd FIELD, O/E FIELD=Low in Even FIELD.

VSYNC Input

Regenerated FI ELD

< FO / Regenerated FIELD>

Horizontal Period

Sync Input

FIELD (R1E[0]=0)

< FO / Regenerated FIELD>

Horizontal Period

Input Sync

FIELD (R1E[0]=1)

FIELD (R1E[0]=0)

ODD Field -> EVEN Field

EVEN Field -> ODD Field

Horizontal Period

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R1F[6:5] Reserved *Must be set to 00b for proper operation (Default value: 00b)

R1F[4] PLL HSYNC Filter Enable

By using Filtered HSYNC generated by HSYNC Filter that eliminates the extraneous pulses such as equalization pulses

and copy protection signal from the HSYNC input (Raw HSYNC) , the PLL COAST period (PLL free-run period) can

be set shorter. However, the HSYNC input with high jitter makes HSYNC Filter Window unstable and possibly causes

PLL unlock.

0: Raw HSYNC is used as the reference signal of PLL.

1: Filtered HSYNC is used as the reference signal of PLL.

R1F[3:0] HSYNC Filter Window Width

Set HSYNC Filter Window Width of HSYNC Filter. The setting range is from about +/-100ns (in ternal oscillator clock

+/-4 cycles) to about +/-1600ns (internal oscillator clock +/-64 cycles) around the leading edge of the HSYNC input

(the leading edge of the positive pulse for 3-level sync) . The setting step is +/-100ns (internal oscillator clock +/-4

cycles) and bigger value results in wider width.

Input HSYNC Leading Edge

Input HSYNC

with extraneous pulses

Excessive Edge

Suppressed

Filter Window W id th

Filter Window

Filtered HSYNC

Filter Window = High: Not supp ressed

Filter Window = Low: Falling Edges are suppressed

< HSYNC Filter >

*Input HSYNC into HSYNC Filter is always Active-Low

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*About timing of input VSY NC

When the transition of VSYNC is in “Input VSYNC Forbidden Region”, it is possible that following vertical timing fluc-

tuates about one line.

VSYNC output (VO, Regenerated VSYNC) ---Setting Register: R20[6:0]/R21[5:0 ]

PLL COAST Timing ---Setting Register: R22[6:0]/R23[6:0]

Clamp COAST Timing ---Setting Register: R24[6:0]/R25[6:0]

DE Restraint period ---Setting Register: R2A[6:0]/R2B[6:0]

The edge of Input VSYNC must be outside "Input VSYNC Forbidden Region" to prevent fluctuation of these vertical

timing.

R20[7] VSYNC Output (VO, Regenerated VSYNC) Timing Automatic Setting Enable

When set to 1, VSYNC Output Start Position (R20[6:0]) and VSYNC Output Pulse Width (R21[5:0]) are automatically

set to match the VSYNC input timing. The VSYNC Output Start Position is set to 0 and the VSYNC Output Pulse W idth

is determined by sync processo r based on the result of VSYNC Input Pulse Width Measurement (R2F[7:0]).

R20[6:0] VSYNC Output (VO, Regenerated VSYNC) Start Position

The starting position of VO and Regenerated VSYNC, which are the possible output from VSOUT-pin, is set in steps of

1 line based on leading edge of Input VSYNC. The set value is expressed by complement of 2 and the set range is from -

64 to +63.

R21[5:0] VSYNC Output (VO, Regenerated VSYNC) Pulse Width

The pulse width of VO and Regenerated VSYNC, which are the possible output from VSOUT-pin, is set in steps of 1

line.

0% 15% 35% 65% 85% 100%

Input HSYNC

Input VSYNC

Input VSYNC Forbidden Region

Input VSYNC

< Output VSYNC Start Position / Pulse Width >

Horizontal Period

(R20[6:0]= -1)

Output VSYNC

(R20[6:0]= 0)

(R20[6:0]= +1)

Output VSYNC Pulse Width

Output VSYNC

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R22[7] PLL COAST Timing Automatic Setting Enable

PLL should stop synchronization with the HSY NC inp ut during the vertical blank time inclu ding the pulses disturbing

PLL lock and the sampling clock generation such as equalization pulses and copy protection signal. PLL COAST signal

causes PLL to stop synchronization with the HSYNC input and free-run.

1: PLL Pre-COAST (R22[6:0]) and PLL Post-COAST (R23[6:0]) are automatically set

PLL COAST Period generated by automatic setting is depend o n the set ting of PLL HSYNC Filter Enable (R1F[4]) .

* When HSYNC Filter is disabled (R1F[4]=0) , the PLL COAST period covers the period incl udi ng extraneous and

missing pulses in vertical blank time.

* Even in the case Input Sync Type is set to “Separate Sync” (R12[1:0]=00b) , the PLL COAST signal covers the

VSYNC pulse period.

* When HSYNC Filter is enabled (R1F[4]=1) , the PLL COAST period covers the VSYNC pulse period because

extraneous pulses are eliminated by HSYNC Filter.

R22[6:0] PLL Pre-COAST

Set the start position of PLL COAST in steps of 1 line with reference to the leading edge of the VSY NC inp ut.

R23[6:0] PLL Post-COAST

Set the end position of PLL COAST in steps of 1 line with reference to the leading edge of the VSYNC input.

Input HSYNC

Raw HSYNC

PLL COAST

Filtered HSYNC

< PLL COAST Auto Mode>

Horizontal Period

HSYNC Filter Disable (R1F[4]=0)

HSYNC Filter Enable (R1F[4]=1)

PLL COAST

Input VSYNC

PLL COAST

< PLL COAST Timing>

Horizontal Period

PLL Pre-COAST PLL Post-COAST

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R24[6:0] Clamp Pre-COAST

Clamp should be suspended during the vertical blank time including the pulses disturbing clamp such as copy protection

signal. Clamp COAST signal causes clamp to be suspend.

Set the start position of Clamp COAST in steps of 1 line with reference to the leading edge of the VSYNC input.

R25[6:0] Clamp Post-COAST

Set the end position of Clamp COAST in steps of 1 line with referen ce to the leadin g edge of th e VSYNC input.

* Clamp COAST timing is related to a 3-level slicer. In case that Sync type select is "Sync on Video (3-level) "

(R12[1:0]=11b) , Clamp COAST timing should cover VSYNC pulse (and the period which includes eq ualization pulses

in interlace signal) , and end at least 12 lines prio r to the active line start.

(Setting example: Clamp Pre-COAST=2 / Clamp Post-COAST=8).

R26[3:0] / R27[7:0] DE Start Position

set the start position of DE (Data Enable) available from O/E FIELD-pin in steps of 1 pixel with reference to the leading

edge of the HSYNC input (the leading edge of th e positive pulse for 3-level sync) .

R28[3:0] / R29[7:0] DE Pulse Width

set the pulse width of DE (Data Enable) available from O/E FIELD-pi n in steps of 1 pixel.

The output polarity of DE is Active-High.

R2A[6:0] V-Blank Front Porch (DE End Line Position)

Set the end line of DE (Data Enable) availabl e from O/E FIELD -pi n in steps of 1 li ne with reference to the VSYNC

Output Start Position (R20[6:0]) .

R2B[6:0] V-Blank Back Porch (DE Start Line Position)

Set the start line of DE (Data Enable) available from O/E FIELD-pin in steps of 1 line with reference to the VSYNC

Output End Position (R20[6:0]+R21[5: 0]) .

Analog Input

Clamp COAST

< Clamp COAST Timing>

Horizontal Period

Clamp Pre-COAST Clamp Post-CO AST

Input HSYNC

DE Pulse Width

DE Start Posi ti on

< DE Horizontal Timing>

Input VSYNC

Output VSYNC

< V-Bl ank Front Porch / V-Blank Back Porch >

Horizontal Period

DE V-Blank Front Porch V-Blank Back Porch

Output VSYNC Pulse Width

THC7984_Rev.2.0_E

38 / 45 THine Electronics, Inc.

R2C[3:2] Port-1 Input Sync Type Detection

R2C[1:0] Port-0 Input Sync Type Detection

The result of Input Sync Type Detection can be read.

R2D[2] VSYNC Input Polarity Detectio n

The result of VSYNC Input Polarity Detection can be read.

0: Input polarity is Active-Low.

1: Input polarity is Active-High.

R2D[1] HSYNC Input Polarity Detection

The result of HSYNC Input Polarity Detection can be read.

0: Input polarity is Active-Low.

1: Input polarity is Active-High.

R2D[0] Sync on Video 2-level / 3-level Detection

When the result of Input Sync Type Detection of the selected input port (R12[3]) is Sync on Vi deo (R2C[6:5],

R2C[4:3]=10b) , the result of Sync on Video 2-level / 3-level Detection can be read.

0: Sync on Video is 2-level.

1: Sync on Video is 3-level.

* When Input Sync Type is not Sync on Vid eo, 0 can be read.

R2E[7] Interlace Detection

The result of Interlace Detection detected by the HSYNC and VSYNC input can be read.

0: Input signal is non-interlace (progressive) .

1: Input signal is interlace.

R2E[6:0] / R2F[7:0] Vertical Total Line Measurement

The result of Vertical Total Line Measurement measured by the HSYNC and VSYNC input can be read in 1/4 line unit.

R30[7:0] VSYNC Input Pulse Width Measurement

The result of VSYNC Input Pulse Wi dth Measurement measur ed by the HSYNC and VSYNC inpu t can be read in 1/4

line unit.

R31[2] Reserved * Must be set to 0 (Default Value: 0)

R31[1] External REFCLK Input Enable

1: It is possible to measure the horizontal period (R32[3:0] / R33[7:0] / R34[7:0]) by inputting clock which is 7 - 40 MHz

to CLAMP-pin. The frequency precision of the inp ut clock influences a result of measurement directly, so please input

the clock with the high frequency precision.

* If the external REFCLK input is enable (R31[1]=1) , the function of external clamp pulse (R16[2]) can not be used.

< Input Sync Type Detection >

HSYNC VSYNC SOGIN Input Sync Type R2C[3:2]

R2C[1:0]

Not Active Not Active Not Active No Signal 11b

Not Active Not Active Active Sync on Video 10b

Not Active Active Not Active No Signal 11b

Not Active Active Active Sync on Video 10b

Active Not Active Not Active Composite Sync 01b

Active Not Active Active Composite Sync 01b

Active Active Not Active Separate Sync 00b

Active Active Active Separate Sync 00b

THC7984_Rev.2.0_E

39 / 45 THine Electronics, Inc.

R31[0] HSYNC Period Measurement Run

0: Stop the Measurement of HSYNC Period.

1: Start Measurement of HSYNC Period. (A result of measu rem ent is renewed every 100 lines.) .

*When reading the result of measurement (R32[3:0] / R33[7:0] / R34[7:0 ]) , please suspend measurement.

R32[3:0]/R33[7:0]/R34[7:0] HSYNC Period Measurement Result

The period of 100 lines of horizontal period is counted by External REFCLK and the result can be read.

The horizontal period and frequency are calculated by the following formula.

Horizontal period [us] = Measurement result / (100 * fREFCLK)

Horizontal Frequency [kHz] = fREFCLK * 105 / Measurement result

* fREFCLK is REFCLK frequency (unit :MHz)

*Input a reference clock (7-40MHz) to CLAMP-pi n to measure period of Hori zontal, an d the setting of External R EF-

CLK input should be enabled(R31[1]=1) .

*Stop the measurement after more than 20ms(or more than 300 lines) from the start of measurement of horizontal period

(R31[0]=1), and read the result(R32[3:0] / R33[7:0] / R34[7:0]) .

R35[7] Sync Signal Valid Flag (Event Recorder)

1 is set when HSYNC and VSYNC are detected in input sync. At this point, all the measurement and detection are

completed.

R35[4] Port-1 Input Sync Type Change Detection (Event Recorder)

R35[3] Port-0 Input Sync Type Change Detection (Event Recorder)

1 is set when Port-1 Input Sync Type Detection (R2C[6:5]) , Port-0 Input Sync Typ e Detection (R2C[4:3]) changes.

R35[2] Input Signal Format Change Detection

When following even one detection and result of measurement changed, 1 is set

HSYNC Input polarity Detection

VSYNC Input polarity Detection

Vertical Total Line Measurement (Change detection threshod(R37[7:5]) default setting is +/-1 line)

VSYNC Input Pulse Wi dth Measurement (Change detecti on threshold (R37 [4:3]) default setting:+/- 1 line.)

HSYNC Period Measurement (Change detectio n threshold (R37 [2:0] ) default setting:+/- 64)

*It's possible to detect the switching of seamless input format change of which the input SYNC type doesn't change.

R35[1] Input HSYNC Missing Edge Detection (Event Recorder)

1 is set when HSYNC edges are not detected inside the pr ospective period. The PLL COAST period (R22[6:0]/R23[6:0])

is not the subject of detection.

* In case input sync signal includes no pulses during the vertical sync time such as OR-type CSYNC, these missing

pulses should be covered by PLL COAST signal.

R35[0] Input HSYNC Extraneous Edge Detection (Event Recorder)

‘1’ is read when HSYNC edges are detected outside the prospective period. The PLL COAST period (R22[6:0]/

R23[6:0]) is not the subject of detection.

* In case input sync signal includes extraneous pulses such as equalization pulses and copy protection signal du ring the

vertical blank time, these pulses should be cov ered by PLL COAST signal or eliminat ed by HSYNC Filt er (R1F[4]) .

* Event recorders must be cleared by writing 1 to them to start the measurement and detection by them.

THC7984_Rev.2.0_E

40 / 45 THine Electronics, Inc.

R36[7]/R36[4:0] Sync Processor IRQ Output Enable by Event Recorder

1: When corresponding bit of event recorders R34[5:0] is set to 1, interrupt request is triggered. Interrupt request signal is

available from O/E FIELD-pin (R1E[3:1]=011b) .

R37[7:5] Input Signal Format Change Detection---Threshold of Vertical Total Line Change

Set the change detection threshold of vertical total line for Input Signal Format Change Detection (R35[2]). When the

result of vertical total line measurement (R2E[6:0] / R2F[7:0]) change more than this value, R35[2] will be 1.

000b: 0.5 lines

001b: 1 line

010b: 2 lines

011b: 4 lines

100b: 8 lines

101b: 16 lines

110b: 32 lines

111b: Do not observe the change

R37[4:3] Input Signal Format Change Detection---Threshold of VSYNC Input Pulse Width

Set the change detection threshold of VSYNC Input Pulse Width for Input Signal Format Change Detection (R35[2]).

When the result of VSYNC Input Pulse Width measurement (R30[7:0]) change more than this value, R35[2] will be 1.

00b: 0.5 lines

01b: 1 line

10b: 4 lines

11b: Do not observe the chan ge

R37[2:0] Input Signal Format Change Detection---Threshold of HSYNC Period

Set the change detection threshold of VSYNC Input Pulse Width for Input Signal Format Change Detection (R35[2]).

When the result of VSYNC Input Pulse Width measurement (R32[3:0]/R33[7:0]/R34[7:0]) change more than this value,

R35[2] will be 1.

000b: 8

001b: 16

010b: 32

011b: 64

100b: 128

101b: 256

110b: 512

111b: Do not observe the change

R39[7:2] Reserved *Must be set to 111111b for proper operation (Default value: 111111b)

R39[1] SOG Slicer Port 1 (SOGIN1) Power-on

R39[0] SOG Slicer Port 0 (SOGIN0) Power-on

When the SOG slicer is not used, it’s possible to be powered down.

When making only SOG slicer Port 1 to be po wered down, set R39=FDh

When making only SOG slicer Port 0 to be po wered down, set R39=FEh

When making both of SOG Slicer Port to be powered down, set R39=FCh.

*R38 and the registers after R39 are for test purpose. Don’t write values to these registers.

< Sync Processor IRQ Enable >

Event Recorder Ev ent IRQ Enable

R35[7] Sync Signal Valid Flag R36[7]

R35[6] Reserved R36[6]

R35[5] Reserved R36[5]

R35[4] Port-1 Input Sync Ty pe Change Detection R36[4]

R35[3] Port-0 Input Sync Ty pe Change Detection R36[3]

R35[2] Input Signal Format Change R36[2]

R35[1] Input HSYNC Missing Edge Detection R36[1]

R35[0] Input HSYNC Extraneous Edge Detection R36[0]

THC7984_Rev.2.0_E

41 / 45 THine Electronics, Inc.

Note1. Power-down / Reset

- When it is not used, set this pin to low. (e.g., pull-down to GND by a resistor (10kohm) ) .

- RST-pin is not made pull-up or pull-down inside of devi ce.

Note2. Device address setting

Pull-down VSOUT/A0-pin to GND by a resistor (10kohm ) : Device address will be 1001100.

Pull-up VSOUT/A0-p in to VDD by a resistor (10kohm) : Device address will be 1001101.

- In case of pull-up, connect a resistor to VDD.

- Don’t connect VSOUT/A0-pin to the input pin wit h bus hold circuit of the subsequent device (Device address can’t be

acquired properly).

- VSOUT-pin is not made pull-up or pu ll-down inside the device, so please be sure to connect the resistor to this pin.

Note3. SYNC Signal Input

- The outside circuit should be designed not to apply hig her vol tage above absolute max imum rat ing (PVD +3.6v) to the

digital input pins when power is not supplied,

- Fix the input level when there is no sync signal on the sync input pins (e.g., pull-down to GND by resistor (10kohm) ) .

BAIN0

RAIN0

SOGIN0

GAIN1

SOGIN1

GND

SOGOUT

RAIN1

O/E FIELD

HSOUT

DATACK

VSOUT/A0

RED<9>

GAIN0

VDD

GND

REFCM

BLUE<2>

38 64

BAIN1

GND

RST

REFLO

REFHI

GND

DAVDD

THC7984

Top View

RED<8>

RED<7>

RED<6>

RED<5>

RED<4>

RED<3>

RED<2>

RED<1>

RED<0>

VDD

GND

GREEN<9>

GREEN<8>

GREEN<7>

GREEN<6>

GREEN<5>

GREEN<4>

GREEN<3>

GREEN<2>

GREEN<1>

GREEN<0>

VDD

GND

BLUE<9>

BLUE<8>

BLUE<7>

BLUE<6>

BLUE<5>

BLUE<4>

BLUE<3>

BLUE<1>

BLUE<0>

VDD

GND

SDA

SCL

HSYNC1

VSYNC1

HSYNC0

CLAMP

EXTCLK/COAST

PVD

GND

FILT

PVD

GND

VSYNC0

PVD

GND

100nF

1nF

PVD 2.2k

56nF

5.6nF

VDD

Note2

Note3

10k

Note

Application Example

100nF

alternative

THC7984_Rev.2.0_E

42 / 45 THine Electronics, Inc.

Notice about the crosstalk when using 2 ports (Port 0/ Port 1) .

Crosstalk of video signal

Although the input sig nal to the non-selected port will give weak noise to the signal on the selected port by crosstalk, it

has little influence as long as the signal level is normal.

If the input signal to non-selected port is abnormally higher amplitude than normal signals (nominally 1.15V peak to

peak from the bottom of the sync to the peak level of copy protection signal) and supply voltage VD is lower (1.7V) than

the typical value, the crosstalk may increase and has influence to the selected port.

The component video signal on the non-selected port should be muted (output disable) by the video switch or video

buffer prior to the device to prevent the crosstalk.

* The amplitude of component video signal (YPbPr) with sync and copy prot ection signal is relatively high.

Crosstalk of SOG slicer

The SOG slicer extract s a sync signal from Sync-On-Video si gnal (SOG, SO Y). In case that the Input Sync Type of the

selected port is Sync-On-Video(2-level) (R12[1:0]=10b) and a signal is inputted to the non-sel ected port, th ere is a pos-

sibility to have an influence on the clock Jitter by crosstalk.

* When the SOG slicer is not used (including YPbPr with separated sync input) , SOG crosstalk doesn’t influence on the

clock jitter.

To prevent crosstalk of the SOG slicer, take one of following countermeasures.

1. SOG slicer of non-selected port should be Power-down

When Port 0 is selected (R12[3]=0) : SOG slicer of port 1 should be powered down (R39=FDh)

When Port 1 is selected (R12[3]=1) : SOG slicer of port 0 should be powered down (R39=FEh)

* The SOG slicer of the port which doesn’t support SOG (e .g., PC input) can be powered down and the capacitor (1nF)

of the SOG input can be eliminated.

2. The video signal on the non-selected port should be muted (output disable) by the video switch or video buffer prior to

the device to prevent the crosstalk.

By above countermeasures, the SOG activity detection of the non-selected port can’t work and the following fu nction

can not be used.

SYNC Type Detection of non-selected port (R2C[3:2]/R2C[1:0])

Input port Automa tic Selection (R12[5])

port selection

RGB selected port

non-selected port

YPbPr

mute

(PC input)

(Component input)

Mute of non-selected port (e.g.)

video switch

THC7984

THC7984_Rev.2.0_E

43 / 45 THine Electronics, Inc.

2-wire Serial Interface

< 2-wire Serial Interface Protocol >

* The THC7984 operates as a slave device.

* While SCL is High, SDA must be stable. SDA can change when SCL is Low. (except for start/end conditions)

* A SDA High to Low transition when SCL is High defines "Start condition". A SDA Low to High transition when SCL

is High defines "Stop condition".

* In write or read cycle, whenever data is written or read, the register address (address pointer) is incremented. The

address pointer is hold when the write cycle ends. However, The address pointer is undefined when the read cycle ends.

* To read the register data, specify a register address by the write cycle, and read the data by read cycle.

* Embedded watch dog timer monit ors SCL transit ions. When SCL stays Hi gh more than 39ms (min.) or stays Low

more than 19ms (min.) , 2-wire serial interface is reset to initial state (this is different from chip reset) .

DEVICE ID

R/W

ACK

SCL

SDA I6 I5 I0

D7 D6 D0D1 A/A

Stop condition

ACK

R/W REGISTER ADDRESS

WRITE DATA

READ DATA

-WRITE CYCYLE-

S DEVICE ID WAREGISTER ADDRESS A WRITE DATA P

-READ CYCYLE-

S DEVICE ID WAREGISTER ADDRESS A

READ DATA P

SDEVICE ID RA

S: Start condition P: Stop condition

From Master to THC7984 From THC7984 to Master

9 cycle

Start condition

9 cycle

W: Write (Low) R: Read (High) A: Acknowledge (Low) A: Not acknowledge (High)

D7 D6 D0D1

ACK

9 cycle

D7 D6 D0D1

ACK

9 cycle

SDA

SCL

tBUFF

tSTAH

tDHO

tDAL

tDAH

tDSU tSTASU tSTOSU

STOP START STOPSTART

< 2-wire Serial Interface Timing >

VIHmin=1.4V

VILmax=0.8V

VIHmin=1.4V

VILmax=0.8V

THC7984_Rev.2.0_E

44 / 45 THine Electronics, Inc.

Package Dimension (Unit: mm)

THC7984

Top View

16.00 BSC.

14.00 BSC.

16.00 BSC.

14.00 BSC.

20 21 40 41

6180

1.60 Max

0 - 7 deg.

0.65 BSC 0.38

0.30

0.22

0.75

0.60

0.45

0.15

1.45

1.40

1.35 Gauge Plane

0.25

Mirror

Finish

0.05

THC7984_Rev.2.0_E

45 / 45 THine Electronics, Inc.

Other Precautions and Requirements

1. The specification in this data sheet are subject to change without prior notice.

2. Circuit diagrams shown i n this dat a sheet are exam pl es of application. Therefore, please pay m ore particul ar attent ion

to circuit designing. Even if there are improper expressions in the documents, we are not responsible for any problem due

to them. Please note that improper expressions may not be corrected immediatel y even if found.

3. Our copyrigh t and know-how ar e included in this data sheet. Duplication of the data sheet and disclosure to the third

party are strictly prohibit e d without our permission.

4. We are not responsible for any problem on ind ustrial pr oprietorship occurrin g due to the use of the THC7984, except

for those directly related to the product structure, manufacturing methods and functions.

5.The THC7984 is designed on the premise that it should be used fo r ordinary electronic devices.

Therefore, it shall not be used for applications that require extremely high-reliability (space equipment, nuclear control

equipment, medical equipment that affects the human life, etc.) . In addition, when the THC7984 is used for traffic

signals, safety devices and control/safety units in transportation equipment, etc., appropriate measures shoul d be taken.

6. We are making every effort to improve the quality and rel iability of our pro ducts. However, a very lo w probability of

failure will occur in semiconductor devices. To av oid damage to socia l or official organization s, much care should be

taken to provide sufficient redundan c y and fail-safe design.

7. Radiation-resistant design is not incorporated in the THC7984.

8. It is due to user's judgement whether or not the THC7984 pertains to one of the strategic products prescribed by the

Foreign Exchange and Foreign Trade Control Law.

THine Electronics, Inc.

sales@thine.co.jp