DS1672U-33/T&R - Maxim Integrated Products, Inc.

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GENERAL DESCRIPTION

The DS1672 incorporates a 32-bit counter and

power-monitoring functions. The 32-bit counter

is designed to count seconds and can be used to

derive time-of-day, week, month, month, and

year by using a software algorithm. A precision,

temperature-compensated reference and

comparator circuit monitors the status of VCC.

When an out-of-tolerance condition occurs, an

internal power-fail signal is generated that forces

the reset to the active state. When VCC returns to

an in-tolerance condition, the reset signal is kept

in the active state for a period of time to allow

the power supply and processor to stabilize.

FEATURES

 32-Bit Counter

 I2C* Serial Interface

 Automatic Power-Fail Detect and Switch

Circuitry

 Power-Fail Reset Output

 Low-Voltage Oscillator Operation

(1.3V min)

 Trickle-Charge Capability

 Underwriters Laboratory (UL) Recognized

 -40°C to +85°C Operating Temperature

Range

PIN CONFIGURATION

*Purchase of I2C components from Maxim Integrated Products,

Inc., or one of its sublicensed Associated Companies, conveys a

license under the Philips I2C Patent Rights to use these

components in an I2C system, provided that the system conforms

to the I2C Standard Specification defined by Philips.

DS1672

I2C 32-Bit Binar

Counter RTC

www.maxim-ic.com

TYPICAL OPERATING CIRCUIT

DIP

µSOP

TOP VIEW

VCC

SCL

SDA

VBACKUP

GND

DS1672

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ORDERING INFORMATION

PART TEMP RANGE VOLTAGE (V) PIN-PACKAGE TOP MARK*

DS1672-2 -40°C to +85°C 2.0 8 DIP (300 mils) DS1672-2

DS1672-3 -40°C to +85°C 3.0 8 DIP (300 mils) DS1672-3

DS1672-33 -40°C to +85°C 3.3 8 DIP (300 mils) DS1672-33

DS1672S-2 -40°C to +85°C 2.0 8 SO (150 mils) DS1672-2

DS1672S-2+ -40°C to +85°C 2.0 8 SO (150 mils) D1672-2

DS1672S-3 -40°C to +85°C 3.0 8 SO (150 mils) DS1672-3

DS1672S-3+ -40°C to +85°C 3.0 8 SO (150 mils) D1672-3

DS1672S-33 -40°C to +85°C 3.3 8 SO (150 mils) DS167233

DS1672S-33+ -40°C to +85°C 3.3 8 SO (150 mils) D167233

DS1672S-3/T&R -40°C to +85°C 3.0 8 SO (150 mils)/Tape

and Reel DS1672-3

DS1672S-3+T&R -40°C to +85°C 3.0 8 SO (150 mils)/Tape

and Reel D1672-3

DS1672S-33/T&R -40°C to +85°C 3.3 8 SO (150 mils)/Tape

and Reel DS167233

DS1672S-33+T&R -40°C to +85°C 3.3 8 SO (150 mils)/Tape

and Reel D167233

DS1672U-2 -40°C to +85°C 2.0 8 µSOP (3mm) 1672

rr -2

DS1672U-2+ -40°C to +85°C 2.0 8 µSOP (3mm) 1672

rr -2

DS1672U-3 -40°C to +85°C 3.0 8 µSOP (3mm) 1672

rr -3

DS1672U-3+ -40°C to +85°C 3.0 8 µSOP (3mm) 1672

rr -3

DS1672U-33 -40°C to +85°C 3.3 8 µSOP (3mm) 1672

rr -33

DS1672U-33+ -40°C to +85°C 3.3 8 µSOP (3mm) 1672

rr -33

DS1672U-33/T&R -40°C to +85°C 3.3 8 µSOP (3mm)/Tape

and Reel

1672

rr -33

DS1672U-33+T&R -40°C to +85°C 3.3 8 µSOP (3mm)/Tape

and Reel

1672

rr -33

+ Denotes a lead-free/RoHS-compliant device.

* A “+” anywhere on the top mark denotes a lead-free device. rr = 2-digit alphanumeric revision code.

DS1672

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ABSOLUTE MAXIMUM RATINGS

Voltage Range on Any Pin Relative to Ground……………………………………………..-0.5V to +6.0V

Operating Temperature Range (noncondensing) ...…………………………………………-40°C to +85°C

Storage Temperature Range……………………………………………………………….-55°C to +125°C

Soldering Temperature………………………………………….See IPC/JEDEC J-STD-020 Specification

This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect device

reliability.

RECOMMENDED DC OPERATING CONDITIONS

(TA = -40°C to +85°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

DS1672-2 VCC 1.8 2.0 2.2

DS1672-3 VCC 2.7 3.0 3.3

Supply

Voltage DS1672-33 VCC 2.97 3.3 3.63

V 1

Logic 1 VIH 0.7 x VCC V

CC + 0.5 V 1

Logic 0 VIL -0.5 +0.3 x VCC V 1

Backup Supply Voltage VBACKUP 1.3 3.0 3.63 V 1

DC ELECTRICAL CHARACTERISTICS

(VCCMIN < VCC < VCCMAX, TA = -40°C to +85°C.)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Active Supply Current ICCA 600

µA 2

Standby Current ICCS 500

µA 3

2.70 2.88 2.97

2.45 2.6 2.7

Power-Fail Voltage VPF

1.58 1.7 1.8

VBACKUP Leakage Current IBACKUPLKG 25 50 nA

Logic 0 Output (VOL = 0.4V) IOL 3 mA 1, 4

(VCC > 2V;

VOL = 0.4V) 3

Logic 0

Output

(DS1672-2) (VCC < 2V;

VOL = 0.2 x VCC)

IOL

mA 1, 4

Note 1: All voltages referenced to ground.

Note 2: ICCA specified with SCL clocking at max frequency (400kHz), trickle charger disabled.

Note 3: ICCS specified with VCC = VCCTYP and SDA, SCL = VCCTYP, trickle charger disabled.

Note 4: SDA and RST.

DS1672

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DC ELECTRICAL CHARACTERISTICS

(VCC = 0V, TA = -40°C to +85°C.)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

VBACKUP Current (Oscillator On) IBACKUPOSC 0.425 1 µA 5

VBACKUP Current (Oscillator Off) IBACKUP 200 nA

Note 5: Using the recommended crystal on X1 and X2.

CRYSTAL SPECIFICATIONS*

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Nominal Frequency fO 32.768 kHz

Series Resistance ESR 45 kΩ

Load Capacitance CL 6 pF

*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal

Considerations for Dallas Real-Time Clocks for additional specifications

DS1672

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AC ELECTRICAL CHARACTERISTICS

(VCC = 0V, TA = -40°C to +85°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES

Fast mode 100 400

SCL Clock

Frequency fSCL

Standard mode 100

kHz

Fast mode 1.3

Bus Free Time

Between a STOP and

START Condition

tBUF Standard mode 4.7 µs

Fast mode 0.6

Hold Time

(Repeated) START

Condition

tHD:STA Standard mode 4.0 µs 6

Fast mode 1.3

LOW Period of SCL

Clock tLOW Standard mode 4.7 µs

Fast mode 0.6

HIGH Period of SCL

Clock tHIGH Standard mode 4.0 µs

Fast mode 0.6

Setup Time for a

Repeated START

Condition

tSU:STA Standard mode 4.7 µs

Fast mode 0 0.9

Data Hold Time tHD:DAT

Standard mode 0

µs 7, 8

Fast mode 100

Data Setup Time tSU:DAT Standard mode 250 ns 9

Fast mode 20 + 0.1CB 300

Rise Time of Both

SDA and SCL

Signals

tR Standard mode 1000 ns 10

Fast mode 20 + 0.1CB 300

Fall Time of Both

SDA and SCL

Signals

tF Standard mode 300 ns 10

Fast mode 0.6

Setup Time for STOP

Condition tSU:STO Standard mode 4.0 µs

Capacitive Load for

Each Bus Line CB 400 pF 10

I/O Capacitance CI/O 10 pF

Note 6: After this period, the first clock pulse is generated.

Note 7: A device must internally provide a hold time of at least 300ns for the SDA signal (referenced to the VIHMIN of the SCL signal) in

order to bridge the undefined region of the falling edge of SCL.

Note 8:The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.

Note 9: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ to 250ns must then be met. This will

automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW

period of the SCL signal, it must output the next data bit to the SDA line tR max + tSU:DAT = 1000 + 250 = 1250ns before the SCL

line is released.

Note 10: CB–Total capacitance of one bus line in pF.

DS1672

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POWER-UP/POWER-DOWN CHARACTERISTICS

(TA = -40°C to +85°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

VCC Detect to RST (VCC Falling) tRPD 10 µs

VCC Detect to RST (VCC Rising) tRPU 250 ms 11

VCC Fall Time; VPF(MAX) to VPF(MIN) t

F 300 µs

VCC Rise Time; VPF(MIN) to VPF(MAX) t

R 0

µs

Note 11: If the EOSC bit in the control register is set to logic 1, tRPU is equal to 250ms plus the startup time of the crystal oscillator.

Warning: Negative undershoots below –0.3V while the part is in battery-backed mode can cause

loss of data.

Figure 1. Timing Diagram

SCL

START

SDA

STOP

tBUF

REPEATED

START

tHD:STA

tLOW

tHD:STA

tHD:DAT tSU:DAT

tHIGH

tSU:STA

tSU:STO

Figure 2. Power-Up/Power-Down Timing

OUTPUTS

VCC

VPF(max)

INPUTS

HIGH IMPEDANCE

DON'T CARE

VALID

RECOGNIZED RECOGNIZED

VALID

tRPD

VPF(min)

tPD

tRPU

DS1672

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PIN DESCRIPTION

PIN NAME FUNCTION

1, 2 X1, X2

Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator

circuitry is designed for operation with a crystal having a specified load

capacitance (CL) of 6pF. For more information about crystal selection and

crystal layout considerations, refer to Application Note 58: Crystal

Considerations with Dallas Real-Time Clocks. The DS1672 can also be driven

by an external 32.768kHz oscillator. In this configuration, the X1 pin is

connected to the external oscillator signal and the X2 pin is floated.

3 VBACKUP

Battery Input for Any Standard 3V Lithium Cell or Other Energy Source.

Battery voltage must be held between 1.3V and 3.63V for proper operation.

Diodes placed in series between the power source and the VBACKUP may result

in improper operation. If a backup supply is not required, VBACKUP must be

grounded. UL recognized to ensure against reverse charging current when used

in conjunction with a lithium battery (charger disabled). See “Conditions of

Acceptability” at www.maxim-ic.com/qa/info/ul.

4 GND Ground. DC power is provided to the device on this pin.

5 SDA

Serial-Data Input/Output. SDA is the input/output pin for the I2C serial

interface. The SDA pin is open drain and requires an external pullup resistor.

6 SCL

I2C Serial-Clock Input. SCL is used to synchronize data movement on the

serial interface and requires an external pullup resistor.

7 RST Active-Low Reset Output. It functions as a microprocessor reset signal. This

pin is an open-drain output and requires an external pullup resistor.

8 VCC

Power Pin for Primary Power Supply. When VCC is applied within normal

limits, the device is fully accessible and data can be written and read. When

VCC is below VPF, reads and writes are inhibited.

Figure 3. Recommended Layout for Crystal

LOCAL GROUND PLANE (LAYER 2)

CRYSTAL

GND

DS1672

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DETAILED DESCRIPTION

The DS1672 provides a 32-bit counter that increments once-per-second. The counter data is accessible

via an I2C serial interface. A precision, temperature-compensated, voltage reference and comparator

circuit monitors VCC. When VCC drops below VPF, RST becomes active and the interface is disabled to

prevent data corruption. The device switches to the backup supply input, which maintains oscillator and

counter operation while VCC is absent. When VCC rises above VPF, RST remains low for a period of time

(tRPU) to allow VCC to stabilize.

The block diagram in Figure 4 shows the main elements of the DS1672. As shown, communications to

and from the DS1672 occur serially over a I2C, bidirectional bus. The DS1672 operates as a slave device

on the I2C bus. Access is obtained by implementing a START condition and providing a device

identification code followed by a register address. Subsequent registers can be accessed sequentially until

a STOP condition is executed.

Figure 4. Block Diagram

Oscillator Circuit

The DS1672 uses an external 32.768kHz crystal. The oscillator circuit does not require any external

resistors or capacitors to operate. Table 1 specifies several crystal parameters for the external crystal.

Figure 4 shows a functional schematic of the oscillator circuit. If using a crystal with the specified

characteristics, the startup time is usually less than one second.

Table 1. Crystal Specifications*

PARAMETER SYMBOL MIN TYP MAX UNITS

Nominal Frequency fO 32.768 kHz

Series Resistance ESR 45 kΩ

Load Capacitance CL 6 pF

*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58:

Crystal Considerations with Dallas Real-Time Clocks.

32-BIT COUNTER

(4 BYTES)

I2C INTERFACE

POWER CONTROL

ADDRESS REGISTER

CONTROL LOGIC

1Hz

BACKUP

GND

SCL

SDA

CONTROL

TRICKLE CHARGER

X1 X2

Dallas

Semiconductor

DS1672

L C

OSCILLATOR

AND

DIVIDER

DS1672

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Clock Accuracy

The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match

between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was

trimmed. Additional error will be added by crystal frequency drift caused by temperature shifts. External

circuit noise coupled into the oscillator circuit may result in the clock running fast. Refer to Application

Note 58: “Crystal Considerations with Dallas Real-Time Clocks” for detailed information.

Address Map

The counter is accessed by reading or writing the first 4 bytes of the DS1672 (00h–03h). The control

in Table 2. If the master continues to send or request more data after the address pointer has reached 05h,

the address pointer will wrap around to location 00h.

Table 2. Registers

ADDRESS B7 B6 B5 B4 B3 B2 B1 B0 FUNCTION

00h

LSB Counter Byte 1

01h

Counter Byte 2

02h

Counter Byte 3

03h MSB Counter Byte 4

04h EOSC Control

05h TCS TCS TCS TCS DS DS RS RS Trickle Charger

Power Control

The device is fully accessible and data can be written and ready only when VCC is greater than VPF.

However, when VCC falls below VPF, (point at which write protection occurs) the internal clock registers

are blocked from any access. If VPF is less than VBACKUP, the device power is switched from VCC to

VBACKUP when VCC drops below VPF. If VPF is greater than VBACKUP, the device power is switched from

VCC to VBACKUP when VCC drops below VBACKUP. Oscillator and counter operation are maintained from

the VBACKUP source until VCC is returned to nominal levels (see Table 3).

Table 3. Power Control

SUPPLY CONDITION READ/WRITE

ACCESS RST POWERED BY

VCC < VPF, VCC < VBACKUP No Active VBACKUP

VCC < VPF, VCC > VBACKUP No Active VCC

VCC > VPF, VCC < VBACKUP Yes Inactive VCC

VCC > VPF, VCC > VBACKUP Yes Inactive VCC

Oscillator Control

The EOSC bit (bit 7 of the control register) controls the oscillator when in back-up mode. This bit when

set to logic 0 will start the oscillator. When this bit is set to a logic 1, the oscillator is stopped and the

DS1672 is placed into a low-power standby mode (IBACKUP) when in backup mode. When the DS1672 is

is incremented only when EOSC is a logic 0.

DS1672

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Microprocessor Monitor

A temperature-compensated comparator circuit monitors the level of VCC. When VCC falls to the power-

fail trip point, the RST signal (open drain) is pulled active and read/write access is inhibited. When VCC

returns to nominal levels, the RST signal is kept in the active state for tRPU (typically) to allow the power

supply and microprocessor to stabilize. Note, however, that if the EOSC bit is set to a logic 1 (to disable

the oscillator during write protection), the reset signal will be kept in an active state for tRPU plus the

startup time of the oscillator.

Trickle Charger

The trickle charger is controlled by the trickle charge register. The simplified schematic of Figure 5

shows the basic components of the trickle charger. The trickle charge select (TCS) bit (bits 4–7) controls

the selection of the trickle charger. In order to prevent accidental enabling, only a pattern on 1010 will

enable the trickle charger. All other patterns will disable the trickle charger. The DS1672 powers up with

the trickle charger disabled. The diode select (DS) bits (bits 2, 3) select whether or not a diode is

connected between VCC and VBACKUP. If DS is 01, no diode is selected or if DS is 10, a diode is selected.

The RS bits (bits 0, 1) select whether a resistor is connected between VCC and VBACKUP and what the value

of the resistor is. The resistor selected by the resistor select (RS) bits and the diode selected by the diode

select (DS) bits are as follows:

TCS TCS TCS TCS DS DS RS RS FUNCTION

X X X X 0 0 X X Disabled

X X X X 1 1 X X Disabled

X X X X X X 0 0 Disabled

1 0 1 0 0 1 0 1

No diode, 250Ω resistor

1 0 1 0 1 0 0 1

One diode, 250Ω resistor

1 0 1 0 0 1 1 0

No diode, 2kΩ resistor

1 0 1 0 1 0 1 0

One diode, 2kΩ resistor

1 0 1 0 0 1 1 1

No diode, 4kΩ resistor

1 0 1 0 1 0 1 1

One diode, 4kΩ resistor

0 0 0 0 0 0 0 0 Initial default value—disabled

Diode and resistor selection is determined by the user according to the maximum current desired for

battery or super cap charging. The maximum charging current can be calculated as illustrated in the

following example. Assume that a system power supply of 3V is applied to VCC and a super cap is

connected to VBACKUP. Also assume that the trickle charger has been enabled with a diode and resistor R2

between VCC and VBACKUP. The maximum current IMAX would, therefore, be calculated as follows:

IMAX = (5.0V - diode drop) / R1 ≈ (5.0V - 0.7V) / 2kΩ ≈ 2.2mA

As the super cap changes, the voltage drop between VCC and VBACKUP will decrease and, therefore, the

charge current will decrease.

DS1672

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Figure 5. Programmable Trickle Charger

1 OF 16 SELECT

NOTE: ONLY 1010 ENABLES 1 OF 2

SELECT

1 OF 3

SELECT

TCS TCS TCS TCS DS DS RS RS

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

250Ω

TRICKLE CHARGE REGISTER

TCS = TRICKLE CHARGER SELECT

DS = DIODE SELECT

RS = RESISTOR SELECT

VCC VBACKUP

2kΩ

4kΩ

DS1672

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I2C Serial Data Bus

The DS1672 supports a bidirectional I2C bus and data transmission protocol. A device that sends data

onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that controls

the message is called a master. The devices that are controlled by the master are slaves. The bus must be

controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates

the START and STOP conditions. The DS1672 operates as a slave on the I2C bus. Connections to the bus

are made via the open-drain I/O lines SDA and SCL. Within the bus specifications, a standard mode

(100kHz maximum clock rate) and a fast mode (400kHz maximum clock rate) are defined. The DS1672

operates in both modes.

The following bus protocol has been defined (Figure 6):

 Data transfer may be initiated only when the bus is not busy.

 During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in

the data line while the clock line is high will be interpreted as control signals.

Accordingly, the following bus conditions have been defined:

Bus not busy: Both data and clock lines remain HIGH.

Start data transfer: A change in the state of the data line from high to low, while the clock line is

high, defines a START condition.

Stop data transfer: A change in the state of the data line from low to high, while the clock line is

high, defines a STOP condition.

Data valid: The state of the data line represents valid data when, after a START condition, the

data line is stable for the duration of the high period of the clock signal. The data on the line must

be changed during the low period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition.

The number of data bytes transferred between the START and the STOP conditions is not limited,

and is determined by the master device. The information is transferred byte-wise and each

receiver acknowledges with a ninth bit. Within the I2C bus specifications a standard mode

(100kHz clock rate) and a fast mode (400kHz clock rate) are defined.

Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge

after the reception of each byte. The master device must generate an extra clock pulse that is

associated with this acknowledge bit.

A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in

such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related

clock pulse. Of course, setup and hold times must be taken into account. A master must signal an

end of data to the slave by not generating an acknowledge bit on the last byte that has been

clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master

to generate the STOP condition.

DS1672

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Figures 7 and 8 detail how data transfer is accomplished on the I2C bus. Depending upon the state of the

R/W bit, two types of data transfer are possible:

1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the

master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge

bit after each received byte.

2) Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is

transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data

bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received

bytes other than the last byte. At the end of the last received byte, a “not acknowledge” is returned.

The master device generates all of the serial clock pulses and the START and STOP conditions. A

transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START

condition is also the beginning of the next serial transfer, the bus will not be released.

The DS1672 can operate in the following two modes:

1) Slave receiver mode (DS1672 write mode): Serial data and clock are received through SDA and

SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are

recognized as the beginning and end of a serial transfer. Address recognition is performed by

hardware after reception of the slave address and direction bit (Figure 7). The slave address byte is the

first byte received after the START condition is generated by the master. The slave address byte

contains the 7-bit DS1672 address, which is 1101000, followed by the direction bit (R/W), which for

a write is a 0. After receiving and decoding the slave address byte the DS1672 outputs an

acknowledge on the SDA line. After the DS1672 acknowledges the slave address + write bit, the

master transmits a word address to the DS1672. This will set the register pointer on the DS1672, with

the DS1672 acknowledging the transfer. The master may then transmit zero or more bytes of data,

with the DS1672 acknowledging each byte received. The register pointer will increment after each

byte is transferred. The master will generate a stop condition to terminate the data write.

2) Slave transmitter mode (DS1672 read mode): The first byte is received and handled as in the slave

receiver mode. However, in this mode, the direction bit will indicate that the transfer direction is

reversed. Serial data is transmitted on SDA by the DS1672 while the serial clock is input on SCL.

START and STOP conditions are recognized as the beginning and end of a serial transfer (Figure 8).

The slave address byte is the first byte received after the START condition is generated by the master.

The slave address byte contains the 7-bit DS1672 address, which is 1101000, followed by the

direction bit (R/W), which for a read is a 1. After receiving and decoding the slave address byte the

DS1672 outputs an acknowledge on the SDA line. The DS1672 then begins to transmit data starting

with the register address pointed to by the register pointer. If the register pointer is not written to

before the initiation of a read mode the first address that is read is the last one stored in the register

pointer. The DS1672 must receive a “not acknowledge” to end a read.

DS1672

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Figure 6. Data Transfer on I2C Serial Bus

MSB

slave address

R/W

direction

bit

SDA

SCL

START

CONDITION

12 6789 12 89

STOP CONDITION

REPEATED

START CONDITION

3 - 8

acknowledgement

signal from receiver

acknowledgement

signal from receiver

ACK ACK

repeated if more bytes

are transferred

Figure 7. Data Write: Slave Receiver Mode

Figure 8. Data Read: Slave Transmitter Mode

AXXXXXXXXA1101000S 1 XXXXXXXX AXXXXXXXX AXXXXXXXX A P

S - START

A - ACKNOWLEDGE

P - STOP

A - NOT ACKNOWLEDGE

<RW>

R/W - READ/WRITE OR DIRECTION BIT ADDRESS = D1H

DATA TRANSFERRED

(X+1 BYTES + ACKNOWLEDGE); NOTE: LAST DATA BYTE IS

FOLLOWED BY A NOT ACKNOWLEDGE (A) SIGNAL)

AXXXXXXXXA1101000S 0 XXXXXXXX AXXXXXXXX AXXXXXXXX A P

S - START

A - ACKNOWLEDGE

P - STOP

<RW>

R/W - READ/WRITE OR DIRECTION BIT ADDRESS = D0H

DATA TRANSFERRED

(X+1 BYTES + ACKNOWLEDGE)

DS1672

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Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.

No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.

THERMAL INFORMATION

PACKAGE THETA-JA THETA-JC

8 DIP (300 mils) 110°C/W 40°C/W

8 SO (150 mils) 170°C/W 40°C/W

8 µSOP (3mm) 221°C/W 39°C/W

PACKAGE INFORMATION

For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.

PACKAGE TYPE DOCUMENT

NUMBER

8 DIP (300 mils) 56-G5005-000

8 SO (150 mils) 56-G2008-001

8 µSOP (3mm) 56-G2018-001