ADC0848BCVX/NOPB - National Semiconductor

December 2, 2008

ADC0844/ADC0848

8-Bit μP Compatible A/D Converters with Multiplexer

Options

General Description

The ADC0844 and ADC0848 are CMOS 8-bit successive ap-

proximation A/D converters with versatile analog input multi-

plexers. The 4-channel or 8-channel multiplexers can be

software configured for single-ended, differential or pseudo-

differential modes of operation.

The differential mode provides low frequency input common

mode rejection and allows offsetting the analog range of the

converter. In addition, the A/D's reference can be adjusted

enabling the conversion of reduced analog ranges with 8-bit

resolution.

The A/Ds are designed to operate from the control bus of a

wide variety of microprocessors. TRI-STATE output latches

that directly drive the data bus permit the A/Ds to be config-

ured as memory locations or I/O devices to the microproces-

sor with no interface logic necessary.

Features

■Easy interface to all microprocessors

■Operates ratiometrically or with 5 VDC

voltage reference

■No zero or full-scale adjust required

■4-channel or 8-channel multiplexer with address logic

■Internal clock

■0V to 5V input range with single 5V power supply

■0.3″ standard width 20-pin or 24-pin DIP

■28 Pin Molded Chip Carrier Package

Key Specifications

■Resolution 8 Bits

■Total Unadjusted Error ±½ LSB and ± 1 LSB

■Single Supply 5 VDC

■Low Power 15 mW

■Conversion Time 40 μs

Block Diagram

501601

* ADC0848 shown in DIP Package CH5-CH8 not included on the ADC0844

ADC0844/ADC0848 8-Bit μP Compatible A/D Converters with Multiplexer Options

Connection Diagrams

Molded Chip Carrier Package

501629

Top View

See Ordering Information

Dual-In-Line Package

501602

Top View

Dual-In-Line Package

501630

Top View

Ordering Information

Temperature

Range

Total Unadjusted Error MUX

Channels Package Outline

±½ LSB ±1 LSB

0°C to +70°C

ADC0844CCN 4 N20A

Molded Dip

ADC0848BCN ADC0848CCN 8 N24D

Molded Dip

−40°C to +85°C

ADC0844BCJ* ADC0844CCJ* 4 J20A

Cerdip

ADC0848BCV ADC0848CCV 8 V28A

Molded Chip Carrier

ADC0848BCVX ADC0848CCVX 8 V28A Molded Chip Carrier

in Tape and Reel

* Product/package combination obsolete; shown for reference only

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ADC0844/ADC0848

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (VCC)6.5V

Voltage

Logic Control Inputs −0.3V to +15V

At Other Inputs and Outputs −0.3V to VCC+0.3V

Input Current at Any Pin (Note 3) 5 mA

Package Input Current (Note 3) 20 mA

Storage Temperature −65°C to +150°C

Package Dissipation at TA=25°C 875 mW

ESD Susceptibility (Note 4) 800V

Lead Temperature

(Soldering, 10 seconds)

Dual-In-Line Package (Plastic) 260°C

Dual-In-Line Package (Ceramic) 300°C

Molded Chip Carrier Package

Vapor Phase (60 seconds) 215°C

Infrared (15 seconds) 220°C

Operating Conditions

(Notes 1, 2)

Supply Voltage (VCC) 4.5 VDC to 6.0 VDC

Temperature Range TMIN≤TA≤TMAX

ADC0844CCN, ADC0848BCN, 0°C≤TA≤70°C

ADC0848CCN

ADC0844BCJ *, ADC0844CCJ

−40°C≤TA≤85°C

ADC0848BCV, ADC0848CCV

* Product/package combination obsolete; shown for reference only.

Electrical Characteristics

The following specifications apply for VCC = 5 VDC unless otherwise specified.Boldface limits apply from TMIN to TMAX; all other

limits TA = Tj = 25°C.

Parameter Conditions

ADC0844BCJ (Note 12)

ADC0844CCJ (Note 12)

ADC0844CCN

ADC0848BCN, ADC0848CCN

ADC0848BCV, ADC0848CCV Limit

Units

Typ

(Note 5)

Tested

Limit

(Note 6)

Design

Limit

(Note 7)

Typ

(Note 5)

Tested

Limit

(Note 6)

Design

Limit

(Note 7)

CONVERTER AND MULTIPLEXER CHARACTERISTICS

Maximum Total VREF=5.00 VDC

Unadjusted Error (Note 8)

ADC0844BCN, ADC0848BCN, BCV ±½ ±½ LSB

ADC0844CCN, ADC0848CCN, CCV ±1 ±1 LSB

ADC0844CCJ (Note 12) ±1 LSB

Minimum Reference Input Resistance 2.4 1.1 2.4 1.2 1.1 kΩ

Maximum Reference Input Resistance 2.4 5.9 2.4 5.4 5.9 kΩ

Maximum Common-Mode Input Voltage (Note 9) VCC+0.05 VCC+0.05 VCC+0.05 V

Minimum Common-Mode Input Voltage (Note 9) GND

−0.05 GND

−0.05

GND

−0.05 V

DC Common-Mode Error Differential Mode ±1/16 ±¼ ±1/16 ±¼ ±¼ LSB

Power Supply Sensitivity VCC=5V±5% ±1/16 ±⅛ ±1/16 ±⅛ ±⅛ LSB

Off Channel Leakage Current

(Note 10)

On Channel=5V, −1 −0.1 −1 μA

Off Channel=0V

On Channel=0V, 1 0.1 1μA

Off Channel=5V

DIGITAL AND DC CHARACTERISTICS

VIN(1), Logical “1” Input Voltage (Min) VCC=5.25V 2.0 2.0 2.0 V

VIN(0), Logical “0” Input Voltage (Max) VCC=4.75V 0.8 0.8 0.8 V

IIN(1), Logical “1” Input Current (Max) VIN=5.0V 0.005 1 0.005 1μA

IIN(0), Logical “0” Input Current (Max) VIN=0V −0.005 −1 −0.005 −1 μA

VOUT(1), Logical “1” Output Voltage (Min)

VCC=4.75V,

IOUT=−360 μA 2.4 2.8 2.4 V

IOUT=−10 μA 4.5 4.6 4.5 V

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ADC0844/ADC0848

Parameter Conditions

ADC0844BCJ (Note 12)

ADC0844CCJ (Note 12)

ADC0844CCN

ADC0848BCN, ADC0848CCN

ADC0848BCV, ADC0848CCV Limit

Units

Typ

(Note 5)

Tested

Limit

(Note 6)

Design

Limit

(Note 7)

Typ

(Note 5)

Tested

Limit

(Note 6)

Design

Limit

(Note 7)

VOUT(0), Logical “0” Output Voltage (Max) VCC=4.75V,

IOUT=1.6 mA

0.4 0.34 0.4 V

IOUT, TRI-STATE Output Current (Max) VOUT=0V −0.01 −3 −0.01 −0.3 −3 μA

VOUT=5V 0.01 3 0.01 0.3 3μA

ISOURCE, Output Source Current (Min) VOUT=0V −14 −6.5 −14 −7.5 −6.5 mA

ISINK, Output Sink Current (Min) VOUT=VCC 16 8.0 16 9.0 8.0 mA

ICC, Supply Current (Max) CS =1, VREF Open 12.5 1 2.3 2.5 mA

AC Electrical Characteristics

The following specifications apply for VCC = 5VDC, tr = tf = 10 ns unless otherwise specified. Boldface limits apply from TMIN to

TMAX; all other limits TA = Tj = 25°C.

Parameter Conditions Typ

(Note 5)

Tested

Limit

(Note 6)

Design

Limit

(Note 7)

Units

tC, Maximum Conversion Time (See Graph) 30 40 60 μs

tW(WR), Minimum WR Pulse Width (Note 11) 50 150 ns

tACC, Maximum Access Time (Delay from Falling Edge of RD to

Output Data Valid) CL = 100 pF (Note 11) 145 225 ns

t1H, t0H, TRI-STATE Control (Maximum Delay from Rising Edge

of RD to Hi-Z State)

CL = 10 pF, RL = 10k

(Note 11) 125 200 ns

tWI, tRI, Maximum Delay from Falling Edge of WR or RD to Reset

of INTR (Note 11) 200 400 ns

tDS, Minimum Data Set-Up Time (Note 11) 50 100 ns

tDH, Minimum Data Hold Time (Note 11) 0 50 ns

CIN, Capacitance of Logic Inputs 5 pF

COUT, Capacitance of Logic Outputs 5 pF

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating

the device beyond its specified operating conditions.

Note 2: All voltages are measured with respect to the ground pins.

Note 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V−or VIN > V+) the absolute value of the current at that pin should be limited

to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four.

Note 4: Human body model, 100 pF discharged through a 1.5 kΩ resistor.

Note 5: Typical figures are at 25°C and represent most likely parametric norm.

Note 6: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

Note 7: Design limits are guaranteed by not 100% tested. These limits are not used to calculate outgoing quality levels.

Note 8: Total unadjusted error includes offset, full-scale, linearity, and multiplexer error.

Note 9: For VIN (−) ≥ VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input, which will forward-conduct for analog

input voltages one diode drop below ground or one diode drop greater than VCC supply. Be careful during testing at low VCC levels (4.5V), as high level analog

inputs (5V) can cause this input diode to conduct, especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV

forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct.

To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial

tolerance and loading.

Note 10: Off channel leakage current is measured after the channel selection.

Note 11: The temperature coefficient is 0.3%/°C.

Note 12: This product/package combination is obsolete. Shown for reference only.

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ADC0844/ADC0848

Typical Performance Characteristics

Logic Input Threshold

Voltage vs. Supply Voltage

501631

Output Current vs.

Temperature

501632

Power Supply Current vs.

Temperature

501633

Linearity Error vs. VREF

501634

Conversion Time vs. VSUPPLY

501635

Conversion Time vs.

Temperature

501636

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ADC0844/ADC0848

Unadjusted Offset Error vs.

VREF Voltage

501637

TRI-STATE Test Circuits and Waveforms

t1H

501604

t1H, CL = 10 pF

501605

tr = 20 ns

t0H

501606

t0H, CL = 10 pF

501607

tr = 20 ns

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ADC0844/ADC0848

Leakage Current Test Circuit

501608

Timing Diagrams

Programming New Channel Configuration and Starting a Conversion

501609

Note 13: Read strobe must occur at least 600 ns after the assertion of interrupt to guarantee reset of INTR .

Note 14: MA stands for MUX address.

Using the Previously Selected Channel Configuration and Starting a Conversion

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ADC0844/ADC0848

501610

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ADC0844/ADC0848

ADC0848 Functional Block Diagram

501611

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ADC0844/ADC0848

Functional Description

The ADC0844 and ADC0848 contain a 4-channel and 8-

channel analog input multiplexer (MUX) respectively. Each

MUX can be configured into one of three modes of operation

differential, pseudo-differential, and single ended. These

modes are discussed in the Applications Information Section.

The specific mode is selected by loading the MUX address

latch with the proper address (see Table 1 and Table 2). In-

puts to the MUX address latch (MA0-MA4) are common with

data bus lines (DB0-DB4) and are enabled when the RD line

is high. A conversion is initiated via the CS and WR lines. If

the data from a previous conversion is not read, the INTR line

will be low. The falling edge of WR will reset the INTR line

high and ready the A/D for a conversion cycle. The rising edge

of WR, with RD high, strobes the data on the MA0/DB0-MA4/

DB4 inputs into the MUX address latch to select a new input

configuration and start a conversion. If the RD line is held low

during the entire low period of WR the previous MUX config-

uration is retained, and the data of the previous conversion is

the output on lines DB0-DB7. After the conversion cycle (tC

≤ 40 μs), which is set by the internal clock frequency, the dig-

ital data is transferred to the output latch and the INTR is

asserted low. Taking CS and RD low resets INTR output high

and outputs the conversion result on the data lines (DB0-

DB7).

Applications Information

1.0 MULTIPLEXER CONFIGURATION

The design of these converters utilizes a sampled-data com-

parator structure which allows a differential analog input to be

converted by a successive approximation routine.

The actual voltage converted is always the difference be-

tween an assigned “+” input terminal and a “−” input terminal.

The polarity of each input terminal of the pair being converted

indicates which line the converter expects to be the most pos-

itive. If the assigned “+” input is less than the “−” input the

converter responds with an all zeros output code.

A unique input multiplexing scheme has been utilized to pro-

vide multiple analog channels. The input channels can be

software configured into three modes: differential, single end-

ed, or pseudo-differential. Figure 1 shows the three modes

using the 4-channel MUX ADC0844. The eight inputs of the

ADC0848 can also be configured in any of the three modes.

In the differential mode, the ADC0844 channel inputs are

grouped in pairs, CH1 with CH2 and CH3 with CH4. The po-

larity assignment of each channel in the pair is interchange-

able. The single-ended mode has CH1–CH4 assigned as the

positive input with the negative input being the analog ground

(AGND) of the device. Finally, in the pseudo-differential mode

CH1–CH3 are positive inputs referenced to CH4 which is now

a pseudo-ground. This pseudo-ground input can be set to any

potential within the input common-mode range of the con-

verter. The analog signal conditioning required in transducer-

based data acquisition systems is significantly simplified with

this type of input flexibility. One converter package can now

handle ground referenced inputs and true differential inputs

as well as signals with some arbitrary reference voltage.

The analog input voltages for each channel can range from

50 mV below ground to 50 mV above VCC (typically 5V) with-

out degrading conversion accuracy.

TABLE 1. ADC0844 MUX ADDRESSING

MUX Address CS WR RD Channel# MUX Mode

MA3 MA2 MA1 MA0 CH1 CH2 CH3 CH4 AGND

X L L L L H + −

Differential

X L L H L NP H−+

X L H L L H + −

X L H H L H −+

L H L L L H + −

Single-Ended

L H L H L NP H + −

L H H L L H + −

L H H H L H + −

H H L L L H + −

Pseudo-

Differential

H H L H L NP H + −

H H H L L H + −

X X X X L NP L Previous Channel Configuration

X = don't care, NP = negative pulse

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ADC0844/ADC0848

4 Single-Ended

501612

2 Differential

501613

3 Pseudo-Differential

501614

Combined

501615

FIGURE 1. Analog Input Multiplexer Options

2.0 REFERENCE CONSIDERATIONS

The voltage applied to the reference input of these converters

defines the voltage span of the analog input (the difference

between VIN(MAX) and VIN(MIN)) over which the 256 possible

output codes apply. The devices can be used in either ratio-

metric applications or in systems requiring absolute accuracy.

The reference pin must be connected to a voltage source ca-

pable of driving the minimum reference input resistance of 1.1

kΩ. This pin is the top of a resistor divider string used for the

successive approximation conversion.

In a ratiometric system (Figure 2a), the analog input voltage

is proportional to the voltage used for the A/D reference. This

voltage is typically the system power supply, so the VREF pin

can be tied to VCC. This technique relaxes the stability re-

quirements of the system reference as the analog input and

A/D reference move together maintaining the same output

code for a given input condition. For absolute accuracy (Fig-

ure 2b), where the analog input varies between very specific

voltage limits, the reference pin can be biased with a time and

temperature stable voltage source. The LM385 and LM336

reference diodes are good low current devices to use with

these converters.

The maximum value of the reference is limited to the VCC

supply voltage. The minimum value, however, can be quite

small (see Typical Performance Characteristics) to allow di-

rect conversions of transducer outputs providing less than a

5V output span. Particular care must be taken with regard to

noise pickup, circuit layout and system error voltage sources

when operating with a reduced span due to the increased

sensitivity of the converter (1 LSB equals VREF/256).

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ADC0844/ADC0848

3.0 THE ANALOG INPUTS

3.1 Analog Differential Voltage Inputs and Common-

Mode Rejection

The differential input of these converters actually reduces the

effects of common-mode input noise, a signal common to

both selected “+” and “−” inputs for a conversion (60 Hz is

most typical). The time interval between sampling the “+” input

and then the “−” inputs is ½ of a clock period. The change in

the common-mode voltage during this short time interval can

cause conversion errors. For a sinusoidal common-mode sig-

nal this error is:

501638

where fCM is the frequency of the common-mode signal,

Vpeak is its peak voltage value and tC is the conversion time.

For a 60 Hz common-mode signal to generate a ¼ LSB error

(≈5 mV) with the converter running at 40 μS, its peak value

would have to be 5.43V. This large a common-mode signal is

much greater than that generally found in a well designed data

acquisition system.

TABLE 2. ADC0848 MUX Addressing

MUX Address CS WR RD Channel MUX Mode

MA4 MA3 MA2 MA1 MA0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 AGND

X L L L L L H + −

Differential

X L L L H L H −+

X L L H L L H + −

X L L H H L NP H −+

X L H L L L H + −

X L H L H L H −+

X L H H L L H + −

X L H H H L H −+

L H L L L L H + −

Single-Ended

L H L L H L H + −

L H L H L L H + −

L H L H H L NP H + −

L H H L L L H + −

L H H L H L H + −

L H H H L L H + −

L H H H H L H + −

H H L L L L H + −

Pseudo-

Differential

H H L L H L H + −

H H L H L L H + −

H H L H H L NP H + −

H H H L L L H + −

H H H L H L H + −

H H H H L L H + −

X X X X X L L Previous Channel Configuration

X = don't care, NP = negative pulse

3.2 Input Current

Due to the sampling nature of the analog inputs, short dura-

tion spikes of current enter the “+” input and exit the “−” input

at the clock edges during the actual conversion. These cur-

rents decay rapidly and do not cause errors as the internal

comparator is strobed at the end of a clock period. Bypass

capacitors at the inputs will average these currents and cause

an effective DC current to flow through the output resistance

of the analog signal source. Bypass capacitors should not be

used if the source resistance is greater than 1 kΩ.

3.3 Input Source Resistance

The limitation of the input source resistance due to the DC

leakage currents of the input multiplexer is important. A worst-

case leakage current of ± 1 μA over temperature will create a

1 mV input error with a 1 kΩ source resistance. An op amp

RC active low pass filter can provide both impedance buffer-

ing and noise filtering should a high impedance signal source

be required.

4.0 OPTIONAL ADJUSTMENTS

4.1 Zero Error

The zero of the A/D does not require adjustment. If the mini-

mum analog input voltage value, VIN(MIN), is not ground, a zero

offset can be done. The converter can be made to output 0000

0000 digital code for this minimum input voltage by biasing

any VIN (−) input at this VIN(MIN) value. This is useful for either

differential or pseudo-differential modes of input channel con-

figuration.

The zero error of the A/D converter relates to the location of

the first riser of the transfer function and can be measured by

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ADC0844/ADC0848

grounding the V− input and applying a small magnitude pos-

itive voltage to the V+ input. Zero error is the difference

between actual DC input voltage which is necessary to just

cause an output digital code transition from 0000 0000 to

0000 0001 and the ideal ½ LSB value (½ LSB=9.8 mV for

VREF=5.000 VDC).

4.2 Full-Scale

The full-scale adjustment can be made by applying a differ-

ential input voltage which is 1 ½ LSB down from the desired

analog full-scale voltage range and then adjusting the mag-

nitude of the VREF input for a digital output code changing from

1111 1110 to 1111 1111.

4.3 Adjusting for an Arbitrary Analog Input Voltage

Range

If the analog zero voltage of the A/D is shifted away from

ground (for example, to accommodate an analog input signal

which does not go to ground), this new zero reference should

be properly adjusted first. A VIN (+) voltage which equals this

desired zero reference plus ½ LSB (where the LSB is calcu-

lated for the desired analog span, 1 LSB = analog span/256)

is applied to selected “+” input and the zero reference voltage

at the corresponding “−” input should then be adjusted to just

obtain the 00HEX to 01HEX code transition.

501616

a) Ratiometric

501617

b) Absolute with a Reduced Span

FIGURE 2. Referencing Examples

The full-scale adjustment should be made [with the proper

VIN (−) voltage applied] by forcing a voltage to the VIN (+) input

which is given by:

where VMAX=the high end of the analog input range and

VMIN=the low end (the offset zero) of the analog range. (Both

are ground referenced.)

The VREF (or VCC) voltage is then adjusted to provide a code

change from FEHEX to FFHEX. This completes the adjustment

procedure.

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ADC0844/ADC0848

For an example see the Zero-Shift and Span Adjust circuit

below.

Zero-Shift and Span Adjust (2V≤VIN≤5V)

501618

Differential Voltage Input 9-Bit A/D

501619

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ADC0844/ADC0848

Span Adjust (0V≤VIN≤3V)

501620

Protecting the Input

501621

Diodes are 1N914

High Accuracy Comparators

501622

DO = all 1s if VIN(+)>VIN(−)

DO = all 0s if VIN(+)<VIN(−)

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ADC0844/ADC0848

Operating with Automotive Ratiometric Transducers

501623

* VIN(−)=0.15 VCC

15% of VCC≤VXDR≤85% of VCC

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ADC0844/ADC0848

A Stand Alone Circuit

501625

Note: DUT pin numbers in parentheses are for ADC0844, others are for ADC0848.

Start a Conversion without Updating the Channel Configuration

501626

CS •WR will update the channel configuration and start a conversion.

CS •RD will read the conversion data and start a new conversion without updating the channel configuration.

Waiting for the end of this conversion is not necessary. A CS •WR can immediately follow the CS•RD .

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ADC0844/ADC0848

ADC0844—INS8039 Interface

501627

SAMPLE PROGRAM FOR ADC0844—INS8039 INTERFACE

CONVERTING TWO RATIOMETRIC, DIFFERENTIAL SIGNALS

ORG 0H

0000 04 10 JMP BEGIN ;START PROGRAM AT ADDR 10

ORG 10H ;MAIN PROGRAM

0010 B9 FF BEGIN: MOV R1,#0FFH ;LOAD R1 WITH A UNUSED ADDR

;LOCATION

0012 B8 20 MOV R0,#20H ;A/D DATA ADDRESS

0014 89 FF ORL P1,#0FFH ;SET PORT 1 OUTPUTS HIGH

0016 23 00 MOV A,00H ;LOAD THE ACC WITH A/D MUX DATA

;CH1 AND CH2 DIFFERENTIAL

0018 14 50 CALL CONV ;CALL THE CONVERSION SUBROUTINE

001A 23 02 MOV A,#02H ;LOAD THE ACC WITH A/D MUX DATA

;CH3 AND CH4 DIFFERENTIAL

001C 18 INC R0 ;INCREMENT THE A/D DATA ADDRESS

001D 14 50 CALL CONV ;CALL THE CONVERSION SUBROUTINE

;CONTINUE MAIN PROGRAM

;CONVERSION SUBROUTINE

;ENTRY:ACC—A/D MUX DATA

;EXIT: ACC—CONVERTED DATA

ORG 50H

0050 99 FE CONV: ANL P1,#0FEH ;CHIP SELECT THE A/D

0052 91 MOVX @R1,A ;LOAD A/D MUX & START CONVERSION

0053 09 LOOP: IN A,P1 ;INPUT INTR STATE

0054 32 53 JB1 LOOP ;IF INTR = 1 GOTO LOOP

0056 81 MOVX A,@R1 ;IF INTR = 0 INPUT A/D DATA

0057 89 01 ORL P1,&01H ;CLEAR THE A/D CHIP SELECT

0059 A0 MOV @R0,A ;STORE THE A/D DATA

005A 83 RET ;RETURN TO MAIN PROGRAM

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ADC0844/ADC0848

I/O Interface to NSC800

501628

SAMPLE PROGRAM FOR ADC0848—NSC800 INTERFACE

0008 NCONV EQU 16

000F DEL EQU 15 ;DELAY 50 μsec CONVERSION

001F CS EQU 1FH ;THE BOARD ADDRESS

3C00 ADDTA EQU 003CH ;START OF RAM FOR A/D

;DATA

0000′08 09 0A 0B MUXDTA: DB 08H,09H,0AH,0BH ;MUX DATA

0004′0C 0D 0E 0F DB 0CH,0DH,0EH,0FH

0008′0E 1F START: LD C,CS

000A′06 16 LD B,NCONV

000C′21 0000′ LD HL,MUXDTA

000F′11 003C LD DE,ADDTA

0012′ED A3 STCONV: OUTI ;LOAD A/D'S MUX DATA

;AND START A CONVERSION

0014′EB EX DE,HL ;HL=RAM ADDRESS FOR THE

;A/D DATA

0015′3E 0F LD A,DEL

0017′3D WAIT: DEC A ;WAIT 50 μsec FOR THE

0018′C2 0013′ JP NZ,WAIT ;CONVERSION TO FINISH

001B′ED A2 INI ;STORE THE A/D'S DATA

;CONVERTED ALL INPUTS?

001D′EB EX DE,HL

001E′C2 000E′ JP NZ,STCONV ;IF NOT GOTO STCONV

END

Note 15: This routine sequentially programs the MUX data latch in the signal-ended mode. For CH1-CH8 a conversion is started, then a 50 μs wait for the A/D

to complete a conversion and the data is stored at address ADDTA for CH1, ADDTA + 1 for CH2, etc.

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ADC0844/ADC0848

Physical Dimensions inches (millimeters) unless otherwise noted

Ceramic Dual-In-Line Package (J) (product obsolete in this package)

NS Package Number J20A

Molded Dual-In-Line Package (N)

NS Package Number N20A

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ADC0844/ADC0848

Molded Dual-In-Line Package (N)

NS Package Number N24D

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ADC0844/ADC0848

Molded Chip Carrier Package (V)

NS Package Number V28A

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ADC0844/ADC0848

Notes

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ADC0844/ADC0848

Notes

ADC0844/ADC0848 8-Bit μP Compatible A/D Converters with Multiplexer Options

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