G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT May 1997 (Rev 1) Features : Description : The GLT41016 is a 65,536 x 16 bit highperformance CMOS dynamic random access memory. The GLT41016 offers Fast Page mode with Extended Data Output, and has both BYTE WRITE and WORD WRITE access cycles via two CAS pins. The GLT41016 accepts 256-cycle refresh in 4ms interval. All inputs are TTL compatible. EDO Page Mode operation allows random access up to 256 x 16 bits, within a page, with cycle times as short as 13ns. The GLT41016 is best suited for graphics, and DSP applications requiring high performance memories. 65,536 words by 16 bits organization. Fast access time and cycle time. Dual CAS Input. Low power dissipation. Read-Modify-Write, RAS -Only Refresh, CAS -Before- RAS Refresh, Hidden Refresh and Test Mode Capability. 256 refresh cycles per 4ms. Available in 40-pin 400 mil SOJ and 40/44 pin TSOP (II). Single 5.0Vr10% Power Supply. All inputs and Outputs are TTL compatible. Extended Data-Out(EDO) Page Mode operation. HIGH PERFORMANCE 35 40 45 50 Max. RAS Access Time, (tRAC) 35 ns 40 ns 45 ns 50 ns Max. Column Address Access Time, (tAA) 18 ns 20 ns 22 ns 25 ns Min. Extended Data Out Page Mode Cycle Time, (tPC) 13 ns 15 ns 18 ns 20 ns Min. Read/Write Cycle Time, (tRC) 70 ns 75 ns 80 ns 90 ns Max. CAS Access Time (tCAC) 11 ns 12 ns 12 ns 13 ns G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -1- G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT May 1997 (Rev 1) Pin Configuration : GLT41016 SOJ Top View TSOP(Type II) Top View Pin Descriptions: Name A 0 - A7 Function RAS Address Inputs Row Address Strobe UCAS Column Address Strobe/Upper Byte Control LCAS Column Address Strobe/Lower Byte Control WE Write Enable OE DQ0 - DQ15 VCC VSS NC Output Enable Absolute Maximum Ratings* Data Inputs / Outputs +5V Power Supply Ground No Connection Capacitance* G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -2- G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT May 1997 (Rev 1) TA=25qC, VCC=5Vr10%, VSS=0V Operating Temperature, TA (ambient) Parameter Symbol .......................................-0 qC to +70qC Address Input Storage Temperature(plastic)....-55qC to +125qC CIN1 Voltage Relative to VSS...............-1.0V to + 7.0V CIN2 Short Circuit Output Current......................50mA Power Dissipation......................................1.0W COUT *Note: Operation above Absolute Maximum Ratings can adversely affect device reliability. Max. Unit 5 pF RAS , LCAS , UCAS , WE , OE 7 pF Data Input/ Output 7 pF *Note: Capacitance is sampled and not 100% tested Electrical Specifications z CAS means UCAS and LCAS . z All voltages are referenced to GND. z After power up, wait more than 100Ps and then, execute eight CAS -before- RAS or RAS -only refresh cycles as dummy cycles to initialize internal circuit. Block Diagram : Extended Data Output (EDO) Page Mode G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -3- G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT May 1997 (Rev 1) The EDO page mode is a kind of page mode with enhanced features. The two major features of the EDO page mode are as follows. 1. Data output time is extended. In the EDO page mode, the output data is held to the next CAS cycle`s falling edge, instead of the rising edge. For this reason, valid data output time in the EDO page mode is extended compared with the fast page mode (=data extend function). In the fast page mode, the data output time becomes shorter as the CAS cycle time becomes shorter. Therefore, in the EDO page mode, the timing margin in read cycle is larger than of the fast page mode even if the CAS cycle time becomes shorter. 2. The CAS cycle time in the EDO page mode is shorter than that in the fast page mode. In the EDO page mode, due to the data extend function, the CAS cycle time can be shorter than in the fast page mode if the timing margin is the same. Taking a device whose tRAC is 60ns as an example, the CAS cycle time in the EDO page mode is 25ns while that in the fast page mode is 40ns. In the EDO page mode, read (data out) and write (data in) cycles can be executed repeatedly during one RAS cycle. The EDO page mode allows both read and write operations during one cycle, but the performance is equivalent to that of the fast page mode in that case. Truth Table: GLT41016 Function Standby RAS H o o CASL H X H X CASH ADDRESS WE X OE X DQs Notes High-Z G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -4- G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT May 1997 (Rev 1) Read: Word L L L H L ROW/COL Data Out Read: Lower Byte L L H H L Read: Upper Byte L H L H L Write: Word(Early Write) L L L L X ROW/COL Lower Byte,Data-Out Upper Byte,High-Z ROW/COL Lower Byte,High-Z Upper Byte,Data-Out ROW/COL Data-In Write: Lower Byte (Early) L L H L X Write: Upper Byte (Early) L H L L X Read Write L L L H L o L H H L H L H L L X L X EDO-Page- 1st Cycle L Mode Read 2nd Cycle L EDO-Page- 1st Cycle L Mode Write 2nd Cycle L EDO-Page- 1st Cycle L o HoL HoL HoL HoL 2nd Cycle L H L o o o o o HoL HoL HoL HoL H L o L H H L o H L o L H H L o ROW/COL Lower Byte,Data-In Upper Byte,High-Z ROW/COL Lower Byte,High-Z Upper Byte,Data-In ROW/COL Data-Out,Data-In 1,2 ROW/COL Data-Out COL 1 Data-Out 1 ROW/COL Data-In COL 2 Data-In ROW/COL Data-Out,Data-In 2 1,2 Mode ReadWrite Hidden Refresh o COL Data-Out,Data-In Read L H L L L H L ROW/COL Data-Out Write L H L L o o L L L X ROW/COL Data-In H H X X o L L X X RAS -Only Refresh CBR Refresh H L ROW 1,2 1 2,3 High-Z High-Z Notes: 1. These READ cycles may also be BYTE READ cycles (either UCAS or LCAS active). 2. These WRITE cycles may also be BYTE READ cycles (either UCAS or LCAS active). 3. EARLY WRITE only. 4. At least one of the two CAS signals must be active ( UCAS or LCAS ). DC and Operating Characteristics (1-2) q q r TA = 0 C to 70 C, VCC=5V 10%, VSS=0V, unless otherwise specified. G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -5- 4 G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT May 1997 (Rev 1) Sym . Parameter ILI Input Leakage Current (any input pin) ILO Output Leakage Current (for High-Z State) Operating Current, Random READ/WRITE ICC1 ICC2 Standby Current,(TTL) ICC3 Refresh Current, RAS -Only ICC4 Operating Current, EDO Page Mode Test Conditions d d d d 0V VIN 5.5V (All other pins not under test=0V) 0V Vout 5.5V Output is disabled (Hiz) CAS Before RAS Min. Typ Max. +10 PA -10 +10 PA 170 160 150 140 RAS , UCAS , LCAS at VIH other inputs VSS t RAS cycling, UCAS , LCAS at VIH tRC = tRC (min.) RAS at VIL, RAS , UCAS , LCAS address cycling: tRC = tRC (min.) Unit Notes -10 tRAC = 35ns tRAC = 40ns tRAC = 45ns tRAC = 50ns tRC = tRC (min.) UCAS , LCAS address cycling: tPC = tPC(min.) ICC5 Refresh Current, Access Time 2 170 160 150 140 170 160 150 140 170 160 150 140 tRAC = 35ns tRAC = 40ns tRAC = 45ns tRAC = 50ns tRAC = 35ns tRAC = 40ns tRAC = 45ns tRAC = 50ns tRAC = 35ns tRAC = 40ns tRAC = 45ns tRAC = 50ns t ICC6 Standby Current, (CMOS) RAS VCC-0.2V, t LCAS tV mA 1,2 mA mA 2 mA 1,2 mA 1 1 mA +0.8 VCC+1 0.4 V V V V UCAS VCC-0.2V, CC-0.2V, All other inputs VSS VIL VIH VOL VOH Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage -1 2.4 IOL = 4.2mA IOH = -5mA 2.4 3 3 Notes: 1. ICC is dependent on output loading when the device output is selected. Specified I CC(max.) is measured with the output open. 2. ICC is dependent upon the number of address transitions specified ICC(max.) is measured with a maximum of one transition per address cycle in random Read/Write and EDO Fast Page Mode. 3. Specified VIL(min.) is steady state operation. During transitions VIL(min.) may undershoot to -1.0V for a period not to exceed 20ns. All AC parameters are measured with VIL(min.) VSS and VIH(max.) VCC. t d AC Characteristics TA = 0qC to 70qC , VCC = 5 V r 10, VIH/VIL = 2.4/0.8 V, VOH/VOL = 2.0/0.8V An initial pause of 100 Ps and 8 CAS -before- RAS or RAS -only refresh cycles are required after power-up. G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -6- G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT May 1997 (Rev 1) 35 40 45 50 Parameter Symbol Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes Read or Write Cycle Time tRC 70 75 80 90 ns Read Modify Write Cycle Time tRWC 87 93 103 109 ns RAS Precharge Time tRP 25 25 30 30 ns RAS Pulse Width tRAS 35 100k 40 100k 45 100k 50 100k ns Access Time from RAS tRAC 35 40 45 50 ns 1,2,3 tCAC 11 12 12 13 ns 1,5,10 tAA 18 20 22 25 ns 1,5,6 Access Time from CAS Access Time from Column Address CAS to Output Low-Z tCLZ 0 CAS to Output High-Z tCEZ 3 RAS Hold Time tRSH 12 12 13 14 ns RAS Hold Time Referenced to OE tROH 8 8 9 9 ns CAS Hold Time tCSH 30 34 40 45 ns CAS Pulse Width tCAS 6 10k 6 10K 7 10K 8 10K ns RAS to CAS Delay Time tRCD 17 24 18 28 18 33 19 37 ns RAS to Column Address Delay Time tRAD 12 17 13 20 13 23 14 25 ns tCRP 5 5 5 5 ns CAS to RAS Precharge Time Row Address Set-Up Time 0 8 0 3 8 0 3 8 3 ns 8 ns 7 tASR 0 0 0 0 ns Row Address Hold Time tRAH 7 8 8 9 ns Column Address Set-Up Time tASC 0 0 0 0 ns Column Address Hold Time tCAH 6 6 6 7 ns Column Address to RAS Lead Time tRAL 18 20 23 25 ns t 30 34 39 44 ns 0 0 0 0 ns tRCH 0 0 0 0 ns 4 Read Command Hold Time Referenced to RAS RRH Write Command Set-Up Time tWCS t 0 0 0 0 ns 4 0 0 0 0 ns 8,9 Write Command Hold Time tWCH 6 6 6 7 ns Write Command Pulse Width tWP 6 6 6 7 ns Column Address Hold Time Referenced to RAS AR Read Command Set-Up Time tRCS Read Command Hold Time Referenced to CAS AC Characteristics 35 40 45 50 Parameter Symbol Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes Write Command to RAS Lead Time tRWL 11 12 12 13 ns G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -7- G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT May 1997 (Rev 1) Write Command to CAS Lead Time Data Set-Up Time tCWL 11 12 12 13 ns tDS 0 0 0 0 ns Data Hold Time tDH 7 8 8 9 ns Data Hold Time Referenced to RAS tDHR 31 36 41 46 ns RAS to WE Delay Time tRWD 49 54 59 64 ns tCWD 23 24 24 25 ns tAWD 30 32 34 37 ns tRPC 0 0 0 0 ns CAS to WE Delay Time Column Address to WE Delay Time RAS to CAS Precharge Time Access Time from CAS Precharge EDO Page Mode Cycle Time tCPA tPC EDO Page Mode Read-Modify-Write Cycle Time tPRWC 20 22 24 30 ns 13 15 18 20 ns 47 50 52 59 ns 5 7 8 ns CAS Precharge Time (EDO Page Mode) tCP 5 RAS Pulse Width (EDO Page Mode Only) tRASP 35 100k 40 100k 45 100k 50 100k ns Access Time from OE tOEA OE to Data Delay Time tOED 8 OE to Output High-Z tOEZ 3 OE Command Hold Time tOEH 6 7 7 7 ns Data Output Hold after CAS low tDOH 3 3 5 5 ns RAS to Output High-Z tREZ 3 8 3 8 3 8 3 8 ns WE to Output High-Z tWEZ 3 10 3 10 3 10 3 12 ns OE to CAS Hold Time tOCH 8 8 8 8 ns CAS Hold Time to OE tCHO 8 8 8 8 ns OE Precharge Time tOEP 8 8 8 8 ns CAS Set-Up Time for CAS -before- RAS Cycle tCSR 10 10 10 10 ns tCHR 10 10 10 10 ns tT 2 CAS Hold Time for CAS -before- RAS Cycle Transition Time Refresh Period 11 tREF 12 8 8 50 4 3 2 12 8 8 50 4 3 2 13 8 8 50 4 3 2 ns ns 8 ns 50 ns 4 ms Notes: 1. Measure with a load equivalent to two TTL inputs and 50 pF. 2. Assumes that tRCD d tRCD (max.). If tRCD is greater than tRCD (max.), access time will be tAA dominant. 3. Assumes that tRAD d tRAD (max.). If tRAD is greater than tRCD (max.), access time will be G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -8- G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT May 1997 (Rev 1) controlled by tCAC. 4. Either tRRH or tRCH must be satisfied for a Read Cycle. 5. Access time is determined by the longest of tAA, tCAC and tCPA. 6. Assumes that tRAD t tRAD (max.). 7. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by t AA and tCAC. 8. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. 9. tWCS (min.) must be satisfied in an Early Write Cycle. 10. tDS and tDH are referenced to the latter occurrence of CAS of WE . 11. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 2 ns. G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -9- G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT May 1997 (Rev 1) Read CYCLE Note : DIN = OPEN G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 10 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT May 1997 (Rev 1) Early Write Cycle NOTE : DOUT = OPEN OETechnology Controlled Write Cycle G-Link Corporation G-Link Technology Corporation, Taiwan 2701Northwestern NOTE : DParkway OUT = OPEN Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 11 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT May 1997 (Rev 1) Read - Modify - Write Cycle G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 12 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT May 1997 (Rev 1) EDO Page Mode Read Cycle G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 13 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT May 1997 (Rev 1) EDO Page Mode Early Write Cycle NOTE : DOUT = OPEN G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 14 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT May 1997 (Rev 1) EDO Page Mode Read - Modify - Write Cycle NOTE : DOUT = OPEN G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 15 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT May 1997 (Rev 1) CAS - Before - RAS Refresh Cycle G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 16 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT May 1997 (Rev 1) RAS-Only Refresh Cycle Hidden Refresh Cycle ( Read ) G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 17 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT May 1997 (Rev 1) Hidden Refresh Cycle ( Write ) NOTE : DOUT = OPEN G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 18 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT May 1997 (Rev 1) CAS -Before- RAS Refresh Counter Test Cycle G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 19 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT May 1997 (Rev 1) Read Cycle Write Cycle Read-Modify-Write Ordering Information G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 20 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT May 1997 (Rev 1) Part Number GLT41016-35J4 GLT41016-40J4 GLT41016-45J4 GLT41016-50J4 GLT41016-35TC GLT41016-40TC GLT41016-45TC GLT41016-50TC SPEED 35ns 40ns 45ns 50ns 35ns 40ns 45ns 50ns POWER Normal Normal Normal Normal Normal Normal Normal Normal FEATURE EDO EDO EDO EDO EDO EDO EDO EDO PACKAGE SOJ 400mil 40L SOJ 400mil 40L SOJ 400mil 40L SOJ 400mil 40L TSOP 400mil 44L TSOP 400mil 44L TSOP 400mil 44L TSOP 400mil 44L Parts Numbers (Top Mark) Definition : GLT 4 10 4 : DRAM 6 : Standard SRAM 7 : Cache SRAM 8 : Synchronous Burst SRAM -SRAM 064 : 8K 256 : 256K 512 : 512K 100 : 1M -DRAM 10 : 1M(C/EDO)* 11 : 1M(C/FPM)* 12 : 1M(H/EDO)* 13 : 1M(H/FPM)* 20 : 2M(EDO) 21 : 2M(FPM) 40 : 4M(EDO) 41 : 4M(FPM) 80 : 8M(EDO) 81 : 8M(FPM) *See note 16 - 40 J4 CONFIG. 04 : x04 08 : x08 16 : x16 32 : x32 VOLTAGE Blank : 5V L : 3.3V M : Mix Voltage SPEED -SRAM 12 : 12ns 15 : 15ns 20 : 20ns 70 : 70ns -DRAM 35 : 35ns 40 : 40ns 45 : 45ns 50 : 50ns 60 : 60ns PACKAGE T : PDIP(300mil) TS : TSOP(Type I) TC : TSOP(Type ll) PL : PLCC FA : 300mil SOP FB : 330mil SOP FC : 445mil SOP J3 : 300mil SOJ J4 : 400mil SOJ P : PDIP(600mil) Q : PQFP TQ : TQFP Note : CCDROM , HHDD. Example : 1.GLT710008-15T 1Mbit(128Kx8)15ns 5V SRAM PDIP(300mil)Package type. 2.GLT44016-40J4 4Mbit(256Kx16)40ns 5V DRAM SOJ(400mil)Package type. G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 21 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT May 1997 (Rev 1) Package Information 400mil 40 pin Small Outline J-form Package (SOJ) 40/44 Lead Thin Small Outline Package TSOP(Type II) G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 22 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT May 1997 (Rev 1) G-Link Technology Corporation G-Link Technology Corporation, Taiwan 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 23 -