Micro PMU with 800 mA Buck, 300 mA LDO, Supervisory, Watchdog, and Manual Reset ADP5043 Data Sheet FEATURES GENERAL DESCRIPTION Input voltage range: 2.3 V to 5.5 V One 800 mA buck regulator One 300 mA LDO 20-lead, 4 mm x 4 mm LFCSP package Initial regulator accuracy: 1% Overcurrent and thermal protection Soft start Undervoltage lockout Open-drain processor reset with threshold monitoring 1.5% threshold accuracy over the full temperate range Guaranteed reset output valid to VCC = 1 V Dual watchdog for secure systems Watchdog 1 controls reset Watchdog 2 controls reset and regulators power cycle Buck regulator key specifications Current-mode topology for excellent transient response 3 MHz operating frequency Uses tiny multilayer inductors and capacitors Mode pin selects forced PWM or auto PFM/PSM modes 100% duty cycle low dropout mode LDO key specifications Low VIN from 1.7 V to 5.5 V Stable with1 F ceramic output capacitors High PSRR, 60 dB up to 1 kHz/10 kHz Low output noise Low dropout voltage: 150 mV at 300 mA load -40C to +125C junction temperature range The ADP5043 combines one high performance buck regulator and one low dropout regulator (LDO) in a small 20-lead LFCSP to meet demanding performance and board space requirements. The high switching frequency of the buck regulator enables use of tiny multilayer external components and minimizes board space. The MODE pin selects the buck's mode of operation. When set to logic high, the buck regulator operates in forced PWM mode. When the MODE pin is set to logic low, the buck regulator operates in PWM mode when the load is around the nominal value. When the load current falls below a predefined threshold, the regulator operates in power save mode (PSM) improving the light-load efficiency. The low quiescent current, low dropout voltage, and wide input voltage range of the ADP5043 LDO extend the battery life of portable devices. The LDO maintains a power supply rejection of greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage. Each regulator is activated by a high level on the respective enable pin. The ADP5043 is available with factory programmable default output voltages and can be set to a wide range of options. The ADP5043 contains supervisory circuits that monitor power supply voltage levels and code execution integrity in microprocessor-based systems. The ADP5043 also provides power-on reset signals. An on-chip dual watchdog timer can reset the microprocessor or power cycle the system (Watchdog 2) if it fails to strobe within a preset timeout period. HIGH LEVEL BLOCK DIAGRAM ADP5043 AVIN VIN1 L1 1H VOUT1 BUCK C6 10F PGND C5 4.7F EN_BK ON MODE EN1 OFF VIN2 = 1.7V TO 5.5V SW PSM/PWM LDO C2 1F EN_LDO ON OFF FPWM VOUT2 VIN2 C1 1F VOUT1 @ 800mA EN2 AVIN SUPERVISOR WSTAT MR NC NC nRSTO WDI1 WDI2 WMOD GND AGND GND VOUT2 @ 300mA MICROPROCESSOR VIN1 = 2.3V TO 5.5V AVIN VIN WD1 MODE SELECTION 09682-001 RFILT 30 Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2011 Analog Devices, Inc. All rights reserved. ADP5043 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power Management Unit........................................................... 16 General Description ......................................................................... 1 Buck Section................................................................................ 17 High Level Block Diagram .............................................................. 1 LDO Section ............................................................................... 18 Revision History ............................................................................... 2 Supervisory Section ................................................................... 18 Specifications..................................................................................... 3 Applications Information .............................................................. 21 General Specifications ................................................................. 3 Buck External Component Selection....................................... 21 Supervisory Specifications .......................................................... 3 LDO Capacitor Selection .......................................................... 22 Buck Specifications....................................................................... 5 Supervisory Section ................................................................... 23 LDO Specifications ...................................................................... 5 PCB Layout Guidelines.............................................................. 24 Input and Output Capacitor, Recommended Specifications .. 6 Power Dissipation/Thermal Considerations ............................. 25 Absolute Maximum Ratings............................................................ 7 Evaluation Board Schematics and Artwork ............................ 27 Thermal Data ................................................................................ 7 Suggested Layout ........................................................................ 27 Thermal Resistance ...................................................................... 7 Bill of Materials ........................................................................... 28 ESD Caution .................................................................................. 7 Application Diagram ................................................................. 28 Pin Configuration and Function Descriptions ............................. 8 Factory Programmable Options ................................................... 29 Typical Performance Characteristics ............................................. 9 Outline Dimensions ....................................................................... 30 Theory of Operation ...................................................................... 16 Ordering Guide .......................................................................... 30 REVISION HISTORY 10/11--Rev. 0 to Rev. A Updated Outline Dimensions ....................................................... 30 Changes to Ordering Guide .......................................................... 30 4/11--Revision 0: Initial Version Rev. A | Page 2 of 32 Data Sheet ADP5043 SPECIFICATIONS GENERAL SPECIFICATIONS AVIN, VIN1 = (VOUT1 + 0.5 V) or 2.3 V, whichever is greater, AVIN, VIN1 VIN2, TA = 25C, unless otherwise noted. Regulators are enabled. Table 1. Parameter AVIN UNDERVOLTAGE LOCKOUT Input Voltage Rising Option A Option B Input Voltage Falling Option A Option B SHUTDOWN CURRENT Thermal Shutdown Threshold Thermal Shutdown Hysteresis ENx, WDIx, MODE, WMOD, MR INPUTS Input Logic High Input Logic Low Input Leakage Current (WMOD Excluded) WMOD Input Leakage Current OPEN-DRAIN OUTPUTS nRSTO, WSTAT Output Voltage Open-Drain Reset Output Leakage Current Symbol UVLOAVIN UVLOAVINRISE Test Conditions/Comments TJ = -40C to +125C Min Typ Max Unit 2.25 3.9 V V UVLOAVINFALL 1.95 3.1 IGND-SD TSSD TSSD-HYS VIH VIL VI-LEAKAGE ENx = GND ENx = GND, TJ = -40C to +125C TJ rising VI-LKG-WMOD 2.5 V AVIN 5.5 V 2.5 V AVIN 5.5 V ENx = AVIN or GND ENx = AVIN or GND, TJ = -40C to +125C VWMOD = 3.6 V, TJ = -40C to +125C VOL AVIN = 2.3 V to 5.5 V, InRSTO/WSTAT = 3 mA 0.1 2 150 20 1.2 1 50 V V A A A 1 mV A 0.4 0.05 30 SUPERVISORY SPECIFICATIONS AVIN, VIN1 = full operating range, TJ = -40C to +125C, unless otherwise noted. Table 2. Parameter SUPPLY Supply Current (Supervisory Circuit Only) Min Typ Max Unit Test Conditions/Comments RESET THRESHOLD ACCURACY VTH - 0.8% VTH - 1.5% 50 45 43 VTH VTH 125 55 52 VTH + 0.8% VTH + 1.5% 400 A A V V s AVIN = 5.5 V, EN1 = EN2 = VIN1 AVIN = 3.6 V, EN1 = EN2 = VIN1 TA = 25C, sensed on VOUTx TJ = -40C to +125C, sensed on VOUTx VTH = VOUT - 50 mV 30 200 5 150 2 36 240 7 ms ms ms s ms 102 1.6 122.4 1.92 RESET THRESHOLD TO OUTPUT DELAY GLITCH IMMUNITY (tUOD) RESET TIMEOUT PERIOD WATCHDOG1 (tRP1) Option A Option B RESET TIMEOUT PERIOD WATCHDOG2 (tRP2) VCC TO RESET DELAY (tRD) REGULATORS SEQUENCING DELAY (tD1, tD2) WATCHDOG INPUTS Watchdog 1 Timeout Period (tWD1) Option A Option B 24 160 3.5 81.6 1.28 Rev. A | Page 3 of 32 ms sec VIN1 falling at 1 mV/s V V A A C C ADP5043 Parameter Watchdog 2 Timeout Period (tWD2) Option A Option B Option C Option D Option E Option F Option G Option H Watchdog 2 Power Off Period (tPOFF) Option A Option B WDI1 Pulse Width WDI2 Pulse Width Watchdog Status Timeout Period (tWDCLEAR) WDI1 Input Current (Source) WDI1 Input Current (Sink) WDI2 Internal Pull-Down MANUAL RESET INPUT MR Input Pulse Width MR Glitch Rejection MR Pull-Up Resistance MR to Reset Delay Data Sheet Min Typ Max 6 7.5 9 Watchdog 2 disabled 3.2 4 4.8 6.4 8 9.6 11.2 16 19.2 25.6 32 38.4 51.2 64 76.8 102.4 128 153.8 210 400 80 8 8 -30 11.2 15 -25 45 20 -14 1 25 220 52 280 80 Rev. A | Page 4 of 32 Unit Test Conditions/Comments sec min min min min min min ms ms ns s sec A A k s ns k ns VIL = 0.4 V, VIH = 1.2 V VIL = 0.4 V, VIH = 1.2 V VWDI1 = VCC, time average VWDI1 = 0, time average VCC = 5 V Data Sheet ADP5043 BUCK SPECIFICATIONS AVIN, VIN1 = 3.6 V, VOUT1 = 1.8 V, TJ = -40C to +125C for minimum/maximum specifications, L = 1 H, COUT = 10 F, and TA = 25C for typical specifications, unless otherwise noted. 1 Table 3. Parameter INPUT CHARACTERISTICS Input Voltage Range (VIN1) OUTPUT CHARACTERISTICS Output Voltage Accuracy Test Conditions/Comments PWM mode, ILOAD = 100 mA PSM mode VIN1 = 2.3 V to 5.5 V, PWM mode, ILOAD = 1 mA to 800 mA PWM TO POWER SAVE MODE CURRENT THRESHOLD INPUT CURRENT CHARACTERISTICS DC Operating Current Shutdown Current SW CHARACTERISTICS SW On Resistance Current Limit ACTIVE PULL-DOWN OSCILLATOR FREQUENCY START-UP TIME 1 Min Typ Max Unit 2.3 5.5 V -1 -2 -3 +1 +2 +3 % % % 100 mA ILOAD = 0 mA, device not switching ENx = 0 V, TA = TJ = -40C to +125C 21 0.2 35 1.0 A A PFET PFET, AVIN = VIN1 = 5 V NFET NFET, AVIN = VIN1 = 5 V PFET switch peak current limit EN1 = 0 V 180 140 170 150 1360 75 3.0 250 240 190 235 210 1600 m m m m mA MHz s 1100 2.5 3.5 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). LDO SPECIFICATIONS AVIN = 3.6 V, VIN2 = (VOUT2 + 0.2 V) or 2.3 V, whichever is greater; AVIN, VIN1 VIN2; IOUT = 10 mA; CIN = COUT = 1 F; TA = 25C, unless otherwise noted. Table 4. Parameter INPUT VOLTAGE RANGE OPERATING SUPPLY CURRENT (per LDO) FIXED OUTPUT VOLTAGE ACCURACY Symbol VIN2 IGND VOUT2 Test Conditions/Comments TJ = -40C to +125C IOUT = 0 A, VOUT = 3.3 V IOUT = 0 A, VOUT = 3.3 V, TJ = -40C to +125C IOUT = 10 mA IOUT = 10 mA, TJ = -40C to +125C IOUT = 200 mA IOUT = 200 mA, TJ = -40C to +125C IOUT = 10 mA 100 A < IOUT < 300 mA VIN2 = (VOUT2 + 0.5 V) to 5.5 V 100 A < IOUT < 300 mA VIN2 = (VOUT2 + 0.5 V) to 5.5 V TJ = -40C to +125C Rev. A | Page 5 of 32 Min 1.7 Typ Max 5.5 15 50 67 Unit V A A -1 -2 245 +1 +2 A A A A % % -3 +3 % 105 100 ADP5043 Parameter REGULATION Line Regulation Load Regulation 1 DROPOUT VOLTAGE 2 ACTIVE PULL-DOWN START-UP TIME CURRENT-LIMIT THRESHOLD 3 OUTPUT NOISE POWER SUPPLY REJECTION RATIO Data Sheet Symbol Test Conditions/Comments Min VOUT2/VIN2 VIN2= (VOUT2 + 0.5 V) to 5.5 V IOUT2 = 1 mA TJ = -40C to +125C IOUT2 = 1 mA to 200 mA IOUT2 = 1 mA to 200 mA TJ = -40C to +125C VOUT2 = 3.3 V IOUT2 = 10 mA IOUT2 = 10 mA, TJ = -40C to +125C IOUT2 = 200 mA IOUT2 = 200 mA, TJ = -40C to +125C EN2 = 0 V VOUT2 = 3.3 V TJ = -40C to +125C 10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 3.3 V 10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 2.8 V 10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 1.5 V 1 kHz, VIN2 = 3.3 V, VOUT2 = 2.8 V, IOUT = 100 mA 100 kHz, VIN2 = 3.3 V, VOUT2 = 2.8 V, IOUT = 100 mA 1 MHz, VIN2 = 3.3 V, VOUT2 = 2.8 V, IOUT = 100 mA -0.03 VOUT2/IOUT2 VDROPOUT RPDLDO TSTART-UP ILIMIT OUTLDONOISE PSRR Typ Max Unit +0.03 %/ V 0.0075 %/mA %/mA 0.002 4 600 85 470 123 mV mV mV mV s mA V rms 110 V rms 59 V rms 66 dB 57 dB 60 dB 5 60 100 335 Based on an end-point calculation using 1 mA and 100 mA loads. Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages above 2.3 V. 3 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V. 1 2 INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS Table 5. Parameter OUTPUT CAPACITANCE (BUCK)1 MINIMUM INPUT AND OUTPUT CAPACITANCE2 (LDO) CAPACITOR ESR Symbol CMIN1 CMIN2 RESR Test Conditions/Comments TJ = -40C to +125C TJ = -40C to +125C TJ = -40C to +125C Min 7 0.70 0.001 Typ Max 40 1 Unit F F The minimum output capacitance should be greater than 4.7 F over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. 2 The minimum input and output capacitance should be greater than 0.70 F over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended, Y5V and Z5U capacitors are not recommended for use with LDOs or the buck. 1 Rev. A | Page 6 of 32 Data Sheet ADP5043 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Rating AVIN, VINx, VOUTx, ENx, MODE, MR, WDIx, WMOD, WSTAT, nRSTO to GND Storage Temperature Range Operating Junction Temperature Range Soldering Conditions ESD Human Body Model ESD Charged Device Model ESD Machine Model -0.3 V to +6 V -65C to +150C -40C to +125C JEDEC J-STD-020 3000 V 1500 V 100 V Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Junction-to-ambient thermal resistance (JA) of the package is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal board design is required. The value of JA may vary, depending on PCB material, layout, and environmental conditions. The specified value of JA is based on a four-layer, 4" x 3", 2.5 oz copper board, as per JEDEC standard. For additional information, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale (LFCSP). THERMAL RESISTANCE JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 7. Thermal Resistance Package Type 20-Lead, 0.5 mm pitch LFCSP THERMAL DATA Absolute maximum ratings apply individually only, not in combination. ESD CAUTION The ADP5043 can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that the junction temperature is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. In applications with moderate power dissipation and low PCB thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature of the device is dependent on the ambient temperature, the power dissipation of the device (PD), and the junction-to-ambient thermal resistance of the package. Maximum junction temperature is calculated from the ambient temperature and power dissipation using the formula TJ = TA + (PD x JA) Rev. A | Page 7 of 32 JA 38 JC 4.2 Unit C/W ADP5043 Data Sheet 20 19 18 17 16 MR WDI1 WMOD MODE GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 ADP5043 TOP VIEW (Not to Scale) 15 14 13 12 11 WSTAT NC GND WDI2 VOUT1 NOTES 1. EXPOSED PAD SHOULD BE CONNECTED TO AGND. 2. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. THE PIN SHOULD BE LEFT FLOATING. 09682-002 AVIN 6 VIN1 7 SW 8 PGND 9 EN1 10 NC VOUT2 VIN2 EN2 nRSTO Figure 2. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mnemonic NC VOUT2 VIN2 EN2 nRSTO AVIN VIN1 SW PGND EN1 VOUT1 WDI2 GND NC WSTAT 16 17 GND MODE 18 WMOD 19 20 TP WDI1 MR AGND Description Do not connect to this pin. The pin should be left floating. LDO Output Voltage and Sensing Input. LDO Input Supply (1.7 V to 5.5 V). Enable LDO. EN2 = high: turn on the LDO; EN2 = low: turn off the LDO. Open-Drain Reset Output, Active Low. Regulators Housekeeping and Supervisory Input Supply (2.3 V to 5.5 V). Buck Input Supply (2.3 V to 5.5 V). Buck Switching Node. Dedicated Power Ground for Buck Regulator. Enable Buck. EN1 = high: turn on buck; EN1 = low: turn off buck. Buck Sensing Node. Watchdog 2 (Long Timeout) Refresh Input from Processor. This pin can be disabled only by a factory option. Connect to the ground plane. Do not connect to this pin. The pin should be left floating. Open-Drain Watchdog Timeout Status. WSTAT = high: Watchdog 1 timeout or power-on reset; WSTAT = low: Watchdog 2 timeout. Auto cleared after one second. Connect to the ground plane. Buck Mode. MODE = high: buck regulator operates in fixed PWM mode; MODE = low: (auto mode) buck regulator operates in power save mode (PSM) at light load and in constant PWM at higher load. Watchdog Mode. WMOD = low: Watchdog 1 normal mode; WMOD = high: Watchdog 1 cannot be disabled by a three-state condition applied on WDI1. WMOD has an internal 200 k pull-down resistor connected to AGND. Watchdog 1 Refresh Input from Processor. If WDI1 is in high-Z and WMOD is low, Watchdog 1 is disabled. Manual Reset Input, Active Low. Analog Ground (TP = Exposed Thermal Pad). Exposed pad should be connected to AGND. Rev. A | Page 8 of 32 Data Sheet ADP5043 TYPICAL PERFORMANCE CHARACTERISTICS VIN1 = VIN2 = AVIN = 5.0 V, TA = 25C, unless otherwise noted. 3.34 -40C +25C +85C 3.32 1 OUTPUT VOLTAGE (V) VOUT1 VOUT2 2 3.30 3.28 3.26 A CH1 1.76V 200s/DIV 20.0ns/pt 3.22 09682-003 CH1 2.0V/DIV 1M BW 20.0M CH2 2.0V/DIV 1M BW 20.0M 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Figure 6. Buck Load Regulation Across Temperature, VOUT1 = 3.3 V, Auto Mode 1.830 0.9 1.825 0.8 1.820 OUTPUT VOLTAGE (V) 1.0 0.7 0.6 0.5 0.4 0.3 VOUT1 = 1.5V, VOUT2 = 3.3V 0.2 0.1 OUTPUT CURRENT (A) Figure 3. 3-Channel Start-Up Waveforms -40C +25C +85C 1.815 1.810 1.805 1.800 1.795 1.790 1.785 0.1 3.3 3.8 4.3 4.8 1.775 09682-004 2.8 5.3 INPUT VOLTAGE (V) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 OUTPUT CURRENT (A) Figure 4. System Quiescent Current (Sum of All the Input Currents) vs. Input Voltage, VOUT1 = 1.5 V, VOUT2 = 3.3 V 09682-008 1.780 0 2.3 Figure 7. Buck Load Regulation Across Temperature, VOUT1 = 1.8 V, Auto Mode 1.795 SW 4 1.794 +85C 1.793 VOUT1 OUTPUT VOLTAGE (V) 2 EN 1 IIN +25C 1.791 1.790 1.789 1.788 1.787 1.786 CH1 CH2 CH3 CH4 2.0V/DIV 2.0V/DIV 100mA/DIV 5.0V/DIV 1M BW 20.0M A CH1 1M BW 500M 1M BW 20.0M 1M BW 500M 2.92V 50s/DIV 50.0MS/s 20.0ns/pt -40C 1.785 1.784 09682-005 3 1.792 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 OUTPUT CURRENT (A) Figure 5. Buck Startup, VOUT1 = 1.8 V, IOUT1 = 20 mA Figure 8. Buck Load Regulation Across Temperature, VOUT1 = 1.8 V, PWM Mode Rev. A | Page 9 of 32 09682-009 SYSTEM QUIESCENT CURRENT (mA) 0 09682-007 3.24 ADP5043 Data Sheet 100 1.797 90 1.796 70 VIN = 5.5V 1.794 VIN = 4.5V 1.793 VIN = 3.6V 60 50 40 30 1.792 20 1.791 10 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 0.0001 OUTPUT CURRENT (A) 90 90 80 80 70 70 EFFICIENCY (%) 1 60 50 40 2.4V 3.6V 4.5V 5.5V 60 50 40 30 20 20 3.6V 4.5V 5.5V 0 0.0001 0.001 0.01 0.1 10 1 OUTPUT CURRENT (A) 0 0.001 09682-011 10 0.01 0.1 1 OUTPUT CURRENT (A) Figure 10. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.3 V, Auto Mode 09682-014 EFFICIENCY (%) 100 30 Figure 13. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1= 1.8 V, PWM Mode 100 100 3.6V 4.5V 5.5V 90 80 70 70 EFFICIENCY (%) 80 60 50 40 50 40 30 20 20 10 10 0.01 0.1 1 OUTPUT CURRENT (A) Figure 11. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.3 V, PWM Mode -40C +25C +85C 60 30 0 0.001 09682-012 EFFICIENCY (%) 0.1 Figure 12. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 1.8 V, Auto Mode 100 0 0.001 0.01 OUTPUT CURRENT (A) Figure 9. Buck Load Regulation Across Input Voltage, VOUT1 = 1.8 V, PWM Mode 90 0.001 0.01 0.1 OUTPUT CURRENT (A) 1 09682-015 0 09682-010 1.790 2.4V 3.6V 4.5V 5.5V 09682-013 1.795 EFFICIENCY (%) OUTPUT VOLTAGE (V) 80 Figure 14. Buck Efficiency vs. Load Current, Across Temperature, VOUT1 = 1.8 V, PWM Mode Rev. A | Page 10 of 32 Data Sheet 100 90 ADP5043 3.10 -40C +25C +85C -40C 3.05 80 FREQUENCY (MHz) EFFICIENCY (%) 70 60 50 40 30 +25C 3.00 2.95 +85C 2.90 20 0.001 0.01 0.1 1 OUTPUT CURRENT (A) 2.85 09682-016 0 0.0001 0 0.1 0.3 0.4 0.5 0.6 0.7 0.8 OUTPUT CURRENT (A) Figure 15. Buck Efficiency vs. Load Current, Across Temperature, VOUT1 = 3.3 V, Auto Mode Figure 18. Buck Switching Frequency vs. Output Current, Across Temperature, VOUT1 = 1.8 V, PWM Mode 100 90 0.2 09682-019 10 VOUT -40C +25C +85C 1 80 EFFICIENCY (%) 70 ISW 60 2 50 40 SW 30 20 10 0.01 0.1 1 OUTPUT CURRENT (A) B 20.0M CH1 20.0mV/DIV W CH2 200mA/DIV 1M BW 20.0M CH3 2.0V/DIV 1M BW 20.0M Figure 16. Buck Efficiency vs. Load Current, Across Temperature, VOUT1 = 1.8 V, Auto Mode A CH1 2.4mV 5.0s/DIV 20.0MS/s 50.0ns/pt 09682-020 0.001 09682-017 0 0.0001 3 Figure 19. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, Auto Mode 1.7 VOUTx 2 1.5 ISW 1.4 3 1.3 SW 1.2 1.1 3.6 4.6 INPUT VOLTAGE (V) 5.6 CH1 2.0V/DIV 1M BW 20.0M B 20.0M CH2 50.0mV/DIV W B 20.0M CH3 500mA/DIV W 09682-018 1.0 2.6 1 Figure 17. Buck DC Current Capability vs. Input Voltage, VOUT1 = 1.8 V A CH1 1.56mV 5.0s/DIV 200MS/s 5.0ns/pt 09682-021 OUTPUT CURRENT (A) 1.6 Figure 20. Typical Waveforms, VOUT1 = 1.8 V, IOUT1= 30 mA, Auto Mode Rev. A | Page 11 of 32 ADP5043 Data Sheet VOUTx 2 VINx ISW VOUTx 3 2 SW SW 3 A CH1 1.56mV 500ns/DIV 200MS/s 5.0ns/pt B 20.0M A CH3 CH2 50mV/DIV W CH3 1V/DIV 1M BW 20.0M CH4 2V/DIV 1M BW 20.0M 09682-022 CH1 2.0V/DIV 1M BW 20.0M B 20.0M CH2 50.0mV/DIV W B 20.0M CH3 500mA/DIV W Figure 21. Typical Waveforms, VOUT1 = 1.8 V, IOUT1 = 30 mA, PWM Mode 1 4.96mV 100s/DIV 20MS/s 100ns/pt 09682-025 4 1 Figure 24. Buck Response to Line Transient, VIN = 4.5 V to 5.0 V, VOUT1 = 1.8 V, PWM Mode VOUTx SW 1 2 ISW VOUTx 2 SW 2.4mV 200ns/DIV 500MS/s 2.0ns/pt B 20.0M CH1 4V/DIV W CH2 50mV/DIV 1M BW 20.0M CH3 50mA/DIV 1M BW 20.0M 09682-023 B 20.0M A CH1 CH1 20.0mV/DIV W CH2 200mA/DIV 1M BW 20.0M CH3 2.0V/DIV 1M BW 20.0M IOUT Figure 22. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, PWM Mode A CH3 44mA 200s/DIV 10MS/s 100ns/pt 09682-026 3 3 Figure 25. Buck Response to Load Transient, IOUT1 from 1 mA to 50 mA, VOUT1 = 3.3 V, Auto Mode SW 1 VINx VOUTx 2 VOUTx VOUT 2 SW 1 3 LOAD A CH3 4.79V 100s/DIV 10.0MS/s 100ns/pt B 20.0M CH1 4V/DIV W B 20.0M CH2 50mV/DIV W B CH3 50mA/DIV 1M W 20.0M 09682-024 B 20.0M CH1 3V/DIV W B 20.0M CH2 50mV/DIV W B CH3 900mV/DIV 1M W 20.0M Figure 23. Buck Response to Line Transient, Input Voltage from 4.5 V to 5.0 V, VOUT1 = 3.3 V, PWM Mode A CH3 28mA 200s/DIV 5MS/s 200ns/pt 09682-027 3 Figure 26. Buck Response to Load Transient, IOUT2 from 1 mA to 50 mA, VOUT1 = 1.8 V, Auto Mode Rev. A | Page 12 of 32 Data Sheet ADP5043 3.35 SW 3.34 1 3.6V 4.5V 5.0V 5.5V OUTPUT VOLTAGE (V) 3.33 VOUTx 2 3.32 3.31 3.30 3.29 3.28 LOAD 3.27 3 200s/DIV 10MS/s 100ns/pt 3.25 0.0001 09682-028 86mA 0.001 0.01 0.1 OUTPUT CURRENT (A) Figure 27. Buck Response to Load Transient, IOUT1 from 20 mA to 140 mA, VOUT1 = 3.3 V, Auto Mode 09682-035 3.26 B 20.0M A CH3 CH1 4V/DIV W B 20.0M CH2 50mV/DIV W CH3 50mA/DIV 1M BW 20.0M Figure 30. LDO Load Regulation Across Input Voltage, VOUT2 = 3.3 V 3.35 SW 3.34 +85C +25C -40C 2 OUTPUT VOLTAGE (V) 3.33 VOUT1 3 LOAD 3.32 3.31 3.30 3.29 3.28 3.27 4 145mA 200s/DIV 50MS/s 20ns/pt 3.25 0.0001 09682-029 CH2 4V/DIV CH3 50mV/DIV CH4 50mA/DIV 0.001 0.01 0.1 OUTPUT CURRENT (A) 09682-036 3.26 1M BW 20.0M A CH3 1M BW 20.0M 1M BW 20.0M Figure 31. LDO Load Regulation Across Temperature, VIN2 = 3.6 V, VOUT2 = 3.3 V Figure 28. Buck Response to Load Transient, IOUT1 = 20 mA to 180 mA, VOUT1 = 1.8 V, PWM Mode 3.325 3.320 IIN 3.315 OUTPUT VOLTAGE (V) 3 VOUTx 1 100A 1mA 10mA 100mA 150mA 3.310 3.305 3.300 3.295 3.290 EN 2 100s/DIV 1MS/s 1.0s/pt 3.280 09682-031 1.14V 3.5 4.5 5.0 5.5 INPUT VOLTAGE (V) Figure 29. LDO Startup, VOUT2 = 3.3 V, IOUT2 = 5 mA Figure 32. LDO Line Regulation Across Output Load, VOUT2 = 3.3 V Rev. A | Page 13 of 32 09682-037 3.285 CH1 1V/DIV 1M BW 500M A CH2 CH2 3V/DIV 1M BW 500M CH3 50mA/DIV 1M BW 20.0M ADP5043 Data Sheet 250 CURRENT (A) 200 VIN 150 VOUT 1 2 100 50 0 0.05 0.10 0.15 LOAD (A) Figure 33. LDO Ground Current vs. Output Load, VOUT2 = 2.8 V B 20.0M CH1 10.0mV/DIV W CH2 800mV/DIV 1M BW 20.0M 5.33V Figure 36. LDO Response to Line Transient, VIN2 = 4.5 V to 5.5 V, VOUT2 = 3.3 V 0.50 3.0 1A 100A 1mA 10mA 100mA 150mA 0.40 2.5 OUTPUT VOLTAGE (V) 0.45 0.35 0.30 0.25 0.20 0.15 0.10 2.0 1.5 1.0 0.5 2.8 3.3 3.8 4.3 4.8 5.3 5.8 INPUT VOLTAGE (V) 0 09682-039 0 2.3 RMS NOISE (V) VOUT CH1 50mV/DIV 1M BW 500M CH3 50mA/DIV 1M BW 20.0M A CH3 28mA 200s/DIV 500kS/s 2.0s/pt 0.3 0.4 0.5 0.6 0.7 0.8 100 10 0.0001 Figure 35. LDO Response to Load Transient, IOUT2 from 1 mA to 80 mA, VOUT2 = 3.3 V 0.2 Figure 37. LDO Output Current Capability vs. Output Voltage 09682-040 1 IOUT 0.1 LOAD CURRENT (A) Figure 34. LDO Ground Current vs. Input Voltage, Across Output Load, VOUT2 = 2.8 V 3 0 09682-056 5.5V 4.5V 3.6V 0.05 VOUT = 3.3V; VIN = 5V VOUT = 3.3V; VIN = 3.6V VOUT = 2.8V; VIN = 3.1V VOUT = 1.5V; VIN = 5V VOUT = 1.5V; VIN = 1.8V 0.001 0.01 0.1 1 LOAD (mA) 10 100 1k 09682-045 GROUND CURRENT (mA) A CH2 09682-042 0 09682-038 2 Figure 38. LDO Output Noise vs. Load Current, Across Input and Output Voltage Rev. A | Page 14 of 32 Data Sheet ADP5043 -10 100 VOUT2 = 3.3V, VIN2 = 3.6V, VOUT2 = 1.5V, VIN2 = 1.8V, VOUT2 = 2.8V, VIN2 = 3.1V, ILOAD = 300mA ILOAD = 300mA ILOAD = 300mA -20 -30 -40 PSRR (dB) NOISE (V/Hz) 10 1mA 10mA 100mA 200mA 300mA 1 -50 -60 -70 0.1 -80 10 100 1k 10k FREQUENCY (Hz) 100k 1M -100 10 Figure 39. LDO Output Noise Spectrum, Across Input and Output Voltage -30 -10 1mA 10mA 100mA 200mA 300mA -20 1M 10M 1mA 10mA 100mA 200mA PSRR (dB) -40 -50 -60 -50 -60 -70 -70 -80 -80 -90 -90 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 09682-049 PSRR (dB) 10k 100k FREQUENCY (Hz) -30 -40 -100 10 1k Figure 41. LDO PSRR vs. Frequency, VIN2 = 3.1 V, VOUT2 = 2.8 V -10 -20 100 Figure 40. LDO PSRR Across Output Load, VIN2 = 3.3 V, VOUT2 = 2.8 V -100 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 42. LDO PSRR vs. Frequency, VIN2 = 5 V, VOUT2 = 3.3 V Rev. A | Page 15 of 32 09682-051 1 09682-055 0.01 09682-050 -90 ADP5043 Data Sheet THEORY OF OPERATION VOUT1 WDI2 WDI1 WMOD MR 40k 75 ENWD1 ENBK VDDA VDDA AVIN GM ERROR AMP ENWD2 WATCHDOG DETECTOR1 52k POFF 200k PWM COMP WATCHDOG STATUS MONITOR SOFT START VIN1 WATCHDOG DETECTOR2 ILIMIT WSTAT DEBOUNCE PSM COMP R0 LOW CURRENT PWM/PSM CONTROL BUCK1 VDDA SW R1 A nRSTO B Y RESET GENERATOR C OSCILLATOR DRIVER AND ANTISHOOT THROUGH PGND EN1 600 ENLDO THERMAL SHUTDOWN POFF MODE VREF SYSTEM UNDERVOLTAGE LOCK OUT ENABLE AND MODE CONTROL MODE ENBK R1 ENLDO EN2 SEL VDDA LDO CONTROL OPMODE_FUSES AGND VIN2 VOUT2 09682-057 R2 ADP5043 Figure 43. Functional Block Diagram POWER MANAGEMENT UNIT The ADP5043 is a micro power management unit (micro PMU) combing one step-down (buck) dc-to-dc regulator, one low dropout linear regulator (LDO), and a supervisory circuit, with dual watchdog, for processor control. The regulators are activated by a logic level high applied to the respective EN pins. EN1 controls the buck regulator while EN2 controls the LDO. The ADP5043 has factory programmed output voltages and reset voltage threshold. Other features available in this device are the MODE pin to control the buck switching operation, a status pin (WSTAT) informing the external processor which watchdog caused a reset, and a push-button reset input (nRSTO). When a regulator is turned on, the output voltage is controlled through a soft start circuit, which prevents a large inrush current due to the discharged output capacitors. The buck regulator can operate in forced PWM mode if the MODE pin is at a logic high level. In forced PWM mode, the switching frequency of the buck is always constant and does not change with the load current. If the MODE pin is at a logic low level, the switching regulator operates in auto PWM/PSM mode. In this mode, the regulator operates at fixed PWM frequency when the load current is above the power saving current threshold. When the load current falls below the power saving current threshold, the regulator enters power saving mode where the switching occurs in bursts. The burst repetition rate is a function of the current load and the output capacitor value. This operating mode reduces the switching and quiescent current losses. Rev. A | Page 16 of 32 Data Sheet ADP5043 Thermal Protection In the event that the junction temperature rises above 150C, the thermal shutdown circuit turns off the buck and LDO. Extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temperature. A 20C hysteresis is included in the thermal shutdown circuit so that if thermal shutdown occurs, the buck and LDO do not return to normal operation until the on-chip temperature drops below 130C. When coming out of thermal shutdown, a soft start is initiated. Undervoltage Lockout To protect against battery discharge, undervoltage lockout (UVLO) circuitry is integrated in the ADP5043. If the input voltage on AVIN drops below a typical 2.15 V UVLO threshold, all channels shut down. In the buck channel, both the power switch and the synchronous rectifier turn off. When the voltage on AVIN rises above the UVLO threshold, the part is enabled once more. Alternatively, the user can select device models with a UVLO set at a higher level, suitable for 5 V applications. For these models, the device hits the turn-off threshold when the input supply drops to 3.65 V typical. Enable/Shutdown The ADP5043 has individual control pins for each regulator. A logic level high applied to the ENx pin activates a regulator; a logic level low turns off a regulator. When regulators are turned off after a Watchdog 2 event (see the Watchdog 2 Input section), the reactivation of the regulator occurs with a factory programmed order (see Table 9). The delay between the regulator activation (tD1, tD2) is 2 ms. Table 9. ADP5043 Regulators Sequencing REGSEQ[1:0] 0 0 0 1 1 0 1 1 Regulators Sequence (First to Last) LDO to buck Buck to LDO Buck to LDO No sequence, all regulators start at same time BUCK SECTION The buck uses a fixed frequency and high speed current-mode architecture. The buck operates with an input voltage of 2.3 V to 5.5 V. Control Scheme The buck operates with a fixed frequency current-mode PWM control at medium to high loads for high efficiency; operation shifts to a power save mode (PSM) control scheme at light loads to lower the regulation power losses. When operating in fixed frequency PWM mode, the duty cycle of the integrated switch is adjusted to regulate the output voltage. When operating in PSM at light loads, the output voltage is controlled in a hysteretic manner that produces a higher output voltage ripple. During part of this time, the converter is able to stop switching and enters an idle mode, which improves conversion efficiency. PWM Mode In PWM mode, the buck operates at a fixed frequency of 3 MHz, set by an internal oscillator. At the start of each oscillator cycle, the high-side PFET switch is turned on, sending a positive voltage across the inductor. Current in the inductor increases until the current sense signal crosses the peak inductor current threshold that turns off the PFET switch and turns on the lowside NFET synchronous rectifier. This sends a negative voltage across the inductor, causing the inductor current to decrease. The synchronous rectifier stays on for the rest of the cycle. The buck regulates the output voltage by adjusting the peak inductor current threshold. Power Save Mode (PSM) The buck smoothly transitions to PSM operation when the load current decreases below the PSM current threshold. When the buck enters power save mode, an offset is induced in the PWM regulation level, which makes the output voltage rise. When the output voltage reaches a level that is approximately 1.5% above the PWM regulation level, PWM operation is turned off. At this point, both power switches are off, and the buck enters an idle state. The output capacitor discharges until the output voltage falls to the PWM regulation voltage, at which point the device drives the inductor to make the output voltage rise again to the upper threshold. This process is repeated while the load current stays below the PSM current threshold. PSM Current Threshold The PSM current threshold is set to 100 mA. The buck employs a scheme that enables this current to remain accurately controlled, independent of input and output voltage levels. This scheme also ensures that there is very little hysteresis between the PSM current threshold for entry to, and exit from, the PSM mode. The PSM current threshold is optimized for high efficiency over all load currents. Short-Circuit Protection The buck includes frequency foldback to prevent current runaway with a hard short on the output. When the voltage at the feedback pin falls below half the target output voltage, indicating the possibility of a hard short at the output, the switching frequency is reduced to half the internal oscillator frequency. The reduction in the switching frequency allows more time for the inductor to discharge, preventing a runaway of output current. Soft Start The buck has an internal soft start function that ramps the output voltage in a controlled manner upon startup, thereby limiting the inrush current. This prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the converter. Rev. A | Page 17 of 32 ADP5043 Data Sheet The buck has protection circuitry to limit the amount of positive current flowing through the PFET switch and the amount of negative current flowing through the synchronous rectifier. The positive current limit on the power switch limits the amount of current that can flow from the input to the output. The negative current limit prevents the inductor current from reversing direction and flowing out of the load. 100% Duty Operation With a dropping input voltage or with an increase in load current, the buck may reach a limit where, even with the PFET switch on 100% of the time, the output voltage drops below the desired output voltage. At this limit, the buck transitions to a mode where the PFET switch stays on 100% of the time. When the input conditions change again and the required duty cycle falls, the buck immediately restarts PWM regulation without allowing overshoot on the output voltage. LDO SECTION The ADP5043 contains one LDO with a low quiescent current that provides an output current up to 300 mA. The low, 15 A typical, quiescent current at no load makes the LDO ideal for battery-operated portable equipment. The LDO operates with an input voltage range of 1.7 V to 5.5 V. The wide operating range makes this LDO suitable for a cascade configuration where the LDO supply voltage is provided from the buck regulator. The LDO also provides high power supply rejection ratio (PSRR), low output noise, and excellent line and load transient response with a small 1 F ceramic input and output capacitors. The LDO is optimized to supply analog circuits by offering better noise performance than the buck regulator. Internally, an LDO consists of a reference, an error amplifier, a feedback voltage divider, and a PMOS pass transistor. Output current is delivered via the PMOS pass device, which is controlled by the error amplifier. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more current to flow and increasing the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is pulled higher, reducing the current flowing to the output. SUPERVISORY SECTION The ADP5043 provides microprocessor supply voltage supervision by controlling the reset input of the microprocessor. Code execution errors are avoided during power-up, powerdown, and brownout conditions by asserting a reset signal when the supply voltage is below a preset threshold and by allowing supply voltage stabilization with a fixed timeout reset pulse after the supply voltage rises above the threshold. In addition, problems with microprocessor code execution can be monitored and corrected with a dual-watchdog timer. Reset Output The ADP5043 has an active-low, open-drain reset output. This output structure requires an external pull-up resistor to connect the reset output to a voltage rail that is no higher than 6 V. The resistor should comply with the logic low and logic high voltage level requirements of the microprocessor while supplying input current and leakage paths on the nRSTO pin. A 10 k pull-up resistor is adequate in most situations. The reset output is asserted when the monitored rail is below the reset threshold (VTH), when WDI1 or WDI2 is not serviced within the watchdog timeout period (tWD1 and tWD2). Reset remains asserted for the duration of the reset active timeout period (tRP) after the monitored rail rises above the reset threshold or after the watchdog timer times out. Figure 44 illustrates the behavior of the reset output, nRSTO, and it assumes that VOUT2 is selected as the rail to be monitored and supplies the external pullup connected to the nRSTO output. VTH VTH VOUT2 1V 0V tRP1 nRSTO tRD 0V RSTO tRP1 1V 0V tRD 09682-058 Current Limit Figure 44. Reset Timing Diagram The reset threshold voltage and the sensed rail (VOUT1, VOUT2, or AVIN) are factory programmed. Refer to Table 16 for a complete list of the reset thresholds available for the ADP5043. When monitoring the input supply voltage, AVIN, if the selected reset threshold is below the UVLO level (factory programmable to 2.25 V or 3.6 V) the reset output, nRSTO, is asserted low as soon as the input voltage falls below the UVLO threshold. Below the UVLO threshold, the reset output is maintained low down to ~1 V VIN. This is to ensure that the reset output is not released when there is sufficient voltage on the rail supplying a processor to restart the processor operations. Manual Reset Input The ADP5043 features a manual reset input (MR) which, when driven low, asserts the reset output. When MR transitions from low-to-high, reset remains asserted for the duration of the reset active timeout period before deasserting. The MR input has a 52 k, internal pull-up, connected to AVIN, so that the input is always high when unconnected. An external push-button switch can be connected between MR and ground so that the user can generate a reset. Debounce circuitry for this purpose is integrated on chip. Noise immunity is provided on the MR input, and fast, negative-going transients of up to 100 ns (typical) are ignored. A 0.1 F capacitor between MR and ground provides additional noise immunity. Rev. A | Page 18 of 32 Data Sheet ADP5043 Watchdog 1 Input Watchdog 2 Input The ADP5043 features a watchdog timer that monitors microprocessor activity. The watchdog timer circuit is cleared with every low-to-high or high-to-low logic transition on the watchdog input pin (WDI1), which detects pulses as short as 80 ns. If the timer counts through the preset watchdog timeout period (tWD1), an output reset is asserted. The microprocessor is required to toggle the WDI1 pin to avoid being reset. Failure of the microprocessor to toggle WDI1 within the timeout period, therefore, indicates a code execution error, and the reset pulse generated restarts the microprocessor into a known state. The ADP5043 features an additional watchdog timer that monitors microprocessor activity in parallel with the first watchdog but with a much longer timeout. This provides additional security and safety in case Watchdog 1 is incorrectly strobed. A timer circuit is cleared with every low-to-high or high-to-low logic transition on the watchdog input pin (WDI2), which detects pulses as short as 8 s. If the timer counts through the preset watchdog timeout period (tWD2), reset is asserted, followed by a power cycle of all regulators. The microprocessor is required to toggle the WDI2 pin to avoid being reset and powered down. Failure of the microprocessor to toggle WDI2 within the timeout period, therefore, indicates a code execution error, and the reset output nRSTO is forced low for tRP2. Then, all the regulators are turned off for the tPOFF time. After the tPOFF period, the regulators are reactivated according to a predefined sequence (see Table 9). Finally, the reset line (nRSTO) is asserted for tRP1. This guarantees a clean power-up of the system and proper reset. As well as logic transitions on WDI1, the watchdog timer is also cleared by a reset assertion due to an undervoltage condition on the monitored rail. When reset is asserted, the watchdog timer is cleared and does not begin counting again until reset deasserts. Watchdog 1 timer can be disabled by leaving WDI1 floating or by three-stating the WDI1 driver. The pin WMOD controls the Watchdog 1 operating mode. If WMOD is set to logic level low, Watchdog 1 is enabled as long as WDI1 is not in three-state. If WMOD is set to logic level high, Watchdog 1 is always active and cannot be disabled by a three-state condition. WMOD input has an internal 200 k pull-down resistor. As well as logic transitions on WDI2, the watchdog timer is also cleared by a reset assertion due to an undervoltage condition on the VTH monitored rail which can be factory programmable between VOUT1, VOUT2, and AVIN (see Table 21). When reset is asserted, the watchdog timer is cleared and does not begin counting again until reset deasserts. Watchdog 1 timeout is factory set to two possible values, as indicated in Table 18. VSENSED 1V 0V Watchdog 2 timeout is factory set to seven possible values as indicated in Table 19. One additional option allows Watchdog 2 to be factory disabled. VTH tWD1 tRP1 nRSTO tRP1 09682-059 0V WDI1 0V Figure 45. Watchdog 1 Timing Diagram AVIN/VINx/ENx tPOFF VOUT1 0V tD1 tD1 tD2 VOUT2 tD2 VTH 0V tRP2 tRP1 nRSTO tWD2 tRP1 0V WDI2 0V tWDCLEAR 09682-060 WSTAT Figure 46. Watchdog 2 Timing Diagram (Assuming That VOUT2 Is the Monitored Rail) Rev. A | Page 19 of 32 ADP5043 Data Sheet Watchdog Status Indicator The external processor can further distinguish a reset caused by a Watchdog 1 timeout from a power failure, status monitor WSTAT indicating a high level, by implementing a RAM check or signature verification after reset. A RAM check or signature failure indicates that a power failure has occurred, whereas a RAM check or signature validation indicates that a Watchdog 1 timeout has occurred. In addition to the dual watchdog function, the ADP5043 features a watchdog status monitor available on the WSTAT pin. This pin can be queried by the external processor to determine the origin of a reset. WSTAT is an open-drain output. WSTAT outputs a logic level depending on the condition that has generated a reset. WSTAT is forced low if the reset was generated because of a Watchdog 2 timeout. WSTAT is pulled high, through external pull-up, for any other reset cause (Watchdog 1 timeout, power failure or monitored voltage be low threshold). The status monitor is automatically cleared (set to logic level high) 10 seconds after the nRSTO low-to-high transition (tWDCLEAR). The processor firmware must be designed to read the WSTAT flag before tWDCLEAR expiration after a Watchdog 2 reset. Table 10 shows the possible watchdog decoded statuses. Table 10. Watchdog Status Decoding WSTAT High High Low RAM Checksum Failed Ok Don't care Reset Origin Power failure Watchdog 1 Watchdog 2 The WSTAT flag is not updated in the event of a reset due to a low voltage threshold detection or Watchdog 1 event occurring within 10 seconds after an nRSTO low-to-high transition. In this situation, WSTAT maintains the previous state (see the state flow in Figure 47). NO POWER APPLIED TO AVIN. ALL REGULATORS AND SUPERVISORY TURNED OFF NO POWER AVIN > VUVLO AVIN < VUVLO TRANSITION STATE AVIN < VUVLO POR INTERNAL CIRCUIT BIASED REGULATORS AND SUPERVISORY NOT ACTIVATED END OF POR STANDBY ALL ENx = HIGH AVIN < VUVLO ALL ENx = LOW AVIN < VUVLO TRANSITION STATE WSTAT = HIGH WSTAT TIMEOUT (tWDCLEAR ) WDOG2 TIMEOUT (tWD2) TRANSITION STATE WSTAT = 0 WSTAT = LOW WSTAT = 1 ACTIVE ALL REGULATORS AND SUPERVISOR ACTIVATED WDOG1 TIMEOUT (tWD1) AND WSTAT TIMEOUT END OF RESET PULSE (tRP1 ) END OF RESET PULSE (tRP2 ) WSTAT = HIGH POWER OFF VMON < VTH WSTAT = 1 RESET NORMAL Figure 47. ADP5043 State Flow Rev. A | Page 20 of 32 END OF (tPOFF) PULSE 09682-061 TRANSITION STATE WDOG1 TIMEOUT (tWD1) RESET SHORT Data Sheet ADP5043 APPLICATIONS INFORMATION BUCK EXTERNAL COMPONENT SELECTION Trade-offs between performance parameters such as efficiency and transient response are made by varying the choice of external components in the applications circuit, as shown in Figure 48. VCC VCORE VDDIO nRSTO RESET WDI2 ADP5043 I/O I/O MICROPROCESSOR 09682-067 WDI1 Figure 48. Typical Applications Circuit Inductor The high switching frequency of the buck regulator of the ADP5043 allows for the selection of small chip inductors. For best performance, use inductor values between 0.7 H and 3 H. Suggested inductors are shown in Table 11. The peak-to-peak inductor current ripple is calculated using the following equation: I RIPPLE = VOUT x (VIN - VOUT ) VIN x f SW x L The minimum dc current rating of the inductor must be greater than the inductor peak current. The inductor peak current is calculated using the following equation: I = I LOAD( MAX ) + RIPPLE 2 Table 11. Suggested 1.0 H Inductors Vendor Murata Murata Taiyo Yuden Coilcraft TDK Coilcraft Toko Model LQM2MPN1R0NG0B LQM18FN1R0M00B CBMF1608T1R0M EPL2014-102ML GLFR1608T1R0M-LR 0603LS-102 MDT2520-CN Dimensions (mm) 2.0 x 1.6 x 0.9 1.6 x 0.8 x 0.8 1.6 x 0.8 x 0.8 2.0 x 2.0 x 1.4 1.6 x 0.8 x 0.8 1.8 x 1.69 x 1.1 2.5 x 2.0 x 1.2 ISAT (mA) 1400 150 290 900 230 400 1350 Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are highly recommended for best performance. Y5V and Z5U dielectrics are not recommended for use with any dc-to-dc converter because of their poor temperature and dc bias characteristics. The worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage is calculated using the following equation: CEFF = COUT x (1 - TEMPCO) x (1 - TOL) where: CEFF is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. where: fSW is the switching frequency. L is the inductor value. I PEAK Higher output capacitor values reduce the output voltage ripple and improve load transient response. When choosing the capacitor value, it is also important to account for the loss of capacitance due to output voltage dc bias. DCR (m) 85 26 90 59 80 81 85 In this example, the worst-case temperature coefficient (TEMPCO) over -40C to +85C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and COUT is 9.2481 F at 1.8 V, as shown in Figure 49. Substituting these values in the equation yields CEFF = 9.2481 F x (1 - 0.15) x (1 - 0.1) = 7.0747 F To guarantee the performance of the buck regulator, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. Inductor conduction losses are caused by the flow of current through the inductor, which has an associated internal dc resistance (DCR). Larger sized inductors have smaller DCR, which may decrease inductor conduction losses. Inductor core losses are related to the magnetic permeability of the core material. 12 10 8 6 4 2 0 0 1 2 3 4 5 DC BIAS VOLTAGE (V) Figure 49. Typical Capacitor Performance Rev. A | Page 21 of 32 6 09682-062 VOUT2 Output Capacitor CAPACITANCE (F) VIN1 VOUT1 Because the buck is a high switching frequency dc-to-dc converter, shielded ferrite core material is recommended for its low core losses and low EMI. ADP5043 Data Sheet Input Capacitor The peak-to-peak output voltage ripple for the selected output capacitor and inductor values is calculated using the following equation: VRIPPLE = Higher value input capacitors help to reduce the input voltage ripple and improve transient response. Maximum input capacitor current is calculated using the following equation: VIN I RIPPLE = (2 x f SW ) x 2 x L x COUT 8 x f SW x COUT I CIN I LOAD( MAX ) Capacitors with lower equivalent series resistance (ESR) are preferred to guarantee low output voltage ripple, as shown in the following equation: ESRCOUT VOUT (VIN - VOUT ) VIN To minimize supply noise, place the input capacitor as close to the VIN pin of the buck as possible. As with the output capacitor, a low ESR input capacitor is recommended. VRIPPLE I RIPPLE The effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 3 F and a maximum of 10 F. Suggested capacitors are shown in Table 13. The effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 7 F and a maximum of 40 F. Table 13. Suggested 4.7 F Capacitors Table 12. Suggested 10 F Capacitors Vendor Murata Taiyo Yuden TDK Panasonic Type X5R X5R X5R X5R Case Size 0603 0603 0603 0603 Model GRM188R60J106 JMK107BJ475 C1608JB0J106K ECJ1VB0J106M Voltage Rating (V) 6.3 6.3 6.3 6.3 L1 1H SW PROCESSOR VIN1 C2 4.7F VIN2 C3 1F VOUT2 VDDIO C4 1F R1 100k nRSTO RESET WDIx Table 14. Suggested 1.0 F Capacitors GPIO1 MODE ENx Connecting a 1 F capacitor from VIN2 to GND reduces the circuit sensitivity to printed circuit board (PCB) layout, especially when long input traces or high source impedance is encountered. If greater than 1 F of output capacitance is required, increase the input capacitor to match it. C6 4.7F PGND GPIO2 09682-063 VIN 2.3V TO 5.5V LDO CAPACITOR SELECTION Input Bypass Capacitor VCORE VOUT1 Model GRM188R60J475ME19D JMK107BJ475 ECJ-0EB0J475M The ADP5043 LDO is designed for operation with small, spacesaving ceramic capacitors but functions with most commonly used capacitors as long as care is taken with the ESR value. The ESR of the output capacitor affects stability of the LDO control loop. A minimum of 0.70 F capacitance with an ESR of 1 or less is recommended to ensure stability of the LDO. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the LDO to large changes in load current. ADP5043 MICRO PMU Type X5R X5R X5R Voltage Rating (V) 6.3 6.3 6.3 Output Capacitor The buck regulator requires 10 F output capacitors to guarantee stability and response to rapid load variations and to transition in and out the PWM/PSM modes. In certain applications, where the buck regulator powers a processor, the operating state is known because it is controlled by software. In this condition, the processor can drive the MODE pin according to the operating state; consequently, it is possible to reduce the output capacitor from 10 F to 4.7 F because the regulator does not expect a large load variation when working in PSM mode (see Figure 50). RFILT 30 AVIN Vendor Murata Taiyo Yuden Panasonic Case Size 0603 0603 0402 2 GPIO[x:y] Figure 50. Processor System Power Management with PSM/PWM Control Vendor Murata TDK Panasonic Taiyo Yuden Rev. A | Page 22 of 32 Type Model X5R GRM155R61A105ME15 X5R X5R X5R C1005JB0J105KT ECJ0EB0J105K LMK105BJ105MV-F Case Size 0402 0402 0402 0402 Voltage Rating (V) 10.0 6.3 6.3 10.0 Data Sheet ADP5043 Input and Output Capacitor Properties Use any good quality ceramic capacitors with the ADP5043 as long as they meet the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are highly recommended for best performance. Y5V and Z5U dielectrics are not recommended for use with any LDO because of their poor temperature and dc bias characteristics. Figure 51 depicts the capacitance vs. voltage bias characteristic of a 0402 1 F, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is about 15% over the -40C to +85C temperature range and is not a function of package or voltage rating. 1.2 0.8 Substituting these values into the following equation yields: CEFF = 0.94 F x (1 - 0.15) x (1 - 0.1) = 0.719 F Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP5043, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. SUPERVISORY SECTION Watchdog 1 Input Current To minimize watchdog input current (and minimize overall power consumption), leave WDI1 low for the majority of the watchdog timeout period. When driven high, WDI1 can draw as much as 25 A. Pulsing WDI1 low-to-high-to-low at a low duty cycle reduces the effect of the large input current. When WDI1 is unconnected and WMOD is set to logic level low, a window comparator disconnects the watchdog timer from the reset output circuitry so that reset is not asserted when the watchdog timer times out. Negative-Going VCC Transients 0.6 0.4 0 0 1 2 3 4 DC BIAS VOLTAGE (V) 5 6 09682-064 0.2 Figure 51. Capacitance vs. Voltage Characteristic Use the following equation to determine the worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage. To avoid unnecessary resets caused by fast power supply transients, the ADP5043 is equipped with glitch rejection circuitry. The typical performance characteristic in Figure 52 plots the monitored rail voltage, VTH, transient duration vs. the transient magnitude. The curve shows combinations of transient magnitude and duration for which a reset is not generated for a 2.93 V reset threshold part. For example, with the 2.93 V threshold, a transient that goes 100 mV below the threshold and lasts 8 s typically does not cause a reset, but if the transient is any larger in magnitude or duration, a reset is generated. 1000 900 CEFF = CBIAS x (1 - TEMPCO) x (1 - TOL) 800 TRANSIENT DURATION (s) where: CBIAS is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. 700 600 500 400 300 200 100 0 0.1 1 10 COMPARATOR OVERDRIVE (% OF VTH) Figure 52. Maximum VTH Transient Duration vs. Reset Threshold Overdrive Rev. A | Page 23 of 32 100 09682-065 CAPACITANCE (F) 1.0 In this example, the worst-case temperature coefficient (TEMPCO) over -40C to +85C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and CBIAS is 0.94 F at 1.8 V as shown in Figure 51. ADP5043 Data Sheet Watchdog Software Considerations In implementing the watchdog strobe code of the microprocessor, quickly switching WDI1 low-to-high and then high-to-low (minimizing WDI1 high time) is desirable for current consumption reasons. However, a more effective way of using the watchdog function can be considered. A low-to-high-to-low WDI1 pulse within a given subroutine prevents the watchdog from timing out. However, if the subroutine becomes stuck in an infinite loop, the watchdog cannot detect this because the subroutine continues to toggle WDI1. A more effective coding scheme for detecting this error involves using a slightly longer watchdog timeout. In the program that calls the subroutine, WDI1 is set high. The subroutine sets WDI1 low when it is called. If the program executes without error, WDI1 is toggled high and low with every loop of the program. If the subroutine enters an infinite loop, WDI1 is kept low, the watchdog times out, and the microprocessor is reset (see Figure 53). START SET WDI HIGH The second watchdog, refreshed through the WDI2 pin, is useful in applications where safety is a very critical factor and the system must recover from unexpected operations, for example, a processor stuck in a continuous loop where Watchdog 1 is kept refreshed or environmental conditions that may unset or damage the processor port controlling the WDI1 pin. In the event of a Watchdog 2 timeout, the ADP5043 power cycles all the supplied rails to guarantee a clean processor start. PCB LAYOUT GUIDELINES Poor layout can affect the ADP5043 performance, causing electro-magnetic interference (EMI) and electromagnetic compatibility (EMC) problems, ground bounce, and voltage losses. Poor layout can also affect regulation and stability. A good layout is implemented using the following guidelines: * * * * RESET PROGRAM CODE SUBROUTINE INFINITE LOOP: WATCHDOG TIMES OUT RETURN 09682-066 SET WDI LOW Figure 53. Watchdog Flow Diagram Rev. A | Page 24 of 32 Place the inductor, input capacitor, and output capacitor close to the IC using short tracks. These components carry high switching frequencies, and large tracks act as antennas. Route the output voltage path away from the inductor and SW node to minimize noise and magnetic interference. Maximize the size of ground metal on the component side to help with thermal dissipation. Use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes. Data Sheet ADP5043 POWER DISSIPATION/THERMAL CONSIDERATIONS The ADP5043 is a highly efficient micro PMU, and in most cases the power dissipated in the device is not a concern. However, if the device operates at high ambient temperatures and with maximum loading conditions, the junction temperature can reach the maximum allowable operating limit (125C). A third way to estimate the power dissipation is analytical and involves modeling the losses in the buck circuit provided by Equation 8 to Equation 11 and the losses in the LDO provided by Equation 12. Buck Regulator Power Dissipation The power loss of the buck regulator is approximated by When the junction temperature exceeds 150C, the ADP5043 turns off all the regulators, allowing the device to cool down. Once the die temperature falls below 135C, the ADP5043 resumes normal operation. This section provides guidelines to calculate the power dissipated in the device and to make sure the ADP5043 operates below the maximum allowable junction temperature. PLOSS = PDBUCK + PL where: PDBUCK is the power dissipation on the ADP5043 buck regulator. PL is the inductor power losses. The inductor losses are external to the device and they don't have any effect on the die temperature. The inductor losses are estimated (without core losses) by PL I OUT1( RMS )2 x DCRL The efficiency for each regulator on the ADP5043 is given by = POUT x 100% PIN (1) (5) where r is the inductor ripple current. Power loss is given by (2a) or PLOSS = POUT (1-)/ (4) where IOUT1(RMS) is the RMS load current of the buck regulator. I OUT1( RMS ) = I OUT1 x 1 + r/12 where: is efficiency. PIN is the input power. POUT is the output power. PLOSS = PIN - POUT (3) (2b) The power dissipation of the supervisory function is small and can be neglected. Power dissipation can be calculated in several ways. The most intuitive and practical is to measure the power dissipated at the input and all the outputs. The measurements should be performed at the worst-case conditions (voltages, currents, and temperature). The difference between input and output power is dissipated in the device and the inductor. Use Equation 4 to derive the power lost in the inductor, and from this use Equation 3 to calculate the power dissipation in the ADP5043 buck regulator. A second method to estimate the power dissipation uses the efficiency curves provided for the buck regulator, while the power lost on the LDO is calculated using Equation 12. Once the buck efficiency is known, use Equation 2b to derive the total power lost in the buck regulator and inductor, use Equation 4 to derive the power lost in the inductor, and thus calculate the power dissipation in the buck converter using Equation 3. Add the power dissipated in the buck and in the LDO to find the total dissipated power. r VOUT1 x (1-D)/(IOUT1 x L x fSW) (6) D = VOUT1/VIN1 (7) fSW is switching frequency. L is inductance. DCRL is the inductor series resistance. D is duty cycle. The ADP5043 buck regulator power dissipation, PDBUCK, includes the power switch conductive losses, the switch losses, and the transition losses of each channel. There are other sources of loss, but these are generally less significant at high output load currents, where the thermal limit of the application will be. Equation 8 shows the calculation made to estimate the power dissipation in the buck regulator. PDBUCK = PCOND + PSW + PTRAN (8) The power switch conductive losses are due to the output current, IOUT1, flowing through the PMOSFET and the NMOSFET power switches that have internal resistance, RDSON-P and RDSON-N. The amount of conductive power loss is found by: PCOND = [RDSON-P x D + RDSON-N x (1 - D)] x IOUT12 For the ADP5043, at 125C junction temperature and VIN = 3.6 V, RDSON-P is approximately 0.2 , and RDSON-N is approximately 0.16 . At VIN = 2.3 V, these values change to 0.31 and 0.21 respectively, and at VIN = 5.5 V, the values are 0.16 and 0.14 . It should be noted that the buck efficiency curves are typical values and may not be provided for all possible combinations of VIN, VOUT, and IOUT. To account for these variations, it is necessary to include a safety margin when calculating the power dissipated in the buck. Rev. A | Page 25 of 32 (9) ADP5043 Data Sheet Switching losses are associated with the current drawn by the driver to turn on and turn off the power devices at the switching frequency. The amount of switching power loss is given by: PSW = (CGATE-P + CGATE-N) x VIN12 x fSW (10) where: CGATE-P is the PMOSFET gate capacitance. CGATE-N is the NMOSFET gate capacitance. Junction Temperature The total power dissipation in the ADP5043 simplifies to: PD = {[PDBUCK + PDLDO1 + PDLDO2]} In cases where the board temperature (TA) is known, the thermal resistance parameter, JA, can be used to estimate the junction temperature rise. TJ is calculated from TA and PD using the formula: For the ADP5043, the total of (CGATE-P + CGATE-N) is ~150 pF. TJ = TA + (PD x JA) The transition losses occur because the PMOSFET cannot be turned on or off instantaneously, and the SW node takes some time to slew from near ground to near VOUT1 (and from VOUT1 to ground). The amount of transition loss is calculated by: PTRAN = VIN1 x IOUT1 x (tRISE + tFALL) x fSW (11) where tRISE and tFALL are the rise time and the fall time of the switching node, SW. For the ADP5043, the rise and fall times of SW are in the order of 5 ns. If the equations and parameters previously given are used for estimating the converter efficiency, it must be noted that the equations do not describe all of the converter losses, and the parameter values given are typical numbers. The converter performance also depends on the choice of passive components and board layout, so a sufficient safety margin should be included in the estimate. LDO Regulator Power Dissipation The power loss of a LDO regulator is given by: PDLDO = [(VIN - VOUT) x ILOAD] + (VIN x IGND) where: ILOAD is the load current of the LDO regulator. VIN and VOUT are input and output voltages of the LDO, respectively. IGND is the ground current of the LDO regulator. Power dissipation due to the ground current is small and it can be ignored. (12) (13) (14) The typical JA value for the 20-lead, 4 mm x 4 mm LFCSP is 38C/W, see Table 7. A very important factor to consider is that JA is based on a four-layer 4" x 3", 2.5 oz copper, as per Jedec standard, and real applications may use different sizes and layers. It is important to maximize the copper used to remove the heat from the device, and copper exposed to air dissipates heat better than copper used in the inner layers. The thermal pad (TP) should be connected to the ground plane with several vias as shown in Figure 55. If the case temperature can be measured, the junction temperature is calculated by: TJ = TC + (PD x JC) (15) where: TC is the case temperature. JC is the junction-to-case thermal resistance provided in Table 7. When designing an application for a particular ambient temperature range, calculate the expected ADP5043 power dissipation (PD) due to the losses of all channels by using Equation 8 to Equation 13. From this power calculation, the junction temperature, TJ, can be estimated using Equation 14. The reliable operation of the buck regulator and the LDO regulator can be achieved only if the estimated die junction temperature of the ADP5043 (Equation 14) is less than 125C. Reliability and mean time between failures (MTBF) is highly affected by increasing the junction temperature. Additional information about product reliability can be found in the Analog Devices, Inc., Reliability Handbook. Rev. A | Page 26 of 32 Data Sheet ADP5043 EVALUATION BOARD SCHEMATICS AND ARTWORK AVIN AVIN RFILT 30 BUCK VIN1 C5 4.7F TP12 MODE EN1 TP2 VOUT2 @ 300mA C2 1F EN_LDO C1 1F TP11 EN2 WSTAT SUPERVISOR VIN2 = 1.7V TO 5.5V VOUT1 @ 800mA VOUT2 LDO VIN2 C6 10F PGND EN_BK TP6 TP1 VOUT1 TP5 VIN1 = 2.3V TO 5.5V TP4 L1 1H SW AVIN TP8 MR TP9 nRSTO TP10 WDI1 TP7 WDI2 TP3 NC WMOD GND 09682-068 NC GND AGND Figure 54. Evaluation Board Schematic SUGGESTED LAYOUT 0.5 1 1.5 2 2.5 3.5 3 5 4.5 4 5.5 3.3V 1u C3 - 1uF V/XR 5 6.3V/XR 402 0402 0.5 6 6.5 7 mm C4 - 1uF 10 V/XR 5 0402 1 VIN 1 C5 - 4.7uF 10V/XR5 0603 L1 - 1uH 0603 3 3.5 N.C. 2.5 VOUT 2 AVIN VIN 2 2 EN 2 nRSTO RSTO R 10 ohms 0402 1.5 MR WDI 1 AGND SW MOD WMOD PGND MODE 4 ADP5043 G GND EN 1 4.5 C6 - 10uF 6.3V/XR5 0603 WSTAT STAT N.C. GND G WDI 2 VOUT OUT 1 5 VIAs LEGEND: PPL = POWER PLANE (+4V) GPL = GROUND PLANE 5.5 2ND LAYER 1.5V mm Figure 55. Layout Rev. A | Page 27 of 32 09682-069 TOP LAYER 6 ADP5043 Data Sheet BILL OF MATERIALS Table 15. Reference C1, C2 C5 C6 RFILT L1 IC1 Value 1 F, X5R, 6.3 V 4.7 F, X5R, 10 V 10 F, X5R, 6.3 V 30 1 H, 0.09 , 290 mA 1 H, 0.08 , 230 mA Dual regulator micro PMU Part Number LMK105BJ105MV-F LMK107BJ475MA-T JMK107BJ106MA-T Vendor Taiyo Yuden Taiyo Yuden Taiyo Yuden BRC1608T1R0M GLFR1608T1R0M-LR ADP5043 Taiyo Yuden TDK Analog Devices Package 0402 0603 0603 0201/0402 0603 0603 20-Lead LFCSP APPLICATION DIAGRAM RFILT 30 AVIN VIN1 = 2.3V TO 5.5V VIN1 AVIN 6 BUCK 8 11 7 9 EN_BK C5 4.7F SW L1 1H VOUT1 C6 10F PGND VOUT1 @ 800mA FPWM ON OFF VIN2 17 MODE PWM/PSM 10 LDO 3 C1 1F 2 VOUT2 C2 1F EN_LDO VOUT2 @ 300mA VDD EN2 SUPERVISOR 4 AVIN R1 15 MR 20 POFF PUSH-BUTTON RESET RESET 5 WDOG2 12 WDOG1 19 R2 WSTAT nRSTO WDI2 WDI1 VDD 18 WMOD ON OFF IC1 1 14 TP AGND 13 GND NC NC 16 GND Figure 56. Application Diagram Rev. A | Page 28 of 32 09682-070 ON OFF MAIN MICROCONTROLLER VIN2 = 1.7V TO 5.5V EN1 Data Sheet ADP5043 FACTORY PROGRAMMABLE OPTIONS Table 16. Reset Voltage Threshold Options 1 Selection 111 (For VIN = 5 V - 6%) 110 (For VOUT = 3.3 V) 101 (For VOUT = 3.3 V) 100 (For VOUT = 2.8 V) 011 (For VOUT = 2.8 V) 010 (For VOUT = 2.5 V - 6%) 001 (For VOUT = 2.2 V - 6%) 000 (For VOUT = 1.8 V - 6%) 1 Min 3.034 2.886 2.591 2.463 TA = +25C Typ 4.630 3.080 2.930 2.630 2.500 2.350 2.068 1.692 Max Min 3.126 2.974 2.669 2.538 3.003 2.857 2.564 2.438 TA = -40C to +85C Max 4.700 3.157 3.000 2.696 2.563 2.385 2.099 1.717 Unit V V V V V V V V When monitoring AVIN, the reset threshold selected, by fuse option or by the external resistor divided, must be higher than the UVLO threshold (2.25 V or 3.6 V). Table 17. Reset Timeout Options Selection 0 1 Min 24 160 Typ 30 200 Max 36 240 Unit ms ms Typ 102 1.6 Max 122.4 1.92 Unit ms sec Max 9 Unit sec 4.8 9.6 19.2 38.4 76.8 153.6 min min min min min min Max 280 560 Unit ms ms Table 18. Watchdog 1 Timer Options Selection 0 1 Min 81.6 1.12 Table 19. Watchdog 2 Timer Options Selection 000 001 010 011 100 101 110 111 Min 6 3.2 6.4 12.8 25.6 51.2 102.4 Typ 7.5 Watchdog 2 disabled 4 8 16 32 64 128 Table 20. Power-Off Timing Options Selection 0 1 Min 140 280 Typ 200 400 Table 21. Reset Sensing Options Selection 00 01 10 11 1 Monitored Rail VOUT1 pin Reserved VOUT2 pin AVIN 1 pin When monitoring AVIN, the reset threshold selected, by fuse option or by the external resistor divided, must be higher than the UVLO threshold (2.25 V or 3.6 V). Table 22. BUCK and LDO Output Voltage Options Selection Buck LDO Output Voltage 3.3 V, 3.0 V, 2.8 V, 2.5 V, 2.3 V, 2.0 V, 1.82 V, 1.8 V, 1.6 V, 1.5 V, 1.4 V, 1.3 V, 1.2 V, 1.1 V, 1.0 V, 0.9 V 3.3 V, 3.0 V, 2.8 V, 2.5 V, 2.25 V, 2.0 V, 1.8 V, 1.7 V, 1.6 V, 1.5 V, 1.2 V, 1.1 V, 1 V, 0.9 V, 0.8 V Rev. A | Page 29 of 32 ADP5043 Data Sheet OUTLINE DIMENSIONS PIN 1 INDICATOR 4.10 4.00 SQ 3.90 0.30 0.25 0.20 0.50 BSC 20 16 15 PIN 1 INDICATOR 1 EXPOSED PAD 2.65 2.50 SQ 2.35 5 11 0.80 0.75 0.70 SEATING PLANE 0.50 0.40 0.30 10 6 0.25 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 061609-B TOP VIEW COMPLIANT TO JEDEC STANDARDS MO-220-WGGD. Figure 57. 20-Lead, Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm x 4 mm Body, Very Very Thin Quad (CP-20-10) Dimensions shown in millimeters ORDERING GUIDE Model1, 2 ADP5043ACPZ-1-R7 Regulator Settings VOUT1 = 1.5 V Supervisory Settings WD1 tOUT = 1.6 sec VOUT2 = 3.3 V UVLO = 2.25 V Sequencing: LDO, buck WD2 tOUT = 128 min Reset tOUT = 200 ms POFF = 200 ms VTH sensing = VOUT2, 2.93 V Temperature Range TJ = -40C to +125C ADP5043CP-1-EVALZ 1 2 Package Description 20-Lead, Lead Frame Scale Package [LFCSP_WQ] Package Option CP-20-10 Evaluation Board Z = RoHS Compliant Part. Monitoring ambient temperature does not guarantee that the junction temperature (TJ) is within the specified temperature limits. See the Power Dissipation/Thermal Considerations section for more information. Rev. A | Page 30 of 32 Data Sheet ADP5043 NOTES Rev. A | Page 31 of 32 ADP5043 Data Sheet NOTES (c)2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09682-0-10/11(A) Rev. A | Page 32 of 32