Micro PMU with 800 mA Buck, 300 mA LDO,
Supervisory, Watchdog, and Manual Reset
Data Sheet
ADP5043
Rev. A
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FEATURES
Input voltage range: 2.3 V to 5.5 V
One 800 mA buck regulator
One 300 mA LDO
20-lead, 4 mm × 4 mm LFCSP package
Initial regulator accuracy: ±1%
Overcurrent and thermal protection
Soft start
Undervoltage lockout
Open-drain processor reset with threshold monitoring
±1.5% threshold accuracy over the full temperate range
Guaranteed reset output valid to VCC = 1 V
Dual watchdog for secure systems
Watchdog 1 controls reset
Watchdog 2 controls reset and regulators power cycle
Buck regulator key specifications
Current-mode topology for excellent transient response
3 MHz operating frequency
Uses tiny multilayer inductors and capacitors
Mode pin selects forced PWM or auto PFM/PSM modes
100% duty cycle low dropout mode
LDO key specifications
Low VIN from 1.7 V to 5.5 V
Stable with1 µF ceramic output capacitors
High PSRR, 60 dB up to 1 kHz/10 kHz
Low output noise
Low dropout voltage: 150 mV at 300 mA load
40°C to +125°C junction temperature range
GENERAL DESCRIPTION
The ADP5043 combines one high performance buck regulator
and one low dropout regulator (LDO) in a small 20-lead LFCSP
to meet demanding performance and board space requirements.
The high switching frequency of the buck regulator enables use
of tiny multilayer external components and minimizes board space.
The MODE pin selects the buck’s mode of operation. When set
to logic high, the buck regulator operates in forced PWM mode.
When the MODE pin is set to logic low, the buck regulator
operates in PWM mode when the load is around the nominal
value. When the load current falls below a predefined threshold,
the regulator operates in power save mode (PSM) improving
the light-load efficiency.
The low quiescent current, low dropout voltage, and wide input
voltage range of the ADP5043 LDO extend the battery life of
portable devices. The LDO maintains a power supply rejection
of greater than 60 dB for frequencies as high as 10 kHz while
operating with a low headroom voltage.
Each regulator is activated by a high level on the respective
enable pin. The ADP5043 is available with factory programmable
default output voltages and can be set to a wide range of options.
The ADP5043 contains supervisory circuits that monitor
power supply voltage levels and code execution integrity in
microprocessor-based systems. The ADP5043 also provides
power-on reset signals. An on-chip dual watchdog timer can
reset the microprocessor or power cycle the system (Watchdog 2)
if it fails to strobe within a preset timeout period.
HIGH LEVEL BLOCK DIAGRAM
VIN
WD1 MODE
SELECTION
FPWM
PSM/PWM
MODE
SW
VOUT1
PGND C6
10µF
L1
1µH
EN_BK
BUCK
EN_LDO
LDO
VIN1
EN1
VIN2
EN2
C2
1µF
VOUT2
GND GND
C5
4.7µF ON
OFF
ON
OFF
NC
VIN1 = 2.3V
TO 5.5V
AVIN
R
FILT
30Ω
VIN2 = 1.7V
TO 5.5V
MR
C1
1µF
MICROPROCESSOR
SUPERVISOR
WSTAT
WMOD
WDI1
WDI2
nRSTO
NC
AGND
AVIN
AVIN
ADP5043
V
OUT1
@
800mA
V
OUT2
@
300mA
09682-001
Figure 1.
ADP5043 Data Sheet
Rev. A | Page 2 of 32
TABLE OF CONTENTS
Features .............................................................................................. 1
General Description ......................................................................... 1
High Level Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
General Specifications ................................................................. 3
Supervisory Specifications .......................................................... 3
Buck Specifications ....................................................................... 5
LDO Specifications ...................................................................... 5
Input and Output Capacitor, Recommended Specifications .. 6
Absolute Maximum Ratings ............................................................ 7
Thermal Data ................................................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 16
Power Management Unit ........................................................... 16
Buck Section ................................................................................ 17
LDO Section ............................................................................... 18
Supervisory Section ................................................................... 18
Applications Information .............................................................. 21
Buck External Component Selection ....................................... 21
LDO Capacitor Selection .......................................................... 22
Supervisory Section ................................................................... 23
PCB Layout Guidelines .............................................................. 24
Power Dissipation/Thermal Considerations ............................. 25
Evaluation Board Schematics and Artwork ............................ 27
Suggested Layout ........................................................................ 27
Bill of Materials ........................................................................... 28
Application Diagram ................................................................. 28
Factory Programmable Options ................................................... 29
Outline Dimensions ....................................................................... 30
Ordering Guide .......................................................................... 30
REVISION HISTORY
10/11—Re v. 0 to Rev. A
Updated Outline Dimensions ....................................................... 30
Changes to Ordering Guide .......................................................... 30
4/11—Revision 0: Initial Version
Data Sheet ADP5043
Rev. A | Page 3 of 32
SPECIFICATIONS
GENERAL SPECIFICATIONS
AVIN, VIN1 = (VOUT1 + 0.5 V) or 2.3 V, whichever is greater, AVIN, VIN1 ≥ VIN2, TA = 25°C, unless otherwise noted. Regulators
are enabled.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
AVIN UNDERVOLTAGE LOCKOUT UVLOAVIN TJ = −40°C to +125°C
Input Voltage Rising UVLOAVINRISE
Option A
2.25
V
Option B 3.9 V
Input Voltage Falling UVLOAVINFALL
Option A 1.95 V
Option B 3.1 V
SHUTDOWN CURRENT IGND-SD ENx = GND 0.1 µA
ENx = GND, TJ = −40°C to +125°C 2 µA
Thermal Shutdown Threshold TSSD TJ rising 150 °C
Thermal Shutdown Hysteresis TSSD-HYS 20 °C
ENx, WDIx, MODE, WMOD, MR INPUTS
Input Logic High VIH 2.5 V ≤ AVIN ≤ 5.5 V 1.2 V
Input Logic Low VIL 2.5 V ≤ AVIN ≤ 5.5 V 0.4 V
Input Leakage Current (WMOD Excluded) VI-LEAKAGE ENx = AVIN or GND 0.05 µA
ENx = AVIN or GND, TJ = −40°C to +125°C 1 µA
WMOD Input Leakage Current VI-LKG-WMOD VWMOD = 3.6 V, TJ = −40°C to +125°C 50 µA
OPEN-DRAIN OUTPUTS
nRSTO, WSTAT Output Voltage VOL AVIN = 2.3 V to 5.5 V, InRSTO/WSTAT = 3 mA 30
mV
Open-Drain Reset Output Leakage Current 1 µA
SUPERVISORY SPECIFICATIONS
AVIN, VIN1 = full operating range, TJ = −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
SUPPLY
Supply Current (Supervisory Circuit Only) 45 55 µA AVIN = 5.5 V, EN1 = EN2 = VIN1
43 52 µA AVIN = 3.6 V, EN1 = EN2 = VIN1
RESET THRESHOLD ACCURACY VTH − 0.8% VTH VTH + 0.8% V TA = 25°C, sensed on VOUTx
VTH − 1.5% VTH VTH + 1.5% V TJ = −40°C to +125°C, sensed on VOUTx
RESET THRESHOLD TO OUTPUT DELAY
GLITCH IMMUNITY (tUOD)
50 125 400 µs VTH = VOUT − 50 mV
RESET TIMEOUT PERIOD WATCHDOG1 (tRP1)
Option A 24 30 36 ms
Option B 160 200 240 ms
RESET TIMEOUT PERIOD WATCHDOG2 (tRP2) 3.5 5 7 ms
VCC TO RESET DELAY (tRD) 150 µs VIN1 falling at 1 mV/µs
REGULATORS SEQUENCING DELAY (tD1, tD2) 2 ms
WATCHDOG INPUTS
Watchdog 1 Timeout Period (tWD1)
Option A 81.6 102 122.4 ms
Option B 1.28 1.6 1.92 sec
ADP5043 Data Sheet
Rev. A | Page 4 of 32
Parameter Min Typ Max Unit Test Conditions/Comments
Watchdog 2 Timeout Period (tWD2)
Option A 6 7.5 9 sec
Option B Watchdog 2 disabled
Option C 3.2 4 4.8 min
Option D
6.4
8
9.6
min
Option E 11.2 16 19.2 min
Option F 25.6 32 38.4 min
Option G 51.2 64 76.8 min
Option H 102.4 128 153.8 min
Watchdog 2 Power Off Period (tPOFF)
Option A
210
ms
Option B 400 ms
WDI1 Pulse Width 80 ns VIL = 0.4 V, VIH = 1.2 V
WDI2 Pulse Width 8 µs VIL = 0.4 V, VIH = 1.2 V
Watchdog Status Timeout Period (tWDCLEAR) 11.2 sec
WDI1 Input Current (Source) 8 15 20 µA VWDI1 = VCC, time average
WDI1 Input Current (Sink) −30 −25 −14 µA VWDI1 = 0, time average
WDI2 Internal Pull-Down 45
MANUAL RESET INPUT
MR Input Pulse Width 1 µs
MR Glitch Rejection 220 ns
MR Pull-Up Resistance 25 52 80
MR to Reset Delay 280 ns VCC = 5 V
Data Sheet ADP5043
Rev. A | Page 5 of 32
BUCK SPECIFICATIONS
AVIN, VIN1 = 3.6 V, VOUT1 = 1.8 V, TJ = −40°C to +125°C for minimum/maximum specifications, L = 1 µH, COUT = 10 µF, and TA = 25°C
for typical specifications, unless otherwise noted.1
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Input Voltage Range (VIN1) 2.3 5.5 V
OUTPUT CHARACTERISTICS
Output Voltage Accuracy PWM mode, ILOAD = 100 mA −1 +1 %
PSM mode −2 +2 %
VIN1 = 2.3 V to 5.5 V, PWM mode,
ILOAD = 1 mA to 800 mA
−3 +3 %
PWM TO POWER SAVE MODE CURRENT THRESHOLD 100 mA
INPUT CURRENT CHARACTERISTICS
DC Operating Current ILOAD = 0 mA, device not switching 21 35 μA
Shutdown Current ENx = 0 V, TA = TJ = −40°C to +125°C 0.2 1.0 μA
SW CHARACTERISTICS
SW On Resistance PFET 180 240
PFET, AVIN = VIN1 = 5 V 140 190
NFET 170 235
NFET, AVIN = VIN1 = 5 V
150
210
Current Limit PFET switch peak current limit 1100 1360 1600 mA
ACTIVE PULL-DOWN EN1 = 0 V 75 Ω
OSCILLATOR FREQUENCY 2.5 3.0 3.5 MHz
START-UP TIME 250 μs
1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
LDO SPECIFICATIONS
AVIN = 3.6 V, VIN2 = (VOUT2 + 0.2 V) or 2.3 V, whichever is greater; AVIN, VIN1 ≥ VIN2; IOUT = 10 mA; CIN = COUT = 1 µF;
TA = 25°C, unless otherwise noted.
Table 4.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT VOLTAGE RANGE VIN2 TJ = −40°C to +125°C 1.7 5.5 V
OPERATING SUPPLY CURRENT (per LDO)
I
GND
I
OUT
= 0 µA, VOUT = 3.3 V
15
µA
IOUT = 0 µA, VOUT = 3.3 V,
TJ = 40°C to +125°C
50 µA
IOUT = 10 mA 67 µA
IOUT = 10 mA, TJ = −40°C to +125°C 105 µA
IOUT = 200 mA 100 µA
IOUT = 200 mA, TJ = −40°C to +125°C 245 µA
FIXED OUTPUT VOLTAGE ACCURACY VOUT2 IOUT = 10 mA −1 +1 %
100 µA < I
OUT
< 300 mA
−2
+2
%
VIN2 = (VOUT2 + 0.5 V) to 5.5 V
100 µA < IOUT < 300 mA −3 +3 %
VIN2 = (VOUT2 + 0.5 V) to 5.5 V
TJ = −40°C to +125°C
ADP5043 Data Sheet
Rev. A | Page 6 of 32
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
REGULATION
Line Regulation ∆VOUT2/∆VIN2 VIN2= (VOUT2 + 0.5 V) to 5.5 V −0.03 +0.03 %/V
IOUT2 = 1 mA
TJ = −40°C to +125°C
Load Regulation1
∆V
OUT2
/∆I
OUT2
I
OUT2
= 1 mA to 200 mA
0.002
%/mA
IOUT2 = 1 mA to 200 mA 0.0075 %/mA
TJ = −40°C to +125°C
DROPOUT VOLTAGE2
V
DROPOUT
VOUT2 = 3.3 V
IOUT2 = 10 mA 4 mV
IOUT2 = 10 mA, TJ = −40°C to +125°C 5 mV
IOUT2 = 200 mA 60 mV
IOUT2 = 200 mA, TJ = −40°C to +125°C 100 mV
ACTIVE PULL-DOWN RPDLDO EN2 = 0 V 600 Ω
START-UP TIME TSTART-UP VOUT2 = 3.3 V 85 µs
CURRENT-LIMIT THRESHOLD3 ILIMIT TJ = −40°C to +125°C 335 470 mA
OUTPUT NOISE OUTLDONOISE 10 Hz to 100 kHz, VIN2 = 5 V,
VOUT2 = 3.3 V
123 µV rms
10 Hz to 100 kHz, VIN2 = 5 V,
VOUT2 = 2.8 V
110 µV rms
10 Hz to 100 kHz, VIN2 = 5 V,
VOUT2 = 1.5 V
59 µV rms
POWER SUPPLY REJECTION RATIO PSRR 1 kHz, VIN2 = 3.3 V, VOUT2 = 2.8 V,
IOUT = 100 mA
66 dB
100 kHz, VIN2 = 3.3 V, VOUT2 = 2.8 V,
IOUT = 100 mA
57 dB
1 MHz, VIN2 = 3.3 V, VOUT2 = 2.8 V,
IOUT = 100 mA
60 dB
1 Based on an end-point calculation using 1 mA and 100 mA loads.
2 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 2.3 V.
3 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
Table 5.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
OUTPUT CAPACITANCE (BUCK)1 CMIN1 TJ = −40°C to +125°C 7 40 µF
MINIMUM INPUT AND OUTPUT CAPACITANCE2 (LDO) CMIN2 TJ = −40°C to +125°C 0.70 µF
CAPACITOR ESR
R
ESR
T
J
= −40°C to +125°C
0.001
1
Ω
1 The minimum output capacitance should be greater than 4.7 µF over the full range of operating conditions. The full range of operating conditions in the application
must be considered during device selection to ensure that the minimum capacitance specification is met.
2 The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended,
Y5V and Z5U capacitors are not recommended for use with LDOs or the buck.
Data Sheet ADP5043
Rev. A | Page 7 of 32
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
AVIN, VINx, VOUTx, ENx, MODE, MR, WDIx,
WMOD, WSTAT, nRSTO to GND
−0.3 V to +6 V
Storage Temperature Range 65°C to +150°C
Operating Junction Temperature Range 40°C to +125°C
Soldering Conditions JEDEC J-STD-020
ESD Human Body Model 3000 V
ESD Charged Device Model 1500 V
ESD Machine Model
100 V
Stresses above those listed under absolute maximum ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination.
The ADP5043 can be damaged when the junction temperature
limits are exceeded. Monitoring ambient temperature does not
guarantee that the junction temperature is within the specified
temperature limits. In applications with high power dissipation
and poor thermal resistance, the maximum ambient temper-
ature may have to be derated. In applications with moderate
power dissipation and low PCB thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long
as the junction temperature is within specification limits. The
junction temperature of the device is dependent on the ambient
temperature, the power dissipation of the device (PD), and the
junction-to-ambient thermal resistance of the package. Maxi-
mum junction temperature is calculated from the ambient
temperature and power dissipation using the formula
TJ = TA + (PD × θJA)
Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending on
PCB material, layout, and environmental conditions. The specified
value of θJA is based on a four-layer, 4 × 3, 2.5 oz copper board,
as per JEDEC standard. For additional information, see the
AN-772 Application Note, A Design and Manufacturing Guide
for the Lead Frame Chip Scale (LFCSP).
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 7. Thermal Resistance
Package Type θJA θJC Unit
20-Lead, 0.5 mm pitch LFCSP 38 4.2 °C/W
ESD CAUTION
ADP5043 Data Sheet
Rev. A | Page 8 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. E X P OSED P AD S HOUL D BE CONNECTED TO AGND.
2. NC = NO CO NNE CT. DO NO T CO NNE CT T O T HIS P IN.
THE PIN SHOULD BE LEFT FLOATING.
14
13
12
1
3
4
NC
15 WSTAT
GND
WDI2
11 VOUT1
NC
VIN2 2
VOUT2
EN2 5
nRSTO
7
VIN1 6
AVIN
8
SW 9
PGND 10
EN1
19 WDI1
20
18 WMOD
17 MODE
16 GND
ADP5043
MR
TOP VI EW
(No t t o Scal e)
09682-002
Figure 2. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
1 NC Do not connect to this pin. The pin should be left floating.
2 VOUT2 LDO Output Voltage and Sensing Input.
3 VIN2 LDO Input Supply (1.7 V to 5.5 V).
4 EN2 Enable LDO. EN2 = high: turn on the LDO; EN2 = low: turn off the LDO.
5
nRSTO
Open-Drain Reset Output, Active Low.
6 AVIN Regulators Housekeeping and Supervisory Input Supply (2.3 V to 5.5 V).
7 VIN1 Buck Input Supply (2.3 V to 5.5 V).
8 SW Buck Switching Node.
9 PGND Dedicated Power Ground for Buck Regulator.
10 EN1 Enable Buck. EN1 = high: turn on buck; EN1 = low: turn off buck.
11
VOUT1
Buck Sensing Node.
12 WDI2 Watchdog 2 (Long Timeout) Refresh Input from Processor. This pin can be disabled only by a factory option.
13 GND Connect to the ground plane.
14 NC Do not connect to this pin. The pin should be left floating.
15 WSTAT Open-Drain Watchdog Timeout Status. WSTAT = high: Watchdog 1 timeout or power-on reset; WSTAT = low:
Watchdog 2 timeout. Auto cleared after one second.
16 GND Connect to the ground plane.
17 MODE Buck Mode. MODE = high: buck regulator operates in fixed PWM mode; MODE = low: (auto mode) buck
regulator operates in power save mode (PSM) at light load and in constant PWM at higher load.
18 WMOD Watchdog Mode. WMOD = low: Watchdog 1 normal mode; WMOD = high: Watchdog 1 cannot be disabled by a
three-state condition applied on WDI1. WMOD has an internal 200pull-down resistor connected to AGND.
19
WDI1
Watchdog 1 Refresh Input from Processor. If WDI1 is in high-Z and WMOD is low, Watchdog 1 is disabled.
20 MR Manual Reset Input, Active Low.
TP AGND Analog Ground (TP = Exposed Thermal Pad). Exposed pad should be connected to AGND.
Data Sheet ADP5043
Rev. A | Page 9 of 32
TYPICAL PERFORMANCE CHARACTERISTICS
VIN1 = VIN2 = AVIN = 5.0 V, TA = 25°C, unless otherwise noted.
CH1 2.0V/DIV 1MΩ
BW
20.0M
CH2 2.0V/DIV 1MΩ
BW
20.0M A CH1 1.76V 200µs/DIV
20.0ns/pt
1
2
VOUT1
VOUT2
09682-003
Figure 3. 3-Channel Start-Up Waveforms
0
0.1
0.2
0.3
0.4
0.5
0.6
1.0
0.9
0.8
0.7
2.3 2.8 3.3 3.8 4.3 4.8 5.3
SYS TEM QUI E S CE NT CURRENT (mA)
INPUT VOLTAGE (V)
VOUT1 = 1.5V,
VOUT2 = 3.3V
09682-004
Figure 4. System Quiescent Current (Sum of All the Input Currents) vs. Input
Voltage, VOUT1 = 1.5 V, VOUT2 = 3.3 V
CH1 2.0V/DIV 1MΩ
BW
20.0M
CH2 2.0V/DIV 1MΩ
BW
500M
CH3 100mA/DI V 1MΩ
BW
20.0M
CH4 5.0V/DIV 1MΩ
BW
500M
A CH1 2.92V 50µs/DIV
50.0MS/s
20.0ns/pt
2
4
1
3
SW
VOUT1
EN
IIN
09682-005
Figure 5. Buck Startup, VOUT1 = 1.8 V, IOUT1 = 20 mA
3.22
3.24
3.26
3.28
3.30
3.32
3.34
OUTPUT VOLTAGE (V)
OUTPUT CURRE NT (A)
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
+25°C
–40°C
+85°C
09682-007
Figure 6. Buck Load Regulation Across Temperature, VOUT1 = 3.3 V, Auto Mode
1.775
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
1.825
1.830
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
OUTPUT CURRE NT (A)
OUTPUT VOLTAGE (V)
+25°C
–40°C
+85°C
09682-008
Figure 7. Buck Load Regulation Across Temperature, VOUT1 = 1.8 V, Auto Mode
1.784
1.785
1.786
1.787
1.788
1.789
1.790
1.791
1.792
1.793
1.794
1.795
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
–40°C
+25
°C
+85°C
OUTPUT CURRE NT (A)
OUTPUT VOLTAGE (V)
09682-009
Figure 8. Buck Load Regulation Across Temperature, VOUT1 = 1.8 V,
PWM Mode
ADP5043 Data Sheet
Rev. A | Page 10 of 32
1.790
1.791
1.792
1.793
1.794
1.795
1.796
1.797
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
OUTPUT CURRE NT (A)
OUTPUT VOLTAGE (V)
VIN = 5.5V
VIN = 4.5V
VIN = 3.6V
09682-010
Figure 9. Buck Load Regulation Across Input Voltage, VOUT1 = 1.8 V,
PWM Mode
0
10
20
30
40
50
60
70
80
90
100
0.0001 0.001 0.01 0.1 1
EF FICIENCY ( %)
OUTPUT CURRE NT (A)
3.6V
4.5V
5.5V
09682-011
Figure 10. Buck Efficiency vs. Load Current, Across Input Voltage,
VOUT1 = 3.3 V, Auto Mode
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1
EF FICIENCY ( %)
OUTPUT CURRE NT (A)
3.6V
4.5V
5.5V
09682-012
Figure 11. Buck Efficiency vs. Load Current, Across Input Voltage,
VOUT1 = 3.3 V, PWM Mode
0
10
20
30
40
50
60
70
80
90
100
0.0001 0.001 0.01 0.1 1
EF FICIENCY ( %)
OUTPUT CURRE NT (A)
2.4V
3.6V
4.5V
5.5V
09682-013
Figure 12. Buck Efficiency vs. Load Current, Across Input Voltage,
VOUT1 = 1.8 V, Auto Mode
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1
EF FICIENCY ( %)
OUTPUT CURRE NT (A)
2.4V
3.6V
4.5V
5.5V
09682-014
Figure 13. Buck Efficiency vs. Load Current, Across Input Voltage,
VOUT1= 1.8 V, PWM Mode
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1
EF FICIENCY ( %)
OUTPUT CURRE NT (A)
+25°C
–40°C
+85°C
09682-015
Figure 14. Buck Efficiency vs. Load Current, Across Temperature, VOUT1 = 1.8 V,
PWM Mode
Data Sheet ADP5043
Rev. A | Page 11 of 32
0
10
20
30
40
50
60
70
80
90
100
0.0001 0.001 0.01 0.1 1
EF FICIENCY ( %)
OUTPUT CURRE NT (A)
+25°C
–40°C
+85°C
09682-016
Figure 15. Buck Efficiency vs. Load Current, Across Temperature, VOUT1 = 3.3 V,
Auto Mode
0
10
20
30
40
50
60
70
80
90
100
0.0001 0.001 0.01 0.11
EF FICIENCY ( %)
OUTPUT CURRE NT (A)
+25°C
–40°C
+85°C
09682-017
Figure 16. Buck Efficiency vs. Load Current, Across Temperature, VOUT1 = 1.8 V,
Auto Mode
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.02.6 3.6 4.6 5.6
INPUT VOLTAGE (V)
OUTPUT CURRE NT (A)
09682-018
Figure 17. Buck DC Current Capability vs. Input Voltage, VOUT1 = 1.8 V
2.85
2.90
2.95
3.00
3.05
3.10
00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
FREQUENCY (MHz)
+25°C
–40°C
+85°C
OUTPUT CURRE NT (A)
09682-019
Figure 18. Buck Switching Frequency vs. Output Current, Across
Temperature, VOUT1 = 1.8 V, PWM Mode
CH1 20.0mV/DI V
BW
20.0M
CH2 200mA/DIV 1M
BW
20.0M
CH3 2.0V/DI V 1MΩ
BW
20.0M
A CH1 2.4mV 5.0µs/DIV
20.0MS/s
50.0ns/pt
1
2
3
VOUT
I
SW
SW
09682-020
Figure 19. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, Auto Mode
CH1 2.0V/DIV 1MΩ
BW
20.0M
CH2 50.0mV/DI V
BW
20.0M
CH3 500mA/DI V
BW
20.0M
A CH1 1.56mV 5.0µs/DIV
200MS/s
5.0ns/pt
2
3
1
VOUTx
I
SW
SW
09682-021
Figure 20. Typical Waveforms, VOUT1 = 1.8 V, IOUT1= 30 mA, Auto Mode
ADP5043 Data Sheet
Rev. A | Page 12 of 32
CH1 2.0V/DIV 1MΩ
BW
20.0M
CH2 50.0mV/DI V
BW
20.0M
CH3 500mA/DI V
BW
20.0M
A CH1 1.56mV 500ns/DIV
200MS/s
5.0ns/pt
2
3
1
VOUTx
I
SW
SW
09682-022
Figure 21. Typical Waveforms, VOUT1 = 1.8 V, IOUT1 = 30 mA, PWM Mode
CH1 20.0mV/DI V
BW
20.0M
CH2 200mA/DIV 1M
BW
20.0M
CH3 2.0V/DIV 1M
BW
20.0M
A CH1 2.4mV 200ns/DIV
500MS/s
2.0ns/pt
1
2
3
VOUTx
I
SW
SW
09682-023
Figure 22. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, PWM Mode
CH1 3V/DIV
BW
20.0M
CH2 50mV/DIV
BW
20.0M
CH3 900mV/DIV 1MΩ
BW
20.0M
A CH3 4.79V 100µs/DIV
10.0MS/s
100ns/pt
1
3
VINx
VOUTx
SW
2
09682-024
Figure 23. Buck Response to Line Transient, Input Voltage from 4.5 V to 5.0 V,
VOUT1 = 3.3 V, PWM Mode
CH2 50mV/DIV
BW
20.0M
CH3 1V/DIV 1M
BW
20.0M
CH4 2V/DIV 1M
BW
20.0M
A CH3 4.96mV 100µs/DIV
20MS/s
100ns/pt
2
3
4
VINx
VOUTx
SW
09682-025
Figure 24. Buck Response to Line Transient, VIN = 4.5 V to 5.0 V, VOUT1 = 1.8 V,
PWM Mode
CH1 4V/DIV
BW
20.0M
CH2 50mV/DIV 1M
BW
20.0M
CH3 50mA/DI V 1M
BW
20.0M
A CH3 44mA 200µs/DIV
10MS/s
100ns/pt
2
3
1
SW
VOUTx
IOUT
09682-026
Figure 25. Buck Response to Load Transient, IOUT1 from 1 mA to 50 mA,
VOUT1 = 3.3 V, Auto Mode
CH1 4V/DIV
BW
20.0M
CH2 50mV/DIV
BW
20.0M
CH3 50mA/DI V 1M
BW
20.0M
A CH3 28mA 200µs/DIV
5MS/s
200ns/pt
2
3
1
VOUTx
SW
V
OUT
LOAD
09682-027
Figure 26. Buck Response to Load Transient, IOUT2 from 1 mA to 50 mA,
VOUT1 = 1.8 V, Auto Mode
Data Sheet ADP5043
Rev. A | Page 13 of 32
A CH3 86mA
2
3
1
VOUTx
SW
LOAD
CH1 4V/DIV BW20.0M
CH2 50mV/DIV BW20.0M
CH3 50mA/DIV 1MBW20.0M
200µs/DIV
10MS/s
100ns/pt
09682-028
Figure 27. Buck Response to Load Transient, IOUT1 from 20 mA to 140 mA,
VOUT1 = 3.3 V, Auto Mode
3
4
2
VOUT1
LOAD
SW
CH2 4V/DIV 1M
BW
20.0M
CH3 50mV/DIV 1M
BW
20.0M
CH4 50mA/DI V 1M
BW
20.0M
200µs/DIV
50MS/s
20ns/pt
A CH3 145mA
09682-029
Figure 28. Buck Response to Load Transient, IOUT1 = 20 mA to 180 mA,
VOUT1 = 1.8 V, PWM Mode
1
2
3
VOUTx
I
IN
EN
A CH2 1.14V
CH1 1V/DIV 1M
BW
500M
CH2 3V/DIV 1M
BW
500M
CH3 50mA/DIV 1M
BW
20.0M
100µs/DIV
1MS/s
1.0µs/pt
09682-031
Figure 29. LDO Startup, VOUT2 = 3.3 V, IOUT2 = 5 mA
3.25
3.26
3.27
3.28
3.29
3.30
3.31
3.32
3.33
3.34
3.35
0.0001 0.001 0.01 0.1
OUTPUT VOLTAGE (V)
OUTPUT CURRE NT (A)
3.6V
4.5V
5.0V
5.5V
09682-035
Figure 30. LDO Load Regulation Across Input Voltage, VOUT2 = 3.3 V
3.25
3.26
3.27
3.28
3.29
3.30
3.31
3.32
3.33
3.34
3.35
0.0001 0.001 0.01 0.1
OUTPUT VOLTAGE (V)
OUTPUT CURRE NT (A)
+85°C
+25°C
–40°C
09682-036
Figure 31. LDO Load Regulation Across Temperature, VIN2 = 3.6 V,
VOUT2 = 3.3 V
3.280
3.285
3.290
3.295
3.300
3.305
3.310
3.315
3.320
3.325
3.5 4.5 5.0 5.5
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
100µA
1mA
10mA
100mA
150mA
09682-037
Figure 32. LDO Line Regulation Across Output Load, VOUT2 = 3.3 V
ADP5043 Data Sheet
Rev. A | Page 14 of 32
00.05 0.10 0.15
LOAD (A)
CURRENT ( µ A)
0
50
100
150
200
250
09682-038
Figure 33. LDO Ground Current vs. Output Load, VOUT2 = 2.8 V
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.8
GROUND CURRENT ( mA)
INPUT VOLTAGE (V)
1µA
100µA
1mA
10mA
100mA
150mA
09682-039
Figure 34. LDO Ground Current vs. Input Voltage, Across Output Load,
VOUT2 = 2.8 V
3
1
VOUT
IOUT
CH1 50mV/DIV 1M
BW
500M
CH3 50mA/DI V 1M
BW
20.0M 200µs/DIV
500kS/s
2.0µs/pt
A CH3 28mA
09682-040
Figure 35. LDO Response to Load Transient, IOUT2 from 1 mA to 80 mA,
VOUT2 = 3.3 V
21
2
2
CH1 10.0mV /DIV
CH2 800mV/DIV A CH2 5.33V
1MΩ BW20.0M
VOUT
VIN
BW20.0M
09682-042
Figure 36. LDO Response to Line Transient, VIN2 = 4.5 V to 5.5 V, VOUT2 = 3.3 V
LOAD CURRENT ( A)
OUTPUT VOLTAGE (V)
00.1 0.2 0.3
0.5
0
1.0
1.5
2.0
2.5
3.0
0.4 0.5 0.6 0.7 0.8
5.5V
4.5V
3.6V
09682-056
Figure 37. LDO Output Current Capability vs. Output Voltage
LOAD (mA)
RMS NOISE (µV)
100
10
V
OUT
= 3.3V ; V
IN
= 5V
V
OUT
= 3.3V ; V
IN
= 3.6V
V
OUT
= 2.8V