RHL (QFN) D-8 (SOIC) D-14 (SOIC) SN65HVD30 - SN65HVD35 www.ti.com SLLS665I - SEPTEMBER 2005 - REVISED APRIL 2010 3.3 V FULL-DUPLEX RS-485 DRIVERS AND RECEIVERS Check for Samples: SN65HVD30 - SN65HVD35 FEATURES 1 * * * * * * * * * * (1) 1/8 Unit-Load Option Available (Up to 256 Nodes on the Bus) Bus-Pin ESD Protection Exceeds 15 kV HBM Optional Driver Output Transition Times for Signaling Rates(1) of 1 Mbps, 5 Mbps and 26 Mbps Low-Current Standby Mode: < 1 mA Glitch-Free Power-Up and Power-Down Protection for Hot-Plugging Applications 5-V Tolerant Inputs Bus Idle, Open, and Short Circuit Failsafe Driver Current Limiting and Thermal Shutdown Designed for RS-422 and RS-485 Networks 5-V Devices available, SN65HVD50-55 Line Signaling Rate is the number of voltage transitions made per second expressed in units of bps (bits per second). APPLICATIONS * * * * Utility Meters DTE/DCE Interfaces Industrial, Process, and Building Automation Point-of-Sale (POS) Terminals and Networks DESCRIPTION The SN65HVD3X devices are 3-state differential line drivers and differential-input line receivers that operate with 3.3-V power supply. Each driver and receiver has separate input and output pins for full-duplex bus communication designs. They are designed for RS-422 and RS-485 data transmission over cable lengths of up to 1500 meters. The SN65HVD30, SN65HVD31, and SN65HVD32 are fully enabled with no external enabling pins. The SN65HVD33, SN65HVD34, and SN65HVD35 have active-high driver enables and active-low receiver enables. A low, less than 1mA, standby current can be achieved by disabling both the driver and receiver. All devices are characterized for ambient temperatures from -40C to 85C. Low power dissipation allows operation at temperatures up to 105C or 125C, depending on package option. IMPROVED REPLACEMENT FOR: Part Number Replace with xxx3491 xxx3490 SN65HVD33: SN65HVD30: Better ESD protection (15kV vs 2kV or not specified) Higher Signaling Rate (26Mbps vs 20Mbps) Fractional Unit Load (64 Nodes vs 32) MAX3491E MAX3490E SN65HVD33: SN65HVD30: Higher Signaling Rate (26Mbps vs 12Mbps) Fractional Unit Load (64 Nodes vs 32) MAX3076E MAX3077E SN65HVD33: SN65HVD30: Higher Signaling Rate (26Mbps vs 16Mbps) Lower Standby Current (1 mA vs 10 mA) MAX3073E MAX3074E SN65HVD34: SN65HVD31: Higher Signaling Rate (5Mbps vs 500kbps) Lower Standby Current (1 mA vs 10 mA) MAX3070E MAX3071E SN65HVD35: SN65HVD32: Higher Signaling Rate (1Mbps vs 250kbps) Lower Standby Current (1 mA vs 10 mA) 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2005-2010, Texas Instruments Incorporated SN65HVD30 - SN65HVD35 SLLS665I - SEPTEMBER 2005 - REVISED APRIL 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. SN65HVD30, SN65HVD31, SN65HVD32 SN65HVD33, SN65HVD34, SN65HVD35 D PACKAGE (TOP VIEW) VCC R D GND R D 1 8 2 7 3 6 4 5 8 2 A 7 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC VCC A B Z Y NC NC - No internal connection Pins 6 and 7 are connected together internally Pins 13 and 14 are connected together internally B 5 3 NC R RE DE D GND GND A B Z Y Y 6 Z SN65HVD33 RHL PACKAGE (TOP VIEW) VCC NC 2 R VCC 19 NC 3 18 A RE 4 17 B NC 5 16 NC DE 6 15 Z D 7 14 Y NC 8 13 NC 12 NC NC 9 1 20 10 11 GND GND R RE DE D 18 3 17 4 A B 6 14 7 15 Y Z NC - No internal connection Pins 10 and 11 are connected together internally Pins 1 and 20 are connected together internally 2 Submit Documentation Feedback Copyright (c) 2005-2010, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 - SN65HVD35 SN65HVD30 - SN65HVD35 www.ti.com SLLS665I - SEPTEMBER 2005 - REVISED APRIL 2010 AVAILABLE OPTIONS SIGNALING RATE UNIT LOADS ENABLES BASE PART NUMBER SOIC MARKING 26 Mbps 1/2 No SN65HVD30 VP30 5 Mbps 1/8 No SN65HVD31 VP31 1 Mbps 1/8 No SN65HVD32 VP32 26 Mbps 1/2 Yes SN65HVD33 65HVD33 5 Mbps 1/8 Yes SN65HVD34 65HVD34 1 Mbps 1/8 Yes SN65HVD35 65HVD35 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) (2) UNIT VCC Supply voltage range -0.3 V to 6 V V(A), V(B), V(Y), V(Z) Voltage range at any bus terminal (A, B, Y, Z) -9 V to 14 V V(TRANS) Voltage input, transient pulse through 100 . See Figure 12 (A, B, Y, Z) (3) -50 to 50 V VI Input voltage range (D, DE, RE) -0.5 V to 7 V IO Output current (receiver output only, R) (1) (2) (3) 11 mA Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. This tests survivability only and the output state of the receiver is not specified. DISSIPATION RATINGS PACKAGE SOIC (D) 8 pin SOIC (D) 14 pin QFN (RHL) 20 pin JEDEC THERMAL MODEL TA < 25C RATING DERATING FACTOR ABOVE TA = 25C TA = 85C RATING TA = 105C RATING TA = 125C RATING Low k 625 mW 5 mW/C 325 mW High k 1000 mW 8 mW/C 520 mW 360 mW Low k 765 mW 6.1 mW/C 400 mW 275 mW High k 1350 mW 10.8 mW/C 705 mW 485 mW 270 mW High k 1710 mW 13.7 mW/C 890 mW 6150 mW 340 mW Copyright (c) 2005-2010, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 - SN65HVD35 Submit Documentation Feedback 3 SN65HVD30 - SN65HVD35 SLLS665I - SEPTEMBER 2005 - REVISED APRIL 2010 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range unless otherwise noted MIN VCC Supply voltage VI or VIC Voltage at any bus terminal (separately or common mode) 1/tUI Signaling rate NOM MAX 3 3.6 -7 (1) 12 SN65HVD30, SN65HVD33 26 SN65HVD31, SN65HVD34 5 SN65HVD32, SN65HVD35 1 Differential load resistance VIH High-level input voltage D, DE, RE 2 VCC VIL Low-level input voltage D, DE, RE 0 0.8 VID Differential input voltage -12 12 IOH High-level output current IOL Low-level output current TJ Junction temperature Driver 60 -60 Receiver V Mbps RL (1) 54 UNIT V mA -8 Driver 60 Receiver 8 -40 150 mA C The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet. ELECTROSTATIC DISCHARGE PROTECTION PARAMETER MIN TYP (1) TEST CONDITIONS Human body model Bus terminals and GND Human body model (2) All pins 4 Charged-device-model (3) All pins 1 (1) (2) (3) 4 MAX UNIT 16 kV All typical values at 25C with 3.3-V supply. Tested in accordance with JEDEC Standard 22, Test Method A114-A. Tested in accordance with JEDEC Standard 22, Test Method C101. Submit Documentation Feedback Copyright (c) 2005-2010, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 - SN65HVD35 SN65HVD30 - SN65HVD35 www.ti.com SLLS665I - SEPTEMBER 2005 - REVISED APRIL 2010 DRIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER VI(K) TEST CONDITIONS Input clamp voltage II = -18 mA RL = 54 , See Figure 1 (RS-485) Steady-state differential output voltage |VOD(SS)| Change in magnitude of steady-state differential output voltage between states RL = 54 , See Figure 1 and Figure 2 VOD(RING) Differential Output Voltage overshoot and undershoot RL = 54 , CL = 50 pF, See Figure 5 and Figure 3 VOC(PP) Peak-to-peak common-mode output voltage VOC(SS) Steady-state common-mode output voltage (2) (RS-422) Vtest = -7 V to 12 V, See Figure 2 VOC(SS) HVD30, HVD31, HVD32 IZ(Z) or IY(Z) High-impedance state output current HVD33, HVD34, HVD35 IZ(S) or IY(S) Short Circuit output current (4) II Input current C(OD) Differential output capacitance (1) (2) (3) (4) VCC 1.5 2 2 2.3 V 1.5 -0.2 HVD30, HVD33 Change in steady-state common-mode output voltage UNIT V 2.5 |VOD(SS)| HVD31, HVD34, HVD32, HVD35 MAX -1.5 IO = 0 RL = 100 , See Figure 1 , MIN TYP (1) 0.2 V 10% (3) V 0.5 See Figure 4 V 0.25 1.6 2.3 -0.05 0.05 See Figure 4 V VCC = 0 V, VZ or VY = 12 V, Other input at 0 V 90 VCC = 0 V, VZ or VY = -7 V, Other input at 0 V VCC = 3 V or 0 V, DE = 0 V VZ or VY = 12 V VCC = 3 V or 0 V, DE = 0 V VZ or VY = -7 V VZ or VY = -7 V VZ or VY = 12 V -10 mA Other input at 0 V Other input at 0 V D, DE VOD = 0.4 sin (4E6pt) + 0.5 V, DE at 0 V 90 -10 -250 250 -250 250 0 100 16 mA mA pF All typical values are at 25C and with a 3.3-V supply. VCC is 3.3 Vdc 5% 10% of the peak-to-peak differential output voltage swing, per TIA/EIA-485 Under some conditions of short-circuit to negative voltages, output currents exceeding the ANSI TIA/EIA-485-A maximum current of 250 mA may occur. Continuous exposure may affect device reliability. This applies to the HVD30,HVD31,HVD33, and HVD34. Copyright (c) 2005-2010, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 - SN65HVD35 Submit Documentation Feedback 5 SN65HVD30 - SN65HVD35 SLLS665I - SEPTEMBER 2005 - REVISED APRIL 2010 www.ti.com DRIVER SWITCHING CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER tPLH TEST CONDITIONS HVD30, HVD33 4 Propagation delay time, low-to-high-level HVD31, HVD34 output HVD32, HVD35 25 38 65 120 175 305 18 HVD30, HVD33 Propagation delay time, high-to-low-level HVD31, HVD34 output HVD32, HVD35 tPHL Differential output signal rise time tf Differential output signal fall time tsk(p) Pulse skew (|tPHL - tPLH|) 10 4 9 38 65 120 175 305 2.5 5 12 20 37 60 HVD32, HVD35 120 185 300 HVD30, HVD33 2.5 5 12 HVD31, HVD34 20 35 60 HVD32, HVD35 120 180 300 HVD31, HVD34 RL = 54 , CL = 50 pF, See Figure 5 HVD30, HVD33 0.6 HVD31, HVD34 2.0 HVD32, HVD35 5.1 HVD33 tPZH1 Propagation delay time, high-impedance-to-high-level output HVD34 HVD35 HVD33 Propagation delay time, high-level-to-high-impedance output tPHZ HVD34 Propagation delay time, high-impedance-to-low-level output 235 RL = 110 , RE at 0 V, D = 3 V and S1 = Y, or D = 0 V and S1 = Z See Figure 6 Propagation delay time, low-level-to-high-impedance output tPLZ 65 35 RL = 110 , RE at 0 V, D = 3 V and S1 = Z, or D = 0 V and S1 = Y See Figure 7 VO= 2 V (Typ) tPZH2 tPZL2 6 ns ns 490 30 120 ns 290 Driver enable delay with bus voltage offset (1) ns 165 HVD35 tPZH1, tPZL1 ns 25 190 HVD34 ns 490 HVD34 HVD33 ns ns HVD33 HVD35 ns 45 HVD35 tPZL1 UNIT 18 25 HVD30, HVD33 tr MIN TYP (1) MAX 500 900 ns Propagation delay time, standby-to-high-level output RL = 110 , RE at 3 V, D = 3 V and S1 = Y, or D = 0 V and S1 = Z See Figure 6 4000 ns Propagation delay time, standby-to-low-level output RL = 110 , RE at 3 V, D = 3 V and S1 = Z, or D = 0 V and S1 = Y See Figure 7 4000 ns All typical values are at 25C and with a 3.3-V supply. Submit Documentation Feedback Copyright (c) 2005-2010, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 - SN65HVD35 SN65HVD30 - SN65HVD35 www.ti.com SLLS665I - SEPTEMBER 2005 - REVISED APRIL 2010 RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER MIN TYP (1) TEST CONDITIONS VIT+ Positive-going differential input threshold voltage IO = -8 mA VIT- Negative-going differential input threshold voltage IO = 8 mA Vhys Hysteresis voltage (VIT+ - VIT-) VIK Enable-input clamp voltage VO Output voltage IO(Z) High-impedance-state output current V -0.20 50 II = -18 mA 2.4 0.4 VO = 0 or VCC, RE at VCC -1 VA or VB = -7 V Other input at 0V VA or VB = -7 V, VCC = 0 V Bus input current VA or VB = 12 V, VCC = 0 V VA or VB = -7 V Other input at 0V VA or VB = -7 V, VCC = 0 V IIH Input current, RE VIH = 0.8 V or 2 V CID Differential input capacitance VID = 0.4 sin (4E6pt) + 0.5 V, DE at 0 V 1 0.05 0.1 0.06 0.1 -0.10 -0.04 -0.10 -0.03 VA or VB = 12 V HVD30, HVD33 (1) V VID = -200 mV, IO = 8 mA, See Figure 8 VA or VB = 12 V, VCC = 0 V mV -1.5 VID = 200 mV, IO = -8 mA, See Figure 8 HVD31, HVD32, HVD34, HVD35 UNIT -0.02 VA or VB = 12 V IA or IB MAX 0.20 0.35 0.24 0.4 -0.35 -0.18 -0.25 -0.13 -60 V mA mA mA mA 15 pF All typical values are at 25C and with a 3.3-V supply. SUPPLY CURRENT CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER HVD30 HVD33 Supply current HVD33, HVD34, HVD35 HVD33 HVD34, HVD35 HVD33 HVD34, HVD35 (1) 3.8 RE at VCC, D at VCC, DE at 0 V, No load (Receiver disabled and driver disabled) 6.4 1.8 RE at 0 V, D at 0 V or VCC, DE at 0 V, No load (Receiver enabled and driver disabled) HVD34, HVD35 MAX 2.1 D at 0 V or VCC and No Load HVD31, HVD32 ICC MIN TYP (1) TEST CONDITIONS 2.2 0.022 1 RE at 0 V, D at 0 V or VCC, DE at VCC, No load (Receiver enabled and driver enabled) 2.1 RE at VCC, D at 0 V or VCC, DE at VCC No load (Receiver disabled and driver enabled) 1.8 6.5 6.2 UNIT mA mA mA mA mA All typical values are at 25C and with a 3.3-V supply. Copyright (c) 2005-2010, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 - SN65HVD35 Submit Documentation Feedback 7 SN65HVD30 - SN65HVD35 SLLS665I - SEPTEMBER 2005 - REVISED APRIL 2010 www.ti.com RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER tPLH tPHL TEST CONDITIONS MIN TYP (1) MAX Propagation delay time, low-to-high-level output HVD30, HVD33 26 45 HVD31, HVD32, HVD34, HVD35 47 70 Propagation delay time, high-to-low-level output HVD30, HVD33 29 45 49 70 HVD31, HVD32, HVD34, HVD35 HVD30, HVD33 VID = -1.5 V to 1.5 V, CL = 15 pF, See Figure 9 7 tsk(p) Pulse skew (|tPHL - tPLH|) tr Output signal rise time 5 tf Output signal fall time 6 tPHZ Output disable time from high level HVD31, HVD34, HVD32, HVD35 Output enable time to high level tPZH2 Propagation delay time, standby-to-high-level output tPLZ Output disable time from low level tPZL1 Output enable time to low level tPZL2 Propagation delay time, standby-to-low-level output (1) 10 DE at 3 V tPZH1 UNIT 20 CL = 15 pF, See Figure 10 20 DE at 0 V DE at 3 V ns 4000 20 CL = 15 pF, See Figure 11 20 DE at 0 V 4000 All typical values are at 25C and with a 3.3-V supply DEVICE POWER DISSIPATION - PD PARAMETER TEST CONDITIONS SOIC-8 qJA qJB Junction-to-Ambient Thermal Resistance SOIC-14 Junction-to- Board Thermal Resistance VALU E JEDEC Low-K model 231 JEDEC High-K model 135 JEDEC Low-K model 163 JEDEC High-K model 92 QFN-20 73 SOIC-8 44 SOIC-14 61 UNITS C/W C/W QFN-20 qJC PD TSD 8 Junction-to-Case Thermal Resistance Power Dissipation Driver and receiver enabled, 50% duty cycle square-wave signal at signaling rate: HVD30,33 at 25 Mbps, HVD31,34 at 5 Mbps, HVD32,35 at 1 Mbps SOIC-8 43 SOIC-14 59 QFN-20 14 HVD30,33 Typical HVD31,34 HVD32,35 HVD30,33 Worst-case HVD31,34 HVD32,35 VCC = 3.3V, TJ = 25C, RL = 60 , CL = 50 pF (driver), CL = 15 pF (receiver) VCC = 3.6V, TJ = 140C, RL = 54 , CL = 50 pF (driver), CL = 15 pF (receiver) Thermal Shut-down Junction Temperature Submit Documentation Feedback C/W mW 197 213 mW 248 170 C Copyright (c) 2005-2010, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 - SN65HVD35 SN65HVD30 - SN65HVD35 www.ti.com SLLS665I - SEPTEMBER 2005 - REVISED APRIL 2010 PARAMETER MEASUREMENT INFORMATION VCC DE II Y IY VOD 0 or 3 V Z RL IZ VI VZ VY Figure 1. Driver VOD Test Circuit and Voltage and Current Definitions 375 1% VCC DE D Y VOD 0 or 3 V 60 1% + _ -7 V < V(test) < 12 V Z 375 1% Figure 2. Driver VOD With Common-Mode Loading Test Circuit VOD(SS) VOD(RING) 0 V Differential VOD(RING) -VOD(SS) Figure 3. VOD(RING) Waveform and Definitions VOD(RING) is measured at four points on the output waveform, corresponding to overshoot and undershoot from the VOD(H) and VOD(L) steady state values. Copyright (c) 2005-2010, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 - SN65HVD35 Submit Documentation Feedback 9 SN65HVD30 - SN65HVD35 SLLS665I - SEPTEMBER 2005 - REVISED APRIL 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) VCC 27 1% DE Y D Input Y VY Z VZ VOC(PP) Z 27 1% CL = 50 pF 20% VOC VOC(SS) VOC CL Includes Fixture and Instrumentation Capacitance Input: PRR = 500 kHz, 50% Duty Cycle,t r <6ns, t f <6ns, ZO = 50 Figure 4. Test Circuit and Definitions for the Driver Common-Mode Output Voltage Y W Z W W Figure 5. Driver Switching Test Circuit and Voltage Waveforms D 3V 0V 3V S1 Y Z Y S1 D Z VI VO 1.5 V 1.5 V 0.5 V t PZH(1 & 2) 0V V OH DE Input Generator VI 50 W CL = 50 pF 20% RL = 110 W 1% VO 2.3 V ~0V tPHZ Generator: PRR = 50 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Z 0 = 50 W CL Includes Fixture and Instrumentation Capacitance Figure 6. Driver High-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms 10 Submit Documentation Feedback Copyright (c) 2005-2010, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 - SN65HVD35 SN65HVD30 - SN65HVD35 www.ti.com SLLS665I - SEPTEMBER 2005 - REVISED APRIL 2010 PARAMETER MEASUREMENT INFORMATION (continued) D 3V 0V VCC S1 Z Y RL = 110 1% Y 1.5 V VI S1 D 1.5 V VO 0V Z DE Input Generator 3V t PZL(1&2) t PLZ VCC CL = 50 pF 20% VI 50 0.5 V VO 2.3 V VOL Generator: PRR = 50 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Z 0 = 50 W CL Includes Fixture and Instrumentation Capacitance Figure 7. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms IA VIC VA + VB A IO R VA VID VB B IB 2 VO RE II VI Figure 8. Receiver Voltage and Current Definitions A R Input Generator VI 50 1.5 V 0V B 3V VO RE 1.5 V VI 1.5 V 0V CL = 15 pF 20% t PLH VO CL Includes Fixture and Instrumentation Capacitance Generator: PRR = 500 kHz, 50% Duty Cycle, t r <6 ns, t f <6 ns, Zo = 50 t PHL 90% 90% 1.5 V 10% tr VOH 1.5 V 10% V OL tf Figure 9. Receiver Switching Test Circuit and Voltage Waveforms 1.5 V V CC A R 0V B RE Input Generator VI 1 k W 1% VO C L = 15 pF 20% S1 3V A VI 1.5V 1.5V B 0V t PZH(1 & 2) t PHZ V OH 50 W C L Includes Fixture and Instrumentation Capacitance VO 1.5 V 0.5V ~0 V Generator: PRR = 50 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Z 0 = 50 W Figure 10. Receiver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms Copyright (c) 2005-2010, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 - SN65HVD35 Submit Documentation Feedback 11 SN65HVD30 - SN65HVD35 SLLS665I - SEPTEMBER 2005 - REVISED APRIL 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) 0V V CC A R 1.5 V B RE Input VI Generator V O 1 k W 1% S1 C L = 15 pF 20% 3V A VI 1.5V 1.5V 0V B tPZL(1 & 2) 50 W C L Includes Fixture and Instrumentation Capacitance tPLZ V CC 1.5 V VO 0.5V V OL Generator: PRR = 50 kHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Z 0 = 50 W Figure 11. Receiver Enable Time From Standby (Driver Disabled) 0 V or 3 V DE A Y D R Z 100 W 1% + - Pulse Generator 15 ms duration 1% Duty Cycle tr, tf 100 ns 100 W 1% B RE 0 V or 3 V + - Figure 12. Test Circuit, Transient Over Voltage Test 12 Submit Documentation Feedback Copyright (c) 2005-2010, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 - SN65HVD35 SN65HVD30 - SN65HVD35 www.ti.com SLLS665I - SEPTEMBER 2005 - REVISED APRIL 2010 DEVICE INFORMATION LOW-POWER STANDBY MODE When both the driver and receiver are disabled (DE low and RE high) the device is in standby mode. If the enable inputs are in this state for less than 60 ns, the device does not enter standby mode. This guards against inadvertently entering standby mode during driver/receiver enabling. Only when the enable inputs are held in this state for 300 ns or more, the device is assured to be in standby mode. In this low-power standby mode, most internal circuitry is powered down, and the supply current is typically less than 1 nA. When either the driver or the receiver is re-enabled, the internal circuitry becomes active. 12 R RE 2 11 A B 3 Low-Power Standby DE 4 9 D 5 10 Y Z Figure 13. Low-Power Standby Logic Diagram If only the driver is re-enabled (DE transitions to high) the driver outputs are driven according to the D input after the enable times given by tPZH2 and tPZL2 in the driver switching characteristics. If the D input is open when the driver is enabled, the driver outputs defaults to A high and B low, in accordance with the driver failsafe feature. If only the receiver is re-enabled (RE transitions to low) the receiver output is driven according to the state of the bus inputs (A and B) after the enable times given by tPZH2 and tPZL2 in the receiver switching characteristics. If there is no valid state on the bus the receiver responds as described in the failsafe operation section. If both the receiver and driver are re-enabled simultaneously, the receiver output is driven according to the state of the bus inputs (A and B) and the driver output is driven according to the D input. Note that the state of the active driver affects the inputs to the receiver. Therefore, the receiver outputs are valid as soon as the driver outputs are valid. DRIVER OUTPUT CURRENT LIMITING The RS-485 standard (ANSI/TIA/EIA-485-A or equivalently ISO 8482) specifies a 250 mA driver output current limit to prevent damage caused by data contention on the bus. That applies in the event that two or more transceivers drive the bus to opposing states at the same time. The HVD3x family of devices includes current limiting circuitry that prevents damage under these conditions. Note that this current limit prevents damage during the bus contention, but the logic state of the bus may be indeterminate as specified by the standard, so communication errors may occur. In a specific combination of circumstances, a condition may occur in which current through the bus pin exceeds the 250 mA limit. This combination of conditions is not normally included in RS-485 applications: * loading capacitance on the pin is less than 500 pF * the bus pin is directly connected to a voltage more negative than -1V * the device is supplied with Vcc equal or greater than 3.3V * the driver is enabled * the bus pin is driving to the logic high state. In these specific conditions, the normal current limit circuitry and thermal shutdown circuitry will not limit or shutdown the current flow. If the current is allowed to continue, the device will heat up in a localized area near the driver outputs, and the device may be damaged. Copyright (c) 2005-2010, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 - SN65HVD35 Submit Documentation Feedback 13 SN65HVD30 - SN65HVD35 SLLS665I - SEPTEMBER 2005 - REVISED APRIL 2010 www.ti.com Typical RS-485 twisted-pair cable has capacitance of approximately 50 pF/meter. Therefore it is expected that 10 meters of cable would provide sufficient capacitance to prevent this latch-up condition. The -7 to +12V common mode range specified by RS-485 is intended to allow communication between transceivers separated by significant distances, when ground offsets may occur due to temporary current surges, electrical noise, etc. In those circumstances, the inherent cable needed to connect separated transceivers will ensure that the conditions above do not occur. For transceiver separated by only a short cable length, or backplane applications, it would be unusual for there to be a steady-state negative common-mode voltage. It is possible for a negative power supply to be shorted to the bus lines due to mis-wiring or cable damage, however, this is a different root cause fault, and robust devices such as the HVD178x family should be used for surviving power supply or mis-wiring faults. The 250 mA current limit in the RS-485 standard is intended to prevent damage caused by data contention on the bus; that is, in the event that two or more transceivers drive the bus to different states at the same time. These devices will not be damaged under these conditions, because all RS-485 drivers have output impedance sufficient to prevent the direct connection condition stated above. Typical RS-485 driver output impedance is on the order of 10 to 30 . HOT-PLUGGING These devices are designed to operate in hot swap or hot pluggable applications. Key features for hot-pluggable applications are power-up, power-down glitch-free operation, default disabled input/output pins, and receiver failsafe. As shown in Figure 24, an internal Power-On Reset circuit keeps the driver outputs in a high-impedance state until the supply voltage has reached a level at which the device will reliably operate. This ensures that no spurious bits are transmitted on the bus pin outputs as the power supply turns on or turns off. As shown in the device FUNCTION TABLES, the enable inputs have the feature of default disable on both the driver enable and receiver enable. This ensures that the device will neither drive the bus nor report data on the R pin until the associated controller actively drives the enable pins. RECEIVER FAILSAFE The differential receiver is failsafe to invalid bus states caused by open bus conditions such as, a disconnected connector, shorted bus conditions caused by damaged cabling, or idle bus conditions that occur when no driver is actively driving a valid RD-485 bus state on the network. In any of these cases, the differential receiver will output a failsafe HIGH state, so that small noise signals do not cause spurious transitions at the receiver output. SAFE OPERATION WITH BUS CONTENTION These devices incorporate a driver current limit of 250 mA across the RS-485 common-mode range of -7 V to +12 V. As stated in the "Application Guidelines for TIA/EIA-485-A" (1) this sets a practical limitation to prevent damage during bus contention events. Contention can occur during system initialization, during system faults, or whenever two or more drivers are active at the same time. Figure 14 shows a 2-node system to demonstrate bus contention by forcing both drivers to be active in opposing states. (1) 14 TIA/EIA Telecommunications System Bulletin TSB89, "Application Guidelines for TIA/EIA-485-A" Submit Documentation Feedback Copyright (c) 2005-2010, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 - SN65HVD35 SN65HVD30 - SN65HVD35 www.ti.com SLLS665I - SEPTEMBER 2005 - REVISED APRIL 2010 Vcc2 Vcc1 ALWAYS HIGH D ALWAYS ENABLED DE 7V OFFSET GND 1 GND 2 Node 1 D-pin Node 2 DE -pin Bus Vdiff CONTENTION Figure 14. Bus Contention Example Figure 15 shows typical operation in a bus contention event. The bottom trace illustrates how the SN65HVD33 at Node 1 continues normal operation after a contention event between the two drivers, with a -7 V ground offset on Node 2. This illustrates how the HVD3x family of devices operates robustly in spite of bus contention faults, even with large common-mode offsets. Figure 15. HVD3x Drivers Operate Correctly After Bus Contention Faults Copyright (c) 2005-2010, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 - SN65HVD35 Submit Documentation Feedback 15 SN65HVD30 - SN65HVD35 SLLS665I - SEPTEMBER 2005 - REVISED APRIL 2010 www.ti.com FUNCTION TABLES Table 1. SN65HVD33, SN65HVD34, SN65HVD35 DRIVER INPUTS OUTPUTS D DE Y H H H Z L L H L H X L or open Z Z Open H L H Table 2. SN65HVD33, SN65HVD34, SN65HVD35 RECEIVER DIFFERENTIAL INPUTS VID = V(A) - V(B) ENABLE RE OUTPUT R VID -0.2 V L L -0.2 V < VID < -0.02 V L ? -0.02 V VID L H X H or open Z Open Circuit L H Idle circuit L H Short Circuit, V(A) = V(B) L H Table 3. SN65HVD30, SN65HVD31, SN65HVD32 DRIVER OUTPUTS INPUT D Y Z H H L L L H Open L H Table 4. SN65HVD30, SN65HVD31, SN65HVD32 RECEIVER 16 Submit Documentation Feedback DIFFERENTIAL INPUTS VID = V(A) - V(B) OUTPUT R VID -0.2 V L -0.2 V < VID < -0.02 V ? -0.02 V VID H Open Circuit H Idle circuit H Short Circuit, V(A) = V(B) H Copyright (c) 2005-2010, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 - SN65HVD35 SN65HVD30 - SN65HVD35 www.ti.com SLLS665I - SEPTEMBER 2005 - REVISED APRIL 2010 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS D and DE Input RE Input VCC VCC 130 kW Input 470 W Input 470 W 9V 9V 125 kW A Input B Input VCC VCC R1 22 V R1 22 V R3 R3 Input Input 22 V R2 22 V R2 R Output Y and Z Outputs VCC VCC 16 V 5W Output 16 V Output 9V R1/R2 R3 SN65HVD30, SN65HVD33 9 k 45 k SN65HVD31, SN65HVD32, SN65HVD34, SN65HVD35 36 k 180 k Copyright (c) 2005-2010, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 - SN65HVD35 Submit Documentation Feedback 17 SN65HVD30 - SN65HVD35 SLLS665I - SEPTEMBER 2005 - REVISED APRIL 2010 www.ti.com TYPICAL CHARACTERISTICS HVD30, HVD33 RMS SUPPLY CURRENT vs SIGNALING RATE HVD31, HVD34 RMS SUPPLY CURRENT vs SIGNALING RATE 55 60 TA = 25C RL = 54 W RE = VCC CL = 50 pF DE = VCC 55 ICC - RMS Supply Current - mA 50 ICC - RMS Supply Current - mA TA =25C RL = 54 W RE = VCC CL = 50 pF DE = VCC 45 VCC = 3.3 V 40 35 50 VCC = 3.3 V 45 40 35 30 30 0 5 10 15 20 25 0 1 2 3 Signaling Rate - Mbps Signaling Rate - Mbps Figure 16. Figure 17. 4 5 HVD32, HVD35 RMS SUPPLY CURRENT vs SIGNALING RATE 60 TA =25C RL = 54 W RE = VCC CL = 50 pF DE = VCC ICC - RMS Supply Current - mA 55 50 VCC = 3.3 V 45 40 35 30 0 0.2 0.4 0.6 0.8 1 Signaling Rate - Mbps Figure 18. 18 Submit Documentation Feedback Copyright (c) 2005-2010, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 - SN65HVD35 SN65HVD30 - SN65HVD35 www.ti.com SLLS665I - SEPTEMBER 2005 - REVISED APRIL 2010 TYPICAL CHARACTERISTICS (continued) HVD30, HVD33 BUS INPUT CURRENT vs INPUT VOLTAGE HVD31, HVD32, HVD34, HVD35 BUS INPUT CURRENT vs INPUT VOLTAGE 250 200 60 TA = 25C RE = 0 V DE = 0 V TA = 25C RE = 0 V DE = 0 V 40 100 II - Bus Input Current - uA II - Bus Input Current - mA 150 50 VCC = 3.3 V 0 -50 -100 20 0 VCC = 3.3 V -20 -40 -150 -200 -7 -60 -4 -1 2 5 8 11 14 -7 -4 -1 VI - Bus Input Voltage - V 8 11 Figure 20. DRIVER OUTPUT VOLTAGE vs DRIVER OUTPUT CURRENT DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs DRIVER OUTPUT CURRENT 14 3.5 VCC = 3.3 V, DE = VCC, D=0V VOH 3 VO - Driver Differential Output Voltage - V VO - Driver Output Voltage - V 5 Figure 19. 3.5 2.5 2 1.5 VOL 1 0.5 0 0 2 VI - Bus Input Voltage - V 20 40 60 80 IO - Driver Output Current - mA 100 100 W 60 W 3 VCC = 3.3 V, DE = VCC, D=0V 2.5 2 1.5 1 0.5 0 0 20 40 60 80 IO - Driver Output Current - mA Figure 21. 100 Figure 22. Copyright (c) 2005-2010, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 - SN65HVD35 Submit Documentation Feedback 19 SN65HVD30 - SN65HVD35 SLLS665I - SEPTEMBER 2005 - REVISED APRIL 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE DRIVER OUTPUT CURRENT vs SUPPLY VOLTAGE 2.5 40 3.6 V TA = 25C RL = 54 W D = VCC DE = VCC 35 RL = 60 W 2.3 IO - Driver Output Current - mA VOD - Differential Output Voltage - V 2.4 2.2 3.3 V 2.1 2 1.9 3V 1.8 30 25 20 15 10 1.7 5 1.6 1.5 0 -60 -40 -20 0 20 40 60 80 90 0 0.5 1 o TA - Free-Air Temperature - C 1.5 2 2.5 3 3.5 VCC Supply Voltage - V Figure 23. Figure 24. HVD30, HVD33 DRIVER PROPAGATION DELAY vs FREE-AIR TEMPERATURE HVD30, HVD33 DRIVER RISE/FALL TIME vs FREE-AIR TEMPERATURE 14 5 13 4.5 Driver Rise/Fall Time - ns Driver Propagation Delay - ns 12 3V 11 3.6 V 10 9 3V 4 3.6 V 3.5 3 8 2.5 7 2 6 -60 -40 -20 0 20 40 60 -60 -40 -20 0 20 40 TA - Free-Air Temperature - C TA - Free-Air Temperature - oC Figure 25. Figure 26. o 20 80 90 Submit Documentation Feedback 60 80 90 Copyright (c) 2005-2010, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 - SN65HVD35 SN65HVD30 - SN65HVD35 www.ti.com SLLS665I - SEPTEMBER 2005 - REVISED APRIL 2010 TYPICAL CHARACTERISTICS (continued) RECEIVER THRESHOLD vs COMMON-MODE VOLTAGE 0.00 0.00 -0.02 -0.02 -0.04 -0.04 VIT+ -0.06 Receiver Threshold - V Receiver Threshold - V RECEIVER THRESHOLD vs AMBIENT TEMPERATURE -0.08 -0.10 VIT- -0.12 -0.14 -0.08 -0.10 -0.14 -0.16 -0.18 -0.18 -25 0 25 50 75 100 VIT- -0.12 -0.16 -0.20 -50 VIT+ -0.06 -0.20 -7 125 TA - Ambient Temperature - C -5 -3 1 3 5 7 9 Figure 27. Figure 28. SUPPLY CURRENT vs FREE-AIR TEMPERATURE ENABLE TIME vs COMMON-MODE VOLTAGE (SEE Figure 31) 1.4 11 800 700 1.2 3.6 V HVD35 600 1 3V Enable Time - ns ICC - Supply Current - mA -1 VCM - Common-Mode Voltage - V 0.8 0.6 500 HVD34 400 300 0.4 Static, No Load 200 HVD33 0.2 0 -60 100 0 -40 -20 0 20 40 60 o TA - Free-Air Temperature - C 80 90 -7 -2 3 8 13 V(TEST) - Common-Mode Voltage - V Figure 29. Figure 30. Copyright (c) 2005-2010, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 - SN65HVD35 Submit Documentation Feedback 21 SN65HVD30 - SN65HVD35 SLLS665I - SEPTEMBER 2005 - REVISED APRIL 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) 375 W 1% Y D 0 or 3 V -7 V < V(TEST) < 12 V VOD 60 W 1% Z DE 375 W 1% Input Generator V 50 W 50% tpZH(diff) VOD (high) 1.5 V 0V tpZL(diff) -1.5 V VOD (low) Figure 31. Driver Enable Time From DE to VOD The time tpZL(x) is the measure from DE to VOD(x). VOD is valid when it is greater than 1.5 V. 22 Submit Documentation Feedback Copyright (c) 2005-2010, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD30 - SN65HVD35 PACKAGE OPTION ADDENDUM www.ti.com 19-Oct-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) SN65HVD30D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD30DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD30DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD30DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD31D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD31DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD31DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD31DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD32D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD32DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD32DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD32DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD33D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD33DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD33DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD33DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD33RHLR ACTIVE QFN RHL 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Addendum-Page 1 Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 19-Oct-2011 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) SN65HVD33RHLT ACTIVE QFN RHL 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN65HVD34D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD34DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD34DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD34DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD35D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD35DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD35DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD35DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 19-Oct-2011 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN65HVD30, SN65HVD33 : * Enhanced Product: SN65HVD30-EP, SN65HVD33-EP NOTE: Qualified Version Definitions: * Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65HVD30DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN65HVD31DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN65HVD32DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN65HVD33DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN65HVD33RHLR QFN RHL 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1 SN65HVD33RHLT QFN RHL 20 250 180.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1 SN65HVD34DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN65HVD35DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65HVD30DR SOIC D 8 2500 367.0 367.0 35.0 SN65HVD31DR SOIC D 8 2500 367.0 367.0 35.0 SN65HVD32DR SOIC D 8 2500 367.0 367.0 35.0 SN65HVD33DR SOIC D 14 2500 367.0 367.0 38.0 SN65HVD33RHLR QFN RHL 20 3000 367.0 367.0 35.0 SN65HVD33RHLT QFN RHL 20 250 210.0 185.0 35.0 SN65HVD34DR SOIC D 14 2500 367.0 367.0 38.0 SN65HVD35DR SOIC D 14 2500 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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