D-14(SOIC)RHL (QFN) D-8(SOIC)
SN65HVD30 – SN65HVD35
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SLLS665I –SEPTEMBER 2005–REVISED APRIL 2010
3.3 V FULL-DUPLEX RS-485 DRIVERS AND RECEIVERS
Check for Samples: SN65HVD30 – SN65HVD35
1FEATURES DESCRIPTION
• 1/8 Unit-Load Option Available (Up to
256 Nodes on the Bus) The SN65HVD3X devices are 3-state differential line
drivers and differential-input line receivers that
• Bus-Pin ESD Protection Exceeds 15 kV HBM operate with 3.3-V power supply.
• Optional Driver Output Transition Times for
Signaling Rates(1) of 1 Mbps, 5 Mbps and Each driver and receiver has separate input and
output pins for full-duplex bus communication
26 Mbps designs. They are designed for RS-422 and RS-485
• Low-Current Standby Mode: < 1 mAdata transmission over cable lengths of up to 1500
• Glitch-Free Power-Up and Power-Down meters.
Protection for Hot-Plugging Applications The SN65HVD30, SN65HVD31, and SN65HVD32
• 5-V Tolerant Inputs are fully enabled with no external enabling pins.
• Bus Idle, Open, and Short Circuit Failsafe The SN65HVD33, SN65HVD34, and SN65HVD35
• Driver Current Limiting and Thermal Shutdown have active-high driver enables and active-low
• Designed for RS-422 and RS-485 Networks receiver enables. A low, less than 1mA, standby
current can be achieved by disabling both the driver
• 5-V Devices available, SN65HVD50-55 and receiver.
(1) Line Signaling Rate is the number of voltage transitions made
per second expressed in units of bps (bits per second). All devices are characterized for ambient
temperatures from –40°C to 85°C. Low power
APPLICATIONS dissipation allows operation at temperatures up to
105°C or 125°C, depending on package option.
• Utility Meters
• DTE/DCE Interfaces
• Industrial, Process, and Building Automation
• Point-of-Sale (POS) Terminals and Networks
IMPROVED REPLACEMENT FOR:
Part Number Replace with
xxx3491 SN65HVD33: Better ESD protection (15kV vs 2kV or not specified) Higher Signaling Rate (26Mbps vs 20Mbps)
xxx3490 SN65HVD30: Fractional Unit Load (64 Nodes vs 32)
MAX3491E SN65HVD33: Higher Signaling Rate (26Mbps vs 12Mbps) Fractional Unit Load (64 Nodes vs 32)
MAX3490E SN65HVD30:
MAX3076E SN65HVD33: Higher Signaling Rate (26Mbps vs 16Mbps) Lower Standby Current (1 mA vs 10 mA)
MAX3077E SN65HVD30:
MAX3073E SN65HVD34: Higher Signaling Rate (5Mbps vs 500kbps) Lower Standby Current (1 mA vs 10 mA)
MAX3074E SN65HVD31:
MAX3070E SN65HVD35: Higher Signaling Rate (1Mbps vs 250kbps) Lower Standby Current (1 mA vs 10 mA)
MAX3071E SN65HVD32:
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains Copyright © 2005–2010, Texas Instruments Incorporated
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
R
D
B
A
Z
Y
7
8
6
5
2
3
DP (TOP VIEW)ACKAGE
1
2
3
4
8
7
6
5
R
D
VCC
B
A
Z
Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC
R
RE
DE
D
GND
GND
VCC
VCC
A
B
Z
Y
NC
NC-Nointernalconnection
Pins6and7areconnectedtogetherinternally
Pins13and14areconnectedtogetherinternally
1
2
3
4
5
6
7
8
910 11
19
18
17
16
15
14
13
12
20
VCC VCC
R
RE
DE
D
GND GND
Y
Z
A
B
NC
NC
NC
NC
NC
NC
NC
NC
NC-Nointernalconnection
Pins10and11areconnectedtogetherinternally
Pins1and20areconnectedtogetherinternally
RHL PACKAGE(TOP VIEW)
18
17 A
B
14
15
Y
Z
3
4
6
7
R
RE
DE
D
SN65HVD30 – SN65HVD35
SLLS665I –SEPTEMBER 2005–REVISED APRIL 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
SN65HVD30, SN65HVD31, SN65HVD32 SN65HVD33, SN65HVD34, SN65HVD35
SN65HVD33
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SLLS665I –SEPTEMBER 2005–REVISED APRIL 2010
AVAILABLE OPTIONS BASE
SIGNALING RATE UNIT LOADS ENABLES SOIC MARKING
PART NUMBER
26 Mbps 1/2 No SN65HVD30 VP30
5 Mbps 1/8 No SN65HVD31 VP31
1 Mbps 1/8 No SN65HVD32 VP32
26 Mbps 1/2 Yes SN65HVD33 65HVD33
5 Mbps 1/8 Yes SN65HVD34 65HVD34
1 Mbps 1/8 Yes SN65HVD35 65HVD35
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) (2)
UNIT
VCC Supply voltage range –0.3 V to 6 V
V(A), V(B), V(Y), V(Z) Voltage range at any bus terminal (A, B, Y, Z) –9 V to 14 V
V(TRANS) Voltage input, transient pulse through 100 Ω. See Figure 12 (A, B, Y, Z)(3) –50 to 50 V
VIInput voltage range (D, DE, RE) -0.5 V to 7 V
IOOutput current (receiver output only, R) 11 mA
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) This tests survivability only and the output state of the receiver is not specified.
DISSIPATION RATINGS
JEDEC THERMAL TA< 25°C DERATING FACTOR TA= 85°C TA= 105°C TA= 125°C
PACKAGE ABOVE TA= 25°C RATING RATING RATING
MODEL RATING
Low k 625 mW 5 mW/°C 325 mW
SOIC (D) 8 pin High k 1000 mW 8 mW/°C 520 mW 360 mW
Low k 765 mW 6.1 mW/°C 400 mW 275 mW
SOIC (D) 14 pin High k 1350 mW 10.8 mW/°C 705 mW 485 mW 270 mW
QFN (RHL) 20 pin High k 1710 mW 13.7 mW/°C 890 mW 6150 mW 340 mW
Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
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SN65HVD30 – SN65HVD35
SLLS665I –SEPTEMBER 2005–REVISED APRIL 2010
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range unless otherwise noted MIN NOM MAX UNIT
VCC Supply voltage 3 3.6 V
VIor VIC Voltage at any bus terminal (separately or common mode) –7(1) 12
SN65HVD30, SN65HVD33 26
1/tUI Signaling rate SN65HVD31, SN65HVD34 5 Mbps
SN65HVD32, SN65HVD35 1
RLDifferential load resistance 54 60 Ω
VIH High-level input voltage D, DE, RE 2 VCC
VIL Low-level input voltage D, DE, RE 0 0.8 V
VID Differential input voltage –12 12
Driver –60
IOH High-level output current mA
Receiver –8
Driver 60
IOL Low-level output current mA
Receiver 8
TJJunction temperature –40 150 °C
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
ELECTROSTATIC DISCHARGE PROTECTION
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
Human body model Bus terminals and GND ±16
Human body model(2) All pins ±4 kV
Charged-device-model(3) All pins ±1
(1) All typical values at 25°C with 3.3-V supply.
(2) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(3) Tested in accordance with JEDEC Standard 22, Test Method C101.
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SLLS665I –SEPTEMBER 2005–REVISED APRIL 2010
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VI(K) Input clamp voltage II= –18 mA –1.5 V
IO= 0 2.5 VCC
RL= 54 Ω, See Figure 1 (RS-485) 1.5 2
|VOD(SS)| Steady-state differential output voltage V
RL= 100 Ω, See Figure 1 ,(2) (RS-422) 2 2.3
Vtest = –7 V to 12 V, See Figure 2 1.5
Change in magnitude of steady-state
Δ|VOD(SS)| differential output voltage between RL= 54 Ω, See Figure 1 and Figure 2 –0.2 0.2 V
states
Differential Output Voltage overshoot RL= 54 Ω, CL= 50 pF, See Figure 5 and
VOD(RING) 10%(3) V
and undershoot Figure 3
HVD30, HVD33 0.5
Peak-to-peak
VOC(PP) common-mode See Figure 4 V
HVD31, HVD34, 0.25
output voltage HVD32, HVD35
Steady-state common-mode output
VOC(SS) 1.6 2.3
voltage See Figure 4 V
Change in steady-state common-mode
ΔVOC(SS) –0.05 0.05
output voltage VCC = 0 V, VZor VY= 12 V, 90
Other input at 0 V
HVD30, HVD31,
HVD32 VCC = 0 V, VZor VY= –7 V, –10
Other input at 0 V
IZ(Z) or High-impedance mA
IY(Z) state output current VCC = 3 V or 0 V, DE = 0 V 90
VZor VY= 12 V
HVD33, HVD34, Other input
HVD35 at 0 V
VCC = 3 V or 0 V, DE = 0 V –10
VZor VY= –7 V
VZor VY= –7 V –250 250
IZ(S) or Other input
Short Circuit output current(4) mA
IY(S) at 0 V
VZor VY= 12 V –250 250
IIInput current D, DE 0 100 mA
C(OD) Differential output capacitance VOD = 0.4 sin (4E6pt) + 0.5 V, DE at 0 V 16 pF
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) VCC is 3.3 Vdc ± 5%
(3) 10% of the peak-to-peak differential output voltage swing, per TIA/EIA-485
(4) Under some conditions of short-circuit to negative voltages, output currents exceeding the ANSI TIA/EIA-485-A maximum current of 250
mA may occur. Continuous exposure may affect device reliability. This applies to the HVD30,HVD31,HVD33, and HVD34.
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SN65HVD30 – SN65HVD35
SLLS665I –SEPTEMBER 2005–REVISED APRIL 2010
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DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
HVD30, HVD33 4 10 18
Propagation delay time, low-to-high-level
tPLH HVD31, HVD34 25 38 65 ns
output HVD32, HVD35 120 175 305
HVD30, HVD33 4 9 18
Propagation delay time, high-to-low-level
tPHL HVD31, HVD34 25 38 65 ns
output HVD32, HVD35 120 175 305
HVD30, HVD33 2.5 5 12
RL= 54 Ω, CL= 50 pF,
trDifferential output signal rise time HVD31, HVD34 20 37 60 ns
See Figure 5
HVD32, HVD35 120 185 300
HVD30, HVD33 2.5 5 12
tfDifferential output signal fall time HVD31, HVD34 20 35 60 ns
HVD32, HVD35 120 180 300
HVD30, HVD33 0.6
tsk(p) Pulse skew (|tPHL – tPLH|) HVD31, HVD34 2.0 ns
HVD32, HVD35 5.1
HVD33 45
Propagation delay time,
tPZH1 HVD34 235 ns
high-impedance-to-high-level output RL= 110 Ω, RE at 0 V,
HVD35 490
D = 3 V and S1 = Y, or
D = 0 V and S1 = Z
HVD33 25
See Figure 6
Propagation delay time,
tPHZ HVD34 65 ns
high-level-to-high-impedance output HVD35 165
HVD33 35
Propagation delay time,
tPZL1 HVD34 190 ns
high-impedance-to-low-level output RL= 110 Ω, RE at 0 V,
HVD35 490
D = 3 V and S1 = Z, or
D = 0 V and S1 = Y
HVD33 30
See Figure 7
Propagation delay time,
tPLZ HVD34 120 ns
low-level-to-high-impedance output HVD35 290
tPZH1, Driver enable delay with bus voltage offset VO= 2 V (Typ) 500 900 ns
tPZL1 RL= 110 Ω, RE at 3 V,
D = 3 V and S1 = Y, or
tPZH2 Propagation delay time, standby-to-high-level output 4000 ns
D = 0 V and S1 = Z
See Figure 6
RL= 110 Ω, RE at 3 V,
D = 3 V and S1 = Z, or
tPZL2 Propagation delay time, standby-to-low-level output 4000 ns
D = 0 V and S1 = Y
See Figure 7
(1) All typical values are at 25°C and with a 3.3-V supply.
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SLLS665I –SEPTEMBER 2005–REVISED APRIL 2010
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
Positive-going differential input threshold
VIT+ IO= –8 mA –0.02
voltage V
Negative-going differential input threshold
VIT- IO= 8 mA –0.20
voltage
Vhys Hysteresis voltage (VIT+ - VIT-) 50 mV
VIK Enable-input clamp voltage II= –18 mA –1.5 V
VID = 200 mV, IO= –8 mA, See Figure 8 2.4
VOOutput voltage V
VID = –200 mV, IO= 8 mA, See Figure 8 0.4
IO(Z) High-impedance-state output current VO= 0 or VCC, RE at VCC –1 1 mA
VAor VB= 12 V 0.05 0.1
VAor VB= 12 V, VCC = 0 V 0.06 0.1
HVD31, HVD32, Other input at mA
HVD34, HVD35 0V
VAor VB= -7 V –0.10 –0.04
VAor VB= -7 V, VCC = 0 V –0.10 –0.03
IAor Bus input current
IBVAor VB= 12 V 0.20 0.35
VAor VB= 12 V, VCC = 0 V 0.24 0.4
Other input at
HVD30, HVD33 mA
0V
VAor VB= -7 V –0.35 –0.18
VAor VB= -7 V, VCC = 0 V –0.25 –0.13
IIH Input current, RE VIH = 0.8 V or 2 V –60 mA
CID Differential input capacitance VID = 0.4 sin (4E6pt) + 0.5 V, DE at 0 V 15 pF
(1) All typical values are at 25°C and with a 3.3-V supply.
SUPPLY CURRENT CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
HVD30 2.1
D at 0 V or VCC and No Load mA
HVD31, HVD32 3.8 6.4
HVD33 1.8
RE at 0 V, D at 0 V or VCC, DE at 0 V, mA
No load (Receiver enabled and driver disabled)
HVD34, HVD35 2.2
RE at VCC, D at VCC, DE at 0 V,
ICC Supply current HVD33, HVD34, HVD35 No load (Receiver disabled and driver 0.022 1 mA
disabled)
HVD33 2.1
RE at 0 V, D at 0 V or VCC, DE at VCC,mA
No load (Receiver enabled and driver enabled)
HVD34, HVD35 6.5
HVD33 1.8
RE at VCC, D at 0 V or VCC, DE at VCC mA
No load (Receiver disabled and driver enabled)
HVD34, HVD35 6.2
(1) All typical values are at 25°C and with a 3.3-V supply.
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SLLS665I –SEPTEMBER 2005–REVISED APRIL 2010
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RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
HVD30, HVD33 26 45
Propagation delay time,
tPLH low-to-high-level output HVD31, HVD32, HVD34, HVD35 47 70
HVD30, HVD33 29 45
Propagation delay time,
tPHL high-to-low-level output HVD31, HVD32, HVD34, HVD35 49 70
VID = -1.5 V to 1.5 V,
CL= 15 pF, See Figure 9
HVD30, HVD33 7
tsk(p) Pulse skew (|tPHL – tPLH|) HVD31, HVD34, HVD32, HVD35 10
trOutput signal rise time 5 ns
tfOutput signal fall time 6
tPHZ Output disable time from high level 20
DE at 3 V CL= 15 pF,
tPZH1 Output enable time to high level 20
See Figure 10
tPZH2 Propagation delay time, standby-to-high-level output DE at 0 V 4000
tPLZ Output disable time from low level 20
DE at 3 V CL= 15 pF,
tPZL1 Output enable time to low level 20
See Figure 11
tPZL2 Propagation delay time, standby-to-low-level output DE at 0 V 4000
(1) All typical values are at 25°C and with a 3.3-V supply
DEVICE POWER DISSIPATION – PD
PARAMETER TEST CONDITIONS VALU UNITS
E
JEDEC Low-K model 231
SOIC-8 JEDEC High-K model 135
qJA Junction-to-Ambient Thermal Resistance JEDEC Low-K model 163 °C/W
SOIC-14 JEDEC High-K model 92
QFN-20 73
SOIC-8 44
qJB Junction-to- Board Thermal Resistance SOIC-14 61 °C/W
QFN-20
SOIC-8 43
qJC Junction-to-Case Thermal Resistance SOIC-14 59 °C/W
QFN-20 14
Power Dissipation HVD30,33 VCC = 3.3V, TJ= 25°C,
Driver and receiver enabled, 50% duty RL= 60 Ω, CL= 50 pF (driver),
Typical HVD31,34 mW
cycle square-wave signal at signaling CL= 15 pF (receiver)
HVD32,35
rate:
PDHVD30,33 at 25 Mbps, HVD30,33 VCC = 3.6V, TJ= 140°C, 197
HVD31,34 at 5 Mbps, RL= 54 Ω, CL= 50 pF (driver),
Worst-case HVD31,34 213 mW
HVD32,35 at 1 Mbps CL= 15 pF (receiver)
HVD32,35 248
TSD Thermal Shut-down Junction Temperature 170 °C
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Product Folder Link(s) :SN65HVD30 – SN65HVD35
IY
VOD RL
0or3V
VY
VZ
IZ
DE
VCC
II
VI
Y
Z
60 Ω±1%
VOD
0or3V
_
+−7V<V(test) <12V
DE
VCC
Y
Z
D
375 Ω±1%
375 Ω±1%
VOD(RING)
VOD(RING)
–VOD(SS)
VOD(SS)
0VDifferential
SN65HVD30 – SN65HVD35
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SLLS665I –SEPTEMBER 2005–REVISED APRIL 2010
PARAMETER MEASUREMENT INFORMATION
Figure 1. Driver VOD Test Circuit and Voltage and Current Definitions
Figure 2. Driver VOD With Common-Mode Loading Test Circuit
Figure 3. VOD(RING) Waveform and Definitions
VOD(RING) is measured at four points on the output waveform, corresponding to overshoot and undershoot from
the VOD(H) and VOD(L) steady state values.
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Product Folder Link(s) :SN65HVD30 – SN65HVD35
VOC
27 Ω ±1%
Input
Y
Z
VY
VZ
VOC(PP) ∆VOC(SS)
VOC
27 Ω ±1%
CL=50pF ±20%
DY
Z
DE
VCC
Input:PRR=500kHz,50%DutyCycle,t r<6ns,tf<6ns,ZO=50 Ω
CLIncludesFixtureand
InstrumentationCapacitance
VI
VO
tPZH(1&2)
50 W
D
DS1
3V Y
0VZ Y
Z
VI
RL=110 W
±1%
CL=50 pF
±20%
VO
Generator:PRR=50kHz,50%DutyCycle,tr<6ns,tf<6ns,Z0=50 W
CLIncludesFixtureandInstrumentationCapacitance
3V
1.5V
1.5V
tPHZ
2.3V
DE
Input
Generator
~0V
VOH
0.5V 0V
S1
SN65HVD30 – SN65HVD35
SLLS665I –SEPTEMBER 2005–REVISED APRIL 2010
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PARAMETER MEASUREMENT INFORMATION (continued)
Figure 4. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
Figure 5. Driver Switching Test Circuit and Voltage Waveforms
Figure 6. Driver High-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
10 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated
Product Folder Link(s) :SN65HVD30 – SN65HVD35
Input
Generator 50 Ω
VO
S1
VCC
3V
VCC
1.5V 1.5V
tPZL(1&2) tPLZ
2.3V
0.5V
0V
VOL
VI
VO
RL=110 Ω
±1%
CL=50pF ±20%
D
Y
Z
DE
VI
DS1
3VZ
0V Y
Generator:PRR=50kHz,50%DutyCycle,tr<6ns,tf<6ns,Z0=50 W
CLIncludesFixtureandInstrumentationCapacitance
VID
VA
VB
IO
A
B
IBVO
R
RE
IA
VIC
VA+VB
2IIVI
Input
Generator 50 Ω
Generator:PRR=500kHz,50%DutyCycle,t r<6ns,tf<6ns,Zo=50 Ω
VO
1.5V
0V
1.5V 1.5V
3V
VOH
VOL
1.5V
10%
1.5V
tPLH tPHL
trtf
90%
VI
VO
CL=15pF
±20%
C IncludesFixtureandInstrumentationCapacitance
L
A
B
RE
VI
R
0V
90%
10%
B
A
RVO
50 W
VI
Input
Generator
CL=15 pF
±20%
CLIncludesFixtureand
InstrumentationCapacitance
RE
S1
1k W±1%
A
B
VCC
VI
tPZH(1&2)
3V
1.5V
1.5V
tPHZ
0V
VO
1.5V
~0V
VOH
0.5V
1.5V
0V
Generator:PRR=50kHz,50%DutyCycle,tr<6ns,tf<6ns,Z0=50 W
SN65HVD30 – SN65HVD35
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SLLS665I –SEPTEMBER 2005–REVISED APRIL 2010
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 7. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
Figure 8. Receiver Voltage and Current Definitions
Figure 9. Receiver Switching Test Circuit and Voltage Waveforms
Figure 10. Receiver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s) :SN65HVD30 – SN65HVD35
B
A
RVO
50 W
VI
Input
Generator
CL=15 pF
±20%
CLIncludesFixture
andInstrumentation
Capacitance
RE
S1
1k W±1%
A
B
VCC
VI
VO
3V
1.5V
1.5V
VCC
VOL
0.5V
0V
1.5V
tPZL(1&2) tPLZ
0V
1.5V
Generator:PRR=50kHz,50%DutyCycle,tr<6ns,tf<6ns,Z0=50 W
B
A
R
100 W
±1%
+
-
PulseGenerator
15 msduration
1%DutyCycle
t ,t 100ns
r f £
Z
Y
D
100 W
±1%
+
-
DE
0Vor3V
0Vor3V
RE
SN65HVD30 – SN65HVD35
SLLS665I –SEPTEMBER 2005–REVISED APRIL 2010
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 11. Receiver Enable Time From Standby (Driver Disabled)
Figure 12. Test Circuit, Transient Over Voltage Test
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Product Folder Link(s) :SN65HVD30 – SN65HVD35
4
5
9
10
Y
Z
D
DE
A
B
12
11
2
R
3
RE
Low-Power
Standby
SN65HVD30 – SN65HVD35
www.ti.com
SLLS665I –SEPTEMBER 2005–REVISED APRIL 2010
DEVICE INFORMATION
LOW-POWER STANDBY MODE
When both the driver and receiver are disabled (DE low and RE high) the device is in standby mode. If the
enable inputs are in this state for less than 60 ns, the device does not enter standby mode. This guards against
inadvertently entering standby mode during driver/receiver enabling. Only when the enable inputs are held in this
state for 300 ns or more, the device is assured to be in standby mode. In this low-power standby mode, most
internal circuitry is powered down, and the supply current is typically less than 1 nA. When either the driver or the
receiver is re-enabled, the internal circuitry becomes active.
Figure 13. Low-Power Standby Logic Diagram
If only the driver is re-enabled (DE transitions to high) the driver outputs are driven according to the D input after
the enable times given by tPZH2 and tPZL2 in the driver switching characteristics. If the D input is open when the
driver is enabled, the driver outputs defaults to A high and B low, in accordance with the driver failsafe feature.
If only the receiver is re-enabled (RE transitions to low) the receiver output is driven according to the state of the
bus inputs (A and B) after the enable times given by tPZH2 and tPZL2 in the receiver switching characteristics. If
there is no valid state on the bus the receiver responds as described in the failsafe operation section.
If both the receiver and driver are re-enabled simultaneously, the receiver output is driven according to the state
of the bus inputs (A and B) and the driver output is driven according to the D input. Note that the state of the
active driver affects the inputs to the receiver. Therefore, the receiver outputs are valid as soon as the driver
outputs are valid.
DRIVER OUTPUT CURRENT LIMITING
The RS-485 standard (ANSI/TIA/EIA-485-A or equivalently ISO 8482) specifies a 250 mA driver output current
limit to prevent damage caused by data contention on the bus. That applies in the event that two or more
transceivers drive the bus to opposing states at the same time. The HVD3x family of devices includes current
limiting circuitry that prevents damage under these conditions. Note that this current limit prevents damage
during the bus contention, but the logic state of the bus may be indeterminate as specified by the standard, so
communication errors may occur.
In a specific combination of circumstances, a condition may occur in which current through the bus pin exceeds
the 250 mA limit. This combination of conditions is not normally included in RS-485 applications:
•loading capacitance on the pin is less than 500 pF
•the bus pin is directly connected to a voltage more negative than –1V
•the device is supplied with Vcc equal or greater than 3.3V
•the driver is enabled
• the bus pin is driving to the logic high state.
In these specific conditions, the normal current limit circuitry and thermal shutdown circuitry will not limit or
shutdown the current flow. If the current is allowed to continue, the device will heat up in a localized area near
the driver outputs, and the device may be damaged.
Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s) :SN65HVD30 – SN65HVD35
SN65HVD30 – SN65HVD35
SLLS665I –SEPTEMBER 2005–REVISED APRIL 2010
www.ti.com
Typical RS-485 twisted-pair cable has capacitance of approximately 50 pF/meter. Therefore it is expected that 10
meters of cable would provide sufficient capacitance to prevent this latch-up condition.
The –7 to +12V common mode range specified by RS-485 is intended to allow communication between
transceivers separated by significant distances, when ground offsets may occur due to temporary current surges,
electrical noise, etc. In those circumstances, the inherent cable needed to connect separated transceivers will
ensure that the conditions above do not occur. For transceiver separated by only a short cable length, or
backplane applications, it would be unusual for there to be a steady-state negative common-mode voltage. It is
possible for a negative power supply to be shorted to the bus lines due to mis-wiring or cable damage, however,
this is a different root cause fault, and robust devices such as the HVD178x family should be used for surviving
power supply or mis-wiring faults.
The 250 mA current limit in the RS-485 standard is intended to prevent damage caused by data contention on
the bus; that is, in the event that two or more transceivers drive the bus to different states at the same time.
These devices will not be damaged under these conditions, because all RS-485 drivers have output impedance
sufficient to prevent the direct connection condition stated above. Typical RS-485 driver output impedance is on
the order of 10 to 30 Ω.
HOT-PLUGGING
These devices are designed to operate in hot swap or hot pluggable applications. Key features for hot-pluggable
applications are power-up, power-down glitch-free operation, default disabled input/output pins, and receiver
failsafe. As shown in Figure 24, an internal Power-On Reset circuit keeps the driver outputs in a high-impedance
state until the supply voltage has reached a level at which the device will reliably operate. This ensures that no
spurious bits are transmitted on the bus pin outputs as the power supply turns on or turns off.
As shown in the device FUNCTION TABLES, the enable inputs have the feature of default disable on both the
driver enable and receiver enable. This ensures that the device will neither drive the bus nor report data on the R
pin until the associated controller actively drives the enable pins.
RECEIVER FAILSAFE
The differential receiver is failsafe to invalid bus states caused by open bus conditions such as, a disconnected
connector, shorted bus conditions caused by damaged cabling, or idle bus conditions that occur when no driver
is actively driving a valid RD-485 bus state on the network. In any of these cases, the differential receiver will
output a failsafe HIGH state, so that small noise signals do not cause spurious transitions at the receiver output.
SAFE OPERATION WITH BUS CONTENTION
These devices incorporate a driver current limit of 250 mA across the RS-485 common-mode range of –7 V to
+12 V. As stated in the "Application Guidelines for TIA/EIA-485-A" (1) this sets a practical limitation to prevent
damage during bus contention events. Contention can occur during system initialization, during system faults, or
whenever two or more drivers are active at the same time.
Figure 14 shows a 2-node system to demonstrate bus contention by forcing both drivers to be active in opposing
states.
(1) TIA/EIA Telecommunications System Bulletin TSB89, "Application Guidelines for TIA/EIA-485-A"
14 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated
Product Folder Link(s) :SN65HVD30 – SN65HVD35
Vcc2
Vcc1
GND
1
GND
2
±7V
OFFSET
ALWAYS
ENABLED
ALWAYS
HIGH
Node 1 D-pin
Node 2 DE -pin
BusVdiff
D
DE
CONTENTION
SN65HVD30 – SN65HVD35
www.ti.com
SLLS665I –SEPTEMBER 2005–REVISED APRIL 2010
Figure 14. Bus Contention Example
Figure 15 shows typical operation in a bus contention event. The bottom trace illustrates how the SN65HVD33 at
Node 1 continues normal operation after a contention event between the two drivers, with a –7 V ground offset
on Node 2. This illustrates how the HVD3x family of devices operates robustly in spite of bus contention faults,
even with large common-mode offsets.
Figure 15. HVD3x Drivers Operate Correctly After Bus Contention Faults
Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s) :SN65HVD30 – SN65HVD35
SN65HVD30 – SN65HVD35
SLLS665I –SEPTEMBER 2005–REVISED APRIL 2010
www.ti.com
FUNCTION TABLES
Table 1. SN65HVD33, SN65HVD34, SN65HVD35
DRIVER
INPUTS OUTPUTS
D DE Y Z
H H H L
L H L H
X L or open Z Z
Open H L H
Table 2. SN65HVD33, SN65HVD34, SN65HVD35
RECEIVER
DIFFERENTIAL INPUTS ENABLE OUTPUT
VID = V(A) - V(B) RE R
VID ≤ −0.2 V L L
−0.2 V < VID <−0.02 V L ?
−0.02 V ≤VID L H
X H or open Z
Open Circuit L H
Idle circuit L H
Short Circuit, V(A) = V(B) L H
Table 3. SN65HVD30, SN65HVD31, SN65HVD32
DRIVER
OUTPUTS
INPUT Y Z
D
H H L
L L H
Open L H
Table 4. SN65HVD30, SN65HVD31, SN65HVD32
RECEIVER
DIFFERENTIAL INPUTS OUTPUT
VID = V(A) - V(B) R
VID ≤ −0.2 V L
−0.2 V < VID <−0.02 V ?
−0.02 V ≤VID H
Open Circuit H
Idle circuit H
Short Circuit, V(A) = V(B) H
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Product Folder Link(s) :SN65HVD30 – SN65HVD35
VCC
Input
470 W
130 kW
VCC
5W
Output
ROutput
9 V
9 V
R3
22 V
22 V
Input
R2
R1
VCC
A Input
R3
22 V
22 V
Input
R2
R1
VCC
BInput
16 V
16 V
Y andZOutputs
Output
VCC
RE Input
VCC
Input
470 W
125 kW
9 V
DandDEInput
SN65HVD30 – SN65HVD35
www.ti.com
SLLS665I –SEPTEMBER 2005–REVISED APRIL 2010
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
R1/R2 R3
SN65HVD30, SN65HVD33 9 kΩ45 kΩ
SN65HVD31, SN65HVD32, SN65HVD34, SN65HVD35 36 kΩ180 kΩ
Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s) :SN65HVD30 – SN65HVD35
30
35
40
45
50
55
0 5 10 15 20 25
SignalingRate-Mbps
I -RMSSupplyCurrent-mA
CC
T =25°CR =54
=V C =50pF
DE=V
AL
CC L
CC
W
RE
V =3.3V
CC
30
35
40
45
50
55
60
0 1 2 3 4 5
SignalingRate-Mbps
I -RMSSupplyCurrent-mA
CC
T =25°CR =54
=V C =50pF
DE=V
AL
CC L
CC
W
RE
V =3.3V
CC
30
35
40
45
50
55
60
0 0.2 0.4 0.6 0.8 1
SignalingRate-Mbps
I -RMSSupplyCurrent-mA
CC
T =25°CR =54
=V C =50pF
DE=V
AL
CC L
CC
W
RE
V =3.3V
CC
SN65HVD30 – SN65HVD35
SLLS665I –SEPTEMBER 2005–REVISED APRIL 2010
www.ti.com
TYPICAL CHARACTERISTICS
HVD30, HVD33 HVD31, HVD34
RMS SUPPLY CURRENT RMS SUPPLY CURRENT
vs vs
SIGNALING RATE SIGNALING RATE
Figure 16. Figure 17.
HVD32, HVD35
RMS SUPPLY CURRENT
vs
SIGNALING RATE
Figure 18.
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Product Folder Link(s) :SN65HVD30 – SN65HVD35
–200
–150
–100
–50
50
0
100
150
200
250
–7 –4 –1 2 5 8 11 14
V -BusInputVoltage-V
I
I -BusInputCurrent- A
Im
T =25°C
=0V
DE=0V
A
RE
V =3.3V
CC
-60
-40
-20
20
40
0
60
-7 -4 -1 2 5 8 11 14
V -BusInputVoltage-V
I
I -BusInputCurrent-uA
I
T =25°C
=0V
DE=0V
A
RE
V =3.3V
CC
0
0.5
1
1.5
2
2.5
3
3.5
0 20 40 60 80 100
I -DriverOutputCurrent-mA
O
V -DriverOutputVoltage-V
O
V =3.3V,
DE=V ,
D=0V
CC
CC
VOH
VOL
0
0.5
1
1.5
2
2.5
3
3.5
0 20 40 60 80 100
I -DriverOutputCurrent-mA
O
100 W60 W
V -DriverDifferentialOutputVoltage-V
O
V =3.3V,
DE=V ,
D=0V
CC
CC
SN65HVD30 – SN65HVD35
www.ti.com
SLLS665I –SEPTEMBER 2005–REVISED APRIL 2010
TYPICAL CHARACTERISTICS (continued)
HVD30, HVD33 HVD31, HVD32, HVD34, HVD35
BUS INPUT CURRENT BUS INPUT CURRENT
vs vs
INPUT VOLTAGE INPUT VOLTAGE
Figure 19. Figure 20.
DRIVER OUTPUT VOLTAGE DRIVER DIFFERENTIAL OUTPUT VOLTAGE
vs vs
DRIVER OUTPUT CURRENT DRIVER OUTPUT CURRENT
Figure 21. Figure 22.
Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s) :SN65HVD30 – SN65HVD35
V -DifferentialOutputVoltage-V
OD
2.3
0
T − Free-AirTemperature − C
A
o
2.5
2.4
1.8
2.2
2
1.9
1.6
1.5
-60 -40 90-20 20 40 60 80
2.1
1.7
3V
3.3V
3.6V R =60
LW
0
5
10
15
20
25
30
35
40
0 0.5 1 1.5 2 2.5 3 3.5
V SupplyVoltage-V
CC
I -DriverOutputCurrent-mA
O
T =25°C
R =54
D=V
DE=V
A
L
CC
CC
W
0
T − Free-AirTemperature − C
A
o
DriverRise/FallTime-ns
5
4.5
3
4
3.5
2
-60 -40 90-20 20 40 60 80
2.5
3V
3.6V
12
0
T − Free-AirTemperature − C
A
o
DriverPropagationDelay-ns
14
3V
3.6V
13
8
11
10
9
7
6
-60 -40 90-20 20 40 60 80
SN65HVD30 – SN65HVD35
SLLS665I –SEPTEMBER 2005–REVISED APRIL 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
DRIVER DIFFERENTIAL OUTPUT VOLTAGE DRIVER OUTPUT CURRENT
vs vs
FREE-AIR TEMPERATURE SUPPLY VOLTAGE
Figure 23. Figure 24.
HVD30, HVD33 HVD30, HVD33
DRIVER PROPAGATION DELAY DRIVER RISE/FALL TIME
vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 25. Figure 26.
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Product Folder Link(s) :SN65HVD30 – SN65HVD35
TA − Ambient Temperature − °C
−0.20
−0.18
−0.16
−0.14
−0.12
−0.10
−0.08
−0.06
−0.04
−0.02
0.00
−50 −25 0 25 50 75 100 125
Receiver Threshold − V
VIT+
VIT−
VCM − Common-Mode Voltage − V
−0.20
−0.18
−0.16
−0.14
−0.12
−0.10
−0.08
−0.06
−0.04
−0.02
0.00
−7 −5 −3 −1 1 3 5 7 9 11
Receiver Threshold − V
VIT+
VIT−
1.2
0
T − Free-AirTemperature − C
A
o
I -SupplyCurrent-mA
CC
1.4
3V
3.6V
0.4
1
0.8
0.6
0.2
0
-60 -40 90-20 20 40 60 80
Static,
NoLoad
HVD35
HVD34
0
100
600
700
800
-7 -2 3 8 13
HVD33
EnableTime − ns
V −
(TEST) Common-ModeVoltage − V
200
300
400
500
SN65HVD30 – SN65HVD35
www.ti.com
SLLS665I –SEPTEMBER 2005–REVISED APRIL 2010
TYPICAL CHARACTERISTICS (continued)
RECEIVER THRESHOLD RECEIVER THRESHOLD
vs vs
AMBIENT TEMPERATURE COMMON-MODE VOLTAGE
Figure 27. Figure 28.
SUPPLY CURRENT ENABLE TIME
vs vs
FREE-AIR TEMPERATURE COMMON-MODE VOLTAGE (SEE Figure 31)
Figure 29. Figure 30.
Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s) :SN65HVD30 – SN65HVD35
60 W
1%±
50 W
375 W1%±
-7V<V <12V
(TEST)
VOD
V (low)
OD
t (diff)
pZL
t (diff)
pZH
V
0or3V
375 W1%±
50%
0V
1.5V
D
Z
DE
Y
-1.5V
V (high)
OD
Input
Generator
SN65HVD30 – SN65HVD35
SLLS665I –SEPTEMBER 2005–REVISED APRIL 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Figure 31. Driver Enable Time From DE to VOD
The time tpZL(x) is the measure from DE to VOD(x). VOD is valid when it is greater than 1.5 V.
22 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated
Product Folder Link(s) :SN65HVD30 – SN65HVD35
PACKAGE OPTION ADDENDUM
www.ti.com 19-Oct-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN65HVD30D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD30DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD30DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD30DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD31D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD31DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD31DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD31DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD32D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD32DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD32DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD32DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD33D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD33DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD33DR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD33DRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD33RHLR ACTIVE QFN RHL 20 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 19-Oct-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN65HVD33RHLT ACTIVE QFN RHL 20 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN65HVD34D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD34DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD34DR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD34DRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD35D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD35DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD35DR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65HVD35DRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 19-Oct-2011
Addendum-Page 3
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65HVD30, SN65HVD33 :
•Enhanced Product: SN65HVD30-EP, SN65HVD33-EP
NOTE: Qualified Version Definitions:
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65HVD30DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD31DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD32DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD33DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN65HVD33RHLR QFN RHL 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1
SN65HVD33RHLT QFN RHL 20 250 180.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1
SN65HVD34DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN65HVD35DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65HVD30DR SOIC D 8 2500 367.0 367.0 35.0
SN65HVD31DR SOIC D 8 2500 367.0 367.0 35.0
SN65HVD32DR SOIC D 8 2500 367.0 367.0 35.0
SN65HVD33DR SOIC D 14 2500 367.0 367.0 38.0
SN65HVD33RHLR QFN RHL 20 3000 367.0 367.0 35.0
SN65HVD33RHLT QFN RHL 20 250 210.0 185.0 35.0
SN65HVD34DR SOIC D 14 2500 367.0 367.0 38.0
SN65HVD35DR SOIC D 14 2500 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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