Features * High Performance, Low Power 32-bit AVR(R) Microcontroller * * * * * * * * * * * * * * * - Compact Single-Cycle RISC Instruction Set Including DSP Instructions - Read-Modify-Write Instructions and Atomic Bit Manipulation - Performance * Up to 64 DMIPS Running at 50MHz from Flash (1 Flash Wait State) * Up to 36 DMIPS Running at 25MHz from Flash (0 Flash Wait State) - Memory Protection Unit (MPU) * Secure Access Unit (SAU) providing user defined peripheral protection picoPowerTM Technology for Ultra-Low Power Consumption Multi-Hierarchy Bus System - High-Performance Data Transfers on Separate Buses for Increased Performance - 12 Peripheral DMA Channels Improve Speed for Peripheral Communication Internal High-Speed Flash - 64Kbytes, 32Kbytes, and 16Kbytes Versions - Single-Cycle Access up to 25MHz - FlashVaultTM Technology Allows Pre-programmed Secure Library Support for End User Applications - Prefetch Buffer Optimizing Instruction Execution at Maximum Speed - 4ms Page Programming Time and 8ms Full-Chip Erase Time - 100,000 Write Cycles, 15-year Data Retention Capability - Flash Security Locks and User Defined Configuration Area Internal High-Speed SRAM, Single-Cycle Access at Full Speed - 16Kbytes (64Kbytes and 32Kbytes Flash), or 8Kbytes (16Kbytes Flash) Interrupt Controller (INTC) - Autovectored Low Latency Interrupt Service with Programmable Priority External Interrupt Controller (EIC) Peripheral Event System for Direct Peripheral to Peripheral Communication System Functions - Power and Clock Manager - SleepWalkingTM Power Saving Control - Internal System RC Oscillator (RCSYS) - 32 KHz Oscillator - Multipurpose Oscillator and Digital Frequency Locked Loop (DFLL) Windowed Watchdog Timer (WDT) Asynchronous Timer (AST) with Real-Time Clock Capability - Counter or Calendar Mode Supported Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency Six 16-bit Timer/Counter (TC) Channels - External Clock Inputs, PWM, Capture and Various Counting Capabilities PWM Channels on All I/O Pins (PWMA) - 8-bit PWM up to 150MHz Source Clock Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART) - Independent Baudrate Generator, Support for SPI - Support for Hardware Handshaking One Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals - Up to 15 SPI Slaves can be Addressed 32-bit AVR(R) Microcontroller AT32UC3L064 AT32UC3L032 AT32UC3L016 Preliminary Summary 32099B-05/2010 AT32UC3L * Two Master and Two Slave Two-Wire Interfaces (TWI), 400kbit/s I2C-compatible * One 8-channel Analog-To-Digital Converter (ADC) with up to 12 Bits Resolution * * * * * * - Internal Temperature Sensor Eight Analog Comparators (AC) with Optional Window Detection Capacitive Touch (CAT) Module - Support QTouchTM and QMatrixTM Capture from Capacitive Touch Sensors On-Chip Non-Intrusive Debug System - Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace - aWireTM Single-Pin Programming Trace and Debug Interface Muxed with Reset Pin - NanoTraceTM Provides Trace Capabilities through JTAG or aWire Interface 48-pin TQFP/QFN/TLLGA (36 GPIO Pins) Five High-Drive I/O Pins Single 1.62-3.6V Power Supply 2 32099B-05/2010 AT32UC3L 1. Description The AT32UC3L is a complete System-On-Chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 50MHz. AVR32 UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density, and high performance. The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt controller for supporting modern operating systems and real-time operating systems. The Secure Access Unit (SAU) is used together with the MPU to provide the required security and integrity. Higher computation capability is achieved using a rich set of DSP instructions. The AT32UC3L embeds state-of-the-art picoPower technology for ultra-low power consumption. Combined power control techniques are used to bring active power as low as 0.5mW/MHz, and leakage down to 100nA while still retaining a bank of backup registers. The device allows a wide range of trade-offs between functionality and power consumption, giving the user the ability to reach the lowest possible power consumption with the feature set required for the application. The Peripheral Direct Memory Access (DMA) controller enables data transfers between peripherals and memories without processor involvement. The Peripheral DMA controller drastically reduces processing overhead when transferring continuous and large data streams. The AT32UC3L incorporates on-chip Flash and SRAM memories for secure and fast access. The FlashVault technology allows secure libraries to be programmed into the device. The secure libraries can be executed while the CPU is in Secure State, but not read by non-secure software in the device. The device can thus be shipped to end costumers, who will be able to program their own code into the device, accessing the secure libraries, but without risk of compromising the proprietary secure code. The Peripheral Event System allows peripherals to receive, react to, and send peripheral events without CPU intervention. Asynchronous interrupts allow advanced peripheral operation in low power sleep modes. The Power Manager improves design flexibility and security. The Power Manager supports SleepWalking functionality, by which a module can be selectively activated based on peripheral events, even in sleep modes where the module clock is stopped. Power monitoring is supported by on-chip Power-On Reset (POR), Brown-Out Detector (BOD), and Supply Monitor (SM). The device features several oscillators, such as Digital Frequency Locked Loop (DFLL), Oscillator 0 (OSC0), and system RC oscillator (RCSYS). Either of these oscillators can be used as source for the system clock. The DFLL is a programmable internal oscillator from 40 to 150MHz. It can be tuned to a high accuracy if an accurate oscillator is running, e.g. the 32KHz crystal oscillator. The Watchdog Timer (WDT) will reset the device unless it is periodically serviced by the software. This allows the device to recover from a condition that has caused the system to be unstable. The Asynchronous Timer (AST) combined with the 32KHz crystal oscillator supports powerful real-time clock capabilities, with a maximum timeout of up to 136 years. The AST can operate in counter mode or calendar mode. The Frequency Meter (FREQM) allows accurate measuring of a clock frequency by comparing it to a known reference clock. 3 32099B-05/2010 AT32UC3L The device includes six identical 16-bit Timer/Counter (TC) channels. Each channel can be independently programmed to perform frequency measurement, event counting, interval measurement, pulse generation, delay timing, and pulse width modulation. The Pulse Width Modulation controller (PWMA) provides 8-bit PWM channels which can be synchronized and controlled from a common timer. One PWM channel is available for each I/O pin on the device, enabling applications that require multiple PWM outputs, such as LCD backlight control. The PWM channels can operate independently, with duty cycles set independently from each other, or in interlinked mode, with multiple channels changed at the same time. The AT32UC3L also features many communication interfaces for communication intensive applications like USART, SPI, or TWI. A general purpose 8-channel ADC is provided, as well as eight analog comparators (AC). The ADC can operate in 10-bit mode at full speed or in enhanced mode at reduced speed, offering up to 12-bit resolution. The ADC also provides an internal temperature sensor input channel. The analog comparators can be paired to detect when the sensing voltage is within or outside the defined reference window. The Capacitive Touch (CAT) module senses touch on external capacitive touch sensors, using the QTouch technology. Capacitive touch sensors use no external mechanical components, unlike normal push buttons, and therefore demand less maintenance in the user application. The CAT module allows up to 17 touch sensors, or up to 16 by 8 matrix sensors to be interfaced. One touch sensor can be configured to operate autonomously without software interaction, allowing wakeup from sleep modes when activated. The AT32UC3L integrates a class 2+ Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive real-time trace, full-speed read/write memory access, in addition to basic runtime control. The NanoTrace interface enables trace feature for aWire- or JTAG-based debuggers. The single-pin aWire interface allows all features available through the JTAG interface to be accessed through the RESET pin, allowing the JTAG pins to be used for GPIO or peripherals. 4 32099B-05/2010 AT32UC3L 2. Overview Block Diagram JTAG INTERFACE DATAOUT aWire NEXUS CLASS 2+ OCD MEMORY PROTECTION UNIT INSTR INTERFACE DATA INTERFACE M M M SAU S REGISTERS BUS PERIPHERAL DMA CONTROLLER HSB-PB BRIDGE A POWER MANAGER CLOCK CONTROLLER SLEEP CONTROLLER RESET CONTROLLER 64/32/16 KB FLASH M DMA PA PB GENERALPURPOSE I/Os HSB-PB BRIDGE B 16/8 KB SRAM S S CONFIGURATION LOCAL BUS S HIGH SPEED BUS MATRIX S/M LOCAL BUS INTERFACE CAPACITIVE TOUCH MODULE DMA RESET_N TCK TDO TDI TMS AVR32UC CPU FLASH CONTROLLER MCKO MDO[5..0] MSEO[1..0] EVTI_N EVTO_N MEMORY INTERFACE Block Diagram USART0 USART1 USART2 USART3 DMA Figure 2-1. SPI DMA 2.1 TWI MASTER 0 TWI MASTER 1 CSA[16:0] CSB[16:0] SMP SYNC RXD TXD CLK RTS, CTS RCSYS RC32K XIN32 XOUT32 OSC32K XIN0 XOUT0 OSC0 SYSTEM CONTROL INTERFACE DFLL TWI SLAVE 0 TWI SLAVE 1 INTERRUPT CONTROLLER NMI PWM[35..0] DMA BOD EXTINT[5..1] NPCS[3..0] TWCK TWD TWALM TWCK DMA RC120M MISO, MOSI 8-CHANNEL ADC INTERFACE EXTERNAL INTERRUPT CONTROLLER PWM CONTROLLER FREQUENCY METER PA PB TWALM AD[8..0] ADVREFP A[2..0] TIMER/COUNTER 0 TIMER/COUNTER 1 B[2..0] CLK[2..0] ASYNCHRONOUS TIMER WATCHDOG TIMER TWD GENERAL PURPOSE I/Os SCK GCLK[4..0] AC INTERFACE ACBP[3..0] ACBN[3..0] ACAP[3..0] ACAN[3..0] ACREFN GLUE LOGIC CONTROLLER OUT[1:0] IN[7..0] 5 32099B-05/2010 AT32UC3L 2.2 Configuration Summary Table 2-1. Configuration Summary Feature AT32UC3L064 AT32UC3L032 AT32UC3L016 Flash 64KB 32KB 16KB SRAM 16KB 16KB 8KB GPIO 36 High-drive pins 5 External Interrupts 6 TWI 2 USART 4 Peripheral DMA Channels 12 Peripheral Event System 1 SPI 1 Asynchronous Timers 1 Timer/Counter Channels 6 PWM channels 36 Frequency Meter 1 Watchdog Timer 1 Power Manager 1 Secure Access Unit 1 Glue Logic Controller 1 Oscillators ADC Digital Frequency Locked Loop 40-150 MHz (DFLL) Crystal Oscillator 3-16 MHz (OSC0) Crystal Oscillator 32 KHz (OSC32K) RC Oscillator 120MHz (RC120M) RC Oscillator 115 kHz (RCSYS) RC Oscillator 32 kHz (RC32K) 8-channel 12-bit Temperature Sensor 1 Analog Comparators 8 Capacitive Touch Module 1 JTAG 1 aWire 1 Max Frequency Package 50 MHz TQFP48/QFN48/TLLGA48 6 32099B-05/2010 AT32UC3L 3. Package and Pinout 3.1 Package The device pins are multiplexed with peripheral functions as described in Section 3.2. TQFP48/QFN48 Pinout 36 35 34 33 32 31 30 29 28 27 26 25 PA14 VDDANA ADVREFP GNDANA PB08 PB07 PB06 PB09 PA04 PA11 PA13 PA20 Figure 3-1. PA15 PA16 PA17 PA19 PA18 VDDIO GND PB11 GND PA10 PA12 VDDIO 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 PA21 PB10 RESET_N PB04 PB05 GND VDDCORE VDDIN PB01 PA07 PA01 PA02 12 11 10 9 8 7 6 5 4 3 2 1 PA05 PA00 PA06 PA22 PB03 PB02 PB00 PB12 PA03 PA08 PA09 GND 7 32099B-05/2010 AT32UC3L TLLGA48 Pinout 37 36 35 34 33 32 31 30 29 28 27 26 25 PA15 PA14 VDDANA ADVREFP GNDANA PB08 PB07 PB06 PB09 PA04 PA11 PA13 PA20 Figure 3-2. PA16 PA17 PA19 PA18 VDDIO GND PB11 GND PA10 PA12 VDDIO 24 23 22 21 20 19 18 17 16 15 14 38 39 40 41 42 43 44 45 46 47 48 PA21 PB10 RESET_N PB04 PB05 GND VDDCORE VDDIN PB01 PA07 PA01 13 12 11 10 9 8 7 6 5 4 3 2 1 PA02 PA05 PA00 PA06 PA22 PB03 PB02 PB00 PB12 PA03 PA08 PA09 GND 3.2 Peripheral Multiplexing on I/O lines 3.2.1 Multiplexed signals Each GPIO line can be assigned to one of the peripheral functions.The following table describes the peripheral signals multiplexed to the GPIO lines. Table 3-1. Q F P 48 GPIO Controller Function Multiplexing GPIO Function PIN G PI O Supply 11 PA00 0 14 PA01 1 Pad Type A B C VDDIO Normal I/O USART0TXD USART1RTS SPINPCS[2] VDDIO Normal I/O USART0RXD USART1CTS SPINPCS[3] D E F PWMAPWMA[0] USART1CLK PWMAPWMA[1] ACIFBACAP[0] G H SCIFGCLK[0] CAT-CSA[2] TWIMS0TWALM CAT-CSA[1] 8 32099B-05/2010 AT32UC3L Table 3-1. GPIO Controller Function Multiplexing 13 PA02 2 VDDIO Highdrive I/O USART0RTS ADCIFBTRIGGER USART2TXD TC0-A0 PWMAPWMA[2] ACIFBACBP[0] USART0CLK CAT-CSA[3] 4 PA03 3 VDDIO Normal I/O USART0CTS SPINPCS[1] USART2TXD TC0-B0 PWMAPWMA[3] ACIFBACBN[3] USART0CLK CAT-CSB[3] 28 PA04 4 VDDIO Normal I/O SPI-MISO TWIMS0TWCK USART1RXD TC0-B1 PWMAPWMA[4] ACIFBACBP[1] 12 PA05 5 VDDIO TWI, Normal I/O SPI-MOSI TWIMS1TWCK USART1TXD TC0-A1 PWMAPWMA[5] ACIFBACBN[0] SPI-SCK USART2TXD USART1CLK TC0-B0 PWMAPWMA[6] CAT-CSA[7] TWIMS0TWD CAT-CSB[7] SCIFGCLK[1] CAT-CSB[1] NMI CAT-CSB[2] 10 PA06 6 VDDIO Highdrive I/O, 5V tolerant 15 PA07 7 VDDIO TWI, Normal I/O SPINPCS[0] USART2RXD TWIMS1TWALM TWIMS0TWCK PWMAPWMA[7] 3 PA08 8 VDDIO Highdrive I/O USART1TXD SPINPCS[2] TC0-A2 ADCIFBADP[0] PWMAPWMA[8] 2 PA09 9 VDDIO Highdrive I/O USART1RXD SPINPCS[3] TC0-B2 ADCIFBADP[1] PWMAPWMA[9] SCIF-GCLK[2] EICEXTINT[1] CAT-CSB[4] 46 PA10 10 VDDIO Normal I/O TWIMS0TWD PWMAPWMA[10] ACIFBACAP[1] SCIFGCLK[2] CAT-CSA[5] 27 PA11 11 VDDIN Normal I/O 47 PA12 12 VDDIO Normal I/O ADCIFBPRND USART2CLK TC0-CLK1 CAT-SMP PWMAPWMA[12] ACIFBACAN[1] SCIFGCLK[3] CAT-CSB[5] 26 PA13 13 VDDIN Normal I/O GLOCOUT[0] GLOC-IN[7] TC0-A0 SCIFGCLK[2] PWMAPWMA[13] CAT-SMP EICEXTINT[2] CAT-CSA[0] 36 PA14 14 VDDIO Normal I/O ADCIFBAD[0] TC0-CLK2 USART2RTS CAT-SMP PWMAPWMA[14] SCIFGCLK[4] CAT-CSA[6] 37 PA15 15 VDDIO Normal I/O ADCIFBAD[1] TC0-CLK1 GLOC-IN[6] PWMAPWMA[15] CAT-SYNC EICEXTINT[3] CAT-CSB[6] 38 PA16 16 VDDIO Normal I/O ADCIFBAD[2] TC0-CLK0 GLOC-IN[5] PWMAPWMA[16] ACIFBACREFN EICEXTINT[4] CAT-CSA[8] 39 PA17 17 VDDIO TWI, Normal I/O TWIMS1TWD PWMAPWMA[17] CAT-SMP CAT-DIS CAT-CSB[8] 41 PA18 18 VDDIO Normal I/O ADCIFBAD[4] GLOC-IN[4] PWMAPWMA[18] CAT-SYNC EICEXTINT[5] CAT-CSB[0] 40 PA19 19 VDDIO Normal I/O ADCIFBAD[5] TC0-A2 TWIMS1TWALM PWMAPWMA[19] CAT-SYNC CATCSA[10] 25 PA20 20 VDDIN Normal I/O USART2TXD TC0-A1 GLOC-IN[3] PWMAPWMA[20] SCIFRC32OUT USART2RXD TWIMS0TWD TC0-B1 ADCIFBTRIGGER PWMAPWMA[21] PWMAPWMAOD[21] TC0-A0 ACIFBACAN[0] CAT-CSA[4] PWMAPWMA[11] TC0-A1 USART2CTS TC0-B1 24 PA21 21 VDDIN TWI, 5V tolerant, SMBus, Normal I/O 9 PA22 22 VDDIO Normal I/O USART0CTS USART2CLK TC0-B2 CAT-SMP PWMAPWMA[22] ACIFBACBN[2] 6 PB00 32 VDDIO Normal I/O USART3TXD ADCIFBADP[0] SPINPCS[0] TC0-A1 PWMAPWMA[23] ACIFBACAP[2] 16 PB01 33 VDDIO Highdrive I/O USART3RXD ADCIFBADP[1] SPI-SCK TC0-B1 PWMAPWMA[24] CATCSA[12] SCIFGCLK[0] CAT-SMP CATCSB[10] TC1-A0 CAT-CSA[9] TC1-A1 CAT-CSB[9] 9 32099B-05/2010 AT32UC3L Table 3-1. GPIO Controller Function Multiplexing 7 PB02 34 VDDIO Normal I/O USART3RTS USART3CLK SPI-MISO TC0-A2 PWMAPWMA[25] ACIFBACAN[2] SCIFGCLK[1] CATCSB[11] 8 PB03 35 VDDIO Normal I/O USART3CTS USART3CLK SPI-MOSI TC0-B2 PWMAPWMA[26] ACIFBACBP[2] TC1-A2 CATCSA[11] VDDIN TWI, 5V tolerant, SMBus, Normal I/O TC1-A0 USART1RTS USART1CLK TWIMS0TWALM PWMAPWMA[27] PWMAPWMAOD[27] TWIMS1TWCK CATCSA[14] TC1-B0 USART1CTS USART1CLK TWIMS0TWCK PWMAPWMA[28] PWMAPWMAOD[28] SCIFGCLK[3] CATCSB[14] 21 PB04 36 20 PB05 37 VDDIN TWI, 5V tolerant, SMBus, Normal I/O 30 PB06 38 VDDIO Normal I/O TC1-A1 USART3TXD ADCIFBAD[6] GLOC-IN[2] PWMAPWMA[29] ACIFBACAN[3] NMI CATCSB[13] 31 PB07 39 VDDIO Normal I/O TC1-B1 USART3RXD ADCIFBAD[7] GLOC-IN[1] PWMAPWMA[30] ACIFBACAP[3] EICEXTINT[1] CATCSA[13] 32 PB08 40 VDDIO Normal I/O TC1-A2 USART3RTS ADCIFBAD[8] GLOC-IN[0] PWMAPWMA[31] CAT-SYNC EICEXTINT[2] CATCSB[12] 29 PB09 41 VDDIO Normal I/O TC1-B2 USART3CTS USART3CLK PWMAPWMA[32] ACIFBACBN[1] EICEXTINT[3] CATCSB[15] 23 PB10 42 VDDIN Normal I/O TC1-CLK0 USART1TXD USART3CLK EICEXTINT[4] CATCSB[16] 44 PB11 43 VDDIO Normal I/O TC1-CLK1 USART1RXD 5 PB12 44 VDDIO Normal I/O TC1-CLK2 TWIMS1TWALM GLOCOUT[1] PWMAPWMA[33] ADCIFBTRIGGER PWMAPWMA[34] CAT-VDIVEN EICEXTINT[5] CATCSA[16] CAT-SYNC PWMAPWMA[35] ACIFBACBP[3] SCIFGCLK[4] CATCSA[15] See Section 3.3 for a description of the various peripheral signals. Signals are prioritized according to the function priority listed in Table 3-2 on page 10 if multiple functions are enabled simultaneously. Refer to "Electrical Characteristics" on page 34 for a description of the electrical properties of the pad types used. 3.2.2 Peripheral Functions Each GPIO line can be assigned to one of several peripheral functions. The following table describes how the various peripheral functions are selected. The last listed function has priority in case multiple functions are enabled. Table 3-2. Peripheral Functions Function Description A GPIO peripheral selection A B GPIO peripheral selection B C GPIO peripheral selection C D GPIO peripheral selection D E GPIO peripheral selection E 10 32099B-05/2010 AT32UC3L Table 3-2. 3.2.3 Function Description F GPIO peripheral selection F G GPIO peripheral selection G H GPIO peripheral selection H JTAG Port Connections If the JTAG is enabled, the JTAG will take control over a number of pins, irrespectively of the I/O Controller configuration. Table 3-3. 3.2.4 Peripheral Functions JTAG Pinout 48TQFP/QFN/TLLGA Pin JTAG Function 11 PA00 TCK 14 PA01 TMS 13 PA02 TDO 4 PA03 TDI Nexus OCD AUX Port Connections If the OCD trace system is enabled, the trace system will take control over a number of pins, irrespectively of the I/O Controller configuration. Two different OCD trace pin mappings are possible, depending on the configuration of the OCD AXS register. For details, see the AVR32 UC Technical Reference Manual. Table 3-4. Nexus OCD AUX Port Connections Pin AXS=1 AXS=0 EVTI_N PA05 PB08 MDO[5] PA10 PB00 MDO[4] PA18 PB04 MDO[3] PA17 PB05 MDO[2] PA16 PB03 MDO[1] PA15 PB02 MDO[0] PA14 PB09 EVTO_N PA04 PA04 MCKO PA06 PB01 MSEO[1] PA07 PB11 MSEO[0] PA11 PB12 11 32099B-05/2010 AT32UC3L 3.2.5 Oscillator Pinout The oscillators are not mapped to the normal GPIO functions and their muxings are controlled by registers in the System Control Interface (SCIF). Please refer to the SCIF chapter for more information about this. Table 3-5. 3.2.6 Oscillator Pinout 48TQFP/QFN/TLLGA Pin Oscillator Function 3 PA08 XIN0 46 PA10 XIN32 26 PA13 XIN32_2 2 PA09 XOUT0 47 PA12 XOUT32 25 PA20 XOUT32_2 Other Functions The functions listed in Table 3-6 are not mapped to the normal GPIO functions.The aWire DATA pin will only be active after the aWire is enabled. The aWire DATAOUT pin will only be actice after the aWire is enabled and the 2_PIN_MODE command has been sent. The WAKE_N pin is always enabled. Please refer to Section 6.1.4 on page 40 for constraints on the WAKE_N pin. Table 3-6. Other Functions 48TQFP/TQFN/TLLGA Pin Function 27 PA11 WAKE_N 22 RESET_N aWire DATA 11 PA00 aWire DATAOUT 12 32099B-05/2010 AT32UC3L 3.3 Signal Descriptions The following table gives details on signal name classified by peripheral. Table 3-7. Signal Descriptions List Signal Name Function Type Active Level Comments Analog Comparator Interface - ACIFB ACAN3 - ACAN0 Negative inputs for comparators "A" Analog ACAP3 - ACAP0 Positive inputs for comparators "A" Analog ACBN3 - ACBN0 Negative inputs for comparators "B" Analog ACBP3 - ACBP0 Positive inputs for comparators "B" Analog ACREFN Common negative reference Analog ADC Interface - ADCIFB AD8 - AD0 Analog Signal Analog ADP1 - ADP0 Drive Pin for resistive touch screen Output PRND Pseudorandom output signal Output TRIGGER External trigger Input aWire - AW DATA aWire data I/O DATAOUT aWire data output for 2-pin mode I/O Capacitive Touch Module - CAT CSA16 - CSA0 Capacitive Sense A I/O CSB16 - CSB0 Capacitive Sense B I/O SMP SMP signal SYNC Synchronize signal VDIVEN Voltage divider enable Output Input Output External Interrupt Controller - EIC NMI Non-Maskable Interrupt Input EXTINT5 - EXTINT1 External interrupt Input Glue Logic Controller - GLOC IN7 - IN0 Inputs to lookup tables OUT1 - OUT0 Outputs from lookup tables Input Output JTAG module - JTAG TCK Test Clock Input TDI Test Data In Input TDO Test Data Out TMS Test Mode Select Output Input 13 32099B-05/2010 AT32UC3L Table 3-7. Signal Descriptions List Power Manager - PM RESET_N Reset Input Low Pulse Width Modulation Controller - PWMA PWMA35 - PWMA0 PWMA channel waveforms Output PWMAOD35 PWMAOD0 PWMA channel waveforms, open drain mode Output Not all channels support open drain mode System Control Interface - SCIF GCLK4 - GCLK0 Generic Clock Output Output RC32OUT RC32K output at startup Output XIN0 Crystal 0 Input Analog/ Digital XIN32 Crystal 32 Input (primary location) Analog/ Digital XIN32_2 Crystal 32 Input (secondary location) Analog/ Digital XOUT0 Crystal 0 Output Analog XOUT32 Crystal 32 Output (primary location) Analog XOUT32_2 Crystal 32 Output (secondary location) Analog Serial Peripheral Interface - SPI MISO Master In Slave Out I/O MOSI Master Out Slave In I/O NPCS3 - NPCS0 SPI Peripheral Chip Select I/O SCK Clock I/O Low Timer/Counter - TC0, TC1 A0 Channel 0 Line A I/O A1 Channel 1 Line A I/O A2 Channel 2 Line A I/O B0 Channel 0 Line B I/O B1 Channel 1 Line B I/O B2 Channel 2 Line B I/O CLK0 Channel 0 External Clock Input Input CLK1 Channel 1 External Clock Input Input CLK2 Channel 2 External Clock Input Input Two-wire Interface - TWIMS0, TWIMS1 TWALM SMBus SMBALERT I/O TWCK Two-wire Serial Clock I/O TWD Two-wire Serial Data I/O Low Universal Synchronous/Asynchronous Receiver/Transmitter - USART0, USART1, USART2, USART3 14 32099B-05/2010 AT32UC3L Table 3-7. Signal Descriptions List CLK Clock CTS Clear To Send RTS Request To Send RXD Receive Data Input TXD Transmit Data Output Note: I/O Input Low Output Low 1. ADCIFB: AD3 does not exist. Table 3-8. Signal Description List, continued Signal Name Function Type Active Level Comments Power VDDCORE Core Power Supply / Voltage Regulator Output Power Input/Output 1.62V to 1.98V VDDIO I/O Power Supply Power Input 1.62V to 3.6V. VDDIO should always be equal to or lower than VDDIN. VDDANA Analog Power Supply Power Input 1.62V to 1.98V ADVREFP Analog Reference Voltage Power Input TBD to 1.98V VDDIN Voltage Regulator Input Power Input 1.62V to 3.6V (1) GNDANA Analog Ground Ground GND Ground Ground Auxiliary Port - AUX MCKO Trace Data Output Clock Output MDO5 - MDO0 Trace Data Output Output MSEO1 - MSEO0 Trace Frame Control Output EVTI_N Event In EVTO_N Event Out Input Low Output Low General Purpose I/O pin PA22 - PA00 Parallel I/O Controller I/O Port 0 I/O PB12 - PB00 Parallel I/O Controller I/O Port 1 I/O 1. See Section 6.1 on page 36 15 32099B-05/2010 AT32UC3L 3.4 3.4.1 I/O Line Considerations JTAG Pins The JTAG is enabled if TCK is low while the RESET_N pin is released. The TCK, TMS, and TDI pins have pull-up resistors when JTAG is enabled. The TCK pin always have pull-up enabled during reset. The TDO pin is an output, driven at VDDIO, and has no pull-up resistor. The JTAG pins can be used as GPIO pins and multiplexed with peripherals when the JTAG is disabled. Please refer to Section 3.2.3 on page 11 for the JTAG port connections. 3.4.2 PA00 Note that PA00 is multiplexed with TCK. PA00 GPIO function must only be used as output in the application. 3.4.3 RESET_N Pin The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIO. As the product integrates a power-on reset detector, the RESET_N pin can be left unconnected in case no reset from the system needs to be applied to the product. The RESET_N pin is also used for the aWire debug protocol. When the pin is used for debugging, it must not be driven by external circuitry. 3.4.4 TWI0 Pins When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and inputs with spike filtering. When used as GPIO pins or used for other peripherals, the pins have the characteristics indicated in the Electrical Characteristics section. Selected pins are also SMBus compliant (refer to Section 3.2 on page 8). As required by the SMBus specification, these pins provide no leakage path to ground when the AT32UC3L is powered down. This allows other devices on the SMBus to continue communicating even though the AT32UC3L is not powered. This feature is only available when pins PA21/PB04/PB05 are used for TWI0. 3.4.5 TWI1 Pins When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and inputs with spike filtering. When used as GPIO pins or used for other peripherals, the pins have the same characteristics as other GPIO pins. 3.4.6 GPIO Pins All the I/O lines integrate a pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the GPIO Controllers. After reset, I/O lines default as inputs with pull-up resistors disabled, except PA00. PA20 selects SCIF-RC32OUT (GPIO Function F) as default enabled after reset. 3.4.7 High-Drive Pins The five pins PA02, PA06, PA08, PA09, and PB01 have high-drive output capabilities. Refer to Section 1. on page 34 for electrical characteristics. 3.4.8 RC32OUT Pin 3.4.8.1 Clock output at startup After power-up, the clock generated by the 32kHz RC oscillator (RC32K) will be output on PA20, even when the device is still reset by the Power-On Reset Circuitry. This clock can be used by 16 32099B-05/2010 AT32UC3L the system to start other devices or to clock a switching regulator to rise the power supply voltage up to an acceptable value. The clock will be available on PA20 until one of the following conditions are true: *PA20 is configured to use a GPIO function other than F (SCIF-RC32OUT) *PA20 is configured as a General Purpose Input/Output (GPIO) *The bit FRC32 in the Power Manager PPCR register is written to zero (refer to the Power Manager chapter) The maximum amplitude of the clock signal will be defined by VDDIN. 3.4.8.2 3.4.9 XOUT32_2 function PA20 selects RC32OUT as default enabled after reset. This function is not automatically disabled when the user enables the XOUT32_2 function on PA20. This disturbes the oscillator and may result in the wrong frequency. To avoid this, RC32OUT must be disabled when XOUT32_2 is enabled. ADC Input Pins These pins are regular I/O pins powered from the VDDIO. However, when these pins are used for ADC inputs, the voltage applied to the pin must not exceed 1.98V. Internal circuitry ensures that the pin cannot be used as an analog input pin when the I/O drives to VDD. When the pins are not used for ADC inputs, the pins may be driven to the full I/O voltage range. 17 32099B-05/2010 AT32UC3L 4. Processor and Architecture Rev: 2.1.0.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, and MPU is presented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical Reference Manual. 4.1 Features * 32-bit load/store AVR32A RISC architecture - - - - - 15 general-purpose 32-bit registers 32-bit Stack Pointer, Program Counter and Link Register reside in register file Fully orthogonal instruction set Privileged and unprivileged modes enabling efficient and secure operating systems Innovative instruction set together with variable instruction length ensuring industry leading code density - DSP extension with saturating arithmetic, and a wide variety of multiply instructions * 3-stage pipeline allowing one instruction per clock cycle for most instructions - Byte, halfword, word, and double word memory access - Multiple interrupt priority levels * MPU allows for operating systems with memory protection * Secure State for supporting FlashVaultTM technology 4.2 AVR32 Architecture AVR32 is a new, high-performance 32-bit RISC microprocessor architecture, designed for costsensitive embedded applications, with particular emphasis on low power consumption and high code density. In addition, the instruction set architecture has been tuned to allow a variety of microarchitectures, enabling the AVR32 to be implemented as low-, mid-, or high-performance processors. AVR32 extends the AVR family into the world of 32- and 64-bit applications. Through a quantitative approach, a large set of industry recognized benchmarks has been compiled and analyzed to achieve the best code density in its class. In addition to lowering the memory requirements, a compact code size also contributes to the core's low power characteristics. The processor supports byte and halfword data types without penalty in code size and performance. Memory load and store operations are provided for byte, halfword, word, and double word data with automatic sign- or zero extension of halfword and byte data. The C-compiler is closely linked to the architecture and is able to exploit code optimization features, both for size and speed. In order to reduce code size to a minimum, some instructions have multiple addressing modes. As an example, instructions with immediates often have a compact format with a smaller immediate, and an extended format with a larger immediate. In this way, the compiler is able to use the format giving the smallest code size. Another feature of the instruction set is that frequently used instructions, like add, have a compact format with two operands as well as an extended format with three operands. The larger format increases performance, allowing an addition and a data move in the same instruction in a single cycle. Load and store instructions have several different formats in order to reduce code size and speed up execution. 18 32099B-05/2010 AT32UC3L The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values from function calls and is used implicitly by some instructions. 4.3 The AVR32UC CPU The AVR32UC CPU targets low- and medium-performance applications, and provides an advanced On-Chip Debug (OCD) system, no caches, and a Memory Protection Unit (MPU). Java acceleration hardware is not implemented. AVR32UC provides three memory interfaces, one High Speed Bus master for instruction fetch, one High Speed Bus master for data access, and one High Speed Bus slave interface allowing other bus masters to access data RAMs internal to the CPU. Keeping data RAMs internal to the CPU allows fast access to the RAMs, reduces latency, and guarantees deterministic timing. Also, power consumption is reduced by not needing a full High Speed Bus access for memory accesses. A dedicated data RAM interface is provided for communicating with the internal data RAMs. A local bus interface is provided for connecting the CPU to device-specific high-speed systems, such as floating-point units and I/O controller ports. This local bus has to be enabled by writing a one to the LOCEN bit in the CPUCR system register. The local bus is able to transfer data between the CPU and the local bus slave in a single clock cycle. The local bus has a dedicated memory range allocated to it, and data transfers are performed using regular load and store instructions. Details on which devices that are mapped into the local bus space is given in the CPU Local Bus section in the Memories chapter. Figure 4-1 on page 20 displays the contents of AVR32UC. 19 32099B-05/2010 AT32UC3L OCD interface Reset interface Overview of the AVR32UC CPU Interrupt controller interface Figure 4-1. OCD system Power/ Reset control AVR32UC CPU pipeline MPU 4.3.1 High Speed Bus slave CPU Local Bus master CPU Local Bus High Speed Bus High Speed Bus High Speed Bus master High Speed Bus master High Speed Bus Data memory controller Instruction memory controller CPU RAM Pipeline Overview AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruction Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic (ALU) section, one multiply (MUL) section, and one load/store (LS) section. Instructions are issued and complete in order. Certain operations require several clock cycles to complete, and in this case, the instruction resides in the ID and EX stages for the required number of clock cycles. Since there is only three pipeline stages, no internal data forwarding is required, and no data dependencies can arise in the pipeline. Figure 4-2 on page 21 shows an overview of the AVR32UC pipeline stages. 20 32099B-05/2010 AT32UC3L Figure 4-2. The AVR32UC Pipeline MUL IF ID Prefetch unit Decode unit Regfile Read ALU LS 4.3.2 Multiply unit Regfile write ALU unit Load-store unit AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is targeted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt contexts. Additionally, it does not provide hardware registers for the return address registers and return status registers. Instead, all this information is stored on the system stack. This saves chip area at the expense of slower interrupt handling. 4.3.2.1 Interrupt Handling Upon interrupt initiation, registers R8-R12 are automatically pushed to the system stack. These registers are pushed regardless of the priority level of the pending interrupt. The return address and status register are also automatically pushed to stack. The interrupt handler can therefore use R8-R12 freely. Upon interrupt completion, the old R8-R12 registers and status register are restored, and execution continues at the return address stored popped from stack. The stack is also used to store the status register and return address for exceptions and scall. Executing the rete or rets instruction at the completion of an exception or system call will pop this status register and continue execution at the popped return address. 4.3.2.2 Java Support AVR32UC does not provide Java hardware acceleration. 4.3.2.3 Memory Protection The MPU allows the user to check all memory accesses for privilege violations. If an access is attempted to an illegal memory address, the access is aborted and an exception is taken. The MPU in AVR32UC is specified in the AVR32UC Technical Reference manual. 4.3.2.4 Unaligned Reference Handling AVR32UC does not support unaligned accesses, except for doubleword accesses. AVR32UC is able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an 21 32099B-05/2010 AT32UC3L address exception. Doubleword-sized accesses with word-aligned pointers will automatically be performed as two word-sized accesses. The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Table 4-1. 4.3.2.5 Instructions with Unaligned Reference Support Instruction Supported Alignment ld.d Word st.d Word Unimplemented Instructions The following instructions are unimplemented in AVR32UC, and will cause an Unimplemented Instruction Exception if executed: * All SIMD instructions * All coprocessor instructions if no coprocessors are present * retj, incjosp, popjc, pushjc * tlbr, tlbs, tlbw * cache 4.3.2.6 CPU and Architecture Revision Three major revisions of the AVR32UC CPU currently exist. The device described in this datasheet uses CPU revision 3. The Architecture Revision field in the CONFIG0 system register identifies which architecture revision is implemented in a specific device. AVR32UC CPU revision 3 is fully backward-compatible with revisions 1 and 2, ie. code compiled for revision 1 or 2 is binary-compatible with revision 3 CPUs. 22 32099B-05/2010 AT32UC3L 4.4 4.4.1 Programming Model Register File Configuration The AVR32UC register file is shown below. Figure 4-3. The AVR32UC Register File Application Supervisor INT0 Bit 31 Bit 31 Bit 31 Bit 0 Bit 0 INT1 Bit 0 INT2 Bit 31 Bit 0 INT3 Bit 31 Bit 0 Bit 31 Bit 0 Exception NMI Bit 31 Bit 31 Bit 0 Secure Bit 0 Bit 31 Bit 0 PC LR SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SEC R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR SR SR SR SR SR SR SR SR SS_STATUS SS_ADRF SS_ADRR SS_ADR0 SS_ADR1 SS_SP_SYS SS_SP_APP SS_RAR SS_RSR 4.4.2 Status Register Configuration The Status Register (SR) is split into two halfwords, one upper and one lower, see Figure 4-4 and Figure 4-5. The lower word contains the C, Z, N, V, and Q condition code flags and the R, T, and L bits, while the upper halfword contains information about the mode and state the processor executes in. Refer to the AVR32 Architecture Manual for details. Figure 4-4. The Status Register High Halfword Bit 31 Bit 16 SS LC 1 - - DM D - M2 M1 M0 EM I3M I2M FE I1M I0M GM 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 Bit nam e Initial value G lobal Interrupt M ask Interrupt Level 0 M ask Interrupt Level 1 M ask Interrupt Level 2 M ask Interrupt Level 3 M ask Exception M ask M ode Bit 0 M ode Bit 1 M ode Bit 2 Reserved Debug State Debug State M ask Reserved Secure State 23 32099B-05/2010 AT32UC3L Figure 4-5. The Status Register Low Halfword Bit 15 Bit 0 - T - - - - - - - - L Q V N Z C Bit name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value Carry Zero Sign Overflow Saturation Lock Reserved Scratch Reserved 4.4.3 Processor States 4.4.3.1 Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 4-2. Table 4-2. Overview of Execution Modes, their Priorities and Privilege Levels. Priority Mode Security Description 1 Non Maskable Interrupt Privileged Non Maskable high priority interrupt mode 2 Exception Privileged Execute exceptions 3 Interrupt 3 Privileged General purpose interrupt mode 4 Interrupt 2 Privileged General purpose interrupt mode 5 Interrupt 1 Privileged General purpose interrupt mode 6 Interrupt 0 Privileged General purpose interrupt mode N/A Supervisor Privileged Runs supervisor calls N/A Application Unprivileged Normal program execution mode Mode changes can be made under software control, or can be caused by external interrupts or exception processing. A mode can be interrupted by a higher priority mode, but never by one with lower priority. Nested exceptions can be supported with a minimal software overhead. When running an operating system on the AVR32, user processes will typically execute in the application mode. The programs executed in this mode are restricted from executing certain instructions. Furthermore, most system registers together with the upper halfword of the status register cannot be accessed. Protected memory areas are also not available. All other operating modes are privileged and are collectively called System Modes. They have full access to all privileged and unprivileged resources. After a reset, the processor will be in supervisor mode. 4.4.3.2 Debug State The AVR32 can be set in a debug state, which allows implementation of software monitor routines that can read out and alter system information for use during application development. This implies that all system and application registers, including the status registers and program counters, are accessible in debug state. The privileged instructions are also available. All interrupt levels are by default disabled when debug state is entered, but they can individually be switched on by the monitor routine by clearing the respective mask bit in the status register. 24 32099B-05/2010 AT32UC3L Debug state can be entered as described in the AVR32UC Technical Reference Manual. Debug state is exited by the retd instruction. 4.4.3.3 4.4.4 Secure State The AVR32 can be set in a secure state, that allows a part of the code to execute in a state with higher security levels. The rest of the code can not access resources reserved for this secure code. Secure State is used to implement FlashVault technology. Refer to the AVR32UC Technical Reference Manual for details. System Registers The system registers are placed outside of the virtual memory space, and are only accessible using the privileged mfsr and mtsr instructions. The table below lists the system registers specified in the AVR32 architecture, some of which are unused in AVR32UC. The programmer is responsible for maintaining correct sequencing of any instructions following a mtsr instruction. For detail on the system registers, refer to the AVR32UC Technical Reference Manual. Table 4-3. System Registers Reg # Address Name Function 0 0 SR Status Register 1 4 EVBA Exception Vector Base Address 2 8 ACBA Application Call Base Address 3 12 CPUCR CPU Control Register 4 16 ECR Exception Cause Register 5 20 RSR_SUP Unused in AVR32UC 6 24 RSR_INT0 Unused in AVR32UC 7 28 RSR_INT1 Unused in AVR32UC 8 32 RSR_INT2 Unused in AVR32UC 9 36 RSR_INT3 Unused in AVR32UC 10 40 RSR_EX Unused in AVR32UC 11 44 RSR_NMI Unused in AVR32UC 12 48 RSR_DBG Return Status Register for Debug mode 13 52 RAR_SUP Unused in AVR32UC 14 56 RAR_INT0 Unused in AVR32UC 15 60 RAR_INT1 Unused in AVR32UC 16 64 RAR_INT2 Unused in AVR32UC 17 68 RAR_INT3 Unused in AVR32UC 18 72 RAR_EX Unused in AVR32UC 19 76 RAR_NMI Unused in AVR32UC 20 80 RAR_DBG Return Address Register for Debug mode 21 84 JECR Unused in AVR32UC 22 88 JOSP Unused in AVR32UC 23 92 JAVA_LV0 Unused in AVR32UC 25 32099B-05/2010 AT32UC3L Table 4-3. System Registers (Continued) Reg # Address Name Function 24 96 JAVA_LV1 Unused in AVR32UC 25 100 JAVA_LV2 Unused in AVR32UC 26 104 JAVA_LV3 Unused in AVR32UC 27 108 JAVA_LV4 Unused in AVR32UC 28 112 JAVA_LV5 Unused in AVR32UC 29 116 JAVA_LV6 Unused in AVR32UC 30 120 JAVA_LV7 Unused in AVR32UC 31 124 JTBA Unused in AVR32UC 32 128 JBCR Unused in AVR32UC 33-63 132-252 Reserved Reserved for future use 64 256 CONFIG0 Configuration register 0 65 260 CONFIG1 Configuration register 1 66 264 COUNT Cycle Counter register 67 268 COMPARE Compare register 68 272 TLBEHI Unused in AVR32UC 69 276 TLBELO Unused in AVR32UC 70 280 PTBR Unused in AVR32UC 71 284 TLBEAR Unused in AVR32UC 72 288 MMUCR Unused in AVR32UC 73 292 TLBARLO Unused in AVR32UC 74 296 TLBARHI Unused in AVR32UC 75 300 PCCNT Unused in AVR32UC 76 304 PCNT0 Unused in AVR32UC 77 308 PCNT1 Unused in AVR32UC 78 312 PCCR Unused in AVR32UC 79 316 BEAR Bus Error Address Register 80 320 MPUAR0 MPU Address Register region 0 81 324 MPUAR1 MPU Address Register region 1 82 328 MPUAR2 MPU Address Register region 2 83 332 MPUAR3 MPU Address Register region 3 84 336 MPUAR4 MPU Address Register region 4 85 340 MPUAR5 MPU Address Register region 5 86 344 MPUAR6 MPU Address Register region 6 87 348 MPUAR7 MPU Address Register region 7 88 352 MPUPSR0 MPU Privilege Select Register region 0 89 356 MPUPSR1 MPU Privilege Select Register region 1 26 32099B-05/2010 AT32UC3L Table 4-3. 4.5 System Registers (Continued) Reg # Address Name Function 90 360 MPUPSR2 MPU Privilege Select Register region 2 91 364 MPUPSR3 MPU Privilege Select Register region 3 92 368 MPUPSR4 MPU Privilege Select Register region 4 93 372 MPUPSR5 MPU Privilege Select Register region 5 94 376 MPUPSR6 MPU Privilege Select Register region 6 95 380 MPUPSR7 MPU Privilege Select Register region 7 96 384 MPUCRA Unused in this version of AVR32UC 97 388 MPUCRB Unused in this version of AVR32UC 98 392 MPUBRA Unused in this version of AVR32UC 99 396 MPUBRB Unused in this version of AVR32UC 100 400 MPUAPRA MPU Access Permission Register A 101 404 MPUAPRB MPU Access Permission Register B 102 408 MPUCR MPU Control Register 103 412 SS_STATUS Secure State Status Register 104 416 SS_ADRF Secure State Address Flash Register 105 420 SS_ADRR Secure State Address RAM Register 106 424 SS_ADR0 Secure State Address 0 Register 107 428 SS_ADR1 Secure State Address 1 Register 108 432 SS_SP_SYS Secure State Stack Pointer System Register 109 436 SS_SP_APP Secure State Stack Pointer Application Register 110 440 SS_RAR Secure State Return Address Register 111 444 SS_RSR Secure State Return Status Register 112-191 448-764 Reserved Reserved for future use 192-255 768-1020 IMPL IMPLEMENTATION DEFINED Exceptions and Interrupts In the AVR32 architecture, events are used as a common term for exceptions and interrupts. AVR32UC incorporates a powerful event handling scheme. The different event sources, like Illegal Op-code and interrupt requests, have different priority levels, ensuring a well-defined behavior when multiple events are received simultaneously. Additionally, pending events of a higher priority class may preempt handling of ongoing events of a lower priority class. When an event occurs, the execution of the instruction stream is halted, and execution is passed to an event handler at an address specified in Table 4-4 on page 31. Most of the handlers are placed sequentially in the code space starting at the address specified by EVBA, with four bytes between each handler. This gives ample space for a jump instruction to be placed there, jumping to the event routine itself. A few critical handlers have larger spacing between them, allowing the entire event routine to be placed directly at the address specified by the EVBA-relative offset generated by hardware. All interrupt sources have autovectored interrupt service routine (ISR) addresses. This allows the interrupt controller to directly specify the ISR address as an address 27 32099B-05/2010 AT32UC3L relative to EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception code segments must be set up appropriately. The same mechanisms are used to service all different types of events, including interrupt requests, yielding a uniform event handling scheme. An interrupt controller does the priority handling of the interrupts and provides the autovector offset to the CPU. 4.5.1 System Stack Issues Event handling in AVR32UC uses the system stack pointed to by the system stack pointer, SP_SYS, for pushing and popping R8-R12, LR, status register, and return address. Since event code may be timing-critical, SP_SYS should point to memory addresses in the IRAM section, since the timing of accesses to this memory section is both fast and deterministic. The user must also make sure that the system stack is large enough so that any event is able to push the required registers to stack. If the system stack is full, and an event occurs, the system will enter an UNDEFINED state. 4.5.2 Exceptions and Interrupt Requests When an event other than scall or debug request is received by the core, the following actions are performed atomically: 1. The pending event will not be accepted if it is masked. The I3M, I2M, I1M, I0M, EM, and GM bits in the Status Register are used to mask different events. Not all events can be masked. A few critical events (NMI, Unrecoverable Exception, TLB Multiple Hit, and Bus Error) can not be masked. When an event is accepted, hardware automatically sets the mask bits corresponding to all sources with equal or lower priority. This inhibits acceptance of other events of the same or lower priority, except for the critical events listed above. Software may choose to clear some or all of these bits after saving the necessary state if other priority schemes are desired. It is the event source's responsability to ensure that their events are left pending until accepted by the CPU. 2. When a request is accepted, the Status Register and Program Counter of the current context is stored to the system stack. If the event is an INT0, INT1, INT2, or INT3, registers R8-R12 and LR are also automatically stored to stack. Storing the Status Register ensures that the core is returned to the previous execution mode when the current event handling is completed. When exceptions occur, both the EM and GM bits are set, and the application may manually enable nested exceptions if desired by clearing the appropriate bit. Each exception handler has a dedicated handler address, and this address uniquely identifies the exception source. 3. The Mode bits are set to reflect the priority of the accepted event, and the correct register file bank is selected. The address of the event handler, as shown in Table 4-4 on page 31, is loaded into the Program Counter. The execution of the event handler routine then continues from the effective address calculated. The rete instruction signals the end of the event. When encountered, the Return Status Register and Return Address Register are popped from the system stack and restored to the Status Register and Program Counter. If the rete instruction returns from INT0, INT1, INT2, or INT3, registers R8-R12 and LR are also popped from the system stack. The restored Status Register contains information allowing the core to resume operation in the previous execution mode. This concludes the event handling. 28 32099B-05/2010 AT32UC3L 4.5.3 Supervisor Calls The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is designed so that privileged routines can be called from any context. This facilitates sharing of code between different execution modes. The scall mechanism is designed so that a minimal execution cycle overhead is experienced when performing supervisor routine calls from timecritical event handlers. The scall instruction behaves differently depending on which mode it is called from. The behaviour is detailed in the instruction set reference. In order to allow the scall routine to return to the correct context, a return from supervisor call instruction, rets, is implemented. In the AVR32UC CPU, scall and rets uses the system stack to store the return address and the status register. 4.5.4 Debug Requests The AVR32 architecture defines a dedicated Debug mode. When a debug request is received by the core, Debug mode is entered. Entry into Debug mode can be masked by the DM bit in the status register. Upon entry into Debug mode, hardware sets the SR.D bit and jumps to the Debug Exception handler. By default, Debug mode executes in the exception context, but with dedicated Return Address Register and Return Status Register. These dedicated registers remove the need for storing this data to the system stack, thereby improving debuggability. The Mode bits in the Status Register can freely be manipulated in Debug mode, to observe registers in all contexts, while retaining full privileges. Debug mode is exited by executing the retd instruction. This returns to the previous context. 4.5.5 Entry Points for Events Several different event handler entry points exist. In AVR32UC, the reset address is 0x80000000. This places the reset address in the boot flash memory area. TLB miss exceptions and scall have a dedicated space relative to EVBA where their event handler can be placed. This speeds up execution by removing the need for a jump instruction placed at the program address jumped to by the event hardware. All other exceptions have a dedicated event routine entry point located relative to EVBA. The handler routine address identifies the exception source directly. AVR32UC uses the ITLB and DTLB protection exceptions to signal a MPU protection violation. ITLB and DTLB miss exceptions are used to signal that an access address did not map to any of the entries in the MPU. TLB multiple hit exception indicates that an access address did map to multiple TLB entries, signalling an error. All interrupt requests have entry points located at an offset relative to EVBA. This autovector offset is specified by an interrupt controller. The programmer must make sure that none of the autovector offsets interfere with the placement of other code. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. Special considerations should be made when loading EVBA with a pointer. Due to security considerations, the event handlers should be located in non-writeable flash memory, or optionally in a privileged memory protection region if an MPU is present. If several events occur on the same instruction, they are handled in a prioritized way. The priority ordering is presented in Table 4-4 on page 31. If events occur on several instructions at different locations in the pipeline, the events on the oldest instruction are always handled before any events on any younger instruction, even if the younger instruction has events of higher priority 29 32099B-05/2010 AT32UC3L than the oldest instruction. An instruction B is younger than an instruction A if it was sent down the pipeline later than A. The addresses and priority of simultaneous events are shown in Table 4-4 on page 31. Some of the exceptions are unused in AVR32UC since it has no MMU, coprocessor interface, or floatingpoint unit. 30 32099B-05/2010 AT32UC3L Table 4-4. Priority and Handler Addresses for Events Priority Handler Address Name Event source Stored Return Address 1 0x80000000 Reset External input Undefined 2 Provided by OCD system OCD Stop CPU OCD system First non-completed instruction 3 EVBA+0x00 Unrecoverable exception Internal PC of offending instruction 4 EVBA+0x04 TLB multiple hit MPU PC of offending instruction 5 EVBA+0x08 Bus error data fetch Data bus First non-completed instruction 6 EVBA+0x0C Bus error instruction fetch Data bus First non-completed instruction 7 EVBA+0x10 NMI External input First non-completed instruction 8 Autovectored Interrupt 3 request External input First non-completed instruction 9 Autovectored Interrupt 2 request External input First non-completed instruction 10 Autovectored Interrupt 1 request External input First non-completed instruction 11 Autovectored Interrupt 0 request External input First non-completed instruction 12 EVBA+0x14 Instruction Address CPU PC of offending instruction 13 EVBA+0x50 ITLB Miss MPU PC of offending instruction 14 EVBA+0x18 ITLB Protection MPU PC of offending instruction 15 EVBA+0x1C Breakpoint OCD system First non-completed instruction 16 EVBA+0x20 Illegal Opcode Instruction PC of offending instruction 17 EVBA+0x24 Unimplemented instruction Instruction PC of offending instruction 18 EVBA+0x28 Privilege violation Instruction PC of offending instruction 19 EVBA+0x2C Floating-point UNUSED 20 EVBA+0x30 Coprocessor absent Instruction PC of offending instruction 21 EVBA+0x100 Supervisor call Instruction PC(Supervisor Call) +2 22 EVBA+0x34 Data Address (Read) CPU PC of offending instruction 23 EVBA+0x38 Data Address (Write) CPU PC of offending instruction 24 EVBA+0x60 DTLB Miss (Read) MPU PC of offending instruction 25 EVBA+0x70 DTLB Miss (Write) MPU PC of offending instruction 26 EVBA+0x3C DTLB Protection (Read) MPU PC of offending instruction 27 EVBA+0x40 DTLB Protection (Write) MPU PC of offending instruction 28 EVBA+0x44 DTLB Modified UNUSED 31 32099B-05/2010 AT32UC3L 5. Memories 5.1 Embedded Memories * Internal High-Speed Flash - 64Kbytes (AT32UC3L064) - 32Kbytes (AT32UC3L032) - 16Kbytes (AT32UC3L016) * 0 Wait State Access at up to 25MHz in Worst Case Conditions * 1 Wait State Access at up to 50MHz in Worst Case Conditions * Pipelined Flash Architecture, allowing burst reads from sequential Flash locations, hiding penalty of 1 wait state access * Pipelined Flash Architecture typically reduces the cycle penalty of 1 wait state operation to only 8% compared to 0 wait state operation * 100 000 Write Cycles, 15-year Data Retention Capability * 4ms Page Programming Time, 8ms Chip Erase Time * Sector Lock Capabilities, Bootloader Protection, Security Bit * 32 Fuses, Erased During Chip Erase * User Page For Data To Be Preserved During Chip Erase * Internal High-Speed SRAM, Single-cycle access at full speed - 16Kbytes (AT32UC3L064, AT32UC3L032) - 8Kbytes (AT32UC3L016) 5.2 Physical Memory Map The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot. Note that AVR32 UC CPU uses unsegmented translation, as described in the AVR32 Architecture Manual. The 32-bit physical address space is mapped as follows: Table 5-1. AT32UC3L Physical Memory Map Device Table 5-2. Start Address Size AT32UC3L064 AT32UC3L032 AT32UC3L016 Embedded SRAM 0x00000000 16 Kbytes 16 Kbytes 8 Kbytes Embedded Flash 0x80000000 64 Kbytes 32 Kbytes 16 Kbytes HSB-PB Bridge B 0xFFFE0000 64 Kbytes 64 kBytes 64 Kbytes HSB-PB Bridge A 0xFFFF0000 64 Kbytes 64 Kbytes 64 Kbytes Flash Memory Parameters Part Number Flash Size (FLASH_PW) Number of pages (FLASH_P) Page size (FLASH_W) AT32UC3L064 64 Kbytes 256 256 bytes AT32UC3L032 32 Kbytes 128 256 bytes AT32UC3L016 16 Kbytes 64 256 bytes 32 32099B-05/2010 AT32UC3L 5.3 Peripheral Address Map Table 5-3. Peripheral Address Mapping Address Peripheral Name Bus 0xFFFE0000 FLASHCDW Flash Controller - FLASHCDW 0xFFFE0400 HMATRIX HSB Matrix - HMATRIX 0xFFFE0800 SAU Secure Access Unit - SAU 0xFFFF0000 PDCA Peripheral DMA Controller - PDCA INTC Interrupt controller - INTC 0xFFFF1000 0xFFFF1400 PM Power Manager - PM 0xFFFF1800 SCIF System Control Interface - SCIF AST Asynchronous Timer - AST WDT Watchdog Timer - WDT EIC External Interrupt Controller - EIC 0xFFFF1C00 0xFFFF2000 0xFFFF2400 0xFFFF2800 FREQM Frequency Meter - FREQM 0xFFFF2C00 GPIO 0xFFFF3000 General Purpose Input/Output Controller - GPIO USART0 Universal Synchronous/Asynchronous Receiver/Transmitter - USART0 USART1 Universal Synchronous/Asynchronous Receiver/Transmitter - USART1 USART2 Universal Synchronous/Asynchronous Receiver/Transmitter - USART2 USART3 Universal Synchronous/Asynchronous Receiver/Transmitter - USART3 0xFFFF3400 0xFFFF3800 0xFFFF3C00 0xFFFF4000 SPI Serial Peripheral Interface - SPI 0xFFFF4400 TWIM0 Two-wire Master Interface - TWIM0 33 32099B-05/2010 AT32UC3L Table 5-3. Peripheral Address Mapping 0xFFFF4800 TWIM1 Two-wire Master Interface - TWIM1 TWIS0 Two-wire Slave Interface - TWIS0 TWIS1 Two-wire Slave Interface - TWIS1 PWMA Pulse Width Modulation Controller - PWMA 0xFFFF4C00 0xFFFF5000 0xFFFF5400 0xFFFF5800 TC0 Timer/Counter - TC0 TC1 Timer/Counter - TC1 0xFFFF5C00 0xFFFF6000 ADCIFB ADC Interface - ADCIFB 0xFFFF6400 ACIFB Analog Comparator Interface - ACIFB 0xFFFF6800 CAT Capacitive Touch Module - CAT 0xFFFF6C00 GLOC Glue Logic Controller - GLOC 0xFFFF7000 AW 5.4 aWire - AW CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being mapped on the Peripheral Bus. These registers can therefore be reached both by accesses on the Peripheral Bus, and by accesses on the local bus. Mapping these registers on the local bus allows cycle-deterministic toggling of GPIO pins since the CPU and GPIO are the only modules connected to this bus. Also, since the local bus runs at CPU speed, one write or read operation can be performed per clock cycle to the local busmapped GPIO registers. 34 32099B-05/2010 AT32UC3L The following GPIO registers are mapped on the local bus: Table 5-4. Local Bus Mapped GPIO Registers Port Register Mode Local Bus Address Access 0 Output Driver Enable Register (ODER) WRITE 0x40000040 Write-only SET 0x40000044 Write-only CLEAR 0x40000048 Write-only TOGGLE 0x4000004C Write-only WRITE 0x40000050 Write-only SET 0x40000054 Write-only CLEAR 0x40000058 Write-only TOGGLE 0x4000005C Write-only Pin Value Register (PVR) - 0x40000060 Read-only Output Driver Enable Register (ODER) WRITE 0x40000240 Write-only SET 0x40000244 Write-only CLEAR 0x40000248 Write-only TOGGLE 0x4000024C Write-only WRITE 0x40000250 Write-only SET 0x40000254 Write-only CLEAR 0x40000258 Write-only TOGGLE 0x4000025C Write-only - 0x40000260 Read-only Output Value Register (OVR) 1 Output Value Register (OVR) Pin Value Register (PVR) 35 32099B-05/2010 AT32UC3L 6. Supply and Startup Considerations 6.1 6.1.1 Supply Considerations Power Supplies The AT32UC3L has several types of power supply pins: *VDDIO: Powers I/O lines. Voltage is 1.8 to 3.3V nominal. *VDDIN: Powers I/O lines and the internal regulator. Voltage is 1.8 to 3.3V nominal. *VDDANA: Powers the ADC. Voltage is 1.8V nominal. *VDDCORE: Powers the core, memories, and peripherals. Voltage is 1.8V nominal. The ground pins GND are common to VDDCORE and VDDIO. The ground pin for VDDANA is GNDANA. Refer to Section 7. on page 41 for power consumption on the various supply pins. 6.1.2 Voltage Regulator The AT32UC3L embeds a voltage regulator that converts from 3.3V nominal to 1.8V with a load of up to 60 mA. The regulator supplies the output voltage on VDDCORE. The regulator may only be used to drive internal circuitry in the device. VDDCORE should be externally connected to the 1.8V domains. See Section 6.1.3 for regulator connection figures. Adequate output supply decoupling is mandatory for VDDCORE to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallell between VDDCORE and GND as close to the chip as possible. Please refer to Section 7.9.1 on page 50 for decoupling capacitors values and regulator characteristics. Figure 6-1. Supply Decoupling 3.3V VDDIN C IN3 CIN2 CIN1 1.8V VDDCORE COUT2 6.1.3 1.8V Regulator COUT1 Regulator Connection The AT32UC3L supports three power supply configurations: * 3.3V single supply mode * 1.8V single supply mode * 3.3V supply mode, with 1.8V regulated I/O lines 36 32099B-05/2010 AT32UC3L 6.1.3.1 3.3V Single Supply Mode In 3.3V single supply mode the internal regulator is connected to the 3.3V source (VDDIN pin) and its output feeds VDDCORE. Figure 6-2 shows the power schematics to be used for 3.3V single supply mode. All I/O lines will be powered by the same power (VDDIN=VDDIO). Figure 6-2. 3.3V Single Power Supply mode + 1.98-3.6V - VDDIN VDDIO GND I/O Pins I/O Pins VDDCORE OSC32K RC32K AST Wake POR33 SM33 VDDANA CPU, Peripherals, Memories, SCIF, BOD, RCSYS, DFLL Linear ADC GNDANA 37 32099B-05/2010 AT32UC3L 6.1.3.2 1.8V Single Supply Mode In 1.8V single supply mode the internal regulator is not used, and VDDIO and VDDCORE are powered by a single 1.8V supply as shown in Figure 6-3. All I/O lines will be powered by the same power (VDDIN = VDDIO = VDDCORE). Figure 6-3. 1.8V Single Power Supply Mode. + 1.62-1.98V - VDDIN VDDIO I/O Pins I/O Pins OSC32K RC32K AST Wake POR33 SM33 Linear VDDCORE VDDANA ADC GNDANA GND CPU, Peripherals, Memories, SCIF, BOD, RCSYS, DFLL 38 32099B-05/2010 AT32UC3L 6.1.3.3 3.3V Supply Mode with 1.8V Regulated I/O Lines In this mode, the internal regulator is connected to the 3.3V source and its output is connected to both VDDCORE and VDDIO as shown in Figure 6-4. This configuration is required in order to use Shutdown mode. Figure 6-4. 3.3V Power with 1.8V Regulated I/O Lines 1.98-3.6V + - VDDIN VDDIO I/O Pins I/O Pins Linear OSC32K RC32K AST Wake POR33 SM33 VDDCORE VDDANA ADC GNDANA GND CPU, Peripherals, Memories, SCIF, BOD, RCSYS, DFLL In this mode, some I/O lines are powered by VDDIN while others I/O lines are powered by VDDIO. Refer to Section 3.2 on page 8 for description of power supply for each I/O line. Refer to the Power Manager chapter for a description of what parts of the system are powered in Shutdown mode. Important note: As the regulator has a maximum output current of 60mA, this mode can only be used in applications where the maximum I/O current is known and compatible with the core and peripheral power consumption. Typically, great care must be used to ensure that only a few I/O lines are toggling at the same time and drive very small loads. 39 32099B-05/2010 AT32UC3L 6.1.4 Power-up Sequence 6.1.4.1 Maximum Rise Rate To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values described in Table 7-3 on page 42. Recommended order for power supplies is also described in this chapter. 6.1.4.2 Minimum Rise Rate The integrated Power-Reset circuitry monitoring the VDDIN powering supply requires a minimum rise rate for the VDDIN power supply. See Table 7-3 on page 42 for the minimum rise rate value. If the application can not ensure that the minimum rise rate condition for the VDDIN power supply is met, one of the following configuration can be used: * A logic "0" value is applied during power-up on pin PA11 until VDDIN rises above 1.2V. * A logic "0" value is applied during power-up on pin RESET_N until VDDIN rises above 1.2V. 6.2 Startup Considerations This chapter summarizes the boot sequence of the AT32UC3L. The behavior after power-up is controlled by the Power Manager. For specific details, refer to the Power Manager chapter. 6.2.1 Starting of Clocks After power-up, the device will be held in a reset state by the Power-On Reset circuitry for a short time to allow the power to stabilize throughout the device. After reset, the device will use the System RC Oscillator (RCSYS) as clock source. Please refer to Table 7-17 on page 49 for the frequency for this oscillator. On system start-up, the DFLL is disabled. All clocks to all modules are running. No clocks have a divided frequency; all parts of the system receive a clock with the same frequency as the System RC Oscillator. When powering up the device, there may be a delay before the voltage has stabilized, depending on the rise time of the supply used. The CPU can start executing code as soon as the supply is above the POR threshold, and before the supply is stable. Before switching to a high-speed clock source, the user should use the BOD to make sure the VDDCORE is above the minimum level (1.62V). 6.2.2 Fetching of Initial Instructions After reset has been released, the AVR32 UC CPU starts fetching instructions from the reset address, which is 0x80000000. This address points to the first address in the internal Flash. The code read from the internal Flash is free to configure the system to use for example the DFLL, to divide the frequency of the clock routed to some of the peripherals, and to gate the clocks to unused peripherals. 40 32099B-05/2010 AT32UC3L 7. Electrical Characteristics 7.1 Disclaimer All values in this chapter are preliminary and subject to change without further notice. 7.2 Absolute Maximum Ratings* Table 7-1. Absolute Maximum Ratings Operating temperature..................................... -40C to +85C *NOTICE: Storage temperature...................................... -60C to +150C Voltage on input pins (except for 5V pins) with respect to ground .................................................................-0.3V to VVDD(2)+0.3V Voltage on 5V tolerant(1) pins with respect to ground ............... .............................................................................-0.3V to 5.5V Total DC output current on all I/O pins - VDDIO ........... 120mA Total DC output current on all I/O pins - VDDIN ............. 36mA Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum operating voltage VDDCORE......................... 1.98V Maximum operating voltage VDDIO, VDDIN .................... 3.6V Notes: 1. 5V tolerant pins, see Section 3.2 "Peripheral Multiplexing on I/O lines" on page 8 2. VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pad. Refer to Section 3.2 on page 8 for details. 7.3 Supply Characteristics The following characteristics are applicable to the operating temperature range: TA = -40C to 85C, unless otherwise specified and are certified for a junction temperature up to TJ = 100C. Table 7-2. Supply Characteristics(1) Voltage Symbol Parameter Min Max Unit VVDDIO DC supply peripheral I/Os 1.62 3.6 V DC supply peripheral I/Os, 1.8V single supply mode 1.62 1.98 V DC supply peripheral I/Os and internal regulator, 3.3V single supply mode 1.98 3.6 V VVDDCORE DC supply core 1.62 1.98 V VVDDANA Analog supply voltage 1.62 1.98 V VADVREFP Analog reference voltage 1.62 VVDDANA V VVDDIN Note: 1. VDDANA = VDDCORE 41 32099B-05/2010 AT32UC3L Table 7-3. Supply Rise Rates and Order Rise Rate Symbol Parameter Min Max Unit VVDDIO DC supply peripheral I/Os 0 2.5 V/s VVDDIN DC supply peripheral I/Os and internal regulator 0.002(1) 2.5 V/s VVDDCORE DC supply core 0 2.5 V/s Rise before or at the same time as VDDIO VVDDANA Analog supply voltage 0 2.5 V/s Rise together with VDDCORE Note: 7.4 Comment 1. Slower rise time requires external power-on reset circuit. Maximum Clock Frequencies These parameters are given in the following conditions: VVDDCORE = 1.62 to 1.98V Temperature = -40C to 85C Table 7-4. 7.5 Clock Frequencies Symbol Parameter fCPU Conditions Min Max Units CPU clock frequency 50 MHz fPBA PBA clock frequency 50 MHz fPBB PBB clock frequency 50 MHz fGCLK0 GCLK0 clock frequency 150 MHz fGCLK1 GCLK1 clock frequency 150 MHz fGCLK2 GCLK2 clock frequency 80 MHz fGCLK3 GCLK3 clock frequency 110 MHz fGCLK4 GCLK4 clock frequency 110 MHz fGCLK5 GCLK5 clock frequency 80 MHz Power Consumption * The values in Table 7-5 are measured values of power consumption under the following conditions, except where noted: * Operating conditions - 1.8V single supply mode (all modes except Shutdown) - 3.3V supply mode with 1.8V regulated I/O lines (Shutdown) - VVDDIO = 1.8V - VVDDIN = 1.8V - VVDDCORE = 1.8V - VVDDANA = 1.8V - TA = 25C 42 32099B-05/2010 AT32UC3L * Oscillators - XIN0 (crystal oscillator) stopped - XIN32 (32KHz crystal oscillator) running with external 32KHz crystal - DFLL running at 50MHz with OSC32K as reference * Clocks - Main clock source is DFLL - CPU and HSB clocks undivided - PBA and PBB clocks divided by 8 * I/Os are inactive with internal pull-up * POR33 disabled * Voltage regulator off Figure 7-1. Measurement Schematic Amp0 VDDIN VDDIO VDDCORE VDDANA 43 32099B-05/2010 AT32UC3L Figure 7-2. Measurement Schematic, Shutdown Mode VDDIN Amp0 VDDIO VDDCORE VDDANA Table 7-5. Power Consumption for Different Modes Mode Conditions Measured on Consumption Typ Active Active mode(1) Amp0 300 Amp0 150 Amp0 90 Amp0 70 Amp0 30 Amp0 20 Idle Idle (2) (2) Frozen Frozen sleep mode Standby Standby sleep mode Stop Stop sleep mode(3) (3) DeepStop DeepStop sleep mode Amp0 5.5 Static Static sleep mode with RTC(3) Static sleep mode(4) Amp0 5 Shutdown sleep mode with RTC(5) Amp0 1.5 Shutdown sleep mode (6) Amp0 0.1 Shutdown Notes: Unit A/MHz A 1. CPU performing recursive Fibonacci algorithm running from flash. No peripheral clocks masked. 2. No peripheral clocks masked. 3. DFLL stopped. 4. OSC32K stopped. DFLL stopped. 5. DFLL stopped. 6. OSC32K stopped. DFLL stopped. 44 32099B-05/2010 AT32UC3L 7.6 I/O Pad Characteristics Table 7-6. Normal I/O Pad Characteristics(1) Symbol Parameter RPULLUP Pull-up resistance VIL Input low-level voltage VIH Input high-level voltage VOL Output low-level voltage VOH Output high-level voltage ILEAK Input leakage current Notes: Min Typ Max Units 75 100 145 kOhm VVDD = 3.0V -0.3 0.3*VVDD VVDD = 1.62V -0.3 0.3*VVDD VVDD = 3.6V 0.7*VVDD VVDD + 0.3 VVDD = 1.98V 0.7*VVDD VVDD + 0.3 VVDD = 3.0V, IOL = 3mA 0.4 VVDD = 1.62 V, IOL = 2mA 0.4 V V V VVDD = 3.0V, IOH = 3mA VVDD - 0.4 VVDD = 1.62 V, IOH = 2mA VVDD - 0.4 V Pull-up resistors disabled 1 A 1. VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pad. Refer to Section 3.2 on page 8 for details. Table 7-7. Symbol RPULLUP High-drive I/O Pad Characteristics(1) Parameter Pull-up resistance VIL Input low-level voltage VIH Input high-level voltage VOL Output low-level voltage VOH Output high-level voltage ILEAK Input leakage current Notes: Condition Condition Min Typ Max PA06 30 50 110 PA02, PB01, RESET 75 100 145 PA08, PA09 10 20 45 VVDD = 3.0V -0.3 0.3*VVDD VVDD = 1.62V -0.3 0.3*VVDD VVDD = 3.6V 0.7*VVDD VVDD + 0.3 VVDD = 1.98V 0.7*VVDD VVDD + 0.3 VVDD = 3.0V, IOL = 6mA 0.4 VVDD = 1.62 V, IOL = 4mA 0.4 Units kOhm V V V VVDD = 3.0V, IOH = 6mA VVDD-0.4 VVDD = 1.62 V, IOH = 4mA VVDD-0.4 V Pull-up resistors disabled 1 A 1. VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pad. Refer to Section 3.2 on page 8 for details. Table 7-8. 5V Tolerant Normal I/O Pad Characteristics(1) Symbol Parameter RPULLUP Pull-up resistance VIL Input low-level voltage Condition Min Typ Max Units 75 100 145 kOhm VVDD = 3.0V -0.3 0.3*VVDD VVDD = 1.62V -0.3 0.3*VVDD V 45 32099B-05/2010 AT32UC3L Table 7-8. 5V Tolerant Normal I/O Pad Characteristics(1) Symbol Parameter VIH Input high-level voltage VOL Output low-level voltage VOH Output high-level voltage ILEAK Input leakage current Notes: Min Typ Max VVDD = 3.6V 0.7*VVDD 5.5 VVDD = 1.98V 0.7*VVDD 5.5 Units V VVDD = 3.0V, IOL = 3mA 0.4 VVDD = 1.62 V, IOL = 2mA 0.4 V VVDD = 3.0V, IOH = 3mA VVDD-0.4 VVDD = 1.62 V, IOH = 2mA VVDD-0.4 V 5.5V, pull-up resistors disabled 1 A 1. VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pad. Refer to Section 3.2 on page 8 for details. Table 7-9. 5V Tolerant High-drive I/O Pad Characteristics(1) Symbol Parameter RPULLUP Pull-up resistance VIL Input low-level voltage VIH Input high-level voltage VOL Output low-level voltage VOH Output high-level voltage ILEAK Input leakage current Notes: Condition Condition Min Typ Max Units 30 50 110 kOhm VVDD = 3.0V -0.3 0.3*VVDD VVDD = 1.62V -0.3 0.3*VVDD VVDD = 3.6V 0.7*VVDD 5.5 VVDD = 1.98V 0.7*VVDD 5.5 V V VVDD = 3.0V, IOL = 6mA 0.4 VVDD = 1.62 V, IOL = 4mA 0.4 V VVDD = 3.0V, IOH = 6mA VVDD-0.4 VVDD = 1.62 V, IOH = 4mA VVDD-0.4 V 5.5V, pull-up resistors disabled 1 A 1. VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pad. Refer to Section 3.2 on page 8 for details. Table 7-10. TWI Pad Characteristics(1) Symbol Parameter Condition RPULLUP Pull-up resistance VIL Input low-level voltage VIH Input high-level voltage VOL Output low-level voltage IOL = 3mA ILEAK Input leakage current Pull-up resistors disabled IIL Min Typ Max Units 25 35 50 kOhm VVDD = 3.0V -0.3 0.3*VVDD VVDD = 1.62V -0.3 0.3*VVDD VVDD = 3.6V 0.7*VVDD VVDD + 0.3 VVDD = 1.98V 0.7*VVDD VVDD + 0.3 V V 0.4 V 1 A Input low leakage 1 A IIH Input high leakage 1 A fMAX Max frequency Notes: Cbus = 400pF, VVDD > 2.0V 400 kHz 1. VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pad. Refer to Section 3.2 on page 8 for details. 46 32099B-05/2010 AT32UC3L 7.7 Oscillator Characteristics 7.7.1 Oscillator 0 (OSC0) Characteristics 7.7.1.1 Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN. Table 7-11. Digital Clock Characteristics Symbol Parameter fCPXIN XIN clock frequency tCPXIN XIN clock duty cycle 7.7.1.2 Conditions Min Typ Max 40 Units 50 MHz 60 % Crystal Oscillator Characteristics The following table describes the characteristics for the oscillator when a crystal is connected between XIN and XOUT as shown in Figure 7-3. The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in the table. The exact value of CL can be found in the crystal datasheet. The capacitance of the external capacitors (CLEXT) can then be computed as follows: C LEXT = 2 ( C L - C i ) - C PCB where CPCB is the capacitance of the PCB. Table 7-12. Crystal Oscillator Characteristics Symbol Parameter 1/(tCPMAIN) Crystal oscillator frequency CL Crystal load capacitance Ci Internal equivalent load capacitance tSTARTUP Notes: Startup time Conditions Min Typ Max Unit 3 16 MHz 6 18 pF 2 (1) SCIF.OSCCTRL.GAIN = 2 pF (2) 30 000 cycles 1. Please refer to the SCIF chapter for details. 2. Nominal crystal cycles. 47 32099B-05/2010 AT32UC3L Figure 7-3. Oscillator Connection CLEXT XOUT UC3L Ci CL XIN CLEXT 7.7.2 32KHz Crystal Oscillator (OSC32K) Characteristics Figure 7-3 and the equation above also applies to the 32 KHz oscillator connection. The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in the table. The exact value of CL can then be found in the crystal datasheet. Table 7-13. 32 KHz Crystal Oscillator Characteristics Symbol Parameter 1/(tCP32KHz) Crystal oscillator frequency tST Startup time CL Crystal load capacitance Ci Internal equicalent load capacitance IOSC Current consumption RS Equivalent series resistance Note: Conditions Min RS = 60kOhm, CL = 9pF Typ 35 Unit 32 768 Hz 30 000(1) cycles 6 32 768Hz Max 12.5 pF 2 pF 0.9 A 85 kOhm 1. Nominal crystal cycles. 48 32099B-05/2010 AT32UC3L 7.7.3 Digital Frequency Locked Loop (DFLL) Characteristics Table 7-14. Digital Frequency Locked Loop Characteristics Symbol Parameter fOUT Output frequency fREF Reference frequency FINE resolution Conditions Min Typ Max Unit 40 150 MHz 8 150 kHz FINE>100, all COARSE values 0.25 % Fine lock, fREF=32kHz, SSG disabled 0.1 0.5 Accurate lock, fREF=32kHz, dither clk RCSYS/2, SG disabled 0.06 0.5 Fine lock, fREF=8-150kHz, SSG disabled 0.2 1 Accurate lock, fREF=8-150kHz, dither clk RCSYS/2, SSG disabled 0.1 1 Accuracy % Power consumption Startup time tSTARTUP Lock time tLOCK Note: 22 Within 90% of final values A/MHz 100 fREF = 32kHz, fine lock, SSG disabled 600 fREF = 32kHz, accurate lock, dithering clock = RCSYS/2, SSG disabled 1100 s s 1. Spread Spectrum Generator (SSG) is disabled by writing a zero to the EN bit in the SCIF.DFLL0SSG register. 7.7.4 120MHz RC Oscillator (RC120M) Characteristics Table 7-15. Internal 120MHz RC Oscillator Characteristics Symbol Parameter Conditions Min Typ Max Unit fOUT Output frequency T = 25C, VVDDCORE = 1.8V 88 120 152 MHz Temperature drift Duty 7.7.5 +/-5 Duty cycle % 40 50 60 % 32kHz RC Oscillator (RC32K) Characteristics Table 7-16. 32kHz RC Oscillator Characteristics Symbol Parameter Conditions Min Typ Max Unit fOUT Output frequency T = 25C, VVDDIO = 3.3V 20 32 44 kHz Min Typ Max Unit 7.7.6 System RC Oscillator (RCSYS) Characteristics Table 7-17. System RC Oscillator Characteristics Symbol Parameter Conditions fOUT Output frequency Calibrated at 85C 115 kHz 49 32099B-05/2010 AT32UC3L 7.8 Flash Characteristics Table 7-18 gives the device maximum operating frequency depending on the number of flash wait states and the flash read mode. The FSW bit in the FLASHCDW FSR register controls the number of wait states used when accessing the flash memory. Table 7-18. Maximum Operating Frequency Flash Wait States Read Mode Maximum Operating Frequency 1 50MHz High speed read mode 0 25MHz 1 30MHz Normal read mode 0 7.9 15MHz Analog Characteristics 7.9.1 Voltage Regulator Characteristics 7.9.1.1 Electrical Characteristics Table 7-19. Electrical Characteristics Symbol Parameter VVDDIN Input voltage range VVDDCORE Output voltage Output voltage accuracy IOUT DC output current ISCR Static current of internal regulator 7.9.1.2 Condition Min Typ Max Units 1.98 3.3 3.6 V VVDDIN > 1.98V 1.8 IOUT = 0.1mA to 60mA, VVDDIN>2.2V 2 IOUT = 0.1mA to 60mA, VVDDIN=1.98V to 2.2V 4 V % Normal mode 60 mA Low power mode 1 mA Normal mode 20 A Low power mode 6 A Decoupling Requirements Table 7-20. Decoupling Requirements Symbol Parameter CIN1 Input regulator capacitor 1 33 nF CIN2 Input regulator capacitor 2 100 nF CIN3 Input regulator capacitor 3 10 F COUT1 Output regulator capacitor 1 100 nF COUT2 Output regulator capacitor 2 2.2 Note: Condition Typ Techno. Tantalum 0.5<ESR<10 Units F 1. Refer to Section 6.1.2 on page 36. 50 32099B-05/2010 AT32UC3L 7.9.2 ADC Characteristics Table 7-21. Channel Conversion Time and ADC Clock Symbol Parameter fADC ADC clock frequency tSTARTUP Startup time Conditions Min 6 8-bit resolution mode 6 Return from Idle Mode Conversion time (latency) fADC = 6MHz 26 460 fADC = 6MHz, 8-bit resolution mode, low impedance source 460 kSPS External Voltage Reference Input Min VADVREFP Reference voltage range VADVREFP = VVDDANA 1.62 Current consumption on VVDDANA On 13 samples with ADC Clock = 5MHz Average current fADC = 6MHz Parameter VADn Input Voltage Range V A Conditions 10-bit mode 8-bit mode Min Typ 0 Max Units VADVREFP V Transfer Characteristics 10-bit Resolution Mode Conditions Min Typ Max 10 Differential non-linearity Units Bit +/-2 ADC clock frequency = 6MHz -0.9 1 +/-4 Gain error Resolution 1.98 250 Integral non-linearity Parameter Units mA Resolution Table 7-25. Max Applicable Conditions and Derating Data Parameter Offset error Typ Analog Inputs Symbol Table 7-24. cycles fADC = 6MHz, 10-bit resolution mode, low impedance source Conditions 7.9.2.1 s ns 11 Parameter Table 7-23. MHz 15 Symbol IADVREFP Units 500 Throughput rate Table 7-22. Max 10-bit resolution mode Sample and hold acquisition time tCONV Typ LSB +/-4 Transfer Characteristics 8-bit Resolution Mode Conditions Min Typ 8 Max Units Bit 51 32099B-05/2010 AT32UC3L Table 7-25. Transfer Characteristics 8-bit Resolution Mode Parameter Conditions Min Typ Integral non-linearity Differential non-linearity Offset error ADC clock frequency = 6MHz 0.25 +/-1 LSB +/-1 Analog Comparator Characteristics Table 7-26. Symbol Analog Comparator Characteristics Parameter Condition Min Typ Max Units Positive input voltage range -0.2 VVDDIO + 0.3 V Negative input voltage range -0.2 VVDDIO - 0.6 V Statistical offset fAC Clock frequency for GCLK4 tSTARTUP Startup time Input current per pin Notes: Units +/-0.5 -0.23 Gain error 7.9.3 Max VACREFN = 1.0V, fAC= 12MHz, filter length=2, hysteresis=0.(1) 20 mV 12 3 MHz cycles 0.2 A/MHz(2) 1. AC.CONFn.FLEN and AC.CONFn.HYS fields, refer to the Analog Comparator Interface chapter. 2. Referring to fAC. 52 32099B-05/2010 AT32UC3L 7.9.4 POR18 Table 7-27. Power-on Reset Characteristics Symbol Parameter Condition VPOT+ Voltage threshold on VVDDCORE rising T=25C 1.45 V VPOT- Voltage threshold on VVDDCORE falling T=25C 1.32 V Typ Max Units POR18 Operating Principles VVDDCORE Figure 7-4. Min VPOT+ Reset VPOT- 53 32099B-05/2010 AT32UC3L 7.9.5 POR33 Table 7-28. POR33 Characteristics Symbol Parameter Condition VPOT+ Voltage threshold on VVDDIN rising VPOT- Voltage threshold on VVDDIN falling Typ Max Units 1.49 T=25C V 1.45 POR33 Operating Principles VVDDIN Figure 7-5. Min Reset VPOT+ VPOT- 7.9.6 Temperature Sensor Table 7-29. Symbol Temperature Sensor Characteristics Parameter Condition Min Gradient 7.10 Typ Max Units mV/C 1 Timing Characteristics 7.10.1 RESET_N Characteristics Table 7-30. RESET_N Waveform Parameters Symbol Parameter tRESET RESET_N minimum pulse length Conditions Min 10 Max Units ns 54 32099B-05/2010 AT32UC3L 8. Mechanical Characteristics 8.1 8.1.1 Thermal Considerations Thermal Data Table 8-1 summarizes the thermal resistance data depending on the package. Table 8-1. 8.1.2 Thermal Resistance Data Symbol Parameter Condition Package Typ JA Junction-to-ambient thermal resistance Still Air TQFP48 63.2 JC Junction-to-case thermal resistance TQFP48 21.8 JA Junction-to-ambient thermal resistance QFN48 28.3 JC Junction-to-case thermal resistance QFN48 2.5 JA Junction-to-ambient thermal resistance TLLGA48 30.06 JC Junction-to-case thermal resistance TLLGA48 TBD Still Air Still Air Unit C/W C/W C/W Junction Temperature The average chip-junction temperature, TJ, in C can be obtained from the following: 1. T J = T A + ( P D x JA ) 2. T J = T A + ( P D x ( HEATSINK + JC ) ) where: * JA = package thermal resistance, Junction-to-ambient (C/W), provided in Table 8-1. * JC = package thermal resistance, Junction-to-case thermal resistance (C/W), provided in Table 8-1. * HEAT SINK = cooling device thermal resistance (C/W), provided in the device datasheet. * PD = device power consumption (W) estimated from data provided in the Section 1.5 on page 36. * TA = ambient temperature (C). From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature TJ in C. 55 32099B-05/2010 AT32UC3L 8.2 Package Drawings Figure 8-1. TQFP-48 Package Drawing Table 8-2. Device and Package Maximum Weight 140 Table 8-3. mg Package Characteristics Moisture Sensitivity Level Table 8-4. MSL3 Package Reference JEDEC Drawing Reference MS-026 JESD97 Classification E3 56 32099B-05/2010 AT32UC3L Figure 8-2. Note: QFN-48 Package Drawing The exposed pad is not connected to anything. Table 8-5. Device and Package Maximum Weight 140 Table 8-6. mg Package Characteristics Moisture Sensitivity Level Table 8-7. MSL3 Package Reference JEDEC Drawing Reference M0-220 JESD97 Classification E3 57 32099B-05/2010 AT32UC3L Figure 8-3. TLLGA-48 Package Drawing Table 8-8. Device and Package Maximum Weight 39.3 Table 8-9. mg Package Characteristics Moisture Sensitivity Level Table 8-10. MSL3 Package Reference JEDEC Drawing Reference M0-220 JESD97 Classification E4 58 32099B-05/2010 AT32UC3L 8.3 Soldering Profile Table 8-11 gives the recommended soldering profile from J-STD-20. Table 8-11. Soldering Profile Profile Feature Green Package Average Ramp-up Rate (217C to Peak) 3C/s max Preheat Temperature 175C 25C 150-200C Time Maintained Above 217C 60-150 s Time within 5C of Actual Peak Temperature 30 s Peak Temperature Range 260C Ramp-down Rate 6C/s max Time 25C to Peak Temperature 8 minutes max A maximum of three reflow passes is allowed per component. 59 32099B-05/2010 AT32UC3L 9. Ordering Information Table 9-1. Ordering Information Device Ordering Code Carrier Type Package AT32UC3L064-AUT Tray TQFP 48 AT32UC3L064-AUR Tape & Reel TQFP 48 AT32UC3L064-ZAUT Tray QFN 48 AT32UC3L064-ZAUR Tape & Reel QFN 48 AT32UC3L064-D3HR Tape & Reel TLLGA 48 AT32UC3L032-AUT Tray TQFP 48 AT32UC3L032-AUR Tape & Reel TQFP 48 AT32UC3L032-ZAUT Tray QFN 48 AT32UC3L032-ZAUR Tape & Reel QFN 48 AT32UC3L032-D3HR Tape & Reel TLLGA 48 AT32UC3L016-AUT Tray TQFP 48 AT32UC3L016-AUR Tape & Reel TQFP 48 AT32UC3L016-ZAUT Tray QFN 48 AT32UC3L016-ZAUR Tape & Reel QFN 48 AT32UC3L016-D3HR Tape & Reel TLLGA 48 Package Type Temperature Operating Range JESD97 Classification E3 AT32UC3L064 JESD97 Classification E4 JESD97 Classification E3 AT32UC3L032 Industrial (-40C to 85C) JESD97 Classification E4 JESD97 Classification E3 AT32UC3L016 JESD97 Classification E4 60 32099B-05/2010 AT32UC3L 10. Errata 10.1 10.1.1 Rev. D Processor and Architecture 1. Privilege violation when using interrupts in application mode with protected system stack If the system stack is protected by the MPU and an interrupt occurs in application mode, an MPU DTLB exception will occur. Fix/Workaround Make a DTLB Protection (Write) exception handler which permits the interrupt request to be handled in privileged mode. 2. Hardware breakpoints may corrupt MAC results Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC instruction. Fix/Workaround Place breakpoints on earlier or later instructions. 10.1.2 FLASHCDW 1. Flash Selfprogramming may fail in one wait state mode Writes in flash and user pages may fail if executing code located in the address space mapped to the flash and if the flash controller is configured in one wait state mode (the Flash Wait State bit in the Flash Control Register (FCR.FWS) is 1). Fix/Workaround Solution 1: Configure the flash controller in zero wait state mode (FCR.FWS=0). Solution 2: Configure the HMATRIX master 1 (CPU Instruction) to use the unlimited burst length transfer mode (MCFG1.ULBT=0) and the HMATRIX slave 0 (FLASHCDW) to use the maximum slot cycle limit (SCFG0.SLOT_CYCLE=255). 10.1.3 Power Manager 1. Clock sources will not be stopped in Static mode if the difference between CPU and PBx division factor is larger than 4 If the division factor between the CPU/HSB and PBx frequencies is more than 4 when entering a sleep mode where the system RC oscillator (RCSYS) is turned off, the high speed clock sources will not be turned off. This will result in a significantly higher power consumption during the sleep mode. Fix/Workaround Before going to sleep modes where RCSYS is stopped, make sure the division factor between the CPU/HSB and PBx frequencies is less than or equal to 4. 2. External reset in Shutdown mode If an external reset is asserted while the chip is in Shutdown mode, the Power Manager will register this as a Power-on reset (POR), and not as a SLEEP reset, in the Reset Cause register (RCAUSE). Fix/Workaround None. 61 32099B-05/2010 AT32UC3L 3. Disabling POR33 may generate spurious resest Depending on operating conditions, POR33 may generate a spurious reset in one of the following cases: - When POR33 is disabled from the user interface. - When SM33 supply monitor is enabled. - When entering Shutdown mode while debugging the chip using JTAG or aWire interface. In the listed cases, writing a one to the bit VREGCR.POR33MASK in the System Control Interface (SCIF) to mask the POR33 reset will be ineffective. Fix/Workaround - Do not disable POR33 using the user interface. - Do not use the SM33 supply monitor. - Do not enter Shutdown mode if a debugger is connected to the chip. 10.1.4 SCIF 1. PCLKSR.OSC32RDY bit might not be cleared after disabling OSC32K In some cases the OSC32RDY bit in the PCLKSR register will not be cleared when OSC32K is disabled. Fix/Workaround When re-enabling the OSC32K, read the PCLKSR.OSC32RDY bit. If this bit is: 0: Follow normal procedures. 1: Ignore the PCLKSR.OSC32RDY and ISR.OSC32RDY bit. Use the Frequency Meter (FREQM) to determine if the OSC32K clock is ready. The OSC32K clock is ready when the FREQM measures a non-zero frequency. 10.1.5 AST 1. Reset may set status bits in the AST If a reset occurs and the AST is enabled, the SR.ALARM0, SR.PER0, and SR.OVF bits may be set. Fix/Workaround If the part is reset and the AST is used, clear all bits in the Status Register (SR) before entering sleep mode. 2. AST wake signal is released one AST clock cycle after the BUSY bit is cleared After writing to the Status Clear Register (SCR) the wake signal is released one AST clock cycle after the BUSY bit in the Status Register (SR.BUSY) is cleared. If entering sleep mode directly after the BUSY bit is cleared the part will wake up immediately. Fix/Workaround Read the Wake Enable Register (WER) and write this value back to the same register. Wait for BUSY to clear before entering sleep mode. 10.1.6 GPIO 1. Clearing GPIO interrupt may fail Writing a one to the GPIO.IFRC register to clear the interrupt will be ignored if interrupt is enabled for the corresponding port. Fix / Workaround Disable the interrupt, clear the interrupt by writing a one to GPIO.IFRC, then enable the interrupt. 62 32099B-05/2010 AT32UC3L 10.1.7 SPI 1. SPI disable does not work in SLAVE mode SPI disable does not work in SLAVE mode. Fix/Workaround Read the last received data, then perform a software reset by writing a one to the Software Reset bit in the Control Register (CR.SWRST). 2. SPI Bad Serial Clock Generation on 2nd chip select when SCBR==1, CPOL==1, and NCPHA==0 When multiple chip selects are in use, if one of the baudrates is equal to 1 (CSRn.SCBR==1) and one of the others is not equal to 1, and CSRn.CPOL==1 and CSRn.NCPHA==0, an additional pulse will be generated on SCK. Fix/Workaround When multiple chip selects are in use, if one of the baudrates is equal to 1, the others must also be equal to 1 if CSRn.CPOL==1 and CSRn.NCPHA==0. 3. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0 When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI module will not start a data transfer. Fix/Workaround Disable mode fault detection by writing a one to MR.MODFDIS. 4. Disabling SPI has no effect on the SR.TDRE bit Disabling SPI has no effect on SR.TDRE whereas the write data command is filtered when SPI is disabled. This means that as soon as the SPI is disabled it becomes impossible to reset the SR.TDRE bit by writing to TDR. So if the SPI is disabled during a PDCA transfer, the PDCA will continue to write data to TDR (as SR.TDRE stays high) until its buffer is empty, and all data written after the disable command is lost. Fix/Workaround Disable the PDCA, add 2 NOP (minimum), and disable the SPI. To continue the transfer, enable the SPI and the PDCA. 5. SPI mode fault detection enable causes incorrect behavior When mode fault detection is enabled (MR.MODFDIS==0), the SPI module may not operate properly. Fix/Workaround Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS. 10.1.8 TWI 1. TWIM.SR.IDLE goes high immediately when NAK is received When a NAK is received and there is a non-zero number of bytes to be transmitted, SR.IDLE goes high immediately and does not wait for the STOP condition to be sent. This does not cause any problem just by itself, but can cause a problem if software waits for SR.IDLE to go high and then immediately disables the TWIM by writing a one to CR.MDIS. Disabling the TWIM causes the TWCK and TWD pins to go high immediately, so the STOP condition will not be transmitted correctly. Fix/Workaround If possible, do not disable the TWIM. If it is absolutely necessary to disable the TWIM, there must be a software delay of at least two TWCK periods between the detection of SR.IDLE==1 and the disabling of the TWIM. 63 32099B-05/2010 AT32UC3L 10.1.9 PWMA 1. BUSY bit is never cleared after writes to the Control Register (CR) When writing a non-zero value to CR.TOP, CR.SPREAD, or CR.TCLR when the PWMA is disabled (CR.EN==0), the BUSY bit in the Status Register (SR.BUSY) will be set, but never cleared. Fix/Workaround When writing a non-zero value to CR.TOP, CR.SPREAD, or CR.TCLR, make sure the PWMA is enabled, or simultaneously enable the PWMA by writing a one to CR.EN. 2. Incoming peripheral events are discarded during duty cycle register update Incoming peripheral events to all applied channels will be discarded if a duty cycle update is received from the user interface in the same PWMA clock period. Fix/Workaround Ensure that duty cycle writes from the user interface are not performed in a PWMA clock period when an incoming peripheral event is expected. 10.1.10 CAT 1. CAT asynchronous wake will be delayed by one AST peripheral event period If the CAT detects a condition that should asynchronously wake the chip in Static mode, the asynchronous wake will not occur until the next AST event. For example, if the AST is generating peripheral events to the CAT every 50 milliseconds, and the CAT detects a touch at t=9200 milliseconds, the asynchronous wake will occur at t=9250 milliseconds. Fix/Workaround None. 10.1.11 aWire 1. aWire CPU clock speed robustness The aWire memory speed request command counter wraps at clock speeds below approximately 5kHz. Fix/Workaround None. 2. The aWire debug interface is reset after leaving Shutdown mode If the aWire debug mode is used as debug interface and the program enters Shutdown mode, the aWire interface will be reset when the device receives a wakeup either from the WAKE_N pin or the AST. Fix/Workaround None. 10.1.12 Chip 1. Increased Power Consunption in VDDIO in sleep modes If the OSC0 is enabled in crystal mode when entering a sleep mode where the OSC0 is disabled, this will lead to an increased power consumption in VDDIO. Fix/Workaround Solution 1: Disable the OSC0 bt writing a zero to the Oscillator Enable bit in the System Control Interface (SCIF) Oscillator Control Register (SCIF.OSC0CTRL.OSCEN) before going to any sleep mode where the OSC0 is disabled Solution 2: Pull down or up XIN0 and XOUT0 with 1Mohm resistor. 64 32099B-05/2010 AT32UC3L 2. In 3.3V Single Supply Mode the Analog Comparator inputs affects the device's ability to start When using the 3.3V Single Supply Mode the state of the Analog Comparator input pins can affect the device's ability to release POR reset. This is due to an interaction between the Analog Comparator input pins and the POR circuitry. The issue is not present in the 1.8V Single Supply Mode or the 3.3V Supply mode with 1.8V Regulated I/O Lines. Fix/Workaround: ACREFN (pin PA16) must be connected to GND until the POR reset is released and the Analog Comparator inputs should not be driven higher than 1.0 V until the POR reset is released. 10.2 Rev. C Not sampled. 10.3 10.3.1 Rev. B Processor and Architecture 1. Privilege violation when using interrupts in application mode with protected system stack If the system stack is protected by the MPU and an interrupt occurs in application mode, an MPU DTLB exception will occur. Fix/Workaround Make a DTLB Protection (Write) exception handler which permits the interrupt request to be handled in privileged mode. 2. Hardware breakpoints may corrupt MAC results Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC instruction. Fix/Workaround Place breakpoints on earlier or later instructions. 3. RETS behaves incorrectly when MPU is enabled RETS behaves incorrectly when MPU is enabled and MPU is configured so that system stack is not readable in unprivileged mode. Fix/Workaround Make system stack readable in unprivileged mode, or return from supervisor mode using rete instead of rets. This requires: 1. Changing the mode bits from 001 to 110 before issuing the instruction. Updating the mode bits to the desired value must be done using a single mtsr instruction so it is done atomically. Even if this step is described in general as not safe in the UC technical reference manual, it is safe in this very specific case. 2. Execute the RETE instruction. 10.3.2 FLASHCDW 1. Flash Selfprogramming may fail in one wait state mode Writes in flash and user pages may fail if executing code located in the address space mapped to the flash and if the flash controller is configured in one wait state mode (the Flash Wait State bit in the Flash Control Register (FCR.FWS) is 1). Fix/Workaround Solution 1: Configure the flash controller in zero wait state mode (FCR.FWS=0). 65 32099B-05/2010 AT32UC3L Solution 2: Configure the HMATRIX master 1 (CPU Instruction) to use the unlimited burst length transfer mode (MCFG1.ULBT=0) and the HMATRIX slave 0 (FLASHCDW) to use the maximum slot cycle limit (SCFG0.SLOT_CYCLE=255). 2. Chip Erase When performing a chip erase, the device may report that it is protected (IR=0x11) and that chiperase failed, even if the chip erase was succesful. Fix/Workaround Perform a reset before any further read and programming. 3. Fuse Programming Programming of fuses does not work. Fix/Workaround Do not program fuses. All fuses will be erased during chiperase command. 4. Wait 500ns before reading from the flash after switching read mode After switching between normal read mode and high-speed read mode, the application must wait at least 500ns before attempting any access to the flash. Fix/Workaround Solution 1: Make sure that the appropriate instructions are executed from RAM, and that a waiting-loop is executed from RAM waiting 500ns or more before executing from flash. Solution 2: Execute from flash with a clock with period longer than 500ns. This guarantees that no new read access is attempted before the flash has had time to settle in the new read mode. 5. VERSION register reads 0x100 The VERSION register reads 0x100 instead of 0x102. Fix/Workaround None. 10.3.3 HMATRIX 1. In the PRAS and PRBS registers, the MxPR fields are only two bits In the PRAS and PRBS registers MxPR fields are only two bits wide, instead of four bits. The unused bits are undefined when reading the registers. Fix/Workaround Mask undefined bits when reading PRAS and PRBS. 10.3.4 SAU 1. The SR.IDLE bit reads as zero The IDLE bit in the Status Register (SR.IDLE) reads as zero. Fix/Workaround None. 2. Open Mode is not functional The Open Mode is not functional. Fix/workaround None. 3. VERSION register reads 0x100 The VERSION register reads 0x100 instead of 0x110. Fix/Workaround None. 66 32099B-05/2010 AT32UC3L 10.3.5 PDCA 1. PCONTROL.CHxRES is nonfunctional PCONTROL.CHxRES is nonfunctional. Counters are reset at power-on, and cannot be reset by software. Fix/Workaround SW needs to keep history of performance counters. 2. Transfer error will stall a transmit peripheral handshake interface If a transfer error is encountered on a channel transmitting to a peripheral, the peripheral handshake of the active channel will stall and the PDCA will not do any more transfers on the affected peripheral handshake interface. Fix/workaround Disable and then enable the peripheral after the transfer error. 3. VERSION register reads 0x120 The VERSION register reads 0x120 instead of 0x122. Fix/Workaround None. 10.3.6 Power Manager 1. Clock sources will not be stopped in Static mode if the difference between CPU and PBx division factor is larger than 4 If the division factor between the CPU/HSB and PBx frequencies is more than 4 when entering a sleep mode where the system RC oscillator (RCSYS) is turned off, the high speed clock sources will not be turned off. This will result in a significantly higher power consumption during the sleep mode. Fix/Workaround Before going to sleep modes where RCSYS is stopped, make sure the division factor between the CPU/HSB and PBx frequencies is less than or equal to 4. 3. Disabling POR33 may generate spurious resest Depending on operating conditions, POR33 may generate a spurious reset in one of the following cases: - When POR33 is disabled from the user interface. - When SM33 supply monitor is enabled. - When entering Shutdown mode while debugging the chip using JTAG or aWire interface. In the listed cases, writing a one to the bit VREGCR.POR33MASK in the System Control Interface (SCIF) to mask the POR33 reset will be ineffective. Fix/Workaround - Do not disable POR33 using the user interface. - Do not use the SM33 supply monitor. - Do not enter Shutdown mode if a debugger is connected to the chip. 3. CONFIG register reads 0x4F The CONFIG register reads 0x4F instead of 0x43. Fix/Workaround None. 4. PB writes via debugger in sleep modes are blocked during sleepwalking During sleepwalking, PB writes performed by a debugger will be discarded by all PB modules except the module that is requesting the clock. Fix/Workaround 67 32099B-05/2010 AT32UC3L None. 5. VERSION register reads 0x400 The VERSION register reads 0x400 instead of 0x411. Fix/Workaround None. 6. WCAUSE register should not be used The WCAUSE register should not be used. Fix/Workaround None. 7. Static mode cannot be entered if the WDT is using OSC32K If the WDT is using OSC32K as clock source and the user tries to enter Static mode, the Deepstop mode will be entered instead. Fix/Workaround None. 8. It is not possible to mask the request clock requests It is not possible to mask the request clock requests using PPCR. Fix/Workaround None. 9. Clock failure detector (CFD) does not work The clock failure detector does not work. Fix/Workaround None. 10.3.7 SCIF 1. The DFLL should be slowed down before disabled The frequency of the DFLL should be set to minimum before disabled. Fix/Workaround Before disabling the DFLL the value of the COARSE register should be set to zero. 2. Writing to ICR masks new interrupts received in the same clock cycle Writing to ICR masks any new SCIF interrupt received in the same clock cycle, regardless of write value. Fix/Workaround For every interrupt except BODDET, SM33DET, and VREGOK the CLKSR register can be read to detect new interrupts. BODDET, SM33DET, and VREGOK interrupts will not be generated if they occur when writing to ICR. 3. FINE value for DFLL is not correct when dithering is disabled In open loop mode, the FINE value used by the DFLL DAC is offset by two compared to the value written to the DFLL0CONF.FINE field. I.e. the value to the DFLL DAC is DFLL0CONF.FINE-0x002. If DFLL0CONF.FINE is written to 0x000, 0x001, or 0x002 the value to the DFLL DAC will be 0x1FE, 0x1FF, or 0x000 respectively. Fix/Workaround Write the desired value added by two to the DFLL0CONF.FINE field. 4. BODVERSION register reads 0x100 The BODVERSION register reads 0x100 instead of 0x101. Fix/Workaround 68 32099B-05/2010 AT32UC3L None. 5. BRIFA is non-functional BRIFA is non-functional. Fix/Workaround None. 6. VREGCR.DEEPMODEDISABLE bit is not readable VREGCR.DEEPMODEDISABLE bit is not readable. Fix/Workaround None. 7. DFLL step size should be 7 or lower below 30 MHz If max step size is above 7, the DFLL might not lock at the correct frequency if the target frequency is below 30 MHz. Fix/Workaround If the target frequency is below 30 MHz, use max step size (DFLL0MAXSTEP.MAXSTEP) of 7 or lower. 8. Generic clock sources are kept running in sleep modes If a clock is used as a source for a generic clock when going to a sleep mode where clock sources are stopped, the source of the generic clock will be kept running. Please refer to the Power Manager chapter for details about sleep modes. Fix/Workaround Disable generic clocks before going to sleep modes where clock sources are stopped to save power. 9. DFLL clock is unstable with a fast reference clock The DFLL clock can be unstable when a fast clock is used as reference clock in closed loop mode. Fix/Workaround Use the 32 KHz crystal oscillator clock or a clock with similar frequency as DFLLIF reference clock. 10. DFLLIF indicates coarse lock too early The DFLLIF might indicate coarse lock too early, the DFLL will lose coarse lock and regain it later. Fix/Workaround Use max step size (DFLL0MAXSTEP.MAXSTEP) of 4 or higher. 11. DFLLIF dithering does not work The DFLLIF dithering does not work. Fix/Workaround None. 12. SCIF VERSION register reads 0x100 The VERSION register reads 0x100 instead of 0x102. Fix/Workaround None. 13. DFLLVERSION register reads 0x200 The DFLLVERSION register reads 0x200 instead of 0x201. Fix/Workaround None. 69 32099B-05/2010 AT32UC3L 14. RCCRVERSION register reads 0x100 The RCCRVERSION register reads 0x100 instead of 0x101. Fix/Workaround None. 15. OSC32VERSION register reads 0x100 The OSC32VERSION register reads 0x100 instead of 0x101. Fix/Workaround None. 16. VREGVERSION register reads 0x100 The VREGVERSION register reads 0x100 instead of 0x101. Fix/Workaround None. 17. RC120MVERSION register reads 0x100 The RC120MVERSION register reads 0x100 instead of 0x101. Fix/Workaround None. 18. GCLK5 is non-functional GCLK5 is non-functional. Fix/Workaround None. 19. DFLLIF might loose fine lock when dithering is disabled When dithering is disabled, and fine lock has been acquired the DFLL might loose the fine lock resulting in a up to 20% over-/undershoot. Fix/Workaround Solution 1: When the DFLL is used as main clock source the target frequency of the DFLL should be 20% below the maximum operating frequency of the CPU. Don't use the DFLL as clock source for frequency sensitive applications. Solution 2: Do not use the DFLL in closed loop mode. 20. PCLKSR.OSC32RDY bit might not be cleared after disabling OSC32K In some cases the OSC32RDY bit in the PCLKSR register will not be cleared when OSC32K is disabled. Fix/Workaround When re-enabling the OSC32K, read the PCLKSR.OSC32RDY bit. If this bit is: 0: Follow normal procedures. 1: Ignore the PCLKSR.OSC32RDY and ISR.OSC32RDY bit. Use the Frequency Meter (FREQM) to determine if the OSC32K clock is ready. The OSC32K clock is ready when the FREQM measures a non-zero frequency. 10.3.8 AST 1. AST wake signal is released one AST clock cycle after the BUSY bit is cleared After writing to the Status Clear Register (SCR) the wake signal is released one AST clock cycle after the BUSY bit in the Status Register (SR.BUSY) is cleared. If entering sleep mode directly after the BUSY bit is cleared the part will wake up immediately. Fix/Workaround Read the Wake Enable Register (WER) and write this value back to the same register. Wait for BUSY to clear before entering sleep mode. 70 32099B-05/2010 AT32UC3L 10.3.9 WDT 1. Clearing of the WDT in window mode TBAN In window mode, if the WDT is cleared 2 CLK_WDT cycles after entering the window, the counter will be cleared, but will not exit the window. If this occurs, the SR.WINDOW bit will not be cleared after clearing the WDT. Fix/Workaround Check SR.WINDOW immediately after clearing the WDT. If set then clear the WDT once more. 2. VERSION register reads 0x400 The VERSION register reads 0x400 instead of 0x402. Fix/Workaround None. 10.3.10 10.3.11 FREQM 1. Measured clock (CLK_MSR) sources 15-17 are shifted CLKSEL = 14 selects the RC120M AW clock, CLKSEL = 15 selects the RC120M clock, and CLKSEL = 16 selects the RC32K clock as source for the measured clock (CLK_MSR). Fix/Workaround None. 2. GCLK5 can not be used as source for the CLK_MSR The frequency for GCLK5 can not be measured by the FREQM. Fix/Workaround None. GPIO 1. GPIO interrupt can not be cleared when interrupts are disabled The GPIO interrupt can not be cleared unless the interrupt is enabled for the pin. Fix/Workaround Enable interrupt for the corresponding pin, then clear the interrupt. 2. VERSION register reads 0x210 The VERSION register reads 0x210 instead of 0x211. Fix/Workaround None. 10.3.12 USART 1. The RTS output does not function correctly in hardware handshaking mode The RTS signal is not generated properly when the USART receives data in hardware handshaking mode. When the Peripheral DMA receive buffer becomes full, the RTS output should go high, but it will stay low. Fix/Workaround Do not use the hardware handshaking mode of the USART. If it is necessary to drive the RTS output high when the Peripheral DMA receive buffer becomes full, use the normal mode of the USART. Configure the Peripheral DMA Controller to signal an interrupt when the receive buffer is full. In the interrupt handler code, write a one to the RTSDIS bit in the USART Control Register (CR). This will drive the RTS output high. After the next DMA transfer is started and a receive buffer is available, write a one to the RTSEN bit in the USART CR so that RTS will be driven low. 71 32099B-05/2010 AT32UC3L 10.3.13 SPI 1. SPI disable does not work in SLAVE mode SPI disable does not work in SLAVE mode. Fix/Workaround Read the last received data, then perform a software reset by writing a one to the Software Reset bit in the Control Register (CR.SWRST). 2. SPI Bad Serial Clock Generation on 2nd chip select when SCBR==1, CPOL==1, and NCPHA==0 When multiple chip selects are in use, if one of the baudrates is equal to 1 (CSRn.SCBR==1) and one of the others is not equal to 1, and CSRn.CPOL==1 and CSRn.NCPHA==0, an additional pulse will be generated on SCK. Fix/Workaround When multiple chip selects are in use, if one of the baudrates is equal to 1, the others must also be equal to 1 if CSRn.CPOL==1 and CSRn.NCPHA==0. 3. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0 When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI module will not start a data transfer. Fix/Workaround Disable mode fault detection by writing a one to MR.MODFDIS. 4. Disabling SPI has no effect on the SR.TDRE bit Disabling SPI has no effect on SR.TDRE whereas the write data command is filtered when SPI is disabled. This means that as soon as the SPI is disabled it becomes impossible to reset the SR.TDRE bit by writing to TDR. So if the SPI is disabled during a PDCA transfer, the PDCA will continue to write data to TDR (as SR.TDRE stays high) until its buffer is empty, and all data written after the disable command is lost. Fix/Workaround Disable the PDCA, add 2 NOP (minimum), and disable the SPI. To continue the transfer, enable the SPI and the PDCA. 6. SPI mode fault detection enable causes incorrect behavior When mode fault detection is enabled (MR.MODFDIS==0), the SPI module may not operate properly. Fix/Workaround Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS. 10.3.14 TWI 1. TWIM Version Register reads zero TWIM Version Register (VR) reads zero instead of 0x101. Fix/Workaround None. 2. TWIS Version Register reads zero TWIS Version Register (VR) reads zero instead of 0x112. Fix/Workaround None. 3. TWIS CR.STREN does not work in deep sleep modes When the device is in Stop, DeepStop, or Static mode, address reception will not wake the device if both CR.SOAM and CR.STREN are one. 72 32099B-05/2010 AT32UC3L Fix/Workaround Do not write both CR.STREN and CR.SOAM to one if the device needs to wake from deep sleep modes. 4. TWI pins are not SMBus compliant The TWI pins draws current when the pins are supplied with 3.3 V and the part is left unpowered. Fix/Workaround None. 5. PA21, PB04, and PB05 are not 5V tolerant Pins PA21, PB04, and PB05 are only 3.3V tolerant, not 5V tolerant. Fix/Workaround None. 6. PB04 SMBALERT function should not be used The SMBALERT function from TWIMS0 should not be selected on pin PB04. Fix/Workaround None. 7. TWIMS0.TWCK on PB05 is non-functional TWIMS0.TWCK on PB05 is non-functional. Fix/Workaround Use TWI0.TWCK on other pins. 8. TWIM STOP bit in IMR always read as zero The STOP bit in IMR always reads as zero. Fix/Workaround None. 9. TWIM.SR.IDLE goes high immediately when NAK is received When a NAK is received and there is a non-zero number of bytes to be transmitted, SR.IDLE goes high immediately and does not wait for the STOP condition to be sent. This does not cause any problem just by itself, but can cause a problem if software waits for SR.IDLE to go high and then immediately disables the TWIM by writing a one to CR.MDIS. Disabling the TWIM causes the TWCK and TWD pins to go high immediately, so the STOP condition will not be transmitted correctly. Fix/Workaround If possible, do not disable the TWIM. If it is absolutely necessary to disable the TWIM, there must be a software delay of at least two TWCK periods between the detection of SR.IDLE==1 and the disabling of the TWIM. 10. Disabled TWIM drives TWD and TWCK low When the TWIM is disabled, it drives the TWD and TWCK signals with logic level zero. This can lead to communication problems with other devices on the TWI bus. Fix/Workaround Enable the TWIM first and then enable the TWD and TWCK peripheral pins in the GPIO controller. If it is necessary to disable the TWIM, first disable the TWD and TWCK peripheral pins in the GPIO controller and then disable the TWIM. 10.3.15 PWMA 1. PARAMETER register reads 0x2424 The PARAMETER register reads 0x2424 instead of 0x24. 73 32099B-05/2010 AT32UC3L Fix/Workaround None. 2. Open drain mode does not work The open drain mode does not work. Fix/Workaround None. 3. VERSION register reads 0x100 The VERSION register reads 0x100 instead of 0x101. Fix/Workaround None. 4. Writing to the duty cycle registers when the timebase counter overflows can give an undefined result The duty cycle registers will be corrupted if written when the timebase counter overflows. If the duty cycle registers are written exactly when the timebase counter overflows at TOP, the duty cycle registers may become corrupted. Fix/Workaround Write to the duty cycle registers only directly after the Timebase Overflow bit in the status register is set. 5. BUSY bit is never cleared after writes to the Control Register (CR) When writing a non-zero value to CR.TOP, CR.SPREAD, or CR.TCLR when the PWMA is disabled (CR.EN==0), the BUSY bit in the Status Register (SR.BUSY) will be set, but never cleared. Fix/Workaround When writing a non-zero value to CR.TOP, CR.SPREAD, or CR.TCLR, make sure the PWMA is enabled, or simultaneously enable the PWMA by writing a one to CR.EN. 6. Incoming peripheral events are discarded during duty cycle register update Incoming peripheral events to all applied channels will be discarded if a duty cycle update is received from the user interface in the same PWMA clock period. Fix/Workaround Ensure that duty cycle writes from the user interface are not performed in a PWMA clock period when an incoming peripheral event is expected. 10.3.16 TC 1. When the main clock is RCSYS, TIMER_CLOCK5 is equal to CLK_PBA When the main clock is generated from RCSYS, TIMER_CLOCK5 is equal to CLK_PBA and not CLK_PBA/128. Fix/Workaround None. 10.3.17 ADCIFB 1. Pendetect in sleep modes without CLK_ADCIFB will not wake the system The pendetect will not wake the system from a sleep mode if the clock for the ADCIFB (CLK_ADCIFB) is turned off. Fix/Workaround Use a sleep mode where CLK_ADCIFB is not turned off to wake the part using pendetect. 74 32099B-05/2010 AT32UC3L 2. 8-bit mode is not working Do not use the 8-bit mode of the ADCIFB. Fix/Workaround Use the 10-bit mode and shift right by 2 bits. 3. ADC channels six to eight are non-functional ADC channels six to eight are non-functional. Fix/Workaround None. 4. VERSION register reads 0x100 The VERSION register reads 0x100 instead of 0x101. Fix/Workaround None. 10.3.18 ACIFB 1. Negative offset The static offset of the analog comparator is appriximately -50mV. Fix/Workaround None. 2. Generic clock sources in sleep modes The ACIFB should not use RC32K or CLK_1K as generic clock source if the chip uses sleep modes. Fix/Workaround None. 3. VERSION register reads 0x200 The VERSION register reads 0x200 instead of 0x212. Fix/Workaround None. 4. CONFW.WEVSRC and CONFW.WEVEN are not correctly described in the user interface CONFW.WEVSRC is only two bits instead of three bits wide. Only values 0, 1, and 2 can be written to this register. CONFW.WEVEN is in bit position 10 instead of 11. Fix/Workaround Only write values 0, 1, and 2 to CONFW.WEVSRC. When reading CONFW.WEVSRC, disregard the third bit. Read/write bit 10 to access CONFW.WEVEN. 10.3.19 CAT 1. Switch off discharge current when reaching 0V The discharge current will switch off when reaching MGCFG1.MAX, not when reaching 0V. Fix/Workaround None. 2. CAT external capacitors are not clamped to ground when CAT is idle The CAT module does not clamp the external capacitors to ground when it is idle. The capacitors are left floating, so they could accumulate small amounts of charge. Fix/workaround None. 75 32099B-05/2010 AT32UC3L 3. DISHIFT field is stuck at zero The DISHIFT field in the MGCFG1, TGACFG1, TGBCFG1, and ATCFG1 registers is stuck at zero and cannot be written to a different value. Capacitor discharge time will be determined only by the DILEN field. Fix/Workaround None. 4. MGCFG2.ACCTRL bit is stuck at zero The ACCTRL bit in the MGCFG2 register is stuck at zero and cannot be written to one. The analog comparators will be constantly enabled. Fix/Workaround None. 5. MGCFG2.CONSEN field is stuck at zero The CONSEN field in the MGCFG2 register is stuck at zero and cannot be written to a different value. The CAT consensus filter does not function properly, so termination of QMatrix data acquisition is controlled only by the MAX field in MGCFG1. Fix/Workaround None. 6. VERSION register reads 0x100 The VERSION register reads 0x100 instead of 0x200. Fix/Workaround None. 1. CAT asynchronous wake will be delayed by one AST peripheral event period If the CAT detects a condition that should asynchronously wake the chip in Static mode, the asynchronous wake will not occur until the next AST event. For example, if the AST is generating peripheral events to the CAT every 50 milliseconds, and the CAT detects a touch at t=9200 milliseconds, the asynchronous wake will occur at t=9250 milliseconds. Fix/Workaround None. 10.3.20 GLOC 1. GLOC is non-functional Glue Logic Controller (GLOC) is non-functional. Fix/Workaround None. 10.3.21 aWire 1. aWire PB mapping and PB clock mask number The aWire PB has a different PB address and PB clock mask number. Fix/Workaround Use aWire PB address 0xFFFF6C00 and PB clock (PBAMASK) 24. 2. SAB multiaccess reads are not working Reading more than one word, halfword, or byte in one command is not working correctly. Fix/Workaround Split the access into several single word, halfword, or byte accesses. 3. If a reset happens during the last SAB write, the aWire will stall 76 32099B-05/2010 AT32UC3L If a reset happens during the last word, halfword, or byte write the aWire will wait forever for an acknowledge from the SAB. Fix/Workaround Reset the aWire by keeping the RESET_N line low for 100ms. 4. aWire enable does not work in Static mode aWire enable does not work in Static mode. Fix/Workaround None. 5. VERSION register reads 0x200 The VERSION register reads 0x200 instead of 0x210. Fix/Workaround None. 6. The aWire debug interface is reset after leaving Shutdown mode If the aWire debug mode is used as debug interface and the program enters Shutdown mode, the aWire interface will be reset when the device receives a wakeup either from the WAKE_N pin or the AST. Fix/Workaround None. 10.3.22 I/O pins 1. PB10 is not 3.3V tolerant PB10 should be grounded on the PCB and left unused. Fix/Workaround None. 2. Analog multiplexing consumes extra power Current consumption on VDDIO increases when the voltage on analog inputs is close to VDDIO/2. Fix/Workaround None. 3. PA02, PB01, PB04, PB05, and RESET_N have half of the pull-up strength Pins PA02, PB01, PB04, PB05, and RESET_N have half of the specified pull-up strength. Fix/Workaround None. 4. OCD MCKO and MDO[3] are swapped in the AUX1 mapping When using the OCD AUX1 mapping of trace signals MDO[3] is located on pin PB05 and MCKO is located on PB01. Fix/Workaround Swap pins PB01 and PB05 if using OCD AUX1. 5. The JTAG is enabled at power up The JTAG function on pins PA00, PA01, PA02, and PA03, are enabled after startup. Normal I/O module functionality is not possible on these pins. Fix/Workaround Add a 10kOhm pullup on the reset line. 77 32099B-05/2010 AT32UC3L 10.3.23 Chip 1. Power consumption in static mode is too high Power consumption in static mode is too high when PA21 is high. Fix/Workaround Ensure PA21 is low. 2. Shutdown mode is not functional Do not enter Shutdown mode. Fix/Workaround None. 3. VDDIN current consumption increase above 1.8V When VDDIN increases above 1.8V, current on VDDIN increases with up to 40A. Fix/Workaround None. 1. Increased Power Consunption in VDDIO in sleep modes If the OSC0 is enabled in crystal mode when entering a sleep mode where the OSC0 is disabled, this will lead to an increased power consumption in VDDIO. Fix/Workaround Solution 1: Disable the OSC0 bt writing a zero to the Oscillator Enable bit in the System Control Interface (SCIF) Oscillator Control Register (SCIF.OSC0CTRL.OSCEN) before going to any sleep mode where the OSC0 is disabled Solution 2: Pull down or up XIN0 and XOUT0 with 1Mohm resistor. 78 32099B-05/2010 AT32UC3L 11. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 11.1 Rev. B - 05/2010 1. Package and Pinout: Added pinout figure for TLLGA48 package. 2. Package and Pinout, GPIO function multiplexing:TWIMS0-TWCK on PA20 removed. ADCIFBAD[3] on PA17 removed, number of ADC channels are 8, not 9. 3. I/O Lines Considerations: Added: Following pins have high-drive capability: PA02, PA06, PA08, PA09, and PB01. Some TWI0 pins are SMBUS compliant (PA21, PB04, PB05). 4. HMATRIX Masters: PDCA is master 4, not master 3. SAU is master 3, not master 4. 5. SAU: IDLE bit added in the Status Register. 6. PDCA: Number of PDCA performance monitors is device dependent. 7. Peripheral Event System: Chapter updated. 8. PM: Bits in RCAUSE registers removed and renamed (JTAGHARD and AWIREHARD renamed to JTAG and AWIRE respectively, JTAG and AWIRE removed. BOD33 bit removed). 9. PM: RCAUSE.BOD33 bit removed. SM33 reset will be detected as a POR reset. 10. PM: WDT can be used as wake-up source if WDT is clocked from 32KHz oscillator. 11. PM: Entering Shutdown mode description updated. 12. SCIF: DFLL output frequency is 40-150MHz, not 20-150MHz or 30-150MHz. 13. SCIF: Temperature sensor is connected to ADC channel 9, not 7. 14. SCIF: Updated the oscillator connection figure for OSC0 15. GPIO: Removed unimplemented features (pull-down, buskeeper, drive strength, slew rate, schmitt trigger, open drain). 16. SPI: RDR.PCS field removed (RDR[19:16]). 17. TWIS: Figures updated. 18. ADCIFB: The sample and hold time and the startup time formulas have been corrected (ADC Configuration Register). 19. ADCIFB: Updated ADC signal names. 20. ACIFB: CONFW.WEVSRC is bit 8-10, CONFW.EWEVEN is bit 11. CONF.EVENP and CONF.EVENN bits are swapped. 21. CAT: Matrix size is 16 by 8, not 18 by 8. 22. Electrical Characteristics: General update. 23. Mechanical Characteristics: Added numbers for package drawings. 24. Mechanical Characteristics: In the TQFP-48 package drawing the Lead Coplanarity is 0.102mm, not 0.080mm. 25. Ordering Information: Ordering code for TLLGA-48 package updated. 79 32099B-05/2010 AT32UC3L 11.2 Rev. A - 06/2009 1. Initial revision. 80 32099B-05/2010 AT32UC3L Table of Contents Features ..................................................................................................... 1 1 Description ............................................................................................... 3 2 Overview ................................................................................................... 5 3 4 5 6 7 2.1 Block Diagram ...................................................................................................5 2.2 Configuration Summary .....................................................................................6 Package and Pinout ................................................................................. 7 3.1 Package .............................................................................................................7 3.2 Peripheral Multiplexing on I/O lines ...................................................................8 3.3 Signal Descriptions ..........................................................................................13 3.4 I/O Line Considerations ...................................................................................16 Processor and Architecture .................................................................. 18 4.1 Features ..........................................................................................................18 4.2 AVR32 Architecture .........................................................................................18 4.3 The AVR32UC CPU ........................................................................................19 4.4 Programming Model ........................................................................................23 4.5 Exceptions and Interrupts ................................................................................27 Memories ................................................................................................ 32 5.1 Embedded Memories ......................................................................................32 5.2 Physical Memory Map .....................................................................................32 5.3 Peripheral Address Map ..................................................................................33 5.4 CPU Local Bus Mapping .................................................................................34 Supply and Startup Considerations ..................................................... 36 6.1 Supply Considerations .....................................................................................36 6.2 Startup Considerations ....................................................................................40 Electrical Characteristics ...................................................................... 41 7.1 Disclaimer ........................................................................................................41 7.2 Absolute Maximum Ratings* ...........................................................................41 7.3 Supply Characteristics .....................................................................................41 7.4 Maximum Clock Frequencies ..........................................................................42 7.5 Power Consumption ........................................................................................42 7.6 I/O Pad Characteristics ....................................................................................45 7.7 Oscillator Characteristics .................................................................................47 i 32099B-05/2010 AT32UC3L 8 9 7.8 Flash Characteristics .......................................................................................50 7.9 Analog Characteristics .....................................................................................50 7.10 Timing Characteristics .....................................................................................54 Mechanical Characteristics ................................................................... 55 8.1 Thermal Considerations ..................................................................................55 8.2 Package Drawings ...........................................................................................56 8.3 Soldering Profile ..............................................................................................59 Ordering Information ............................................................................. 60 10 Errata ....................................................................................................... 61 10.1 Rev. D ..............................................................................................................61 10.2 Rev. C ..............................................................................................................65 10.3 Rev. B ..............................................................................................................65 11 Datasheet Revision History .................................................................. 79 11.1 Rev. B - 05/2010 ..............................................................................................79 11.2 Rev. A - 06/2009 .............................................................................................80 Table of Contents....................................................................................... i ii 32099B-05/2010 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support avr32@atmel.com Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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