Quad IF Receiver
Data Sheet AD6657
Rev. B
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FEATURES
11-bit, 200 MSPS output data rate per channel
Integrated noise shaping requantizer (NSR)
Performance with NSR enabled
SNR: 75.5 dBFS in 40 MHz band to 70 MHz @ 185 MSPS
SNR: 73.7 dBFS in 60 MHz band to 70 MHz @ 185 MSPS
Performance with NSR disabled
SNR: 66.5 dBFS to 70 MHz @ 185 MSPS
SFDR: 83 dBc to 70 MHz @ 185 MSPS
Low power: 1.2 W @ 185 MSPS
1.8 V analog supply operation
1.8 V LVDS (ANSI-644 levels) output
1-to-8 integer clock divider
Internal ADC voltage reference
1.75 V p-p analog input range (programmable to 2.0 V p-p)
Differential analog inputs with 800 MHz bandwidth
95 dB channel isolation/crosstalk
Serial port control
User-configurable built-in self-test (BIST) capability
Energy-saving power-down modes
APPLICATIONS
Communications
Diversity radio and smart antenna (MIMO) systems
Multimode digital receivers (3G)
WCDMA, LTE, CDMA2000
WiMAX, TD-SCDMA
I/Q demodulation systems
General-purpose software radios
FUNCTIONAL BLOCK DIAGRAM
VIN+A D0±AB
D10±AB
VIN–A
PIPELINE
ADC
NOISE SHAPING
REQUANTIZER
VIN+B
VIN–B
PIPELINE
ADC
VIN+C
VIN–C
PIPELINE
ADC
VIN+D
VIN–D
PIPELINE
ADC
SERIAL PORT
REFERENCE
14 11
NOISE SHAPING
REQUANTIZER
PORT A
AD6657
PORT B
DATA MULTIPLEXER
AND LVDS DRIVERS
14 11
NOISE SHAPING
REQUANTIZER
14 11
NOISE SHAPING
REQUANTIZER
CLOCK
DIVIDER
08557-001
14 11
VCMA
VCMB
VCMC
VCMD
SCLK SDIO CSB CLK+
A
V
DD
A
GND DR
V
DD DRGND
CLK–
D0±CD
DC0±AB
DC0±CD
D10±CD
MODE
SYNC
PDWN
Figure 1.
PRODUCT HIGHLIGHTS
1. Four ADCs are contained in a small, space-saving,
10 mm × 10 mm × 1.4 mm, 144-ball CSP_BGA package.
2. Pin selectable noise shaping requantizer (NSR) function
that allows for improved SNR within a reduced bandwidth
of up to 60 MHz at 185 MSPS.
3. LVDS digital output interface configured for low cost
FPGA families.
4. 230 mW per ADC core power consumption.
5. Operation from a single 1.8 V supply.
6. Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary or twos complement), NSR, power-down,
test modes, and voltage reference mode.
7. On-chip integer 1-to-8 input clock divider and multichip
sync function to support a wide range of clocking schemes
and multichannel subsystems.
AD6657* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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EVALUATION KITS
•AD6657 Evaluation Board
DOCUMENTATION
Application Notes
•AN-1142: Techniques for High Speed ADC PCB Layout
•AN-282: Fundamentals of Sampled Data Systems
•AN-345: Grounding for Low-and-High-Frequency Circuits
•AN-501: Aperture Uncertainty and ADC System
Performance
•AN-586: LVDS Outputs for High Speed A/D Converters
•AN-737: How ADIsimADC Models an ADC
•AN-741: Little Known Characteristics of Phase Noise
•AN-742: Frequency Domain Response of Switched-
Capacitor ADCs
•AN-756: Sampled Systems and the Effects of Clock Phase
Noise and Jitter
•AN-807: Multicarrier WCDMA Feasibility
•AN-808: Multicarrier CDMA2000 Feasibility
•AN-827: A Resonant Approach to Interfacing Amplifiers to
Switched-Capacitor ADCs
•AN-835: Understanding High Speed ADC Testing and
Evaluation
•AN-851: A WiMax Double Downconversion IF Sampling
Receiver Design
•AN-878: High Speed ADC SPI Control Software
•AN-905: Visual Analog Converter Evaluation Tool Version
1.0 User Manual
•AN-935: Designing an ADC Transformer-Coupled Front
End
Data Sheet
•AD6657: Quad IF Receiver Data Sheet
User Guides
•UG-232: Evaluating the AD6642/AD6657 Analog-to-
Digital Converters
TOOLS AND SIMULATIONS
•Visual Analog
•AD6657 IBIS Model
DESIGN RESOURCES
•AD6657 Material Declaration
•PCN-PDN Information
•Quality And Reliability
•Symbols and Footprints
DISCUSSIONS
View all AD6657 EngineerZone Discussions.
SAMPLE AND BUY
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TECHNICAL SUPPORT
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number.
DOCUMENT FEEDBACK
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AD6657 Data Sheet
Rev. B | Page 2 of 32
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
General Description......................................................................... 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
AC Specifications.......................................................................... 5
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 7
Timing Specifications .................................................................. 8
Absolute Maximum Ratings............................................................ 9
Thermal Characteristics .............................................................. 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 12
Equivalent Circuits......................................................................... 15
Theory of Operation ...................................................................... 16
ADC Architecture ...................................................................... 16
Analog Input Considerations.................................................... 16
Clock Input Considerations...................................................... 18
Power Dissipation and Standby Mode .................................... 20
Channel/Chip Synchronization................................................ 20
Digital Outputs ........................................................................... 21
Timing ......................................................................................... 21
Noise Shaping Requantizer (NSR) ............................................... 22
22% BW Mode (>40 MHz @ 184.32 MSPS)........................... 22
33% BW Mode (>60 MHz @ 184.32 MSPS)........................... 22
MODE Pin................................................................................... 23
Built-In Self-Test (BIST) and Output Test .................................. 24
Built-In Self-Test (BIST)............................................................ 24
Output Test Modes..................................................................... 24
Serial Port Interface (SPI).............................................................. 25
Configuration Using the SPI..................................................... 25
Hardware Interface..................................................................... 25
Memory Map .................................................................................. 26
Reading the Memory Map Register Table............................... 26
Memory Map Register Table..................................................... 27
Memory Map Register Descriptions........................................ 29
Applications Information.............................................................. 30
Design Guidelines ...................................................................... 30
Outline Dimensions ....................................................................... 31
Ordering Guide .......................................................................... 31
REVISION HISTORY
8/11—Rev. A to Rev. B
Changes to Logic Input/Output (SDIO) Parameter Note,
Table 3 ................................................................................................ 6
Added Wake-Up Time (from Standby) Parameter, Table 4 and
Wake-Up Time (from Power Down) Parameter, Table 4............ 7
Changes to Figure 2.......................................................................... 8
Changes to Table 11........................................................................ 21
Updated Outline Dimensions....................................................... 31
7/10—Rev. 0 to Rev. A
Changes to ADC Architecture Section........................................ 16
Changes to Figure 34 and Figure 35............................................. 18
Changes to Timing Section and Data Clock Output (DCO)
Section.............................................................................................. 21
Changes to 22% BW Mode (>40 MHz @ 184.32 MSPS) Section
and 33% BW Mode (>60 MHz @ 184.32 MSPS) Section ......... 22
Changed 0x0C to 0x79, Address 0x01, Table 13......................... 27
Changed DCO Output Delay (Global) to DCO Output Delay
(Local), Address 0x17, Table 13.................................................... 28
Changes to Design Guidelines Section........................................ 30
10/09—Revision 0: Initial Version
Data Sheet AD6657
Rev. B | Page 3 of 32
GENERAL DESCRIPTION
The AD6657 is an 11-bit, 200 MSPS, quad-channel intermediate
frequency (IF) receiver specifically designed to support multi-
antenna systems in telecommunication applications where high
dynamic range performance, low power, and small size are desired.
The device consists of four high performance analog-to-digital
converters (ADCs) and noise shaping requantizer (NSR) digital
blocks. Each ADC consists of a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC features a wide bandwidth switched-capacitor sampling
network within the first stage of the differential pipeline. An
integrated voltage reference eases design considerations. A duty
cycle stabilizer (DCS) compensates for variations in the ADC
clock duty cycle, allowing the converters to maintain excellent
performance.
Each ADC output is connected internally to an NSR block. The
integrated NSR circuitry allows for improved SNR performance
in a smaller frequency band within the Nyquist bandwidth. The
device supports two different output modes selectable via the
external MODE pin or the SPI.
With the NSR feature enabled, the outputs of the ADCs are
processed such that the AD6657 supports enhanced SNR
performance within a limited portion of the Nyquist bandwidth
while maintaining an 11-bit output resolution. The NSR block
can be programmed to provide a bandwidth of either 22% or
33% of the sample clock. For example, with a sample clock rate
of 185 MSPS, the AD6657 can achieve up to 75.5 dBFS SNR for
a 40 MHz bandwidth in the 22% mode and up to 73.7 dBFS
SNR for a 60 MHz bandwidth in the 33% mode.
With the NSR block disabled, the ADC data is provided directly to
the output with a resolution of 11 bits. The AD6657 can achieve
up to 66.5 dBFS SNR for the entire Nyquist bandwidth when
operated in this mode. This allows the AD6657 to be used in
telecommunication applications such as a digital predistortion
observation path where wider bandwidths are desired.
After digital signal processing, multiplexed output data is
routed into two 11-bit output ports such that the maximum
data rate is 400 Mbps (DDR). These outputs are set at 1.8 V
LVDS and support ANSI-644 levels.
The AD6657 receiver digitizes a wide spectrum of IF frequencies.
Each receiver is designed for simultaneous reception of a separate
antenna. This IF sampling architecture greatly reduces compo-
nent cost and complexity compared with traditional analog
techniques or less integrated digital methods.
Flexible power-down options allow significant power savings.
Programming for device setup and control is accomplished
using a 3-wire SPI-compatible serial interface with numerous
modes to support board-level system testing.
The AD6657 is available in a Pb-free/RoHS compliant, 144-ball,
10 mm × 10 mm chip scale package ball grid array (CSP_BGA)
and is specified over the industrial temperature range of −40°C
to +85°C.
AD6657 Data Sheet
Rev. B | Page 4 of 32
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
otherwise noted.
Table 1.
Parameter Temperature Min Typ Max Unit
RESOLUTION Full 11 Bits
ACCURACY
No Missing Codes Full Guaranteed
Offset Error Full −4.5 2 7.4 mV
Gain Error Full ±3 ±7 % FSR
Differential Nonlinearity (DNL)1 Full ±0.1 ±0.5 LSB
Integral Nonlinearity (INL)1 Full ±0.2 ±0.5 LSB
MATCHING CHARACTERISTIC
Offset Error Full −2.4 2.5 8.3 mV
Gain Error Full ±1 ±3 % FSR
TEMPERATURE DRIFT
Offset Error Full 2 ppm/°C
Gain Error Full 40 ppm/°C
ANALOG INPUT
Input Range Full 1.4 1.75 2.0 V p-p
Input Common-Mode Voltage Full 0.9 V
Input Resistance (Differential) Full 20 kΩ
Input Capacitance2 Full 5 pF
POWER SUPPLIES
Supply Voltage
AVDD Full 1.7 1.8 1.9 V
DRVDD Full 1.7 1.8 1.9 V
Supply Current
IAVDD1 Full 510 548 mA
IDRVDD1 (1.8 V LVDS) Full 155 169 mA
POWER CONSUMPTION
Sine Wave Input1 Full 1195 1290 mW
Standby Power3 Full 130 mW
Power-Down Power Full 4.5 18 mW
1 Measured with a 10 MHz, 0 dBFS sine wave, with 100 Ω termination on each LVDS output pair.
2 Input capacitance refers to the effective capacitance between one differential input pin and AGND.
3 Standby power is measured with a dc input and the CLKx pins inactive (set to AVDD or AGND).
Data Sheet AD6657
Rev. B | Page 5 of 32
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
otherwise noted.
Table 2.
Parameter1 Temperature Min Typ Max Unit
SIGNAL-TO-NOISE-RATIO (SNR)—NSR DISABLED
fIN = 30 MHz 25°C 66.5 dBFS
fIN = 70 MHz 25°C 66.5 dBFS
fIN = 170 MHz Full 65.7 66.1 dBFS
fIN = 250 MHz 25°C 65.5 dBFS
SIGNAL-TO-NOISE-RATIO (SNR)—NSR ENABLED
22% BW Mode
fIN = 70 MHz 25°C 75.5 dBFS
fIN = 170 MHz Full 72.8 74.4 dBFS
fIN = 230 MHz 25°C 72.8 dBFS
33% BW Mode
fIN = 70 MHz 25°C 73.7 dBFS
fIN = 170 MHz Full 71.0 72.6 dBFS
fIN = 230 MHz 25°C 71.0 dBFS
SIGNAL-TO-NOISE-AND DISTORTION (SINAD)
fIN = 30 MHz 25°C 65.5 dBFS
fIN = 70 MHz 25°C 66.3 dBFS
fIN = 170 MHz Full 64.1 65.6 dBFS
fIN = 250 MHz 25°C 64.3 dBFS
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 30 MHz 25°C 10.6 Bits
fIN = 70 MHz 25°C 10.7 Bits
fIN = 170 MHz Full 10.3 10.6 Bits
fIN = 250 MHz 25°C 10.3 Bits
WORST SECOND OR THIRD HARMONIC
fIN = 30 MHz 25°C −90 dBc
fIN = 70 MHz 25°C −83 dBc
fIN = 170 MHz Full −72 −78 dBc
fIN = 250 MHz 25°C −80 dBc
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 30 MHz 25°C 90 dBc
fIN = 70 MHz 25°C 83 dBc
fIN = 170 MHz Full 72 78 dBc
fIN = 250 MHz 25°C 80 dBc
WORST OTHER HARMONIC (FOURTH THROUGH EIGHTH)
fIN = 30 MHz 25°C −100 dBc
fIN = 70 MHz 25°C −96 dBc
fIN = 170 MHz Full −82 −90 dBc
fIN = 250 MHz 25°C −95 dBc
TWO-TONE SFDR (−7 dBFS)
fIN1 = 169 MHz, fIN2 = 172 MHz 25°C 82 dBc
CROSSTALK2 Full 95 dB
ANALOG INPUT BANDWIDTH 25°C 800 MHz
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2 Crosstalk is measured at 155 MHz with −1 dBFS on one channel and no input on the alternate channel.
AD6657 Data Sheet
Rev. B | Page 6 of 32
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
otherwise noted.
Table 3.
Parameter Temperature Min Typ Max Unit
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance CMOS/LVDS/LVPECL
Internal Common-Mode Bias Full 0.9 V
Differential Input Voltage Full 0.2 3.6 V p-p
Input Voltage Range Full AGND − 0.3 AVDD + 0.2 V
High Level Input Voltage Full 1.2 2.0 V
Low Level Input Voltage Full 0 0.8 V
High Level Input Current Full −10 +10 μA
Low Level Input Current Full −10 +10 μA
Input Resistance Full 8 10 12 kΩ
Input Capacitance Full 4 pF
SYNC INPUT
Logic Compliance CMOS
Internal Bias Full 0.9 V
Input Voltage Range Full AGND AVDD V
High Level Input Voltage Full 1.2 AVDD V
Low Level Input Voltage Full AGND 0.6 V
High Level Input Current Full −100 +100 μA
Low Level Input Current Full −100 +100 μA
Input Resistance Full 12 16 20 kΩ
Input Capacitance Full 1 pF
LOGIC INPUT (CSB)1
High Level Input Voltage Full 1.22 2.1 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full −10 +10 μA
Low Level Input Current Full 40 132 μA
Input Resistance Full 26 kΩ
Input Capacitance Full 2 pF
LOGIC INPUT (SCLK)2
High Level Input Voltage Full 1.22 2.1 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full −92 −135 μA
Low Level Input Current Full −10 +10 μA
Input Resistance Full 26 kΩ
Input Capacitance Full 2 pF
LOGIC INPUT/OUTPUT (SDIO)1
High Level Input Voltage Full 1.22 2.1 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full −10 +10 μA
Low Level Input Current Full 38 128 μA
Input Resistance Full 26 kΩ
Input Capacitance Full 5 pF
Data Sheet AD6657
Rev. B | Page 7 of 32
Parameter Temperature Min Typ Max Unit
LOGIC INPUT (MODE)1
High Level Input Voltage Full 1.22 2.1 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full −10 +10 μA
Low Level Input Current Full 40 132 μA
Input Resistance Full 26 kΩ
Input Capacitance Full 2 pF
LOGIC INPUT (PDWN)2
High Level Input Voltage Full 1.22 2.1 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full −90 −134 μA
Low Level Input Current Full −10 +10 μA
Input Resistance Full 26 kΩ
Input Capacitance Full 5 pF
DIGITAL OUTPUTS (LVDS)
Differential Output Voltage (VOD) Full 247 454 mV
Output Offset Voltage (VOS) Full 1.125 1.375 V
1 Pull up.
2 Pull down.
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS dierential input, and default SPI, unless
otherwise noted.
Table 4.
Parameter Temperature Min Typ Max Unit
CLOCK INPUT PARAMETERS
Input Clock Rate Full 625 MHz
Conversion Rate1 Full 40 185 200 MSPS
CLK Pulse Width High (tCH) Full 2.7 ns
Aperture Delay (tA) Full 1.3 ns
Aperture Uncertainty (Jitter, tJ) Full 0.13 ps rms
DATA OUTPUT PARAMETERS
Data Propagation Delay (tPD) Full 3.0
4.35 5.7 ns
DCO Propagation Delay (tDCO) Full 3.2
4.55 5.9 ns
DCO to Data Skew (tSKEW) Full −0.4 −0.2 0 ns
Pipeline Delay (Latency) Full 9 Cycles
With NSR Enabled Full 12 Cycles
Wake-Up Time2 (from Standby) Full 0.5 μs
Wake-Up Time2 (from Power Down) Full 350 μs
OUT-OF-RANGE RECOVERY TIME Full 2 Cycles
1 Conversion rate is the clock rate after the divider.
2 Wake-up time is dependent on the value of the decoupling capacitors.
AD6657 Data Sheet
Rev. B | Page 8 of 32
TIMING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
otherwise noted.
Table 5.
Parameter Description Min Typ Max Unit
SYNC TIMING REQUIREMENTS See Figure 3
tSSYNC SYNC to rising edge of CLK setup time 0.24 ns
tHSYNC SYNC to rising edge of CLK hold time 0.40 ns
SPI TIMING REQUIREMENTS See Figure 2
tDS Setup time between the data and the rising edge of SCLK 2 ns
tDH Hold time between the data and the rising edge of SCLK 2 ns
tCLK Period of the SCLK 40 ns
tS Setup time between CSB and SCLK 2 ns
tH Hold time between CSB and SCLK 2 ns
tHIGH SCLK pulse width high 10 ns
tLOW SCLK pulse width low 10 ns
tEN_SDIO Time required for the SDIO pin to switch from an input to
an output relative to the SCLK falling edge
10 ns
tDIS_SDIO Time required for the SDIO pin to switch from an output to
an input relative to the SCLK rising edge
10 ns
Timing Diagrams
N – 1
N + 1 N + 2
N + 3
N + 4
N + 5
N
CLK–
CLK+
DCO+
DCO–
D10(MSB)+AB
D10(MSB)–AB
D0(LSB)+AB
D0(LSB)–AB
VIN
t
A
t
CH
t
DCO
t
CL
t
PD
t
SKEW
1/
f
S
D10A D10B D10A D10B D10A D10B D10A D10B D10A D10B D10A D10B
D0A D0B
D10A D10B
D0A D0B D0A D0B D0A D0B D0A D0B D0A D0B D0A D0B
08557-002
Figure 2. Data Output Timing (Timing for Channel C and Channel D Is Identical to Timing for Channel A and Channel B)
SYNC
CLK+
t
HSYNC
t
SSYNC
08557-003
Figure 3. SYNC Input Timing Requirements
Data Sheet AD6657
Rev. B | Page 9 of 32
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 6.
Parameter Rating
AVDD to AGND −0.3 V to +2.0 V
DRVDD to AGND −0.3 V to +2.0 V
VIN+x, VIN−x to AGND −0.3 V to AVDD + 0.2 V
CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V
SYNC to AGND −0.3 V to AVDD + 0.2 V
VCMx to AGND −0.3 V to AVDD + 0.2 V
CSB to AGND −0.3 V to DRVDD + 0.2 V
SCLK to AGND −0.3 V to DRVDD + 0.2 V
SDIO to AGND −0.3 V to DRVDD + 0.2 V
PDWN to AGND −0.3 V to DRVDD + 0.2 V
MODE to AGND −0.3 V to DRVDD + 0.2 V
Digital Outputs to AGND −0.3 V to DRVDD + 0.2 V
DCO+AB, DCO−AB, DCO+CD,
DCO−CD to AGND
−0.3 V to DRVDD + 0.2 V
Operating Temperature Range
(Ambient)
−40°C to +85°C
Maximum Junction Temperature
Under Bias
150°C
Storage Temperature Range
(Ambient)
−65°C to +150°C
The values in Table 7 are per JEDEC JESD51-7 plus JEDEC
JESD25-5 for a 2S2P test board. Typical θJA is specified for a
4-layer PCB with a solid ground plane. As shown in Table 7,
airflow improves heat dissipation, which reduces θJA. In addi-
tion, metal in direct contact with the package leads from metal
traces, through holes, ground, and power planes reduces θJA.
Table 7.
Package Type
Airflow
Velocity θJA1 θ
JC2 θ
JB3 Unit
0 m/s 26.9 8.9 6.6
1 m/s 24.2
144-Ball CSP_BGA,
10 mm × 10 mm
(BC-144-1) 2.5 m/s 23.0
°C/W
1 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
2 Per MIL-STD 883, Method 1012.1.
3 Per JEDEC JESD51-8 (still air).
The values in Table 8 are from simulations. The PCB is a JEDEC
multilayer board. Thermal performance for actual applications
requires careful inspection of the conditions in the application
to determine whether they are similar to those assumed in these
calculations.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 8.
Package Type
Airflow
Velocity ΨJB ΨJT Unit
0 m/s 14.4 0.23
1 m/s 14.0 0.50
144-Ball CSP_BGA,
10 mm × 10 mm
(BC-144-1) 2.5 m/s 13.9 0.53
°C/W
ESD CAUTION
AD6657 Data Sheet
Rev. B | Page 10 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AGND VIN+C VIN–C AGND AVDD CLK– CLK+ AVDD AGND VIN–B VIN+B AGND
123456789101112
AGND AGND VCMC AGND AVDD AVDD AVDD AVDD AGND VCMB AGND AGND
VIN+D AGND AGND CSB SDIO SCLK PDWN SYNC MODE AGND AGND VIN+A
VIN–D VCMD AGND AVDD AVDD AVDD AVDD AVDD AVDD AGND VCMA VIN–A
AGND AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AGND
AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND
DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND
DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD DRVDD
D0–CD D2–CD D4–CD D6–CD D8–CD D10–CD D0–AB D2–AB D4–AB D6–AB D8–AB D10–AB
D0+CDK D2+CD D4+CD D6+CD D8+CD D10+CD D0+AB D2+AB D4+AB D6+AB D8+AB D10+AB
D1–CD D3–CD D5–CD D7–CD D9–CD DCO–CD D1–AB D3–AB D5–AB D7–AB D9–AB DCO–AB
D1+CD
A
B
C
D
E
F
G
H
J
L
M D3+CD D5+CD D7+CD D9+CD DCO+CD D1+AB D3+AB D5+AB D7+AB D9+AB DCO+AB
0
5887-004
Figure 4. Pin Configuration (Top View)
Table 9. Pin Function Descriptions
Pin No. Mnemonic Type Description
A5, A8, B5, B6, B7, B8,
D4, D5, D6, D7, D8,
D9, E2, E3, E4, E5, E6,
E7, E8, E9, E10, E11
AVDD Supply Analog Power Supply (1.8 V Nominal)
A1, A4, A9, A12, B1,
B2, B4, B9, B11, B12,
C2, C3, C10, C11, D3,
D10, E1, E12, F1, F2,
F3, F4, F5, F6, F7, F8,
F9, F10, F11, F12
AGND Ground Analog Ground
H1, H2, H3, H4, H5,
H6, H7, H8, H9, H10,
H11, H12
DRVDD Supply Digital Output Driver Supply (1.8 V Nominal)
G1, G2, G3, G4, G5,
G6, G7, G8, G9, G10,
G11, G12
DRGND Ground Digital Output Driver Ground
A7 CLK+ Input ADC Clock Input—True
A6 CLK− Input ADC Clock Input—Complement
C12 VIN+A Input Differential Analog Input Pin (+) for Channel A
D12 VIN−A Input Differential Analog Input Pin (−) for Channel A
D11 VCMA Output Common-Mode Level Bias Output for Analog Input Channel A
A11 VIN+B Input Differential Analog Input Pin (+) for Channel B
A10 VIN−B Input Differential Analog Input Pin (−) for Channel B
B10 VCMB Output Common-Mode Level Bias Output for Analog Input Channel B
A2 VIN+C Input Differential Analog Input Pin (+) for Channel C
A3 VIN−C Input Differential Analog Input Pin (−) for Channel C
B3 VCMC Output Common-Mode Level Bias Output for Analog Input Channel C
C1 VIN+D Input Differential Analog Input Pin (+) for Channel D
D1 VIN−D Input Differential Analog Input Pin (−) for Channel D
D2 VCMD Output Common-Mode Level Bias Output for Analog Input Channel D
K7 D0+AB Output Channel A and Channel B LVDS Output Data 0—True
J7 D0−AB Output Channel A and Channel B LVDS Output Data 0—Complement
Data Sheet AD6657
Rev. B | Page 11 of 32
Pin No. Mnemonic Type Description
M7 D1+AB Output Channel A and Channel B LVDS Output Data 1—True
L7 D1−AB Output Channel A and Channel B LVDS Output Data 1—Complement
K8 D2+AB Output Channel A and Channel B LVDS Output Data 2—True
J8 D2−AB Output Channel A and Channel B LVDS Output Data 2—Complement
M8 D3+AB Output Channel A and Channel B LVDS Output Data 3—True
L8 D3−AB Output Channel A and Channel B LVDS Output Data 3—Complement
K9 D4+AB Output Channel A and Channel B LVDS Output Data 4—True
J9 D4−AB Output Channel A and Channel B LVDS Output Data 4—Complement
M9 D5+AB Output Channel A and Channel B LVDS Output Data 5—True
L9 D5−AB Output Channel A and Channel B LVDS Output Data 5—Complement
K10 D6+AB Output Channel A and Channel B LVDS Output Data 6—True
J10 D6−AB Output Channel A and Channel B LVDS Output Data 6—Complement
M10 D7+AB Output Channel A and Channel B LVDS Output Data 7—True
L10 D7−AB Output Channel A and Channel B LVDS Output Data 7—Complement
K11 D8+AB Output Channel A and Channel B LVDS Output Data 8—True
J11 D8−AB Output Channel A and Channel B LVDS Output Data 8—Complement
M11 D9+AB Output Channel A and Channel B LVDS Output Data 9—True
L11 D9−AB Output Channel A and Channel B LVDS Output Data 9—Complement
K12 D10+AB Output Channel A and Channel B LVDS Output Data 10—True
J12 D10−AB Output Channel A and Channel B LVDS Output Data 10—Complement
M12 DCO+AB Output Data Clock LVDS Output for Channel A and Channel B—True
L12 DCO−AB Output Data Clock LVDS Output for Channel A and Channel B—Complement
K1 D0+CD Output Channel C and Channel D LVDS Output Data 0—True
J1 D0−CD Output Channel C and Channel D LVDS Output Data 0—Complement
M1 D1+CD Output Channel C and Channel D LVDS Output Data 1—True
L1 D1−CD Output Channel C and Channel D LVDS Output Data 1—Complement
K2 D2+CD Output Channel C and Channel D LVDS Output Data 2—True
J2 D2−CD Output Channel C and Channel D LVDS Output Data 2—Complement
M2 D3+CD Output Channel C and Channel D LVDS Output Data 3—True
L2 D3−CD Output Channel C and Channel D LVDS Output Data 3—Complement
K3 D4+CD Output Channel C and Channel D LVDS Output Data 4—True
J3 D4−CD Output Channel C and Channel D LVDS Output Data 4—Complement
M3 D5+CD Output Channel C and Channel D LVDS Output Data 5—True
L3 D5−CD Output Channel C and Channel D LVDS Output Data 5—Complement
K4 D6+CD Output Channel C and Channel D LVDS Output Data 6—True
J4 D6−CD Output Channel C and Channel D LVDS Output Data 6—Complement
M4 D7+CD Output Channel C and Channel D LVDS Output Data 7—True
L4 D7−CD Output Channel C and Channel D LVDS Output Data 7—Complement
K5 D8+CD Output Channel C and Channel D LVDS Output Data 8—True
J5 D8−CD Output Channel C and Channel D LVDS Output Data 8—Complement
M5 D9+CD Output Channel C and Channel D LVDS Output Data 9—True
L5 D9−CD Output Channel C and Channel D LVDS Output Data 9—Complement
K6 D10+CD Output Channel C and Channel D LVDS Output Data 10—True
J6 D10−CD Output Channel C and Channel D LVDS Output Data 10—Complement
M6 DCO+CD Output Data Clock LVDS Output for Channel C and Channel D—True
L6 DCO−CD Output Data Clock LVDS Output for Channel C and Channel D—Complement
C9 MODE Input Mode Select Pin (Logic Low Enables NSR; Logic High Disables NSR)
C8 SYNC Input Digital Synchronization Pin
C7 PDWN Input Power-Down Input (Active High)
C6 SCLK Input SPI Clock
C5 SDIO Input/output SPI Data
C4 CSB Input SPI Chip Select (Active Low)
AD6657 Data Sheet
Rev. B | Page 12 of 32
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS, 32k sample, TA = 25°C, unless
otherwise noted.
0
–20
–40
–60
–80
–100
–120
100 2030405060708090
FREQUENCY (MHz)
AMPLITUDE (dBFS)
08557-005
SECOND
HARMONIC THIRD
HARMONIC
f
S
= 185MSPS
f
IN
= 30.3MHz @ –1dBFS
SNR = 65.7dB (66.7dBFS)
SFDR = 89.7dBc
Figure 5. Single-Tone FFT with fIN = 30.3 MHz
0
–20
–40
–60
–80
–100
–120
100 2030405060708090
FREQUENCY (MHz)
AMPLITUDE (dBFS)
f
S
= 185MSPS
f
IN
= 70.3MHz @ –1dBFS
SNR = 65.4dB (66.4dBFS)
SFDR = 86dBc
08557-006
SECOND
HARMONIC
THIRD
HARMONIC
Figure 6. Single-Tone FFT with fIN = 70.3 MHz
0
–20
–40
–60
–80
–100
–120
100 2030405060708090
FREQUENCY (MHz)
AMPLITUDE (dBFS)
08557-007
SECOND
HARMONIC
THIRD
HARMONIC
f
S
= 185MSPS
f
IN
= 140.1MHz @ –1dBFS
SNR = 65.3dB (66.3dBFS)
SFDR = 88dBc
Figure 7. Single-Tone FFT with fIN = 140.1 MHz
0
–20
–40
–60
–80
–100
–120
100 2030405060708090
FREQUENCY (MHz)
AMPLITUDE (dBFS)
08557-108
SECOND
HARMONIC THIRD
HARMONIC
f
S
= 185MSPS
f
IN
= 200.3MHz @ –1dBFS
SNR = 64.8dB (65.8dBFS)
SFDR = 80dBc
Figure 8. Single-Tone FFT with fIN = 200.3 MHz
0
–20
–40
–60
–80
–100
–120
100 2030405060708090
FREQUENCY (MHz)
AMPLITUDE (dBFS)
08557-109
SECOND
HARMONIC
THIRD
HARMONIC
f
S
= 185MSPS
f
IN
= 230.3MHz @ –1dBFS
SNR = 64.6dB (65.6dBFS)
SFDR = 86.1dBc
Figure 9. Single-Tone FFT with fIN = 230.3 MHz
0
–20
–40
–60
–80
–120
–100
–140
100 2030405060708090
FREQUENCY (MHz)
AMPLITUDE (dBFS)
0
8557-110
SECOND
HARMONIC
THIRD
HARMONIC
f
S
= 185MSPS
f
IN
= 140.1MHz @ –1.6dBFS
NSR 22% BW MODE, TW = 28
SNR = 73dB (74.6dBFS) (IN-BAND)
SFDR = 89.7dBc (IN-BAND)
Figure 10. Single-Tone FFT with fIN = 140.1 MHz, NSR Enabled
in 22% BW Mode with Tuning Word = 28
Data Sheet AD6657
Rev. B | Page 13 of 32
0
–20
–40
–60
–80
–120
–100
–140
100 2030405060708090
FREQUENCY (MHz)
AMPLITUDE (dBFS)
08557-111
SECOND
HARMONIC
THIRD
HARMONIC
f
S
= 185MSPS
f
IN
= 230.3MHz @ –1.6dBFS
NSR 33% BW MODE, TW = 17
SNR = 69.3dB (71dBFS) (IN-BAND)
SFDR = 85.4dBc (IN-BAND)
Figure 11. Single-Tone FFT with fIN = 230.3 MHz, NSR Enabled
in 33% BW Mode with Tuning Word = 17
0
10
20
30
40
50
60
70
80
90
100
–90
–85
–80
–75
–70
–65
–60
–55
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
SNR/SFDR (dBc AND dBFS)
INPUT AMPLITUDE (dBFS)
0
8557-112
SNR (dBc)
SFDR (dBc)
SNR (dBFS)
SFDR (dBFS)
Figure 12. Single-Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN = 70.3 MHz
60
65
70
75
80
85
90
95
60 110 160 210 260 300
SNR/SFDR (dBFS/dBc)
INPUT FREQUENCY (MHz)
SNR (dBFS)
SFDR (dBc)
08557-013
Figure 13. Single-Tone SNR/SFDR vs. Input Frequency (fIN)
with 1.75 V p-p Full Scale
60
65
70
75
80
85
90
95
60 110 160 210 260 300
SNR/SFDR (dBFS/dBc)
INPUT FREQUENCY (MHz)
SNR (dBFS)
SFDR (dBc)
08557-114
Figure 14. Single-Tone SNR/SFDR vs. Input Frequency (fIN)
with 2.0 V p-p Full Scale
50
55
60
65
70
75
80
85
90
95
30 50 70 90 110 130 150 170 190 210 230 250
SNR/SFDR (dBFS/dBc)
SAMPLE RATE (MSPS)
SFDR (dBc)
SNR (dBFS)
08557-015
Figure 15. Single-Tone SNR/SFDR vs. Sample Rate (fS)
with fIN = 70.1 MHz
0
–20
–40
–60
–80
–100
–120
100 2030405060708090
FREQUENCY (MHz)
AMPLITUDE (dBFS)
08557-016
f
S
= 185MSPS
f
IN1
= 169.1MHz @ –7dBFS
f
IN2
= 172.1MHz @ –7dBFS
SFDR = 81.8dBc
Figure 16. Two-Tone FFT with fIN1 = 169.1 MHz and fIN2 = 172.1 MHz
AD6657 Data Sheet
Rev. B | Page 14 of 32
–120
–100
–80
–60
–40
–20
0
–90 –78 –66 –54 –42 –30 –18 –6
SFDR/IMD3 (dBc AND dBFS)
INPUT AMPLITUDE (dBFS)
IMD3 (dBFS)
SFDR (dBFS)
IMD3 (dBc)
SFDR (dBc)
0
8557-017
Figure 17. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with fIN1 = 169.1 MHz and fIN2 = 172.1 MHz
0
200,000
400,000
600,000
800,000
1,000,000
1,200,000
N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3
NUMBER OF HITS
OUTPUT CODE
08557-018
Figure 18. Grounded Input Histogram
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
0 500 1000 1500 2000
INL ERROR (LSB)
OUTPUT CODE
08557-019
Figure 19. INL with fIN = 30.3 MHz
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0 500 1000 1500 2000
DNL ERROR (LSB)
OUTPUT CODE
08557-020
Figure 20. DNL with fIN = 30.3 MHz
60
61
62
63
64
65
66
67
68
69
30 35 40 45 50 55 60 65 70
SNR (dBFS)
DUTY CYCLE (%)
08557-021
Figure 21. SNR vs. Duty Cycle with fIN = 10.3 MHz
Data Sheet AD6657
Rev. B | Page 15 of 32
EQUIVALENT CIRCUITS
V
IN
AVDD
08557-008
Figure 22. Equivalent Analog Input Circuit
0.9V
15kΩ15kΩ
C
LK+ CLK–
AVDD
08557-009
AVDD AVDD
Figure 23. Equivalent Clock Input Circuit
0
8557-010
D
R
V
DD
DATAOUT+
V–
V+
DATAOUT–
V+
V–
Figure 24. Equivalent LVDS Output Circuit
AVDD AVDD
16kΩ
0.9V
0.9V
SYNC
0
8557-025
Figure 25. Equivalent SYNC Input Circuit
SCLK
OR
PDWN
350Ω
30kΩ
08557-012
Figure 26. Equivalent SCLK and PDWN Input Circuit
CSB
OR
MODE
350Ω
30kΩ
AVDD
08557-014
Figure 27. Equivalent CSB and MODE Input Circuit
SDIO 350Ω
30kΩ
DRVDD
08557-011
Figure 28. Equivalent SDIO Circuit
AD6657 Data Sheet
Rev. B | Page 16 of 32
THEORY OF OPERATION
ADC ARCHITECTURE
The AD6657 architecture consists of quad front-end sample-
and-hold circuits, followed by pipelined, switched-capacitor
ADCs. The quantized outputs from each stage are combined
into a final 14-bit result in the digital correction logic. Alter-
nately, the 14-bit result can be processed through the noise
shaping requantizer (NSR) block before it is sent to the digital
correction logic.
The pipelined architecture permits the first stage to operate on
a new input sample and the remaining stages to operate on the
preceding samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor digital-
to-analog converter (DAC) and an interstage residue amplifier
(MDAC). The residue amplifier magnifies the difference between
the reconstructed DAC output and the flash input for the next
stage in the pipeline. One bit of redundancy is used in each stage
to facilitate digital correction of flash errors. The last stage
simply consists of a flash ADC.
The input stage of each channel contains a differential sampling
circuit that can be ac- or dc-coupled in differential or single-
ended modes. The output staging block aligns the data, corrects
errors, and passes the data to the output buffers. The output
buffers are powered from a separate supply, allowing adjust-
ment of the output drive current. During power-down, the
output buffers go into a high impedance state.
The AD6657 quad IF receiver can simultaneously digitize four
channels, making it ideal for diversity reception and digital pre-
distortion (DPD) observation paths in telecommunication
systems.
Synchronization capability is provided to allow synchronized
timing between multiple channels or multiple devices.
Programming and control of the AD6657 are accomplished
using a 3-wire SPI-compatible serial interface.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD6657 is a differential switched-
capacitor circuit that has been designed for optimum
performance while processing a differential input signal.
The clock signal alternatively switches the input between sample
mode and hold mode (see Figure 29). When the input is switched
to sample mode, the signal source must be capable of charging
the sample capacitors and settling within 1/2 of a clock cycle.
A small resistor in series with each input can help reduce the
peak transient current required from the output stage of the
driving source. A shunt capacitor can be placed across the
inputs to provide dynamic charging currents. This passive
network creates a low-pass filter at the ADC input; therefore,
the precise values are dependent on the application.
In intermediate frequency (IF) undersampling applications,
any shunt capacitors should be reduced. In combination with
the driving source impedance, the shunt capacitors limit the
input bandwidth. For more information on this subject, see
Application Note AN-742, Frequency Domain Response of
Switched-Capacitor ADCs; Application Note AN-827, A Resonant
Approach to Interfacing Amplifiers to Switched-Capacitor ADCs;
and the Analog Dialogue article, “Transformer-Coupled Front-End
for Wideband A/D Converters” (see www.analog.com).
C
PAR1
C
PAR1
C
PAR2
C
PAR2
S
S
S
S
S
S
C
FB
C
FB
C
S
C
S
BIAS
BIAS
V
IN+
H
V
IN–
08557-037
Figure 29. Switched-Capacitor Input
For best dynamic performance, the source impedances driving
the VIN+ and VIN− pins should be matched.
An internal differential reference buffer creates positive and
negative reference voltages that define the input span of the ADC
core. The span of the ADC core is set by this buffer to 2 × VREF.
Input Common Mode
The analog inputs of the AD6657 are not internally dc biased.
In ac-coupled applications, the user must provide this bias
externally. An on-board common-mode voltage reference is
included in the design and is available from the VCMx pins.
Optimum performance is achieved when the common-mode
voltage of the analog input is set by the VCMx pin voltage
(typically 0.5 × AVDD). The VCMx pins must be decoupled
to ground by a 0.1 µF capacitor.
Data Sheet AD6657
Rev. B | Page 17 of 32
Differential Input Configurations
Optimum performance is achieved when driving the AD6657
in a differential input configuration. For baseband applications,
the AD8138, ADA4937-2, and ADA4938-2 differential drivers
provide excellent performance and a flexible interface to the ADC.
The output common-mode voltage of the ADA4938-2 is easily
set with the VCMx pin of the AD6657 (see Figure 30), and the
driver can be configured in a Sallen-Key filter topology to
provide band limiting of the input signal.
V
IN 76.8Ω
120Ω
0.1µF
200Ω
200Ω
90ΩAVDD
33Ω
33Ω
15Ω
15Ω
5pF
15pF
15pF
ADC
VIN–
VIN+ VCM
ADA4938-2
08557-039
Figure 30. Differential Input Configuration Using the ADA4938-2
For baseband applications where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 31. To bias the
analog input, the VCM voltage can be connected to the center
tap of the secondary winding of the transformer.
2V p-p 49.9Ω
0.1µF
R1
R1
C1 ADC
VIN+
VIN– VCM
C2
R2
R2
C2
08557-040
Figure 31. Differential Transformer-Coupled Configuration
The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few megahertz (MHz). Excessive signal power can also
cause core saturation, which leads to distortion.
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD6657. For applications in
which SNR is a key parameter, differential double balun coupling
is the recommended input configuration (see Figure 32). In this
configuration, the input is ac-coupled and the CML is provided to
each input through a 33 Ω resistor. These resistors compensate
for losses in the input baluns to provide a 50 Ω impedance to
the driver.
In the double balun and transformer configurations, the value
of the input capacitors and resistors is dependent on the input
frequency and source impedance and may need to be reduced
or removed. Table 10 lists recommended values to set the RC
network. At higher input frequencies, good performance can be
achieved by using a ferrite bead in series with a resistor and
removing the capacitors. However, these values are dependent
on the input signal and should be used only as a starting guide.
Table 10. Example RC Network
Frequency
Range
(MHz)
R1 Series
(Each) C1 Differential
R2 Series
(Each)
C2 Shunt
(Each)
0 to 100 33 Ω 5 pF 15 Ω 15 pF
100 to 200 10 Ω 5 pF 10 Ω 10 pF
100 to 300 10 Ω1 Remove 66 Ω Remove
1 In this configuration, R1 is a ferrite bead with a value of 10 Ω @ 100 MHz.
An alternative to using a transformer-coupled input at frequencies
in the second Nyquist zone is to use the AD8352 differential driver
(see Figure 33). For more information, see the AD8352 data sheet.
ADC
R1
0.1µF
0.1µF
2
V p-
p
VIN+
VIN– VCM
C1
C2
R1
R2
R2
0.1µF
S
0.1µF
C2
33Ω
33Ω
SP
A
P
08557-041
Figure 32. Differential Double Balun Input Configuration
AD8352
0Ω
0Ω
0.1µF
0.1µF
0.1µF
0.1µF
16
1
2
5
11
0.1µF
0.1µF
10
14
0.1µF
8, 13
V
CC
200Ω
200Ω
A
NALOG INPUT
A
NALOG INPUT
C
R
ADC
VIN+
VIN– VCM
R
4
3
08557-042
RG
RD
CD
Figure 33. Differential Input Configuration Using the AD8352
AD6657 Data Sheet
Rev. B | Page 18 of 32
431nH
VCM
AIN–
ADC
INTERNAL
INPUT Z
A
NALOG
INPUT XFMR 1:4 Z
ETC4-1T-7
INPUT
Z = 50Ω
3.0pF3.0kΩ
33Ω
121Ω
121Ω
33Ω
0.1µF
0.1µF0.1µF
0.1µF
0.1µF
08557-116
Figure 34. 1:4 Transformer Passive Configuration
AD8376
AD6657
1µH
1µH 1nF
1nF
VPOS
VCM
15pF
68nH
3.0kΩ║3.0pF
301Ω
165Ω
165Ω
5.1pF 3.9pF
180nH1000pF
1000pF
NOTES
1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS
WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (0603LS).
180nH
220nH
220nH
08557-115
Figure 35. Active Front-End Configuration Using the AD8376
For the popular IF band of 140 MHz, Figure 34 shows an
example of a 1:4 transformer passive configuration where a
differential inductor is used to resonate with the internal input
capacitance of the AD6657. This configuration realizes excellent
noise and distortion performance. Figure 35 shows an example
of an active front-end configuration using the AD8376 dual
VGA. This configuration is recommended when signal gain
is required.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD6657 sample clock inputs,
CLK+ and CLK−, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
(see Figure 36) and require no external bias.
1.2V
AVDD
2pF 2pF
CLK–CLK+
08557-055
Figure 36. Equivalent Clock Input Circuit
Clock Input Options
The AD6657 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter is
of the most concern (see the Jitter Considerations section).
Figure 37 and Figure 38 show two preferred methods for clock-
ing the AD6657 (at clock rates up to 625 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using either an RF balun or an RF transformer.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 625 MHz, and the RF transformer config-
uration is recommended for clock frequencies from 10 MHz to
200 MHz. The back-to-back Schottky diodes across the trans-
former/balun secondary limit clock excursions into the AD6657
to approximately 0.8 V p-p differential.
This limit helps to prevent the large voltage swings of the clock
from feeding through to other portions of the AD6657 while
preserving the fast rise and fall times of the signal that are
critical to a low jitter performance.
0.1µF
0.1µF
0.1µF0.1µF
SCHOTTKY
DIODES:
HSMS2822
CLOC
K
INPUT
50Ω100Ω
CLK–
CLK+
ADC
ADT1-1WT, 1:1Z
XFMR
08557-056
Figure 37. Transformer-Coupled Differential Clock (Up to 200 MHz)
0.1µF
0.1µF1nF
CLOCK
INPUT
1nF
50Ω
CLK–
CLK+
SCHOTTKY
DIODES:
HSMS2822
ADC
08557-057
Figure 38. Balun-Coupled Differential Clock (Up to 625 MHz)
Data Sheet AD6657
Rev. B | Page 19 of 32
If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
pins, as shown in Figure 39. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515/AD9516 clock drivers offer excellent
jitter performance.
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
240Ω240Ω
PECL DRIVER
50kΩ50kΩ
CLK–
CLK+
CLOCK
INPUT
CLOCK
INPUT
AD951x ADC
08557-058
Figure 39. Differential PECL Sample Clock (Up to 625 MHz)
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 40. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516 clock
drivers offer excellent jitter performance.
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
50kΩ50kΩ
CLK–
CLK+
ADC
CLOCK
INPUT
CLOCK
INPUT
AD951x
LVDS DRIVER
08557-059
Figure 40. Differential LVDS Sample Clock (Up to 625 MHz)
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended CMOS signal. In such applica-
tions, the CLK+ pin should be driven directly from a CMOS
gate, and the CLK− pin should be bypassed to ground with a
0.1 F capacitor in parallel with a 39 k resistor (see Figure 41).
OPTIONAL
100Ω0.1µF
0.1µF
0.1µF
39kΩ
50Ω
1
1
50Ω RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
V
CC
1kΩ
1kΩ
CLOCK
INPUT
AD951x
CMOS DRIVER
08557-060
Figure 41. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
CLK+ can be driven directly from a CMOS gate. Although
the CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages of up to 3.6 V, making the
selection of the drive logic voltage very flexible (see Figure 42).
150Ω RESISTOR IS OPTIONAL.
OPTIONAL
100Ω0.1µF
0.1µF
0.1µF
VCC
50Ω1
CLK–
CLK+
ADC
1kΩ
1kΩ
CLOCK
INPUT
AD951x
CMOS DRIVER
08557-061
Figure 42. Single-Ended 3.3 V CMOS Input Clock (Up to 200 MHz)
Input Clock Divider
The AD6657 contains an input clock divider with the ability to
divide the input clock by integer values from 1 to 8.
The AD6657 clock divider can be synchronized using the
external SYNC input. Bit 1 of Register 0x3A enables the clock
divider to be resynchronized on every SYNC signal. A valid
SYNC causes the clock divider to reset to its initial state. This
synchronization feature allows multiple parts to have their clock
dividers aligned to guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD6657 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock signal
with a nominal 50% duty cycle. This allows the user to provide a
wide range of clock input duty cycles without affecting the per-
formance of the AD6657. Noise and distortion performance are
nearly flat for a wide range of duty cycles with the DCS enabled.
Jitter in the rising edge of the input is still of paramount concern
and is not easily reduced by the internal stabilization circuit. The
duty cycle control loop does not function for clock rates less
than 40 MHz nominally. The loop has a time constant asso-
ciated with it that must be considered in applications in which
the clock rate can change dynamically. A wait time of 1.5 µs to
5 µs is required after a dynamic clock frequency increase or
decrease before the DCS loop is relocked to the input signal.
During the time period that the loop is not locked, the DCS
loop is bypassed, and internal device timing is dependent on the
duty cycle of the input clock signal.
AD6657 Data Sheet
Rev. B | Page 20 of 32
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR from the low frequency
SNR (SNRLF) at a given input frequency (fIN) due to jitter (tJRMS)
can be calculated by
SNRHF = −10log[(2π × fIN × tJRMS)2 + 10(−SNRLF/10) ]
In the equation, the rms aperture jitter represents the clock
input jitter specification. IF undersampling applications are
particularly sensitive to jitter, as illustrated in Figure 43.
80
75
70
65
60
55
50
1 10 100 1k
INPUT FREQUENCY (MHz)
SNR (dBc)
0.05ps
0.20ps
0.50ps
1.00ps
1.50ps
08557-053
Figure 43. SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal in cases
in which aperture jitter may affect the dynamic range of the
AD6657. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or another
method), it should be retimed by the original clock at the last
step. Refer to Application Note AN-501 and Application Note
AN-756 for more information about jitter performance as it
relates to ADCs (see www.analog.com).
POWER DISSIPATION AND STANDBY MODE
The power dissipated by the AD6657 is proportional to its clock
rate (see Figure 44). The digital power dissipation does not vary
significantly because it is determined primarily by the DRVDD
supply and the bias current of the LVDS drivers.
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 44 was
taken using the same operating conditions as those used in the
Typical Performance Characteristics section, with a 5 pF load
on each output driver.
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
180
190
200
CURRENT (A)
TOTAL POWER (W)
SAMPLING FREQUENCY (MSPS)
IAVDD
TOTAL POWER
IDRVDD
08557-142
Figure 44. Power and Current vs. Sampling Frequency
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the AD6657 is placed in power-down
mode. In this state, the ADC typically dissipates 4.5 mW.
During power-down, the output drivers are placed in a high
impedance state. Asserting the PDWN pin low returns the
AD6657 to its normal operating mode. Note that PDWN is
referenced to the digital output driver supply (DRVDD) and
should not exceed that supply voltage.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering
power-down mode and must be recharged when returning to
normal operation. As a result, wake-up time is related to the
time spent in power-down mode; shorter power-down cycles
result in proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map
Register Descriptions section for more details.
CHANNEL/CHIP SYNCHRONIZATION
The AD6657 has a SYNC input that offers the user flexible syn-
chronization options for synchronizing the clock divider. The
clock divider sync feature is useful for guaranteeing synchronized
sample clocks across multiple ADCs.
The SYNC input is internally synchronized to the sample clock;
however, to ensure that there is no timing uncertainty between
multiple parts, the SYNC input signal should be externally syn-
chronized to the input clock signal, meeting the setup and hold
times shown in Table 5. The SYNC input should be driven using
a single-ended CMOS-type signal.
Data Sheet AD6657
Rev. B | Page 21 of 32
DIGITAL OUTPUTS
The AD6657 output drivers are configured to interface with
LVDS outputs using a DRVDD supply voltage of 1.8 V. The
output bits are DDR LVDS as shown in Figure 2. Applications
that require the ADC to drive large capacitive loads or large
fanouts may require external buffers or latches.
As described in Application Note AN-877, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary or twos complement when using the SPI control.
TIMING
The AD6657 provides latched data with a latency of nine clock
cycles. Data outputs are available one propagation delay (tPD)
after the rising edge of the clock signal.
The length of the output data lines and the loads placed on
them should be minimized to reduce transients within the
AD6657. These transients can degrade converter dynamic
performance.
The lowest typical conversion rate of the AD6657 is 40 MSPS.
At clock rates below 40 MSPS, dynamic performance can degrade.
Data Clock Output (DCO)
The AD6657 provides a data clock output (DCO) signal intended
for capturing the data in an external register. The output data
for Channel A and Channel C is valid when DCO is high; the
output data for Channel B and Channel D is valid when DCO is
low. See Figure 2 for a graphical timing description.
Table 11. Output Data Format
Input (V) Condition (V) Offset Binary Output Mode Twos Complement Mode
VIN+ − VIN− < −VREF − 0.5 LSB 000 0000 0000 100 0000 0000
VIN+ − VIN− = −VREF 000 0000 0000 100 0000 0000
VIN+ − VIN− = 0 100 0000 0000 000 0000 0000
VIN+ − VIN− = +VREF − 1.0 LSB 111 1111 1111 011 1111 1111
VIN+ − VIN− > +VREF − 0.5 LSB 111 1111 1111 011 1111 1111
AD6657 Data Sheet
Rev. B | Page 22 of 32
NOISE SHAPING REQUANTIZER (NSR)
The AD6657 features a noise shaping requantizer (NSR) to
allow higher than 11-bit SNR to be maintained in a subset of
the Nyquist band. The harmonic performance of the receiver
is unaffected by the NSR feature. When enabled, the NSR
contributes an additional 0.6 dB of loss to the input signal, such
that a 0 dBFS input is reduced to −0.6 dBFS at the output pins.
The NSR feature can be independently controlled per channel
via the SPI or the MODE pin.
Two different bandwidth modes are provided; the mode can be
selected from the SPI port. In each of the two modes, the center
frequency of the band can be tuned such that IFs can be placed
anywhere in the Nyquist band.
22% BW MODE (>40 MHZ @ 184.32 MSPS)
The first bandwidth mode offers excellent noise performance
over 22% of the ADC sample rate (44% of the Nyquist band)
and can be centered by setting the NSR mode bits in the NSR
control register (Address 0x3C) to 000. In this mode, the useful
frequency range can be set using the 6-bit tuning word in the
NSR tuning register (Address 0x3E). There are 57 possible
tuning words (TW); each step is 0.5% of the ADC sample rate.
The following three equations describe the left band edge (f0),
the channel center (fCENTER), and the right band edge (f1),
respectively.
f0 = fADC × .005 × TW
fCENTER = f0 + 0.11 × fADC
f1 = f0 + 0.22 × fADC
Figure 45 to Figure 47 show the typical spectrum that can be
expected from the AD6657 in the 22% BW mode for three
different tuning words.
0
–20
–40
–60
–80
–100
–120 0204060
08557-044
AMPLITUDE (dBFS)
FREQUENCY (MHz)
90
10 30 50 8070
fS = 184.32MSPS
fIN = 140MHz @ –1.6dBFS
NSR 22% BW MODE, TW = 13
SNR = 73.4dB (75dBFS) (IN-BAND)
SFDR = 92.6dBc (IN-BAND)
Figure 45. 22% BW Mode, Tuning Word = 13
0204060 9010 30 50 8070
0
–20
–40
–60
–80
–100
–120
08557-045
AMPLITUDE (dBFS)
FREQUENCY (MHz)
fS = 184.32MSPS
fIN = 140MHz @ –1.6dBFS
NSR 22% BW MODE, TW = 28
SNR = 73.4dB (75dBFS) (IN-BAND)
SFDR = 93dBc (IN-BAND)
Figure 46. 22% BW Mode, Tuning Word = 28 (fS/4 Tuning)
0204060 9010 30 50 8070
0
–20
–40
–60
–80
–100
–120
08557-046
AMPLITUDE (dBFS)
FREQUENCY (MHz)
fS = 184.32MSPS
fIN = 140MHz @ –1.6dBFS
NSR 22% BW MODE, TW = 41
SNR = 73.4dB (75dBFS) (IN-BAND)
SFDR = 94dBc (IN-BAND)
Figure 47. 22% BW Mode, Tuning Word = 41
33% BW MODE (>60 MHZ @ 184.32 MSPS)
The second bandwidth mode offers excellent noise performance
over 33% of the ADC sample rate (66% of the Nyquist band)
and can be centered by setting the NSR mode bits in the NSR
control register (Address 0x3C) to 001. In this mode, the useful
frequency range can be set using the 6-bit tuning word in the
NSR tuning register (Address 0x3E). There are 34 possible
tuning words (TW); each step is 0.5% of the ADC sample rate.
The following three equations describe the left band edge (f0),
the channel center (fCENTER), and the right band edge (f1),
respectively.
f0 = fADC × .005 × TW
fCENTER = f0 + 0.165 × fADC
f1 = f0 + 0.33 × fADC
Data Sheet AD6657
Rev. B | Page 23 of 32
Figure 48 to Figure 50 show the typical spectrum that can be
expected from the AD6657 in the 33% BW mode for three
different tuning words.
0204060 9010 30 50 8070
0
–20
–40
–60
–80
–100
08557-047
AMPLITUDE (dBFS)
FREQUENCY (MHz)
fS = 184.32MSPS
fIN = 140MHz @ –1.6dBFS
NSR 33% BW MODE, TW = 5
SNR = 71dB (72.5dBFS) (IN-BAND)
SFDR = 92.5dBc (IN-BAND)
–120
Figure 48. 33% BW Mode, Tuning Word = 5
0204060 9010 30 50 8070
0
–20
–40
–60
–80
–100
–120
08557-048
AMPLITUDE (dBFS)
FREQUENCY (MHz)
fS = 184.32MSPS
fIN = 140MHz @ –1.6dBFS
NSR 33% BW MODE, TW = 17
SNR = 71.2dB (72.8dBFS) (IN-BAND)
SFDR = 93.7dBc (IN-BAND)
Figure 49. 33% BW Mode, Tuning Word = 17 (fS/4 Tuning)
0204060 9010 30 50 8070
0
–20
–40
–60
–80
–100
–120
08557-049
AMPLITUDE (dBFS)
FREQUENCY (MHz)
fS = 184.32MSPS
fIN = 140MHz @ –1.6dBFS
NSR 33% BW MODE, TW = 27
SNR = 71dB (72.5dBFS) (IN-BAND)
SFDR = 93dBc (IN-BAND)
Figure 50. 33% BW Mode, Tuning Word = 27
MODE PIN
The MODE pin input allows convenient control of the NSR
feature. A logic low enables NSR mode and a logic high sets the
receiver to straight 11-bit mode with NSR disabled. By default,
the MODE pin is pulled high internally to disable the NSR.
Each channel can be individually configured to ignore the
MODE pin state by writing to Bit 4 of the NSR control register
at Address 0x3C. Use of the NSR control register in conjunction
with the MODE pin allows for very flexible control of the NSR
feature on a per-channel basis.
AD6657 Data Sheet
Rev. B | Page 24 of 32
BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
The AD6657 includes built-in test features designed to verify
the integrity of each channel and to facilitate board-level debug-
ging. A BIST (built-in self-test) feature is included that verifies
the integrity of the digital datapath of the AD6657. Various
output test options are also provided to place predictable values
on the outputs of the AD6657.
BUILT-IN SELF-TEST (BIST)
The BIST is a thorough test of the digital portion of the selected
AD6657 signal path. When enabled, the test runs from an internal
pseudorandom noise (PN) source through the digital datapath
starting at the ADC block output. The BIST sequence runs for
512 cycles and stops. The BIST signature value for the selected
channel is written to Register 0x24 and Register 0x25.
If more than one channel is BIST-enabled, the channel that
is first according to alphabetical order is written to the BIST
signature registers. For example, if Channel B and Channel C
are BIST-enabled, the results from Channel B are written to the
BIST signature registers.
The outputs are not disconnected during this test, so the PN
sequence can be observed as it runs. The PN sequence can be
continued from its last value or reset from the beginning, based
on the value programmed in Register 0x0E, Bit 2. The BIST
signature result varies based on the channel configuration.
OUTPUT TEST MODES
The output test options are shown in Table 1 3. When an output
test mode is enabled, the analog section of the receiver is dis-
connected from the digital back-end blocks, and the test pattern
is run through the output formatting block. Some of the test
patterns are subject to output formatting. The seed value for the
PN sequence tests can be forced if the PN reset bits are used to
hold the generator in reset mode by setting Bit 4 or Bit 5 of
Register 0x0D. These tests can be performed with or without an
analog signal (if present, the analog signal is ignored), but they
require an encode clock. For more information, see Application
Note AN-877, Interfacing to High Speed ADCs via SPI.
Data Sheet AD6657
Rev. B | Page 25 of 32
SERIAL PORT INTERFACE (SPI)
The AD6657 serial port interface (SPI) allows the user to con-
figure the receiver for specific functions or operations through a
structured internal register space. The SPI provides added flexibility
and customization, depending on the application. Addresses are
accessed via the serial port and can be written to or read from
via the port. Memory is organized into bytes that can be further
divided into fields, which are documented in the Memory Map
section. For detailed operational information, see Application
Note AN-877, Interfacing to High Speed ADCs via SPI.
CONFIGURATION USING THE SPI
Three pins define the SPI of the AD6657: SCLK, SDIO, and CSB
(see Table 1 2). SCLK (a serial clock) is used to synchronize the
read and write data presented from and to the AD6657. SDIO
(serial data input/output) is a bidirectional pin that allows data
to be sent to and read from the internal memory map registers.
CSB (chip select bar) is an active low control that enables or
disables the read and write cycles.
Table 12. Serial Port Interface Pins
Pin Function
SCLK Serial clock. Serial shift clock input. SCLK is used to
synchronize serial interface reads and writes.
SDIO Serial data input/output. Bidirectional pin that serves
as an input or an output, depending on the instruction
being sent and the relative position in the timing frame.
CSB Chip select bar (active low). This control gates the read
and write cycles.
The falling edge of the CSB pin, in conjunction with the rising
edge of the SCLK pin, determines the start of the framing. An
example of the serial timing can be found in Figure 51 (for
symbol definitions, see Table 5).
CSB can be held low indefinitely, which permanently enables
the device; this is called streaming. CSB can stall high between
bytes to allow for additional external timing. When CSB is tied
high, SPI functions are placed in high impedance mode.
During an instruction phase, a 16-bit instruction is transmitted.
The first bit of the first byte in a serial data transfer frame indicates
whether a read command or a write command is issued. Data
follows the instruction phase, and its length is determined by
the W0 and W1 bits. All data is composed of 8-bit words.
The instruction phase determines whether the serial frame is a
read or write operation, allowing the serial port to be used both
to program the chip and to read the contents of the on-chip
memory. If the instruction is a read operation, the serial data
input/output (SDIO) pin changes direction from an input to an
output at the appropriate point in the serial frame.
Data can be sent in MSB first mode or in LSB first mode.
MSB first is the default mode on power-up and can be changed
via the SPI port configuration register. For more information
about this and other features, see Application Note AN-877,
Interfacing to High Speed ADCs via SPI.
HARDWARE INTERFACE
The pins described in Table 12 constitute the physical interface
between the user programming device and the serial port of the
AD6657. The SCLK pin and the CSB pin function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during the write phase and as an output
during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in Application Note AN-812, Micro-
controller-Based Serial Port Interface (SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the AD6657 is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade AD6657 performance. If the on-board SPI bus is used
for other devices, it may be necessary to provide buffers between
this bus and the AD6657 to prevent these signals from transi-
tioning at the receiver inputs during critical sampling periods.
DON’T CARE
DON’T CARE
DON’T
CARE
DON’T
CARE
SDIO
SCLK
CSB
t
S
t
DH
t
CLK
t
DS
t
H
R/W W1W0A12A11A10A9A8 A7 D5 D4 D3D2D1 D0
t
LOW
t
HIGH
08557-073
Figure 51. Serial Port Interface Timing Diagram
AD6657 Data Sheet
Rev. B | Page 26 of 32
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Each row in the memory map register table has eight bit loca-
tions (see Table 13). The memory map is roughly divided into
four sections: the chip configuration registers (Address 0x00
and Address 0x01); the channel index and transfer registers
(Address 0x05 and Address 0xFF); the ADC function registers,
including setup, control, and test (Address 0x08 to Address 0x25);
and the digital feature control registers (Address 0x3A to
Address 0x3E).
The memory map register table (see Table 13) provides the
default hexadecimal value for each hexadecimal address shown.
The column with the heading (MSB) Bit 7 is the start of the
default hexadecimal value given. Application Note AN-877,
Interfacing to High Speed ADCs via SPI, documents the functions
controlled by Register 0x00 to Register 0xFF. The remaining
registers, Register 0x3A to Register 0x3E, are documented in
the Memory Map Register Descriptions section.
Open Locations
All address and bit locations that are not included in Table 13 are
not currently supported for this device. Unused bits of a valid
address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x18). If the entire address location
is open (for example, Address 0x13), this address location
should not be written.
Default Values
After the AD6657 is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register table (see Table 13).
Logic Levels
An explanation of logic level terminology follows:
• “Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
• “Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Transfer Register Map
Address 0x08 to Address 0x3E are shadowed. Writes to these
addresses do not affect part operation until a transfer command
is issued by writing 0x01 to Address 0xFF, setting the transfer
bit. This allows these registers to be updated internally and
simultaneously when the transfer bit is set. The transfer bit is
autoclearing.
Channel-Specific Registers
Some channel setup functions, such as the NSR control func-
tion, can be programmed differently for each channel. In these
cases, channel address locations are internally duplicated for
each channel. These registers and bits are designated in Table 13
as local. Local registers and bits can be accessed by setting the
appropriate channel bits in Register 0x05.
If multiple channel bits are set, the subsequent write affects the
registers of all selected channels. In a read cycle, only a single
channel should be selected to read one of the registers. If multiple
channels are selected during a SPI read cycle, the part returns
the value for Channel A only. Registers and bits designated as
global in Table 13 affect the entire part or the channel features
for which there are no independent per-channel settings. The
settings in Register 0x05 do not affect the global registers and bits.
Data Sheet AD6657
Rev. B | Page 27 of 32
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 13 are not currently supported for this device.
Table 13. Memory Map Registers
Addr.
(Hex)
Register
Name
(MSB)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
(LSB)
Bit 0
Default
Value
(Hex) Comments
Chip Configuration Registers
0x00 SPI port
configuration
(global)
Open LSB first Soft reset 1 1 Soft reset LSB first Open 0x18 Nibbles are
mirrored so
that LSB first
or MSB first
mode is set
correctly,
regardless of
shift mode.
To control
this register,
all channel
index bits in
Register 0x05
must be set.
0x01 Chip ID
(global)
8-bit chip ID, Bits[7:0]
AD6657 = 0x79 (default)
0x79 Read only.
Channel Index and Transfer Registers
0x05 Channel
index
Enable
output
port for
Channel C
and
Channel D
Enable
output
port for
Channel
A and
Channel
B
Open Open Channel
D enable
Channel
C enable
Channel
B enable
Channel
A enable
0xCF Bits are set to
determine
which
channel
on the chip
receives the
next write
command;
applies to
local registers.
0xFF Transfer Open Open Open Open Open Open Open SW
transfer
1 = on
0 = off
(default)
0x00 Synchro-
nously
transfers
data from
the master
shift register
to the slave.
ADC Function Registers
0x08 Power modes Open Open External
power-
down pin
function
(global)
0 = full
power-
down
1 =
standby
Open Open Open Internal power-down
mode (local)
00 = normal operation
(default)
01 = full power-down
10 = standby
0x00 Determines
generic
modes
of chip
operation.
0x0B Clock divide
(global)
Open Open Clock divide phase
000 = 0 input clock cycles delayed
001 = 1 input clock cycle delayed
010 = 2 input clock cycles delayed
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
0x00
0x0C Shuffle mode
(local)
Open Open Open Open Open Open Shuffle mode enable
00 = shuffle disabled
01 = shuffle enabled
0x01 Enables or
disables
shuffle mode
AD6657 Data Sheet
Rev. B | Page 28 of 32
Addr.
(Hex)
Register
Name
(MSB)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
(LSB)
Bit 0
Default
Value
(Hex) Comments
0x0D Test mode
(local)
Open Open Reset
long PN
generator
0 = on
1 = off
(default)
Reset
short PN
generator
0 = on
1 = off
(default)
Open Output test mode
000 = off (normal operation)
001 = midscale short
010 = positive FS
011 = negative FS
100 = alternating checkerboard
101 = PN sequence long
110 = PN sequence short
111 = 1/0 word toggle
0x00 When set,
the test data
is placed on
the output
pins in place
of normal
data.
0x0E BIST enable
(local)
Open Open Open Open Open BIST reset
0 = on
1 = off
(default)
Open BIST
enable
1 = on
0 = off
(default)
0x00 When Bit 0
is set, the
built-in self-
test function
is initiated.
0x10 Offset adjust
(local)
Open Open Offset adjustment in LSBs from +127 to −128
(twos complement format)
011111 = +31 LSB
011110 = +30 LSB
011101 = +29 LSB
…
000010 = +2 LSB
000001 = +1 LSB
000000 = 0 LSB
…
111111 = −1 LSB
111110 = −2 LSB
111101 = −3 LSB
…
100001 = −31 LSB
100000 = −32 LSB
0x00 Device
offset trim.
0x14 Output mode
(local)
Open Open Open Output
enable bar
(local)
1 = off
0 = on
Open Output
invert
(local)
1 = on
0 = off
Output format (local)
00 = offset binary
01 = twos
complement
0x00 Configures
the outputs
and the
format of
the data.
0x15 Output adjust
(local)
Open Open Open Open Output port LVDS drive current
0000 = 3.72 mA
0001 = 3.5 mA (default)
0010 = 3.3 mA
0011 = 2.96 mA
0100 = 2.82 mA
0101 = 2.57 mA
0110 = 2.27 mA
0111 = 2.0 mA
1000 = 2.0 mA
0x01 Output
current
adjustments.
0x16 Clock phase
control
(local)
Invert DCO
clock
0 = off
1 = on
Open Open Open Open Open Open Open 0x00 When Bit 7
is set, clock
polarity is
reversed.
0x17 DCO output
delay
(local)
DCO delay
enable
0 = off
1 = on
Open Open Output port DCO clock delay
00000 = 100 ps additional delay on the DCO pin
00001 = 200 ps additional delay on the DCO pin
00010 = 300 ps additional delay on the DCO pin
…
11101 = 3.0 ns additional delay on the DCO pin
11110 = 3.1 ns additional delay on the DCO pin
11111 = 3.2 ns additional delay on the DCO pin
0x00 Enable DCO
delay and
set the delay
time.
0x18 VREF select
(global)
Open Open Open Internal VREF full-scale adjustment
Main reference full-scale VREF adjustment
01111: internal 2.087 V p-p
…
00001: internal 1.772 V p-p
00000: internal 1.75 V p-p
…
11111: internal 1.727 V p-p
…
10000: internal 1.383 V p-p
0x00 Select
adjustments
for VREF.
Data Sheet AD6657
Rev. B | Page 29 of 32
Addr.
(Hex)
Register
Name
(MSB)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
(LSB)
Bit 0
Default
Value
(Hex) Comments
0x24 BIST signature
LSB (local)
BIST Signature[7:0] 0x00 Read only.
0x25 BIST signature
MSB (local)
BIST Signature[15:8] 0x00 Read only.
Digital Feature Control Registers
0x3A Sync control
(global)
Open Open Open Open Open Open Clock
divider
sync
enable
0 = off
1 = on
Master
sync
enable
0 = off
1 = on
0x00 Control
register to
synchronize
the clock
divider.
0x3C NSR control
(local)
Open Open Open MODE
pin disable
0 = MODE
pin used
1 = MODE
pin dis-
abled
NSR mode
000 = 22% BW mode
001 = 33% BW mode
NSR
enable
0 = off
1 = on
(used
only if
Bit 4 = 1;
otherwise
ignored)
0x00 Noise
shaping
requantizer
(NSR)
controls.
0x3E NSR tuning
word (local)
Open Open NSR tuning word
See the Noise Shaping Requantizer (NSR) section.
Equations for the tuning word are dependent on the NSR mode.
0x1C NSR
frequency
tuning word.
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled
in Register 0x00 to Register 0xFF, see Application Note
AN-877, Interfacing to High Speed ADCs via SPI.
Sync Control (Register 0x3A)
Bits[7:2]—Reserved
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal is
enabled when Bit 1 is high and Bit 0 is high. This is continuous
sync mode.
Bit 0—Master Sync Enable
Bit 0 must be high to enable any of the sync functions. If
the sync capability is not used, this bit should remain low
to conserve power.
NSR Control (Register 0x3C)
Bits[7:5]—Reserved
Bit 4—MODE Pin Disable
Bit 4 specifies whether the selected channels will be controlled
by the MODE pin. Local registers act on the channels that are
selected by the channel index register (Address 0x05).
Bits[3:1]— NSR Mode
Bits[3:1] determine the bandwidth mode of the NSR. When
Bits[3:1] are set to 000, the NSR is configured for a 22% BW
mode that provides enhanced SNR performance over 22% of
the sample rate. When Bits[3:1] are set to 001, the NSR is con-
figured for a 33% BW mode that provides enhanced SNR
performance over 33% of the sample rate.
Bit 0—NSR Enable
The NSR is enabled when Bit 0 is high and disabled when Bit 0
is low. Bit 0 is ignored unless the MODE pin disable bit (Bit 4)
is set.
NSR Tuning Word (Register 0x3E)
Bits[7:6]—Reserved
Bits[5:0]— NSR Tuning Word
The NSR tuning word sets the band edges of the NSR band. In
22% BW mode, there are 57 possible tuning words; in 33% BW
mode, there are 34 possible tuning words. For either mode, each
step represents 0.5% of the ADC sample rate. For the equations
used to calculate the tuning word based on the BW mode of
operation, see the Noise Shaping Requantizer (NSR) section.
AD6657 Data Sheet
Rev. B | Page 30 of 32
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting the design and layout of the AD6657 in a system,
it is recommended that the designer become familiar with these
guidelines, which discuss the special circuit connections and
layout requirements needed for certain pins.
Power and Ground Recommendations
When connecting power to the AD6657, it is recommended
that two separate 1.8 V supplies be used. Use one supply for
analog (AVDD); use a separate supply for the digital outputs
(DRVDD). The AVDD and DRVDD supplies should be isolated
with separate decoupling capacitors. Several different decoupling
capacitors can be used to cover both high and low frequencies.
These capacitors should be located close to the point of entry
at the PCB level and close to the pins of the part, with minimal
trace length.
A single PCB ground plane should be sufficient when using the
AD6657. With proper decoupling and smart partitioning of the
PCB analog, digital, and clock sections, optimum performance
is easily achieved.
VCMx Pins
The VCMx pins are provided to set the common-mode level
of the analog inputs. The VCMx pins should be decoupled to
ground with a 0.1 F capacitor, as shown in Figure 31.
SPI Port
The SPI port should not be active during periods when the full
dynamic performance of the AD6657 is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade AD6657 performance. If the on-board SPI bus is used
for other devices, it may be necessary to provide buffers between
this bus and the AD6657 to prevent these signals from transi-
tioning at the receiver inputs during critical sampling periods.
Data Sheet AD6657
Rev. B | Page 31 of 32
OUTLINE DIMENSIONS
*COMPLIANT WITH JEDEC STANDARDS MO-275-EEAB-1
WITH EXCEPTION TO PACKAGE HEIGHT.
10-21-2010-B
0.80
0.60
REF
A
B
C
D
E
F
G
910 81112 7 564231
BOTTOM VIEW
8.80
BSC SQ
H
J
K
L
M
DETAIL A
TOP VIEW
DETAIL A
COPLANARITY
0.20
0.50
0.45
0.40
*1.40 MAX
BALL DIAMETER
SEATING
PLANE
10.10
10.00 SQ
9.90
A1 BALL
CORNER
A1 BALL
CORNER
0.25 MIN
0.65 MIN
Figure 52. 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-144-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD6657BBCZ −40°C to +85°C 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-144-1
AD6657BBCZRL −40°C to +85°C 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-144-1
AD6657EBZ Evaluation Board
1 Z = RoHS Compliant Part.
