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Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2002-2005, Zarlink Semiconductor Inc. All Rights Reserved.
Features
• 8,192-channel x 8,192-channel non-blocking
unidirectional switching. The Backplane and
Local inputs and outputs can be combined to
form a non-blocking switching matrix with 32
stream inputs and 32 stream outputs.
• 4,096-channel x 4,096 channel non-blocking
Backplane to Local stream switch
• 4,096-channel x 4,096 channel non-blocking
Local to Backplane stream switch
• 4,096-channel x 4,096 channel non-blocking
Backplane input to Backplane output switch
• 4,096-channel x 4,096 channel non-blocking
Local input to Local output stream switch
• Rate conversion on all data paths, Backplane to
Local, Local to Backplane, Backplane to
Backplane and Local to Local streams
• Backplane port accepts 16 ST-BUS streams with
data rates of 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s
or 16.384 Mb/s in any combination
• Local port accepts 16 ST-BUS streams with data
rates of 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s or
16.384 Mb/s, in any combination
• Per-stream channel and bit delay for Local input
streams
• Per-stream channel and bit delay for Backplane
input streams
• Per-stream advancement for Local output streams
• Per-stream advancement for Backplane output
streams
• Constant throughput delay for frame integrity
• Per-channel high impedance output control for
Local and Backplane streams
• Per-channel driven-high output control for Local
and Backplane streams
March 2005
Ordering Information
MT90871AV 196 Ball LBGA
-40C to +85C
MT90871
Flexible 8 K Digital Switch (F8KDX)
Data Sheet
Figure 1 - MT90871 Functional Block Diagram
Backplane Data Memories
(4,096 channels)
DS CS
R/
W
A14-A0
DTA
D15-D0
Test Port
Microprocessor Interface
and Internal Registers
V
SS (GND)
V
DD_CORE
TDi TDo TCK
TRST
TMS
LSTo0-15
(4,096 locations)
RESET
Local
Interface
Connection Memory
BSTi0-15
Backplane
Timing Unit
FP8i
PLL
LSTi0-15
Interface
Backplane
BSTo0-15
Local
C8i
V
DD_IO
LCST0-1
ODE
BCST0-1
C8o
C16o
FP8o
FP16o
V
DD_PLL
(4,096 locations)
Connection Memory
Backplane
Interface
Local
Local Data Memories
(4,096 channels)
BORS LORS
Local
Timing
Unit
MT90871 Data Sheet
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Zarlink Semiconductor Inc.
• High impedance-control outputs for external drivers on Backplane and Local port
• Per-channel message mode for Local and Backplane output streams
• Connection memory block programming for fast device initialization
• Automatic selection between ST-BUS and GCI-BUS operation
• Non-multiplexed Motorola microprocessor interface
• BER testing for Local and Backplane ports
• Conforms to the mandatory requirements of the IEEE-1149.1 (JTAG) standard
• Memory Built-In-Self-Test (BIST), controlled via microprocessor registers
• 1.8 V core supply voltage
• 3.3 V I/O supply voltage
• 5 V tolerant inputs, outputs and I/Os
• Per stream subrate switching at 4-bit, 2-bit, 1-bit depending on stream data rate
Applications
• Central Office Switches (Class 5)
• Mediation Switches
• Class-independent switches
• Access Concentrators
• Scalable TDM-Based Architectures
• Digital Loop Carriers
Device Overview
The MT90871 has two data ports, the Backplane and the Local port. The Backplane port has 16 input and 16
output streams operated at 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s or 16.384 Mb/s, in any combination and the
Local port has 16 input and 16 output streams operated at 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s or 16.384 Mb/s,
in any combination.
The MT90871 contains two data memory blocks (Backplane and Local) to provide the following switching path
configurations:
• Backplane-to-Local, supporting 4 K x 4 K data switching,
• Local-to-Backplane, supporting 4 K x 4 K data switching,
• Backplane-to-Backplane, supporting 4 K x 4 K data switching.
• Local-to-Local, supporting 4 K x 4 K data switching.
The device contains two connection memory blocks, one for the Backplane output and one for the Local output.
Data to be output on the serial streams may come from either of the data memories (Connection Mode) or directly
from the connection memory contents (Message Mode).
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Zarlink Semiconductor Inc.
In Connection Mode the contents of the connection memory defines, for each output stream and channel, the
source stream and channel (stored in data memory) to be switched.
In Message Mode, microprocessor data can be written to the connection memory for broadcast on the output
streams on a per channel basis. This feature is useful for transferring control and status information to external
circuits or other ST-BUS devices.
The device uses a master frame pulse (FP8i) and master clock (C8i) to define the frame boundary and timing for
both the Backplane port and the Local port. The device will automatically detect whether an ST-BUS or a GCI-BUS
style frame pulse is being used. There is a two frame delay from the time RESET is de-asserted to the
establishment of full switch functionality. During this period the frame format is determined before switching begins.
The device provides FP8o, FP16o, C8o and C16o outputs to support external devices connected to the Local port.
Subrate switching can be accomplished by over-sampling (i.e. 1-bit switching can be achieved by sampling a
2 Mbps stream at 16 Mbps). Refer to MSAN-175.
A non-multiplexed Motorola microprocessor port allows programming of the various device operation modes and
switching configurations. The microprocessor port provides access for Register read/write, Connection Memory
read/write and Data Memory read-only operations. The port has a 15-bit address bus, 16-bit data bus and 4 control
signals. The microprocessor may monitor channel data in the Backplane and Local data memories.
The mandatory requirements of the IEEE-1149.1 (JTAG) standard are fully supported via a dedicated test port.
The MT90871 is manufactured in a 15mm x 15mm body, 1.0mm ball-pitch, 196-LBGA to JEDEC standard MS-034
BAL-2 Iss. A.
MT90871 Data Sheet
Table of Contents
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1.0 Bidirectional and Unidirectional Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1 Flexible Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1.1 A. Blocking Bi-directional Configuration (Typical System Configuration). . . . . . . . . . . . . . . . . . . . . . 8
1.1.2 Unidirectional Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1.3 Blocking Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Switching Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.1 Backplane-to-Local Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.2 Local-to-Backplane Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.3 Backplane-to-Backplane Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.4 Local-to-Local Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.5 Uni-directional Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Port Data Rate Modes and Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.1 Local Port Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.1.1 Local Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.1.2 Local Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.2 Backplane Port Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.3 Backplane Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.3.1 Backplane Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Backplane Frame Pulse Input and Master Input Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 Backplane Frame Pulse Input and Local Frame Pulse Output Alignment. . . . . . . . . . . . . . . . . . . . . . . . . 13
3.0 Input and Output Offset Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Input Channel Delay Programming (Backplane and Local Input Streams) . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Input Bit Delay Programming (Backplane and Local Input Streams) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Output Advancement Programming (Backplane and Local Output Streams) . . . . . . . . . . . . . . . . . . . . . . 16
3.3.1 Local Output Advancement Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.3.2 Backplane Output Advancement Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.0 Port High Impedance Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 Local Port High Impedance Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1.1 LORS Set LOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1.2 LORS Set HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2 Backplane High Impedance Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2.1 BORS Set LOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2.2 BORS Set HIGH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.0 Data Delay through the Switching Paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.0 Connection Memory Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1 Local Connection Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.2 Backplane Connection Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.3 Connection Memory Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.3.1 Memory Block Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.0 Microprocessor Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.0 Device Power-up, Initialization and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.1 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.2 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9.0 Bit Error Rate Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10.0 Memory Built-In-Self-Test (BIST) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
11.0 JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
11.1 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11.2 TAP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11.2.1 Test Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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11.2.2 Test Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11.2.2.1 The Boundary-Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11.2.2.2 The Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11.2.2.3 The Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
11.3 Boundary Scan Description Language (BSDL) File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
12.0 Memory Address Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
12.1 Backplane Data Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
12.2 Local Data Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
12.3 Local Connection Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
12.4 Backplane Connection Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
12.5 Internal Register Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
13.0 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
13.1 Control Register (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
13.2 Block Programming Register (BPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
13.3 Bit Error Rate Test Control Register (BERCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
13.4 Local Input Channel Delay Registers (LCDR0 to LCDR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
13.4.1 Local Channel Delay Bits 7-0 (LCD7 - LCD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
13.5 Local Input Bit Delay Registers (LIDR0 to LIDR15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
13.5.1 Local Input Delay Bits 4-0 (LID4 - LID0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
13.6 Backplane Input Channel Delay Registers (BCDR0 to BCDR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13.6.1 Backplane Channel Delay Bits 8-0 (BCDn8 - BCDn0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13.7 Backplane Input Bit Delay Registers (BIDR0 to BIDR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
13.7.1 Backplane Input Delay Bits 4-0 (BID4 - BID0 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
13.8 Local Output Advancement Registers (LOAR0 to LOAR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
13.8.1 Local Output Advancement Bits 1-0 (LOA1-LOA0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
13.9 Backplane Output Advancement Registers (BOAR0 - 15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
13.9.1 Backplane Output Advancement Bits 1-0 (BOA1-BOA0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
13.10 Local Bit Error Rate (BER) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
13.10.2 Local Transmit BER Length Register (LTXBLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
13.10.3 Local Receive BER Length Register (LRXBLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
13.10.4 Local BER Start Receive Register (LBSRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
13.10.5 Local BER Count Register (LBCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
13.11 Backplane Bit Error Rate (BER) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
13.11.1 Backplane BER Start Send Register (BBSSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
13.11.2 Backplane Transmit BER Length Register (BTXBLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
13.11.3 Backplane Receive BER Length Register (BRXBLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
13.11.4 Backplane BER Start Receive Register (BBSRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
13.11.5 Backplane BER Count Register (BBCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
13.12 Local Bit Rate Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
13.12.1 Local Input Bit Rate Registers (LIBRR0-15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
13.12.2 Local Output Bit Rate Resisters (LOBRR0-15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
13.13 Backplane Bit Rate Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
13.13.1 Backplane Input Bit Rate Registers (BIBRR0-15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
13.13.2 Backplane Output Bit Rate Registers (BOBRR0-15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
13.14 Memory BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
13.15 Revision Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
MT90871 Data Sheet
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Zarlink Semiconductor Inc.
Figure 1 - MT90871 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - MT90871 LBGA Connections (196 LBGA) Pin Diagram
(as viewed through top of package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 3 - 4,096 x 4,096 Channels (16 Mb/s), Bidirectional Switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4 - 8,192 x 8,192 Channels (16 Mb/s), Unidirectional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5 - 6 K by 2 K Blocking Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6 - Local Port Timing Diagram for 2,4,8 and 16 Mb/s Stream Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7 - Backplane Port Timing Diagram for 2, 4, 8, and 16 Mb/s stream rates . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8 - Backplane and Local Frame Pulse Alignment for Data Rates of 2 Mb/s, 4 Mb/s, 8 Mb/s and 16 Mb/s. 13
Figure 9 - Backplane and Local Input Channel Delay Timing Diagram (8 Mb/s) . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 16 Mb/s. . . . . . . . . . . . . . . . . 15
Figure 11 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 8 Mb/s. . . . . . . . . . . . . . . . . . 16
Figure 12 - Backplane and Local Output Advancement Timing Diagram for Data Rate of 16 Mb/s . . . . . . . . . . . 17
Figure 13 - Local Port External High Impedance Control Bit Timing (ST-Bus Mode) . . . . . . . . . . . . . . . . . . . . . . 21
Figure 14 - Backplane Port External High Impedance Control Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 15 - Constant Switch Delay: Examples of Different Stream Rates and Routing . . . . . . . . . . . . . . . . . . . . . 26
Figure 16 - Examples of BER Transmission Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 17 - Frame Boundary Conditions, ST- BUS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 18 - Frame Boundary Conditions, GCI - BUS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 19 - Backplane and Local Clock Timing Diagram for ST-BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 20 - Backplane and Local Clock Timing for GCI-BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 21 - ST-BUS Backplane Data Timing Diagram (8 Mb/s, 4 Mb/s, 2 Mb/s) . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 22 - ST-BUS Backplane Data Timing Diagram (16 Mb/s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 23 - GCI BUS Backplane Data Timing Diagram (8 Mb/s, 4 Mb/s, 2 Mb/s) . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 24 - GCI BUS Backplane Data Timing Diagram (16 Mb/s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 25 - ST-BUS Local Timing Diagram (8 Mb/s, 4 Mb/s, 2 Mb/s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 26 - ST-BUS Local Data Timing Diagram (16 Mb/s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 27 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 28 - Output Driver Enable (ODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 29 - Motorola Non-Multiplexed Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
MT90871 Data Sheet
List of Tables
7
Zarlink Semiconductor Inc.
Table 1 - Per-stream Data-Rate Selection: Backplane and Local streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2 - LCSTo Allocation of Channel Control Bits to the Output Streams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3 - BCSTo Allocation of Channel Control Bits to the Output Streams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 4 - Local and Backplane Connection Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 5 - Local Connection Memory in Block Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 6 - Backplane Connection Memory in Block Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 7 - Address Map for Data and Connection Memory Locations (A14=1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 8 - Backplane Data Memory (BDM) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 9 - Local Data Memory (LDM) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 10 - LCM Bits for Local-to-Local and Backplane-to-Local Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 11 - BCM Bits for Local-to-Backplane and Backplane-to-Backplane Switching . . . . . . . . . . . . . . . . . . . . . . 34
Table 12 - Address Map for Register (A14 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 13 - Control Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 14 - Block Programming Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 15 - Bit Error Rate Test Control Register (BERCR) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 16 - Local Channel Delay Register (LCDRn) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 17 - Local Input Channel Delay Programming Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 18 - Local Channel Delay Register (LIDRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 19 - Local Input Bit Delay Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 20 - Backplane Channel Delay Register (BCDRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 21 - Backplane Input Channel Delay (BCD) Programming Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 22 - Backplane Input Bit Delay Register (BIDRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 23 - Backplane Input Bit Delay Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 24 - Local Output Advancement Register (LOARn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 25 - Local Output Advancement (LOAR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 26 - Backplane Output Advancement Register (BOAR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 27 - Backplane Output Advancement (BOAR) Programming Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 28 - Local BER Start Send Register (LBSSR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 29 - Local Transmit BER Length Register (LTXBLR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 30 - Local Receive BER Length Register (LRXBLR) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 31 - Local BER Start Receive Register (LBSRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 32 - Local BER Count Register (LBCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 33 - Backplane BER Start Send Register (BBSSR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 34 - Backplane Transmit BER Length (BTXBLR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 35 - Backplane Receive BER Length (BRXBLR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 36 - Backplane BER Start Receive Register (BBSRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 37 - Backplane BER Count Register (BBCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 38 - Local Input Bit Rate Register (LIBRRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 39 - Local Input Bit Rate (LIBR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 40 - Local Output Bit Rate Register (LOBRRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 41 - Output BitRate (LOBR) Programming Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 42 - Backplane Input Bit Rate Register (BIBRRn) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 43 - Backplane Input Bit Rate (BIBR) Programming Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 44 - Backplane Output Bit Rate Register (BOBRRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 45 - Backplane Output Bit Rate (BOBRR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 46 - Memory BIST Register (MBISTR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 47 - Revision Control Register (RCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
MT90871 Data Sheet
1
Zarlink Semiconductor Inc.
Changes Summary
The following table captures the changes from the December 2002 issue.
Page Item Change
5 Pin Description Table, C8i
The internal frame boundary alignment description
is changed from the clock rising or falling edge to
rising edge only. Also added description to specify
setting the C8IPOL bit in the Control Register to
one for clock rising edge alignment operation.
11 Figure 6, Local Port Timing Diagram for
2,4,8 and 16 Mb/s Stream Rates
Changed C8i frame boundary active edge from
falling to rising edge.
12 Figure 7, Backplane Port Timing Diagram
for 2, 4, 8, and 16 Mb/s stream rates
Changed C8i frame boundary active edge from
falling to rising edge.
13 Section 2.3. Backplane Frame Pulse Input
and Master Input Clock Timing
Removed the falling clock edge frame boundary
alignment option.
13
Figure 8, Backplane and Local Frame
Pulse Alignment for Data Rates of 2 Mb/s,
4 Mb/s, 8 Mb/s and 16 Mb/s
Changed C8i frame boundary active edge from
falling to rising edge.
14 Figure 9, Backplane and Local Input
Channel Delay Timing Diagram (8 Mb/s)
Changed FPo and C8o to FPi and C8i
respectively and showing rising C8i frame
boundary active edge.
15
Figure 10, Backplane and Local Input Bit
Delay Timing Diagram for Data Rate of
16 Mb/s
Changed FPo and C8o to FPi and C8i
respectively and showing rising C8i frame
boundary active edge.
35 Section 13.1. Control Register (CR) Bit 6,
C8IPOL
Changed description to specify Bit 6, C8IPOL
must be set high for rising clock edge frame
boundary alignment operation.
16
Figure 11, Backplane and Local Input Bit
Delay Timing Diagram for Data Rate of
8Mb/s
Changed FPo and C8o to FPi and C8i
respectively.
37 Figure 17, Frame Boundary Conditions,
ST- BUS Operation
Removed waveforms showing C8i falling edge
frame boundary option.
37 Figure 18, Frame Boundary Conditions,
GCI - BUS Operation
Removed waveforms showing C8i falling edge
frame boundary option.
56
Backplane and Local Clock Timing:
Item 2, Backplane Frame Pulse Setup
Time before C8i clock falling edge
Item 3, Backplane Frame Pulse Hold Time
from C8i clock falling edge
Item 2, Backplane Frame Pulse Setup Time
before C8i clock falling edge changed to
Backplane Frame Pulse Setup Time before C8i
clock rising edge.
Item 3, Backplane Frame Pulse Hold Time from
C8i clock falling edge changed to Backplane
Frame Pulse Hold Time from C8i clock rising
edge.
MT90871 Data Sheet
2
Zarlink Semiconductor Inc.
57 Figure 19, Backplane and Local Clock
Timing Diagram for ST-BUS Changed C8i frame boundary active edge from
falling to rising edge.
59 Figure 21, ST-BUS Backplane Data
Timing Diagram (8 Mb/s, 4 Mb/s, 2 Mb/s) Changed C8i frame boundary active edge from
falling to rising edge.
60 Figure 22, ST-BUS Backplane Data
Timing Diagram (16 Mb/s) Changed C8i frame boundary active edge from
falling to rising edge.
63 Figure 25, ST-BUS Local Timing Diagram
(8 Mb/s, 4 Mb/s, 2 Mb/s) Changed C8i frame boundary active edge from
falling to rising edge.
63 Figure 26, ST-BUS Local Data Timing
Diagram (16 Mb/s) Changed C8i frame boundary active edge from
falling to rising edge.
Page Item Change
MT90871 Data Sheet
3
Zarlink Semiconductor Inc.
Figure 2 - MT90871 LBGA Connections (196 LBGA) Pin Diagram
(as viewed through top of package)
A1 corner identified by metallized marking, mold indent, ink dot or right-angled corner
1234567891011121314
B
C
D
E
F
G
H
J
K
L
M
N
A
P
GND GND GND GND
GND GND GND GND
GND GND GND GND
GND GND GND GND
VDD_IO VDD_IO VDD_IO VDD_IO
VDD_CORE VDD_CORE VDD_CORE VDD_CORE
GND
GND
GND
GND
GND
GND
GND
GND
GND GND GND
VDD_IO VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE VDD_CORE VDD_CORE VDD_CORE
VDD_CORE
VDD_CORE
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO VDD_IO VDD_IO VDD_IO
LSTi13
LSTi14
LSTi13
LSTi10
LSTi15
LSTi11 LSTi12
LSTi7
LSTi8
LSTi7
LSTi9
LSTi3
LSTi4
LSTi5
LSTi6
LSTi1
LSTi0
LSTi2
LORS
LSTo15
LSTo14
LSTo11 LSTo10
LSTo13LSTo12
LSTo8
LSTo9
LSTo7 LSTo5
LSTo6LSTo4
D15 D14
D13
D12
D10
D9
D11
D8
D7
D6
D5
D4
D3
D2 D1
IC
D0
IC
IC
IC
NC C8i
VDD_PLL
NC
C16o
C8o
FP16o
FP8o
FP8i
BSTo6 BSTo10
BSTo12 BSTo13BSTo11
BSTo9 BSTo15BSTo14
BORSBSTi0
BSTi1 BSTi2 BSTi3
BSTi4 BSTi5
BSTi6
BSTi7
BSTi8
BSTi9
BSTi10
BSTi11
BSTi12
BSTi15
BSTi13
BSTi14
LSTo2
LSTo3IC IC LCSTo0
LSTo1LSTo0LCSTo1
BCSTo1
BCSTo0 TRST
TCK
TDo
TDi
DTA
TMS
RESET
ODE
CS
R/W
DS
A14
A13A12
A11
A10
A9A8
A7
A6
A5
A2
A4
A3
BSTo2BSTo1
A1
BSTo4
BSTo0BSTo5
BSTo3BSTo8
A0
BSTo7IC
IC
MT90871 Data Sheet
4
Zarlink Semiconductor Inc.
Pin Description Table
Name Package
Coordinates Description
VDD_IO D6, D7, D8, D10,
E4, E11,F4, F11,
G4, G11, H4, H11,
J4, J11, K4, K11,
L5, L6, L7, L8, L9,
L10
Power Supply for Periphery Circuits: +3.3 V
VDD_CORE E6, E7, E8, E9,
F5, F10, G3, G5,
G10, H5, H10, H12,
J5, J10, K6, K7, K8,
K9
Power Supply for Core Logic Circuits: +1.8 V
VDD_PLL N9
Power Supply for Analog PLL: +1.8 V
VSS (GND) D4, D11, E5, E10,
F6, F7, F8, F9,
G6, G7, G8, G9,
H6, H7, H8, H9,
J6, J7, J8, J9
K5, K10, L4, L11,
P1, P13, P14
Ground
BSTi0 - 15 G1, H1, H2, H3,
J1, J2, K1, J3,
L1, K2, M1, L2,
N1, K3, L3, M2
Backplane Serial Input Streams 0 to 7 (5 V Tolerant, Internal pull-
down). These pins accept serial TDM data streams at a data-rate of:
• 16.384 Mb/s (with 256 channels per stream),
• 8.192 Mb/s (with 128 channels per stream),
• 4.096 Mb/s (with 64 channels per stream), or
• 2.048 Mb/s (with 32 channels per stream).
The data-rate is independently programmable for each input stream.
BSTo0 - 15 B3, A1, A2, C4,
C5, B2, D2, C2,
C3, F1, D3, E2,
E1, E3, F2, F3
Backplane Serial Output Streams 0 to 7 (5 V Tolerant, Three-state
Outputs). These pins output serial TDM data streams at a data-rate of:
• 16.384 Mb/s (with 256 channels per stream),
• 8.192 Mb/s (with 128 channels per stream),
• 4.096 Mb/s (with 64 channels per stream), or
• 2.048 Mb/s (with 32 channels per stream).
The data-rate is independently programmable for each output stream.
Refer to descriptions of the BORS and ODE pins for control of the output
High or High-Impedance state.
BCSTo0-1 A13, C10 Backplane Output Channel High Impedance Control (5 V Tolerant
Three-state Outputs). Active high output enable which may be used to
control external buffering of Backplane output streams on a per channel
basis.
BCSTo0 is the output enable for BSTo[0, 2, 4, 6, 8, 10, 12, 14],
BCSTo1 is the output enable for BSTo[1, 3, 5, 7, 9, 11, 13, 15].
Refer to descriptions of the BORS and ODE pins for control of the output
High or High-Impedance state.
MT90871 Data Sheet
5
Zarlink Semiconductor Inc.
FP8i M10 Frame Pulse Input (5 V Tolerant). This pin accepts the Frame Pulse
signal. The pulse width may be active for 122 ns or 244 ns at the frame
boundary and the Frame Pulse Width bit (FPW) of the Control Register
must be set Low (default) for a 122 ns and set High for a the 244 ns pulse
condition.
The device will automatically detect whether an ST-BUS or GCI-BUS style
frame pulse is applied.
C8i P10 Master Clock Input (5 V Tolerant). This pin accepts a 8.192 MHz clock.
The internal Frame Boundary is aligned with the rising edge of this clock.
This rising edge frame boundary alignment is controlled by the C8IPOL bit
in the Control Register as shown in Table 13 on page 35. The C8IPOL bit
MUST be set to ONE for the rising edge frame boundary to be detected
correctly. Falling C8i edge frame boundary alignment is not supported and
should not be used.
CS A10 Chip Select (5 V Tolerant). Active low input used by the microprocessor
to enable the microprocessor port access. This input is internally set LOW
during a device RESET.
DS C8 Data Strobe (5 V Tolerant). This active low input is used in conjunction
with CS to enable the microprocessor port read and write operations.
R/W A9 Read/Write (5 V Tolerant). This input controls the direction of the data bus
lines (D0-D15) during a microprocessor access.
A0 - A14 B1, B4, B5, D5, A3,
A4, C6, B6, A5, A6,
C7, B7, A7, A8, B8
Address 0 - 14 (5 V Tolerant). These pins form the 15-bit address bus to
the internal memories and registers. (Address A0 = LSB).
D0 - D15 N7, P7, P6, N6, P5,
M6, P4, N5, P3, P2,
N3, N4, M5, N2,
M4, M3
Data Bus 0 - 15 (5 V Tolerant). These pins form the 16-bit data bus of the
microprocessor port. (Data D0 = LSB).
DTA D9 Data Transfer Acknowledgment (5 V Tolerant). This active low output
indicates that a data bus transfer is complete. A pull-up resistor is required
to hold a HIGH level. (Max. IOL = 10 mA).
TMS A11
Test Mode Select (5 V Tolerant with internal pull-up).
JTAG signal that
controls the state transitions of the TAP controller.
TCK B11
Test Clock (5 V Tolerant).
Provides the clock to the JTAG test logic.
TDi B10
Test Serial Data In (5 V Tolerant with internal pull-up).
JTAG serial test
instructions and data are shifted in on this pin.
TDo A12
Test Serial Data Out (5 V Tolerant Three-state Output).
JTAG serial data
is output on this pin on the falling edge of TCK. This pin is held in high
impedance state when JTAG is not enabled.
TRST A14
Test Reset (5 V Tolerant with internal pull-up)
Asynchronously initializes
the JTAG TAP controller to the Test-Logic-Reset state. To be pulsed low
during power-up for JTAG testing. This pin must be held LOW for normal
functional operation of the device.
RESET C9 Device Reset (5 V Tolerant with internal pull-up). This input (active
LOW) asynchronously applies reset and synchronously releases reset to
the device. In the reset state, the outputs LSTo0 - 15 and BSTo0 - 15 are
set to a high or high impedance depending on the state of the LORS and
BORS external control pins, respectively. It clears the device registers and
internal counters. This pin must stay low for more than 2 cycles of input
clock C8i for the reset to be invoked.
Pin Description Table (continued)
Name Package
Coordinates Description
MT90871 Data Sheet
6
Zarlink Semiconductor Inc.
LSTi0-15 K14, J13, J14, K13,
M14, J12, L14,
M13, L13, N14,
M12, N12, N13,
M11, L12, K12
Local Serial Input Streams 0 to 15 (5 V Tolerant with internal pull-
down). These pins accept serial TDM data streams at a data-rate of:
• 16.384 Mb/s (with 256 channels per stream),
• 8.192 Mb/s (with 128 channels per stream),
• 4.096 Mb/s (with 64 channels per stream), or
• 2.048 Mb/s (with 32 channels per stream).
The data-rate is independently programmable for each input stream.
C16o M9 C16o Output Clock (Three-state Output). A 16.384 MHz clock output.
The clock falling edge or rising edge is aligned with the Local
frame boundary, and is determined by the COPOL bit of the Control
Register.
C8o N10 C8o Output Clock (Three-state Output). A 8.192 MHz clock output. The
clock falling edge or rising edge is aligned with the Local frame boundary,
and is determined by the COPOL bit of the Control Register.
FP16o P12 Frame Pulse Output (Three-state Output). Frame pulse output is active
for 61ns at the frame boundary. The frame pulse, running at a 8 KHz rate,
will be the same format (ST-BUS or GCI-BUS) as the input frame pulse
(FP8i).
FP8o N11 Frame Pulse Output (Three-state Output). Frame pulse output is active
for 122 ns at the frame boundary. The frame pulse, running at 8 KHz rate,
will be the same style (ST-BUS or GCI-BUS) as the input frame pulse
(FP8i).
LSTo0 - 15 B13, B14, D14,
C14, D12, E14,
D13, E13, E12,
F14, G14, G12,
F12, F13, H14,
G13
Local Serial Output Streams 0 to 15 (5 V Tolerant Three-state
Outputs). These pins output serial TDM data streams at a data-rate of:
• 16.384 Mb/s (with 256 channels per stream),
• 8.192 Mb/s (with 128 channels per stream),
• 4.096 Mb/s (with 64 channels per stream), or
• 2.048 Mb/s (with 32 channels per stream).
The data-rate is independently programmable for each output stream.
Refer to descriptions of the LORS and ODE pins for control of the output
High or High-Impedance state.
LCSTo0-1 C12, B12
Local Output Channel High Impedance Control (5 V Tolerant Three-state
Outputs).
Active high output enable which may be used to control external buffering
individually for a set of Local output streams on a per channel basis.
LCSTo0 is the output enable for LSTo[0, 2, 4, 6, 8, 10, 12, 14],
LCSTo1 is the output enable for LSTo[1, 3, 5, 7, 9, 11, 13, 15].
Refer to descriptions of the LORS and ODE pins for control of the output
High or High-Impedance state.
Pin Description Table (continued)
Name Package
Coordinates Description
MT90871 Data Sheet
7
Zarlink Semiconductor Inc.
ODE B9 Output Drive Enable (5 V Tolerant, Internal pull-up).
An asynchronous input providing Output Enable control to the BSTo0-15,
LSTo0-15, BCSTo0-1 and LCSTo0-1 outputs.
When LOW, the BSTo0-15 and LSTo0-15 outputs are driven high or high
impedance (dependent on the BORS and LORS pin settings respectively)
and the outputs BCSTo0-1 and LCSTo0-1 are driven low.
When HIGH, the outputs BSTo0-15, LSTo0-15, BCSTo0-1 and LCSTo0-1
are enabled.
BORS G2 Backplane Output Reset State (5 V Tolerant, Internal pull-down).
Asynchronous input. When LOW, the device will initialize with the BSTo0-
15 outputs driven high, and the BCSTo0-1 outputs driven low. Following
initialization, the Backplane stream outputs are always active and a high
impedance state, if required on a per-channel basis, may be implemented
with external buffers controlled by outputs BCSTo0-1.
When the input is HIGH, the device will initialize with the BSTo0-15 outputs
at high impedance and the BCSTo0-1 outputs are driven low. Following
initialization, the Backplane stream outputs may be set active or high
impedance using the ODE pin or, on a per-channel basis, with the BE bit in
Backplane Connection Memory.
LORS H13 Backplane Output Reset State (5 V Tolerant, Internal pull-down).
Asynchronous input. When LOW, the device will initialize with the LSTo0-
15 outputs driven high, and the LCSTo0-1 outputs driven low. Following
initialization, the Backplane stream outputs are always active and a high
impedance state, if required on a per-channel basis, may be implemented
with external buffers controlled by outputs LCSTo0-1.
When the input is HIGH, the device will initialize with the LSTo0-15 outputs
at high impedance and the LCSTo0-1 outputs are driven low. Following
initialization, the Backplane stream outputs may be set active or high
impedance using the ODE pin or, on a per-channel basis, with the LE bit in
Backplane Connection Memory.
NC P9, P11 No Connect. These ball-pads MUST remain unconnected.
IC C1, D1, C11, C13,
M7, M8, N8, P8
Internal Connect
s
These inputs MUST be held at logic ‘LOW’.
Pin Description Table (continued)
Name Package
Coordinates Description
MT90871 Data Sheet
8
Zarlink Semiconductor Inc.
1.0 Bidirectional and Unidirectional Applications
The MT90871 has a maximum capacity of 8,192 input channels and 8,192 output channels. This is calculated from
the maximum number of streams and channels: 32 input streams (16 Backplane, 16 Local) at 16.384 Mb/s and 32
output streams (16 Backplane, 16 Local) at 16.384 Mb/s.
One typical mode of operation is to separate the Backplane and Local sides, as shown in Figure 3 below.
Figure 3 - 4,096 x 4,096 Channels (16 Mb/s), Bidirectional Switching
In this system setup, the chip has a capacity of 4,096 input channels and 4,096 output channels on the Backplane
side as well as 4,096 input channels and 4,096 output channels on the Local side. Note that some or all of the
output channels on one side can come from the other side, i.e. Backplane input to Local output switching.
Often a system design does not need to differentiate between Backplane and Local side, and merely needs
maximum switching capacity. In this case, the MT90871 can be used as shown in Figure 4 to give the full 8,192 x
8,192 channel capacity.
Figure 4 - 8,192 x 8,192 Channels (16 Mb/s), Unidirectional Switching
In this system, the Backplane and Local inputs and outputs are combined and the switch appears as a 32 stream
input by 32 stream output switch. This style of operation is similar to older switch designs, such as the MT90826.
1.1 Flexible Configuration
The F8KDX can be configured as a 4 K by 4 K non-blocking bi-directional digital switch, an 8 K by 8 K unidirectional
non-blocking switch, and as a blocking switch with various switching capacities.
1.1.1 A. Blocking Bi-directional Configuration (Typical System Configuration)
• 4,096-channel x 4,096-channel non-blocking switching from backplane to local streams
• 4,096-channel x 4,096-channel non-blocking switching from local to backplane streams
• 4,096-channel x 4,096-channel non-blocking switching from backplane input to backplane output streams
• 4,096-channel x 4,096-channel non-blocking switching from local input to local output streams
MT90871
16 streams
16 streams
16 streams
16 streams
BSTi0-15
BSTo0-15
LSTo0-15
LSTi0-15
BACKPLANE LOCAL
MT90871
16 streams
16 streams
16 streams
16 streams
BSTi0-15
LSTi0-15
BSTo0-15
LSTo0-15
INPUT OUTPUT
MT90871 Data Sheet
9
Zarlink Semiconductor Inc.
1.1.2 Unidirectional Configuration
Because the input and output drivers are synchronous, the user can combine input backplane streams and input
local streams or output backplane streams and output local streams to increase the total number of input and
output streams of the switch in a unidirectional configuration.
• 8,192-channel x 8,192-channel non-blocking switching from input to output streams
1.1.3 Blocking Configuration
The F8KDX can be configured as a blocking switch if it is an application requirement. For example, it can be
configured as a 6 K by 2 K blocking switch.
• 6,144-channel x 2,048-channel blocking switching from ’backplane’ to ’local’ streams
• 2,048-channel x 6,144-channel blocking switching from ’local’ to ’backplane’ streams
• 6,144-channel x 6,144-channel non-blocking switching from ’backplane’ input to ’backplane’ output streams
• 2,048-channel x 2,048-channel non-blocking switching from ’local’ input to ’local’ output streams
Figure 5 - 6 K by 2 K Blocking Configuration
2.0 Functional Description
2.1 Switching Configuration
The device supports five switching configurations. (1) Backplane-to-Local, (2) Local-to-Backplane, (3) Backplane-
to-Backplane, (4) Local-to-Local, and (5) Uni-directional switch. The following sections describe the switching paths
in detail. Configurations (1) - (4) enable a non-blocking switch with a maximum capacity of 4,096 input channels
and 4,096 output channels at Backplane and Local stream data-rates of 16.384 Mb/s. The switch paths of
Configurations (1) to (4) may be operated simultaneously. Configuration (5) provides a uni-directional switch with a
maximum capacity of 8,192 x 8,192 channels at 16.384 Mb/s data rate.
2.1.1 Backplane-to-Local Path
The device can provide data switching between the Backplane input ports and the Local output ports. The Local
Connection Memory determines the switching configurations.
2.1.2 Local-to-Backplane Path
The device can provide data switching between the Local input ports and the Backplane output ports. The
Backplane Connection Memory determines the switching configurations.
MT90871
BSTi0-15
LSTi0-7
BSTo0-15
LSTo0-7
6K by 2K
2K by 6K
2K by 2K
LSTi8-15
LSTo8-15
6K x 6K
Total 24 input streams and Total 8 input streams and
24 output streams. 8 output streams.
MT90871 Data Sheet
10
Zarlink Semiconductor Inc.
2.1.3 Backplane-to-Backplane Path
The device can provide data switching between the Backplane input and output ports. The Backplane
Connection Memory determines the switching configurations.
2.1.4 Local-to-Local Path
The device can provide data switching between the Local input and output ports. The Local Connection Memory
determines the switching configurations.
2.1.5 Uni-directional Switch
The device may be optionally configured to provide an 8,192 x 8,192 uni-directional switch by grouping together
all input and all output streams. All streams (LSTi/LSTo0-15 and BSTi/BSTo0-15) may be operated at a data-
rate of 16.384 Mb/s. Lower data-rates may be employed with a corresponding reduction in switch capacity.
2.2 Port Data Rate Modes and Selection
The selection of individual stream data-rates is summarized in Table 1.
2.2.1 Local Port Rate Selection
The Local port has 16 input (LSTi0-15) and 16 output (LSTo0-15) data streams. All input and output streams
may be individually selected for operation at a data rate of either 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s or
16.384 Mb/s. The timing of the input and output clocks and frame pulses are shown in Figure 6, Local Port
Timing Diagram for 2,4,8 and 16 Mb/s Stream Rates.
2.2.1.1 Local Input Port
The bit rate for each input stream is selected by writing to a dedicated Local Input Bit Rate Register (LIBRR0-
15). Refer to 38, Local Input Bit Rate Register (LIBRRn) Bits.
Stream Number Rate Selection Capability
(for each individual stream)
Input stream - Local 0-15 (LSTi0-15) 2.048, 4.096, 8.192 or 16.384 Mb/s
Output stream - Local 0-15 (LSTo0-15) 2.048, 4.096, 8.192 or 16.384 Mb/s
Input stream - Backplane 0-15 (BSTi0-15) 2.048, 4.096, 8.192 or 16.384 Mb/s
Output stream - Backplane 0-15 (BSTo0-15) 2.048, 4.096, 8.192 or 16.384 Mb/s
Table 1 - Per-stream Data-Rate Selection: Backplane and Local streams
MT90871 Data Sheet
11
Zarlink Semiconductor Inc.
Figure 6 - Local Port Timing Diagram for 2,4,8 and 16 Mb/s Stream Rates
2.2.1.2 Local Output Port
The bit rate for each output stream is selected by writing to a dedicated Local Output Bit Rate Register
(LOBRR0-15). Refer to 40, Local Output Bit Rate Register (LOBRRn) Bits.
Operation of stream data in the Connection Mode or the Message Mode is determined by the state of the LMM
bit, and the channel High-impedance state is controlled by the LE bit of the Local Connection Memory. The data
source (i.e. from the Local or Backplane Data Memory) is determined by the LSRC bit of the Local Connection
Memory. Refer to Section 6.1 and Section 12.3.
2.2.2 Backplane Port Rate Selection
The Backplane port has 16 input (BSTi0-15) and 16 output (BSTo0-15) data streams. All input and output
streams may be individually selected for operation at a data rate of either 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s
or 16.384 Mb/s. The timing of the input and output clocks and frame pulses are shown in Figure 7, Backplane
Port Timing Diagram for 2, 4, 8, and 16 Mb/s stream rates.
FP8i (ST-BUS)
(8.192 MHz)
C8i (GCI)
(8 kHz)
(8 kHz)
FP8i (GCI)
(8.192 MHz)
C8i (ST-BUS)
72
3
456100
LSTi/LSTo0-15
(16 Mb/s) ST
12345610
7
Channel 255
Channel 0
0
LSTi/LSTo0-15
(8 Mb/s) GCI
Channel 0
376
Channel 127
54
7
LSTi/LSTo0-15
(4 Mb/s) ST
Channel 0
6 0
1
Channel 63
7
12
70
0
0
LSTi/LSTo0-15
(2 Mb/s) GCI
Channel 0
7
Channel 31
07
05
4
321677
LSTi/LSTo0-15
(16 Mb/s) GCI
65432167
0
Channel 255
Channel 0
7
LSTi/LSTo0-15
(8 Mb/s) ST
Channel 0
401
Channel 127
23
65
07
0
LSTi/LSTo0-15
(4 Mb/s) GCI
Channel 0
1 7
6
Channel 63
07
7
LSTi/LSTo0-15
(2 Mb/s) ST
Channel 0
0
Channel 31
70
MT90871 Data Sheet
12
Zarlink Semiconductor Inc.
2.2.3 Backplane Input Port
The bit rate for each input stream is selected by writing to a dedicated Backplane Input Bit Rate Register
(BOBRR0-15). Refer to 42, Backplane Input Bit Rate Register (BIBRRn) Bits.
2.2.3.1 Backplane Output Port
The bit rate for each output stream is selected by writing to a dedicated Backplane Output Bit Rate Register
(BOBRR0-15). Refer to 44, Backplane Output Bit Rate Register (BOBRRn) Bits.
Operation of stream data in the Connection Mode or the Message Mode is determined by the state of the BMM
bit, and the channel High-impedance state is controlled by the BE bit of the Backplane Connection Memory. The
data source (i.e., from the Local or Backplane Data Memory) is determined by the BSRC bit of the Backplane
Connection Memory. Refer to section 6.2 "Backplane Connection Memory" and section 12.4 "Backplane
Connection Memory Bit Definition".
Figure 7 - Backplane Port Timing Diagram for 2, 4, 8, and 16 Mb/s stream rates
FP8i (ST-BUS)
(8.192 MHz)
72
3
456100
BSTi/BSTo0-15
(16 Mb/s) ST
12345610
7
Channel 255
Channel 0
C8i (GCI)
0
BSTi/BSTo0-15
(8 Mb/s) GCI
Channel 0
376
Channel 127
54
(8 kHz)
(8 kHz)
FP8i (GCI)
7
BSTi/BSTo0-15
(4 Mb/s) ST
Channel 0
6 0
1
Channel 63
7
12
70
0
(8.192 MHz)
C8i (ST-BUS)
0
BSTi/BSTo0-15
(2 Mb/s) GCI
Channel 0
7
Channel 31
07
05
4
321677
BSTi/BSTo0-15
(16 Mb/s) GCI
65432167
0
Channel 255
Channel 0
7
BSTi/BSTo0-15
(8 Mb/s) ST
Channel 0
401
Channel 127
23
65
07
0
BSTi/BSTo0-15
(4 Mb/s) GCI
Channel 0
1 7
6
Channel 63
07
7
BSTi/BSTo0-15
(2 Mb/s) ST
Channel 0
0
Channel 31
70
MT90871 Data Sheet
13
Zarlink Semiconductor Inc.
2.3 Backplane Frame Pulse Input and Master Input Clock Timing
The Backplane frame pulse (FP8i) is an 8 kHz input signal active for 122 ns or 244 ns at the frame boundary.
The FPW bit in the Control Register must be set according to the applied pulse width. See Pin Description Table
and 13, Control Register Bits, for details.
The active state and timing of FP8i may conform either to the ST-BUS or to the GCI-BUS as shown in Figure 6,
Local Port Timing Diagram for 2,4,8 and 16 Mb/s Stream Rates, and Figure 7, Backplane Port Timing Diagram for
2, 4, 8, and 16 Mb/s stream rates. The MT90869 will automatically detect whether an ST-BUS or a GCI-BUS style
frame pulse is being used for the master frame pulse (FP8i). The device will detect the frame boundary alignment
using the rising edge of the input clock (C8i), provided the C8IPOL bit in Table 13, “Control Register Bits,” on
page 35 is set to one. Before the C8IPOL bit is set to one, the frame boundary will not be detected correctly. For the
purposes of describing the device operation, the remaining part of this document assumes the ST-BUS style frame
pulse with a single width frame pulse of 122 ns and the C8IPOL bit is set to one unless explicitly stated otherwise.
In addition, the device provides FP8o, FP16o, C8o and C16o outputs to support external devices which connect
to the Local port. The Local frame pulses (FP8o, FP16o) will be provided in the same style as the master frame
pulse (FP8i). The polarity of C8o and C16o, at the Frame Boundary, can be controlled by the Control Register
bit, COPOL. An analog phase lock loop (APLL) is used to multiply the external clock frequency to generate an
internal clock signal operated at 131.072 MHz.
2.4 Backplane Frame Pulse Input and Local Frame Pulse Output Alignment
The MT90871 accepts a Backplane Frame Pulse (FP8i) and generates the Local Frame Pulse outputs, FP8o
and FP16o, which are aligned to the master frame pulse. There is a constant three frame delay for data being
switched. Figure 8, Backplane and Local Frame Pulse Alignment for Data Rates of 2 Mb/s, 4 Mb/s, 8 Mb/s and
16 Mb/s, shows the backplane and local frame pulse alignment for different data rates.
For further details of Frame Pulse conditions and options see Section 13.1 "Control Register (CR)", Figure 17,
Frame Boundary Conditions, ST- BUS Operation, and Figure 18, Frame Boundary Conditions, GCI - BUS
Operation.
Figure 8 - Backplane and Local Frame Pulse Alignment for Data Rates of 2 Mb/s, 4 Mb/s, 8 Mb/s
and 16 Mb/s
CH3
CH7
CH0 CH1 CH2
BSTi/BSTo0-15
(16 Mb/s)
C8o
FP8o
LSTi/LSTo0-15
(2 Mb/s)
LSTi/LSTo0-15
(4 Mb/s)
LSTi/LSTo0-15
(8 Mb/s)
LSTi/LSTo0-15
(16 Mb/s)
CH2CH1CH0
CH6CH5
CH4CH3CH2CH0
CH4 CH5
CH10CH9
CH8 CH11
CH
15
CH
14
CH
13
CH
12
CH
11
CH
10
CH
9
CH
8
CH
7
CH
6
CH
5
CH
4
CH
3
CH
2
CH
1
CH
0 CH
19
CH
18
CH
17
CH
16 CH
23
CH
22
CH
21
CH
20
CH1
CH
3
CH
2
CH
1
CH
0CH
7
CH
6
CH
5
CH
4CH
11
CH
10
CH
9
CH
8CH
15
CH
14
CHCH
12 13 CH
17
CH
16 CH
21
CH
20
CHCH
18 19 CH
23
CH
22
FP8i
C8i
CH3
CH7
CH0 CH1 CH2
(2 Mb/s)
BSTi/BSTo0-15
(4 Mb/s)
BSTi/BSTo0-15
CH2CH1CH0
CH6CH5
CH4CH3CH2CH0
CH4 CH5
CH10CH9
CH8 CH11CH1
BSTi/BSTo0-15
(8 Mb/s)
MT90871 Data Sheet
14
Zarlink Semiconductor Inc.
3.0 Input and Output Offset Programming
3.1 Input Channel Delay Programming (Backplane and Local Input Streams)
Various registers are used to control the input sampling point (delay) and the output advancement for the Local
and Backplane streams. The following sections explain the details of these offset programming features.
The control of the Input Channel Delay and the Input Bit Delay allows each input stream to have a different
frame boundary with respect to the master frame pulse, FP8i. By default, all input streams have channel delay
of zero such that Ch0 is the first channel that appears after the frame boundary.
By programming the Backplane or Local input channel delay registers, BCDR0-15 and LCDR0-15, users can
assign the Ch0 position to be located at any one of the channel boundaries in a frame. For delays within
channel boundaries, the input bit delay programming can be used. The use of Input Channel Delay in
combination with Input Bit Delay enables the Ch0 position to be placed anywhere within a frame to a resolution
of 1/4 of the bit period.
Figure 9 - Backplane and Local Input Channel Delay Timing Diagram (8 Mb/s)
3.2 Input Bit Delay Programming (Backplane and Local Input Streams)
In addition to the Input Channel Delay programming, the Input Bit Delay programming feature provides users with
greater flexibility when designing switch matrices for high speed operation. The input bit delay may be programmed
on a per-stream basis to accommodate delays created on PCM highways. For all streams the delay is up to 7 3/4
bits with a resolution of 1/4 bit, for the selected data-rate.
See Figure 10 and Figure 11 for Input Bit Delay Timing at 16 Mb/s and 8 Mb/s data rates, respectively.
The Local input delay is defined by the Local Input Delay registers, LIDR0 to LIDR15, corresponding to the Local
data streams, LSTi0 to LSTi15, and the Backplane input delay is defined by the Backplane Input Delay registers,
BIDR0 to BIDR15, which correspond to the Backplane data streams, BSTi0 to BSTi15.
FP8i
C8i
72345610
BSTi0-15/LSTi0-15
Channel Delay = 0
Ch 0
72345610
Ch 1
2310 72345610
Ch127
2345610
Ch126
76
72345610
BSTi0-15/LSTi0-15
Channel Delay = 1
Ch127
72345610
Ch 0
2310 72345610
Ch126
2345610
Ch125
76
72345610
BSTi0-15/LSTi0-15
Channel Delay = 2
Ch126
72345610
Ch127
2310 72345610
Ch125
2345610
Ch0
76
(Default)
Channel Delay,1
Channel Delay, 2
7
MT90871 Data Sheet
15
Zarlink Semiconductor Inc.
Figure 10 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 16 Mb/s
C8i
72345610
BSTi0-15/LSTi0-15
Bit Delay = 0
Ch0
7456
Ch1
2310
BSTi0-15/LSTi0-15
Bit Delay = 1/4
72345610
BSTi0-15/LSTi0-15
Bit Delay = 1
Ch0
756
Ch1
2310
(Default)
72345610
Ch0
7456
Ch1
2310
Ch255
Ch255
Ch255
Bit Delay, 1/4
Bit Delay, 1
BSTi0-15/LSTi0-15
Bit Delay = 1/2
72345610
Ch0
7456
Ch1
2310
Ch255
Bit Delay, 1/2
BSTi0-15/LSTi0-15
Bit Delay = 3/4
72345610
Ch0
7456
Ch1
2310
Ch255
Bit Delay, 3/4
BSTi0-15/LSTi0-15
Bit Delay = 7
1/2
72345610
Ch255
7456
Ch0
210
Ch254
Bit Delay, 7
1/2
BSTi0-15/LSTi0-15
Bit Delay = 7
3/4
72345610
Ch255
7456
Ch0
210
Ch254
Bit Delay, 7
3/4
FP8i
MT90871 Data Sheet
16
Zarlink Semiconductor Inc.
Figure 11 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 8 Mb/s
3.3 Output Advancement Programming (Backplane and Local Output Streams)
This feature is used to advance the output channel alignment of individual Local or Backplane output streams
with respect to the frame boundary. Each output stream has its own advancement value which can be
programmed by the output advancement registers. The output advancement selection is useful in
compensating for various parasitic loading on the serial data output pins.
3.3.1 Local Output Advancement Programming
The Local output advancement registers, LOAR0-15, are used to control the Local output advancement. The
advancement is determined with reference to the internal system clock rate (131.072 MHz). For 2 Mb/s, 4 Mb/s,
8 Mb/s or 16 Mb/s streams the advancement may be 0, -2 cycles, -4 cycles or -6 cycles, which converts to
approximately 0 ns, -15 ns, -30 ns or -45 ns as shown in Figure 12.
3.3.2 Backplane Output Advancement Programming
The Backplane output advancement registers, BOAR0-15 are used to control the Backplane output
advancement. The advancement is determined with reference to the internal system clock rate (131.072 MHz).
For 2 Mb/s, 4 Mb/s, 8 Mb/s or 16 Mb/s streams the advancement may be 0, -2 cycles, -4 cycles or -6 cycles,
which converts to approximately 0ns, -15 ns, -30 ns or -45 ns as shown in Figure 12.
C8i
72345610
BSTi0-15/LSTi0-15
Bit Delay = 0
Ch0
7456
Ch1
2310
BSTi0-15/LSTi0-15
Bit Delay = 1/4
72345610
BSTi0-15/LSTi0-15
Bit Delay = 1
Ch0
756
Ch1
2310
(Default)
72345610
Ch0
7456
Ch1
2310
Ch127
Ch127
Ch127
Bit Delay, 1/4
Bit Delay, 1
BSTi0-15/LSTi0-15
Bit Delay = 1/2
72345610
Ch0
7456
Ch1
2310
Ch127
Bit Delay, 1/2
BSTi0-15/LSTi0-15
Bit Delay = 3/4
72345610
Ch0
7456
Ch1
2310
Ch127
Bit Delay, 3/4
BSTi0-15/LSTi0-15
Bit Delay = 7
1/2
72345610
Ch127
7456
Ch0
210
Ch126
Bit Delay, 7
1/2
BSTi0-15/LSTi0-15
Bit Delay = 7
3/4
72345610
Ch127
7456
Ch0
210
Ch126
Bit Delay, 7
3/4
FP8i
MT90871 Data Sheet
17
Zarlink Semiconductor Inc.
Figure 12 - Backplane and Local Output Advancement Timing Diagram for Data Rate of 16 Mb/s
4.0 Port High Impedance Control
4.1 Local Port High Impedance Control
The input pin LORS selects whether the Local output streams LSTo0-15 are set to high impedance at the output of
the MT90871 itself or are always driven (active HIGH or active LOW) and a high impedance state, if required on a
per-channel basis, is invoked through an external interface circuit controlled by the LCSTo0-1 signals. Setting
LORS to a LOW state will configure the output streams LSTo0-15 to transmit bi-state channel data with per-
channel high-impedance determined by external circuits under the control of the LCSTo0-1 outputs. Setting LORS
to a HIGH state will configure the output streams LSTo0-15 of the MT90871 to invoke a high-impedance output on
a per-channel basis.
The LORS pin is an asynchronous input and is expected to be hard-wired for a particular system application,
although it may be driven under logic control if preferred.
4.1.1 LORS Set LOW
The data (channel control bit) transmitted by LCSTo0-1 replicates the Local Output Enable Bit (LE) of the Local
Connection Memory, with a LOW state indicating that the channel should be set to High Impedance by external
drivers. Refer to section 12.3 "Local Connection Memory Bit Definition" for setting the Local Output Enable Bit
(LE).
The LCSTo0-1 outputs transmit serial data (channel control bits) at 16.384 Mb/s, with each bit representing the
per-channel high impedance state for specific streams. Eight output streams are allocated to each control line
as follows:
• LCSTo0 outputs the channel control bits for streams LSTo0, 2, 4, 6, 8, 10, 12 and 14.
• LCSTo1 outputs the channel control bits for streams LSTo1, 3, 5, 7, 9, 11, 13 and 15.
(See also “Pin Description”.)
The Channel Control Bit location, within a frame period, for each channel of the Local output streams is
presented in Table 2 "LCSTo Allocation of Channel Control Bits to the Output Streams".
Bit Advancement, -2
Bit Advancement, -4
Bit Advancement, -6
FP8o
System Clock
BSTo0-1
5/LSTo0-15
Bit Advancement = 0
BSTo0-1
5/LSTo0-15
Bit Advancement = -2
(Default)
Bit Advancement = -6
BSTo0-1
5/LSTo0-15
Bit Advancement = -4
BSTo0-1
5/LSTo0-15
131.072 Mhz
Ch255
Ch255
Ch255
Ch255
Ch0
Ch0
Ch0
Ch0
Bit 1 Bit 0 Bit 7 Bit 6 Bit 5
Bit 1 Bit 0 Bit 7 Bit 6 Bit 5
Bit 1 Bit 0 Bit 7 Bit 6 Bit 5
Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4
Bit 4
MT90871 Data Sheet
18
Zarlink Semiconductor Inc.
As an aid to the description, the channel control bit for a single channel on specific streams is presented, with
reference to Table 2.
1. The Channel Control Bit corresponding to Stream 0, Channel 0, LSTo0_Ch0, is transmitted on LCSTo0
and is advanced, relative to the Frame Boundary, by 10 periods of C16o.
2. The Channel Control Bit corresponding to Stream 14, Channel 0, LSTo14_Ch0, is transmitted on LCSTo0
in advance of the Frame Boundary by three periods of output clock, C16o. Similarly, the Channel Control
Bit for LSTo15_Ch0 is advanced relative to the Frame Boundary by three periods of C16o, on LCSTo1.
The LCSTo0-1 outputs data at a constant data-rate of 16.384 Mb/s, independent of the data-rate selected for
the individual output streams, LSTo0-15. Streams at data-rates lower than 16.384 Mb/s will have the value of
the respective channel control bit repeated for the duration of the channel. The bit will be transmitted twice for
8.192 Mb/s streams, four times for 4.096 Mb/s streams and eight times for 2.048 Mb/s streams. The channel
control bit is not repeated for 16.384 Mb/s streams.
Examples are presented, with reference to Table 2:
3. With stream LSTo2 selected to operate at a data-rate of 2.048 Mb/s, the value of the Channel Control Bit
for Channel 0 will be transmitted during the C16o clock period nos. 2040, 2048, 8, 16, 24, 32, 40 and 48.
4. With stream LSTo4 operated at a data-rate of 8.192 Mb/s, the value of the Channel Control Bit for
Channel 1 will be transmitted during the C16o clock period nos. 9 and 17.
Figure 13, Local Port External High Impedance Control Bit Timing (ST-Bus Mode) shows the channel control
bits for LCSTo0 and LCSTo1 in one possible scenario which includes stream LSTo0 at a data-rate of
16.384 Mb/s, LSTo1 at 8.192 Mb/s, LSTo6 at 4.096 Mb/s and LSTo7 at 2.048 Mb/s. All remaining streams are
operated at a data-rate of 16.384 Mb/s.
4.1.2 LORS Set HIGH
The Local Output Enable Bit (LE) of the Local Connection Memory has direct per-channel control on the high-
impedance state of the Local Output streams, LSTo0-15. Programming a LOW state will set the stream output
of the MT90871 to High Impedance for the duration of the channel period. See section 12.3 "Local Connection
Memory Bit Definition", for programming details.
The LCSTo0-1 outputs remain active.
Allocated
Stream
No.
Allocated Channel No. 2
C16o
Period1LCSTo0 LCSTo1 16 Mb/s 8 Mb/s 4 Mb/s 2 Mb/s
2039 0 3-1 1 Ch 0 Ch 0 Ch 0 Ch 0
2040 23-3 3 Ch 0 Ch 0 Ch 0 Ch 0
2041 4 5 Ch 0 Ch 0 Ch 0 Ch 0
2042 6 7 Ch 0 Ch 0 Ch 0 Ch 0
2043 8 9 Ch 0 Ch 0 Ch 0 Ch 0
2044 10 11 Ch 0 Ch 0 Ch 0 Ch 0
2045 12 13 Ch 0 Ch 0 Ch 0 Ch 0
Table 2 - LCSTo Allocation of Channel Control Bits to the Output Streams
MT90871 Data Sheet
19
Zarlink Semiconductor Inc.
2046 143-2 153-2 Ch 0 Ch 0 Ch 0 Ch 0
2047 0 1 Ch 1 Ch 0 Ch 0 Ch 0
2048 2 3-3 3 Ch 1 Ch 0 Ch 0 Ch 0 Frame
1 4 5 Ch 1 Ch 0 Ch 0 Ch 0 Boundary
2 6 7 Ch 1 Ch 0 Ch 0 Ch 0
3 8 9 Ch 1 Ch 0 Ch 0 Ch 0
4 10 11 Ch 1 Ch 0 Ch 0 Ch 0
5 12 13 Ch 1 Ch 0 Ch 0 Ch 0
6 14 15 Ch 1 Ch 0 Ch 0 Ch 0
7 0 1 Ch 2 Ch 1 Ch 0 Ch 0
82 3-3 3 Ch 2 Ch 1 Ch 0 Ch 0
94 3-4 5 Ch 2 Ch 1 Ch 0 Ch 0
10 6 7 Ch 2 Ch 1 Ch 0 Ch 0
11 8 9 Ch 2 Ch 1 Ch 0 Ch 0
12 10 11 Ch 2 Ch 1 Ch 0 Ch 0
13 12 13 Ch 2 Ch 1 Ch 0 Ch 0
14 14 15 Ch 2 Ch 1 Ch 0 Ch 0
15 0 1 Ch 3 Ch 1 Ch 0 Ch 0
16 2 3-3 3 Ch 3 Ch 1 Ch 0 Ch 0
17 4 3-4 5 Ch 3 Ch 1 Ch 0 Ch 0
etc. etc. etc. etc. etc. etc. etc.
etc. etc. etc. etc. etc. etc. etc.
2029 etc. etc. Ch 254 Ch 127 Ch 63 Ch 31
2030 14 15 Ch 254 Ch 127 Ch 63 Ch 31
2031 0 1 Ch 255 Ch 127 Ch 63 Ch 31
2032 2 3 Ch 255 Ch 127 Ch 63 Ch 31
2033 4 5 Ch 255 Ch 127 Ch 63 Ch 31
Allocated
Stream
No.
Allocated Channel No. 2
C16o
Period1LCSTo0 LCSTo1 16 Mb/s 8 Mb/s 4 Mb/s 2 Mb/s
Table 2 - LCSTo Allocation of Channel Control Bits to the Output Streams (continued)
MT90871 Data Sheet
20
Zarlink Semiconductor Inc.
Note 1: Clock Period count is referenced to Frame Boundary.
Note 2: The Channel Numbers presented relate to the data-rate selected for a specific stream.
Note 3-1 to 3-4: See Section 4.1.1 for examples of Channel Control Bit for streams of different data-rates.
2034 6 7 Ch 255 Ch 127 Ch 63 Ch 31
2035 8 9 Ch 255 Ch 127 Ch 63 Ch 31
2036 10 11 Ch 255 Ch 127 Ch 63 Ch 31
2037 12 13 Ch 255 Ch 127 Ch 63 Ch 31
2038 14 15 Ch 255 Ch 127 Ch 63 Ch 31
2039 0 1 Ch 0 Ch 0 Ch 0 Ch 0
2040 2 3 Ch 0 Ch 0 Ch 0 Ch 0
2041 4 5 Ch 0 Ch 0 Ch 0 Ch 0
2042 6 7 Ch 0 Ch 0 Ch 0 Ch 0
2043 8 9 Ch 0 Ch 0 Ch 0 Ch 0
2044 10 11 Ch 0 Ch 0 Ch 0 Ch 0
2045 12 13 Ch 0 Ch 0 Ch 0 Ch 0
2046 14 15 Ch 0 Ch 0 Ch 0 Ch 0
2047 0 1 Ch 1 Ch 0 Ch 0 Ch 0
2048 2 3 Ch 1 Ch 0 Ch 0 Ch 0 Frame
1 4 5 Ch1 Ch0 Ch0 Ch0 Boundary
2 6 7 Ch 1 Ch 0 Ch 0 Ch 0
3 8 9 Ch 1 Ch 0 Ch 0 Ch 0
etc. etc. etc. etc. etc. etc. etc.
Allocated
Stream
No.
Allocated Channel No. 2
C16o
Period1LCSTo0 LCSTo1 16 Mb/s 8 Mb/s 4 Mb/s 2 Mb/s
Table 2 - LCSTo Allocation of Channel Control Bits to the Output Streams (continued)
MT90871 Data Sheet
21
Zarlink Semiconductor Inc.
Figure 13 - Local Port External High Impedance Control Bit Timing (ST-Bus Mode)
4.2 Backplane High Impedance Control
The input pin BORS selects whether the Backplane output streams BSTo0-15 are set to high impedance at the
output of the MT90871 itself, or are always driven (active HIGH or active LOW) and a high impedance state, if
required on a per-channel basis, is invoked through an external interface circuit controlled by the BCSTo0-1
signals. Setting BORS to a LOW state will configure the output streams BSTo0-15 to transmit bi-state channel
data with per-channel high-impedance determined by external circuits under the control of the BCSTo0-1
outputs. Setting BORS to a HIGH state will configure the output streams BSTo0-15 of the MT90871 to invoke a
high-impedance output on a per-channel basis.
The BORS pin is an asynchronous input and is expected to be hard-wired for a particular system application,
although it may be driven under logic control if preferred.
4.2.1 BORS Set LOW
The data (channel control bit) transmitted by BCSTo0-1 replicates the Backplane Output Enable Bit (BE) of the
Backplane Connection Memory, with a LOW state indicating that the channel should be set to High Impedance
by external drivers. Refer to section 12.4 "Backplane Connection Memory Bit Definition" for setting the
Backplane Output Enable Bit (BE).
Chan 0 Bit 7 Chan 0 Bit 6 Chan 63 Bit 1 Chan 63 Bit 0
Chan 0
Bit 7
Chan 63
Bit 0
765432 3210541 60 7 760
Chan 0
Bit 7 Chan 0
Bit 6
Chan 0
Bit 5
Chan 0
Bit 4
Chan 127
Bit 3
Chan 127
Bit 2
Chan 127
Bit 1
Chan 127
Bit 0
Chan 0
Bit 7
Chan 127
Bit 0
Channel 0 Bit 7 Channel 31 Bit 0
Chan 0
Bit 7
Chan 31
Bit 0
LCSTo0
LSTo0
(16 Mb/s)
LSTo1
(8 Mb/s)
LSTo6
(4 Mb/s)
LSTo7
(2 Mb/s)
C8o
FP8o
CH 1
LSTo0
CH 1
LSTo2
CH 1
LSTo4
CH 0
LSTo6
CH 1
LSTo8
CH 1
LSTo10
CH 1
LSTo12
CH 1
LSTo14
CH 2
LSTo0
CH 2
LST02
CH 0
LSTo4
CH 0
LSTo6
CH 0
LSTo8
CH 0
LSTo10
CH 0
LSTo12
CH 0
LSTo14
CH 1
LSTo0
CH 1
LSTo2
CH 1
LSTo4
CH 0
LSTo6
CH 0
LSTo1
CH 1
LSTo3
CH 1
LSTo5
CH 0
LSTo7
CH 1
LSTo9
CH 1
LSTo11
CH 1
LSTo13
CH 1
LSTo15
CH 1
LSTo1
CH 2
LSTo3
CH 0
LSTo5
CH 0
LSTo7
CH 0
LSTo9
CH 0
LSTo11
CH 0
LSTo13
CH 0
LSTo15
CH 0
LSTo1
CH 1
LSTo3
CH 1
LSTo5
CH 0
LSTo7
LCSTo1
One C16o period
Channel 0 Channel 255 bits 7-0
1
MT90871 Data Sheet
22
Zarlink Semiconductor Inc.
The BCSTo0-1 outputs transmit serial data (channel control bits) at 16.384 Mb/s, with each bit representing the
per-channel high impedence state for specific streams. Eight output streams are allocated to each control line
as follows:
• BCSTo0 outputs the channel control bits for streams BSTo0, 2, 4, 6, 8, 10, 12 and 14.
• BCSTo1 outputs the channel control bits for streams BSTo1, 3, 5, 7, 9, 11, 13 and 15.
(See also Pin Description)
The Channel Control Bit location, within a frame period, for each channel of the Backplane output streams is
presented in 3, BCSTo Allocation of Channel Control Bits to the Output Streams.
As an aid to the description, the channel control bit for a single channel on specific streams is presented, with
reference to Table 3:
1. The Channel Control Bit corresponding to Stream 0, Channel 0, BSTo0_Ch0, is transmitted on BCSTo0
and is advanced, relative to the Frame Boundary, by 10 periods of C16o, (i.e., clock period no. 2039).
2. The Channel Control Bit corresponding to Stream 14, Channel 0, BSTo14_Ch0, is transmitted on
BCSTo0 in advance of the Frame Boundary by three periods of output clock, C16o, (i.e., clock period no.
2046). Similarly, the Channel Control Bit for BSTo15_Ch0 is advanced relative to the Frame Boundary by
three periods of C16o, on BCSTo1.
The BCSTo0-1 outputs data at a constant data-rate of 16.384 Mb/s, independent of the data-rate selected for
the individual output streams, BSTo0-15. Streams at data-rates lower than 16.384 Mb/s will have the value of
the respective channel control bit repeated for the duration of the channel. The bit will be transmitted twice for
8.192 Mb/s streams, four times for 4.096 Mb/s streams and eight times for 2.048 Mb/s streams. The channel
control bit is not repeated for 16.384 Mb/s streams.
Examples are presented, with reference to Table 3:
3. With stream BSTo2 selected to operate at a data-rate of 2.048 Mb/s, the value of the Channel Control Bit
for Channel 0 will be transmitted during the C16o clock period nos. 2040, 2048, 8, 16, 24, 32, 40 and 48.
4. With stream BSTo4 operated at a data-rate of 8.192Mb/s, the value of the Channel Control Bit for
Channel 1 will be transmitted during the C16o clock period nos. 9 and 17.
MT90871 Data Sheet
23
Zarlink Semiconductor Inc.
Allocated Stream
No. Channel No. 2
C16o
Period1BCSTo0 BCSTo1 16 Mb/s 8 Mb/s 4 Mb/s 2 Mb/s
2039 0 3-1 1 Ch 0 Ch 0 Ch 0 Ch 0
2040 23-3 3 Ch 0 Ch 0 Ch 0 Ch 0
2041 4 5 Ch 0 Ch 0 Ch 0 Ch 0
2042 6 7 Ch 0 Ch 0 Ch 0 Ch 0
2043 8 9 Ch 0 Ch 0 Ch 0 Ch 0
2044 10 11 Ch 0 Ch 0 Ch 0 Ch 0
2045 12 13 Ch 0 Ch 0 Ch 0 Ch 0
2046 143-2 153-2 Ch 0 Ch 0 Ch 0 Ch 0
2047 0 1 Ch 1 Ch 0 Ch 0 Ch 0
2048 2 3 Ch 1 Ch 0 Ch 0 Ch 0 Frame
1 4 5 Ch 1 Ch 0 Ch 0 Ch 0 Boundary
2 6 7 Ch 1 Ch 0 Ch 0 Ch 0
3 8 9 Ch 1 Ch 0 Ch 0 Ch 0
4 10 11 Ch 1 Ch 0 Ch 0 Ch 0
5 12 13 Ch 1 Ch 0 Ch 0 Ch 0
6 14 15 Ch 1 Ch 0 Ch 0 Ch 0
7 0 1 Ch 2 Ch 1 Ch 0 Ch 0
82
3-3 3 Ch 2 Ch 1 Ch 0 Ch 0
94
3-4 5 Ch 2 Ch 1 Ch 0 Ch 0
10 6 7 Ch 2 Ch 1 Ch 0 Ch 0
11 8 9 Ch 2 Ch 1 Ch 0 Ch 0
12 10 11 Ch 2 Ch 1 Ch 0 Ch 0
13 12 13 Ch 2 Ch 1 Ch 0 Ch 0
14 14 15 Ch 2 Ch 1 Ch 0 Ch 0
15 0 1 Ch 3 Ch 1 Ch 0 Ch 0
16 2 3-3 3 Ch 3 Ch 1 Ch 0 Ch 0
17 4 3-4 5 Ch 3 Ch 1 Ch 0 Ch 0
etc. etc. etc. etc. etc. etc. etc.
Table 3 - BCSTo Allocation of Channel Control Bits to the Output Streams
MT90871 Data Sheet
24
Zarlink Semiconductor Inc.
Note 1: Clock Period count is referenced to Frame Boundary.
Note 2: The Channel Numbers presented relate to the data-rate selected for a specific stream.
Note 3-1 to 3-4: See Section 4.2.1 for examples of Channel Control Bit for streams of different data-rates.
etc. etc. etc. etc. etc. etc. etc.
2029 etc. etc. Ch 254 Ch 127 Ch 63 Ch 31
2030 14 15 Ch 254 Ch 127 Ch 63 Ch 31
2031 0 1 Ch 255 Ch 127 Ch 63 Ch 31
2032 2 3 Ch 255 Ch 127 Ch 63 Ch 31
2033 4 5 Ch 255 Ch 127 Ch 63 Ch 31
2034 6 7 Ch 255 Ch 127 Ch 63 Ch 31
2035 8 9 Ch 255 Ch 127 Ch 63 Ch 31
2036 10 11 Ch 255 Ch 127 Ch 63 Ch 31
2037 12 13 Ch 255 Ch 127 Ch 63 Ch 31
2038 14 15 Ch 255 Ch 127 Ch 63 Ch 31
2039 0 1 Ch 0 Ch 0 Ch 0 Ch 0
2040 2 3 Ch 0 Ch 0 Ch 0 Ch 0
2041 4 5 Ch 0 Ch 0 Ch 0 Ch 0
2042 6 7 Ch 0 Ch 0 Ch 0 Ch 0
2043 8 9 Ch 0 Ch 0 Ch 0 Ch 0
2044 10 11 Ch 0 Ch 0 Ch 0 Ch 0
2045 12 13 Ch 0 Ch 0 Ch 0 Ch 0
2046 14 15 Ch 0 Ch 0 Ch 0 Ch 0
2047 0 1 Ch 1 Ch 0 Ch 0 Ch 0
2048 2 3 Ch1 Ch 0 Ch 0 Ch 0 Frame
1 4 5 Ch 1 Ch 0 Ch 0 Ch 0 Boundary
2 6 7 Ch 1 Ch 0 Ch 0 Ch 0
3 8 7 Ch 1 Ch 0 Ch 0 Ch 0
etc. etc. etc. etc. etc. etc. etc.
Allocated Stream
No. Channel No. 2
C16o
Period1BCSTo0 BCSTo1 16 Mb/s 8 Mb/s 4 Mb/s 2 Mb/s
Table 3 - BCSTo Allocation of Channel Control Bits to the Output Streams (continued)
MT90871 Data Sheet
25
Zarlink Semiconductor Inc.
Figure 14 - Backplane Port External High Impedance Control Bit Timing
Figure 14, Backplane Port External High Impedance Control Bit Timing shows the channel control bits for
BCSTo0 and BCSTo1 in one possible scenario which includes stream BSTo0 at a data-rate of 16.384 Mb/s,
BSTo1 at 8.192 Mb/s, BSTo6 at 4.096 Mb/s and BSTo7 at 2.048 Mb/s. All remaining streams are operated at a
data-rate of 16.384 Mb/s.
4.2.2 BORS Set HIGH
The Backplane Output Enable Bit (BE) of the Backplane Connection Memory has direct per-channel control on
the high-impedance state of the Backplane Output streams, BSTo0-15. Programming a LOW state will set the
stream output of the MT90871 to High Impedance for the duration of the channel period. See Section 12.4
"Backplane Connection Memory Bit Definition", for programming details.
The BCSTo0-1 outputs are held in a high-impedance state.
5.0 Data Delay through the Switching Paths
For all data rates, the received serial data is converted to parallel format and stored sequentially in the data
memory. Each data memory location corresponds to an input stream and channel number. To provide constant
delay and maintain frame integrity, the MT90871 utilizes four pages of data memory. Consecutive frames are
written in turn to each page of memory. Reading is controlled to allow a channel data written in frame N to be
read during frame N+3.
Chan 0 Bit 7 Chan 0 Bit 6 Chan 63 Bit 1 Chan 63 Bit 0
Chan 0
Bit 7
Chan 63
Bit 0
7 6 5 4 3 2 3 2 1 05 41 60 7 7 60
Chan 0
Bit 7 Chan 0
Bit 6
Chan 0
Bit 5
Chan 0
Bit 4
Chan 127
Bit 3
Chan 127
Bit 2
Chan 127
Bit 1
Chan 127
Bit 0
Chan 0
Bit 7
Chan 127
Bit 0
Channel 0 Bit 7 Channel 31 Bit 0
Chan 0
Bit 7
Chan 31
Bit 0
BCSTo0
BSTo0
(16 Mb/s)
BSTo1
(8 Mb/s)
BSTo6
(4 Mb/s)
BSTo7
(2 Mb/s)
C8o
FP8o
CH 1
BSTo0
CH 1
BSTo2
CH 1
BSTo4
CH 0
BSTo6
CH 1
BSTo8
CH 1
BSTo10
CH 1
BSTo12
CH 1
BSTo14
CH 2
BSTo0
CH 2
BST02
CH 0
BSTo4
CH 0
BSTo6
CH 0
BSTo8
CH 0
BSTo10
CH 0
BSTo12
CH 0
BSTo14
CH 1
BSTo0
CH 1
BSTo2
CH 1
BSTo4
CH 0
BSTo6
CH 0
BSTo1
CH 1
BSTo3
CH 1
BSTo5
CH 0
BSTo7
CH 1
BSTo9
CH 1
BSTo11
CH 1
BSTo13
CH 1
BSTo15
CH 1
BSTo1
CH 2
BSTo3
CH 0
BSTo5
CH 0
BSTo7
CH 0
BSTo9
CH 0
BSTo11
CH 0
BSTo13
CH 0
BSTo15
CH 0
BSTo1
CH 1
BSTo3
CH 1
BSTo5
CH 0
BSTo7
BCSTo1
One C16o period
Channel 0 Channel 255 bits 7-0
1
MT90871 Data Sheet
26
Zarlink Semiconductor Inc.
A constant delay of three frames is applied to all switching paths irrespective of data-rate or channel number.
See Figure 15.
Figure 15 - Constant Switch Delay: Examples of Different Stream Rates and Routing
6.0 Connection Memory Description
The MT90871 incorporates two connection memories, Local Connection Memory and Backplane Connection
Memory.
6.1 Local Connection Memory
The Local Connection Memory (LCM) is 16-bit wide with 4,096 memory locations to support the Local output
port. The most significant bit of each word, bit [15], selects the source stream from either the Backplane or the
Local port and determines the Backplane-to-Local or Local-to-Local data routing. Bits [14:13] select the control
CH
254 CH
0CH
1CH
254 CH
255 CH
254 CH
255
CH
0CH
1CH
0CH
1
CH
255
BSTi0
(16 Mb/s)
FP8o
CH
254 CH
0CH
1CH
254 CH
255 CH
254 CH
255
CH
0CH
1CH
0CH
1
CH
255
BSTo1
(16 Mb/s)
Frame N Frame N+3
Frame N+4
CH
0CH
127 CH
127
CH
0CH
0
CH
127
BSTi0
(8 Mb/s)
CH
0CH
127 CH
127
CH
0CH
0
CH
127
LSTo1
(8 Mb/s)
CH
0CH
127 CH
127
CH
0CH
0
CH
127
LSTi0
(8 Mb/s)
CH
0CH
63 CH
63
CH
0CH
0
CH
63
BSTo1
(4 Mb/s)
CH
0CH
127 CH
127
CH
0CH
0
CH
127
LSTi0
(8 Mb/s)
CH
0CH
31 CH
31
CH
0CH
0
CH
31
LSTo1
(2 Mb/s)
Example showing Local to Local switching
Example showing Local to Backplane switching
Example showing Backplane to Local switching
Example showing Backplane to Backplane switching
Frames N+1 and N+2
MT90871 Data Sheet
27
Zarlink Semiconductor Inc.
modes of the Local output streams, namely the per-channel message and the per-channel high impedance
output control modes. In Connection Mode (Bit14 = LOW), Bits [12:0] select the source stream and channel
number as detailed in Table 4, “Local and Backplane Connection Memory Configuration,” on page 27. In
Message Mode (Bit14 = HIGH), Bits [12:8] are unused and Bits [7:0] contain the message byte to be transmitted.
The Control Register bits MS2, MS1, and MS0 must be set to 000, respectively, to select the Local Connection
Memory for the Write and Read operations via the microprocessor port. See Section 7.0 "Microprocessor Port",
and Section 13.1 "Control Register (CR)" for details on microprocessor port access.
6.2 Backplane Connection Memory
The Backplane Connection Memory (BCM) is 16-bit wide with 4,096 memory locations to support the Backplane
output port. The most significant bit of each word, bit [15], selects the source stream from either the Backplane
or the Local port and determines the Local-to-Backplane or Backplane-to-Backplane data routing. Bits [14:13]
select the control modes of the Backplane output streams, namely the per-channel Message Mode and the per-
channel high impedance output control mode. In Connection Mode (Bit14 = LOW), Bits [12:0] select the source
stream and channel number as detailed in Table 4. In Message Mode (Bit14 = HIGH), Bits [12:8] are unused and
Bits [7:0] contain the message byte to be transmitted.
The Control Register bits MS2, MS1, and MS0 must be set to 001, respectively, to select the Backplane
Connection Memory for the Write and Read operations via the microprocessor port. See Section 7.0, and
Section 13.1.
6.3 Connection Memory Block Programming
This feature allows fast simultaneous initialization of the Local and Backplane Connection Memories after
power up. When the Memory Block Programming mode is enabled, the contents of the Block Programming
Register (BPR) will be loaded into the connection memories. See Table 13 and Table 14 for details of the
Control Register and Block Programming Register values, respectively.
6.3.1 Memory Block Programming Procedure
• Set the MBP bit in the Control Register from LOW to HIGH.
• Set the BPE bit to HIGH in the Block Programming Register (BPR). The Local Block Programming data bits,
LBPD2-0, of the Block Programming Register, will be loaded into Bit 15, Bit 14 and Bit 13, respectively, of
the Local Connection Memory. The remaining bit positions are loaded with zeros as shown in Table 5.
Table 5 - Local Connection Memory in Block Programming Mode
Source Stream Bit Rate Source Stream No. Source Channel No.
2 Mb/s [12:8]
legal values 0 - 15
[7:0]
legal values 0 - 31
4 Mb/s [12:8]
legal values 0 - 15
[7:0]
legal values 0 - 63
8 Mb/s [12:8]
legal values 0 - 15
[7:0]
legal values 0 - 127
16 Mb/s [12:8]
legal values 0 - 15
[7:0]
legal values 0 - 255
Table 4 - Local and Backplane Connection Memory Configuration
15 14 13 1211109876543210
LBPD2 LBPD1LBPD00000000000000
MT90871 Data Sheet
28
Zarlink Semiconductor Inc.
The Backplane Block Programming data bits, BBPD2-0, of the Block Programming Register, will be loaded into
Bit 15, Bit 14 and Bit 13, respectively, of the Backplane Connection Memory. The remaining bit positions are
loaded with zeros as shown in Table 6.
Table 6 - Backplane Connection Memory in Block Programming Mode
The Block Programming Register bit, BPE will be automatically reset LOW within 125 us, to indicate completion
of memory programming.
The Block Programming Mode can be terminated at any time prior to completion by setting the BPE bit of the
Block Programming Register or the MBP bit of the Control Register to LOW.
Note the default values (LOW) of LBPD2-0 and BBPD2-0 of the Block Programming Register, following a
device reset, may be used. These settings shall set all output channels to High, or High-Impedance, in
accordance with the LORS and BORS pin conditions, see Pin Description for further details. The Local
Connection Memory shall be configured to select data from Channel 0 of Backplane input Stream 0 (BSTi0),
and the Backplane Connection Memory shall be configured to select data from Channel 0 of Local input Stream
0 (LSTi0). Alternative conditions may be established by programming bits LBPD2-0 and BBPD2-0 of the Block
Programming Register at the time of setting Bit BPE to HIGH. See section 12.3 "Local Connection Memory Bit
Definition", section 12.4 "Backplane Connection Memory Bit Definition", and section 13.2 "Block Programming
Register (BPR)".
7.0 Microprocessor Port
The MT90871 supports non-multiplexed Motorola microprocessors. The microprocessor port consists of 16-bit
parallel data bus (D0-15), 15-bit address bus (A0-14) and four control signals (CS, DS, R/W and DTA). The data
bus provides access to the internal registers, the Backplane Connection and Data memories, and the Local
Connection and Data memories. Each memory has 4,096 locations. See 7, Address Map for Data and
Connection Memory Locations (A14=1), for the address mapping.
Each Connection Memory can be read or written via the 16-bit microprocessor port. The Data Memories can
only be read (but not written) from the microprocessor port.
To prevent the bus ’hanging’, in the event of the MT90871 not receiving a master clock, the microprocessor
port shall complete the DTA handshake when accessed but any data read from the bus will be invalid.
There must be a minimum of 30 ns between CPU accesses, to allow the MT90869 device to recognize the
accesses as separate (i.e., a minimum of 30 ns must separate the de-assertion of DTA (to high) and the assertion
of CS and/or DS to initiate the next access).
8.0 Device Power-up, Initialization and Reset
8.1 Power-Up Sequence
The recommended power-up sequence is for the VDD_IO supply (nominally +3.3 V) to be established before
the power-up of the VDD_PLL and VDD_CORE supplies (nominally +1.8 V). The VDD_PLL and VDD_CORE
supplies may be powered up simultaneously, but neither should 'lead' the VDD_IO supply by more than 0.3 V.
All supplies may be powered-down simultaneously.
15 14 13 1211109876543210
BBPD2 BBPD1 BBPD0 0 000000000000
MT90871 Data Sheet
29
Zarlink Semiconductor Inc.
8.2 Initialization
Upon power up, the MT90871 should be initialized by applying the following sequence:
1. Ensure the TRST pin is permanently LOW to disable the JTAG TAP controller.
2. Set ODE pin to LOW. This configures the LCSTo0-1 output signals to LOW (i.e., to set optional external
output buffers to high impedance), and sets the LSTo0-15 outputs to high or high impedance, dependent
on the LORS input value, and sets the BCSTo0-1 output signals to LOW (i.e., to set optional external
output buffers to high impedance), and sets the BSTo0-15 outputs to high or high impedance, dependent
on BORS input value. Refer to Pin Description for details of the LORS and BORS pins.
3. Reset the device by pulsing the RESET pin to zero for at least two cycles of the input clock, C8i.
4. Use the Block Programming Mode to initialize the Local and the Backplane Connection Memories. Refer
to 6.3 "Connection Memory Block Programming".
5. Set ODE pin to HIGH after the connection memories are programmed to ensure that bus contention will
not occur at the serial stream outputs.
8.3 Reset
The RESET pin is used to reset the device. When set LOW, an asynchronous reset is applied to the MT90871.
It is synchronized to the internal clock and remains active for 50 us following release (set HIGH) of the external
RESET to allow time for the PLL to fully settle. During the reset period, depending on the state of input pins
LORS and BORS, the output streams LSTo0- 15 and BSTo0-15 are set to high or high impedance, and all
internal registers and counters are reset to the default state.
The RESET pin must remain low for two input clock cycles (C8i) to guarantee a synchronized reset release.
When RESET is applied to the MT90871, the CS line is inhibited and the DTA line may become active through
simultaneous microport activity. External gating of the DTA line with CS is recommended to avoid bus conflict in
applications incorporating multiple devices with individual reset conditions.
9.0 Bit Error Rate Test
Independent Bit Error Rate (BER) test mechanisms are provided for the Local and Backplane ports. In both
ports there is a BER transmitter and a BER receiver. The transmitter and receiver are each independently
controlled to allow either looped back or uni-directional testing. The transmitter generates a 215-1 or 223-1
Pseudo Random Binary Sequence (PRBS), which may be allocated to a specific stream and a number of
channels. This is defined by a stream number, a start channel number, and the number of consecutive channels
following the start channel. The stream, channel number and the number of consecutive channels following the
start channel are similarly allocated for the receiver and detection of the PRBS. Examples of a channel
sequence are presented in Figure 16.
When enabled, the receiver attempts to lock to the PRBS on the incoming bit stream. Once lock is achieved by
detection of a seed value, a bit by bit comparison takes place and each error shall increment a 16-bit counter. A
counter ’roll-over’ shall occur in the event of an error count in excess of 65535.
The BER operations are controlled by registers as follows (refer to section 13.3 "Bit Error Rate Test Control
Register (BERCR)" for overall control, section 13.10 "Local Bit Error Rate (BER) Registers" and section 13.11
"Backplane Bit Error Rate (BER) Registers" for register programming details):
• BER Control Register (BERCR) - Independently enables BER transmission and receive testing for
Backplane and Local ports.
• Local and Backplane BER Start Send Registers (LBSSR and BBSSR) - Defines the output stream and start
channel for BER transmission.
MT90871 Data Sheet
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Zarlink Semiconductor Inc.
• Local and Backplane Transmit BER Length Registers (LTXBLR and BTXBLR) - Defines, for transmit
stream, how many consecutive channels to follow the start channel.
• Local and Backplane BER Start Receive Registers (LBSR and BBSR) - Define the input stream and channel
from where the BER sequence will start to be compared.
• Local and Backplane Receive BER Length Registers (LRXBLR and BRXBLR) - Defines, for the receive
stream, how many consecutive channels follow the start channel.
• Local and Backplane BER Count Registers (LBCR and BBCR) - Contain the number of counted errors.
The registers listed completely define the transmit stream and channels. When BER transmission is enabled
for these channels the source bits and the message mode bits, LSRC and LMM in the Local Connection
Memory, and BSRC and BMM in the Backplane Connection Memory are ignored. The enable bits (LE and BE)
of the respective connection memories should be set to HIGH to enable the outputs for the selected channels.
Figure 16 - Examples of BER Transmission Channels
10.0 Memory Built-In-Self-Test (BIST) Mode
As operation of the memory BIST will corrupt existing data, this test must only be instigated when the device is
placed “out-of-service” or isolated from live traffic.
The memory BIST mode is enabled through the microprocessor port (section 13.14 "Memory BIST Register").
Internal BIST memory controllers generate the memory test pattern (S-march) and control the memory test. The
memory test result is monitored through the Memory BIST Register when controlled via the microprocessor
interface.
11.0 JTAG Port
The MT90871 JTAG interface conforms to the Boundary-Scan IEEE 1149.1 standard. The operation of the
boundary-scan circuit shall be controlled by an external Test Access Port (TAP) Controller. The JTAG is
intended to be used during the development cycle. The JTAG interface is operational when the MT90871 Core
(VDD_CORE) is powered at typical voltage levels.
frame boundary
0 1 2 ...... ..... 254
3 ..... ..... 255
0 1 2 ...... ..... 254
3 ..... ..... 255
0 1 2 ...... ..... 254
3 ..... ..... 255 0 1
Channels containing data (traffic)Channels containing PRBS sequence
Start Ch=0
Length=256
Start Ch=0
Length=3
Start Ch=254
Length=4
0
0
1
1
FP8i
FP
stream
Once Started BER transmission continues until stopped by the BER control register.
2
2
2
Note: Length = Start Chan. + No. of Consecutive channels
MT90871 Data Sheet
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Zarlink Semiconductor Inc.
11.1 Test Access Port (TAP)
The Test Access Port (TAP) consists of four input pins and one output pin described as follows:
•Test Clock Input (TCK)
TCK provides the clock for the TAP Controller and is independent of any on-chip clock. TCK permits the
shifting of test data into or out of the Boundary-Scan Registers cells, under the control of the TAP Controller
in Boundary-Scan Mode.
•Test Mode Select Input (TMS)
The TAP controller uses the logic signals applied to the TMS input to control test operations. The TMS
signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to VDD_IO when not
driven from an external source.
•Test Data Input (TDi)
Depending on the previously applied data to the TMS input, the serial input data applied to the TDi port is
connected either to the Instruction Register or to a Test Data Register. Both registers are described in a 11.2
"TAP Registers". The applied input data is sampled at the rising edge of TCK pulses. This pin is internally
pulled to VDD_IO when not driven from an external source.
•Test Data Output (TDo)
Depending on the previously applied sequence to the TMS input, the contents of either the instruction
register or data register are serially shifted out towards the TDo. The data out of the TDo is clocked on the
falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDo output is
set to a high impedance state.
•Test Reset (TRST)
TRST provides an asynchronous Reset to the JTAG scan structure. This pin is internally pulled to VDD_IO
when not driven from an external source. This pin must be held LOW for normal (non-JTAG) device
operation.
11.2 TAP Registers
The MT90871 uses the public instructions defined in the IEEE 1149.1 standard with the provision of an
Instruction Register and three Test Data Registers.
11.2.1 Test Instruction Register
The JTAG interface contains a four-bit instruction register. Instructions are serially loaded into the Instruction
Register from the TDi pin when the TAP Controller is in the shift-IR state. Instructions are subsequently
decoded to achieve two basic functions: to select the Test Data Register to operate while the instruction is
current, and to define the serial Test Data Register path to shift data between TDi and TDo during data register
scanning.
11.2.2 Test Data Registers
11.2.2.1 The Boundary-Scan Register
The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around
the boundary of the MT90871 core logic.
11.2.2.2 The Bypass Register
The Bypass register is a single stage shift register to provide a one-bit path from TDi to TDo.
MT90871 Data Sheet
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Zarlink Semiconductor Inc.
11.2.2.3 The Device Identification Register
The JTAG device ID for the MT90871 is 0087114BH.
11.3 Boundary Scan Description Language (BSDL) File
A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of
the IEEE 1149.1 test interface.
12.0 Memory Address Mappings
The device contains two data memory blocks, one for received Backplane data and one for received Local data.
For all data rates the received data is converted to parallel format by internal serial to parallel converters and
stored sequentially in the relevant data memory.
12.1 Backplane Data Memory Bit Definition
The 8-bit Backplane Data Memory (BDM) has 4,096 positions. The locations are associated with the Backplane
input streams and channels. The address bits (A13:0) of the microprocessor define the addresses of the
streams and the channels. The BDM is configured as follows:
Version, Bits <31:28>: 0000
Part No., Bits <27:12>: 0000 1000 0111 0001
Manufacturer ID, Bits <11:1>: 0001 0100 101
Header, Bit <0> (LSB): 1
Address Bit Description
A14 Selects memory or register access
A13-A9 Stream address (0-15)
A8-A0 Channel address (0-255)
Notes:
1. Bit A14 must be high for accessing to data and connection memory positions. Bit A14 must
be low for accessing registers.
2. Channels 0 to 31 are used when serial stream is at 2.048 Mb/s.
3. Channels 0 to 63 are used when serial stream is at 4.096 Mb/s.
4. Channels 0 to 127 are used when serial stream is at 8.192 Mb/s.
5. Channels 0 to 255 are used when serial stream is at 16.384 Mb/s.
Table 7 - Address Map for Data and Connection Memory Locations (A14=1)
Bit Name Description
15-8 Reserved Set to a default value of 0
7-0 BDM Backplane Data Memory
Backplane Input Channel Data
Table 8 - Backplane Data Memory (BDM) Bits
MT90871 Data Sheet
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Zarlink Semiconductor Inc.
12.2 Local Data Memory Bit Definition
The 8-bit Local Data Memory (LDM) has 4,096 positions. The locations are associated with the Local input
streams and channels. The address bits of the microprocessor define the addresses of the streams and the
channels. The LDM is configured as follows:
12.3 Local Connection Memory Bit Definition
The Local Connection Memory (LCM) has 4,096 addresses of 16-bit words. Each address, accessed through
bits A13-A0 of the microprocessor port, is allocated to an individual Local output stream and channel. The bit
definition for each 16-bit word is presented in 10, LCM Bits for Local-to-Local and Backplane-to-Local
Switching. Bit LSRC selects the switch configuration for Backplane-to-Local or Local-to-Local. When the per-
channel Message Mode is selected (LMM = HIGH), the lower byte of the LCM word (LCAB7-0) will be
transmitted as data on the output stream (LSTo0-15) in place of data defined by the Source Control, Stream and
Channel Address bits.
.
12.4 Backplane Connection Memory Bit Definition
The Backplane Connection Memory (BCM) has 4,096 addresses of 16-bit words. Each address, accessed
through bits A13-A0 of the microprocessor port, is allocated to an individual Backplane output stream and
channel. The bit definition for each 16-bit word is presented in Table 11, BCM Bits for Local-to-Backplane and
Backplane-to-Backplane Switching .
Bit Name Description
15-8 Reserved Set to a default value of 0
7-0 LDM Local Data Memory
Local Input Channel Data
Table 9 - Local Data Memory (LDM) Bits
Bit Name Description
15 LSRC Source Control Bit
When LOW, the source is from the Backplane input port (Backplane Data Memory).
When HIGH, the source is from the Local input port (Local Data Memory).
Ignored when LMM is set HIGH.
14 LMM Local Message Mode Bit
When LOW, the channel is in Connection Mode.
When HIGH, the channel is in Message Mode.
13 LE Local Output Enable Bit
When LOW the channel may be high impedance, either at the device output, or set by an
external buffer dependent upon the LORS pin. When HIGH the channel is active.
12-8 LSAB4-0 Source Stream Address Bits
The binary value of these 5 bits represents the input stream number.
Ignored when LMM is set HIGH.
7-0 LCAB7-0 Source Channel Address Bits
The binary value of these 8 bits represents the input channel number when LMM is set
LOW. Transmitted as data when LMM is set HIGH.
Table 10 - LCM Bits for Local-to-Local and Backplane-to-Local Switching
MT90871 Data Sheet
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Zarlink Semiconductor Inc.
Bit BSRC selects the switch configuration for Local-to-Backplane or Backplane-to-Backplane. When the per-
channel Message Mode is selected (BMM = HIGH), the lower byte of the BCM word (BCAB7-0) will be
transmitted as data on the output stream (BSTo0-15) in place of data defined by the Source Control, Stream
Address and Channel Address bits.
12.5 Internal Register Mappings
Bit Name Description
15 BSRC
Backplane Source Control Bit.
When LOW, the source is from the Local input port (Local Data Memory). When HIGH, the source is
from the Backplane input port (Backplane Data Memory).
BSRC is ignored when BMM is set HIGH in Message Mode.
14 BMM Backplane Message Mode Bit.
When LOW, the channel is in Connection Mode. When HIGH, the channel is in Message Mode.
13 BE Backplane Output Enable Bit.
When LOW the channel may be high impedance, either at the device output or set by an external
buffer, dependent upon the BORS pin. When HIGH the channel is active.
12-8 BSAB4-0 Backplane Source Stream Address Bits.
The binary value of these 5 bits represents the input stream number. BSAB4-0 are ignored when
BMM is set HIGH in Message Mode.
7-0 BCAB7-0 Source Channel Address Bits.
The binary value of these 8 bits represents the input channel number when BMM is set LOW.
BCAB7-0 are transmitted as data when BMM is set HIGH in Message Mode.
Table 11 - BCM Bits for Local-to-Backplane and Backplane-to-Backplane Switching
A14 - A0 Register
0000HControl Register, CR
0001HBlock Programming Register, BPR
0002HBER Control Register, BERCR
0003H - 0012HLocal Input Channel Delay Register 0, LCDR0 - Register 15, LCDR15
0023H - 0032HLocal Input Bit Delay Register 0, LIDR0 - Register 15, LIDR15
0043H - 0052HBackplane Input Channel Delay Register 0, BCDR0 - Register 15, BCDR15
0063H - 0072HBackplane Input Bit Delay Register 0, BIDR0 - Register 15, BIDR15
0083H - 0092HLocal Output Advancement Register 0, LOAR0 - Register 15, LOAR15
00A3H - 00B2HBackplane Output Advancement Register 0, BOAR0 - Register 15, BOAR15
00C3HLocal BER Start Send Register, LBSSR
00C4HLocal Transmit BER Length Register, LTXBLR
00C5HLocal Receive BER Length Register, LRXBLR
00C6HLocal BER Start Receive Register, LBSRR
Table 12 - Address Map for Register (A14 = 0)
MT90871 Data Sheet
35
Zarlink Semiconductor Inc.
13.0 Detailed Register Description
This section describes the registers that are used in the device.
13.1 Control Register (CR)
Address 0000h.
The Control Register defines which memory is to be accessed, initiates the memory block programming mode,
sets the applied clock and frame pulse conditions, and enables stream outputs. The Control Register (CR) is
configured as follows:
00C7HLocal BER Count Register, LBCR
00C8HBackplane BER Start Send Register, BBSSR
00C9HBackplane Transmit BER Length Register, BTXBLR
00CAHBackplane Receive BER Length Register, BRXBLR
00CBHBackplane BER Start Receive Register, BBSRR
00CCHBackplane BER Count Register, BBCR
00CDH - 00DCHLocal Input Bit rate Register 0, LIBRR0 - Register 15, LIBRR15
00EDH - 00FCHLocal Output Bit rate Register 0, LOBRR0 - Register 15, LOBRR15
010DH - 011CHBackplane Input Bit rate Register 0, BIBRR0 - Register 15, BIBRR15
012DH - 013CHBackplane Output Bit rate Register 0, BOBRR0 - Register 15, BOBRR15
014DHMemory BIST Register, MBISTR
3FFFHRevision control register, RCR
Bit Name Reset Description
15-9 Reserved 0 Reserved.
8FPW 0
Frame Pulse Width
When LOW, an input frame pulse width of 122 ns shall be applied to FP8i. When
HIGH, an input frame pulse width of 244 ns shall be applied to FP8i.
7 Reserved 0 Reserved. Must be set LOW.
6C8IPOL 08MHz Input Clock Polarity
The input frame boundary MUST be aligned to the C8i clock rising edge. This bit,
C8IPOL, MUST be set HIGH to achieve correct frame boundary alignment. If this
bit is LOW, the input frame boundary alignment will not work correctly.
Table 13 - Control Register Bits
A14 - A0 Register
Table 12 - Address Map for Register (A14 = 0) (continued)
MT90871 Data Sheet
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Zarlink Semiconductor Inc.
5 COPOL 0
Output Clock Polarity
When set LOW, the output clock is the same polarity as the input clock. When set
HIGH, the output clock is inverted. This applies to both 8 MHz (C8o)and 16 MHz
(C16o) output clocks.
4MBP 0
Memory Block Programming
When LOW, the memory block programming mode is disabled. When HIGH, the
connection memory block programming mode is ready to program the Local
Connection Memory (LCM), and the Backplane Connection Memory (BCM).
3OSB 0
Output Stand By
This bit enables the BSTo0 - 15 and the LSTo0 - 15 serial outputs.
When LOW, the BSTo0-15 and LSTo0-15 are driven high or high impedance,
dependent on the BORS and LORS pin settings respectively, and BCSTo0-1 and
LCSTo0-1 are driven low. When HIGH, the BSTo0-15, LSTo0-15, BCSTo0-1 and
LCSTo0-1 are enabled.
2-0 MS(2:0) 0 Memory Select Bits.
These three bits select the connection or data memory for subsequent micro-port
memory access operations:
000, Local Connection Memory (LCM) is selected for Read or Write operations.
001, Backplane Connection Memory (BCM) is selected for Read or Write
operations. 010, Local Data Memory is selected for Read-only operation. 011,
Backplane Data Memory is selected for Read-only operation.
Bit Name Reset Description
Table 13 - Control Register Bits (continued)
ODE Pin OSB bit BSTo0 - 15, LSTo0 - 15
0 X Disable
1 0 Disable
1 1 Enable
MT90871 Data Sheet
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Zarlink Semiconductor Inc.
Figure 17 - Frame Boundary Conditions, ST- BUS Operation
Figure 18 - Frame Boundary Conditions, GCI - BUS Operation
13.2 Block Programming Register (BPR)
Address 0001h.
The block programming register stores the bit patterns to be loaded into the connection memories when the
Memory Block Programming feature is enabled. The BPE, LBPD2-0 and BBPD2-0 bits in the BPR register must
be defined in the same write operation.
Frame Boundary
C8i
FP8i
Frame Pulse Width = 122 ns,
Control Register Bit8 (FPW) = 0
Control Register Bit6 (C8IPOL) = 1
(a)
Frame Pulse Width = 244 ns,
Control Register Bit8 (FPW) = 1
Control Register Bit6 (C8IPOL) = 1
(b)
C8i
FP8i
Frame Boundary
Pulse Width = 122 ns,
Control Register Bit8 (FPW) = 0
Control Register Bit6 (C8IPOL) = 1
(a)
Pulse Width = 244 ns,
Control Register Bit8 (FPW) = 1
Control Register Bit6 (C8IPOL) = 1
(b)
C8i
FP8i
C8i
FP8i
MT90871 Data Sheet
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Zarlink Semiconductor Inc.
The BPE bit is set HIGH, to commence the block programming operation. Programming is completed in one frame
period and may be instigated at any time within a frame.The BPE bit returns to LOW to indicate the block
programming function has completed.
When BPE is HIGH, no other bits of the BPR register must be changed for at least a single frame period, except to
abort the programming operation. The programming operation may be aborted by setting either BPE to LOW, or
the Control Register bit, MBP, to LOW.
The BPR register is configured as follows.
.
13.3 Bit Error Rate Test Control Register (BERCR)
Address 0002h.
The BER control register controls Backplane and Local port BER testing. It independently enables and disables
transmission and reception. It is configured as follows:
Bit Name Reset Description
15-7 Unused 0 Set LOW.
6-4 BBPD(2:0) 0 Backplane Block Programming Data.
These bits refer to the value loaded into the Backplane Connection Memory
(BCM) when the Memory Block Programming feature is activated. When the
MBP bit in the Control Register (CR) is set HIGH and the BPE is set HIGH, the
contents of Bits BBPD2-0 are loaded into Bits 15-13, respectively, of the BCM.
Bits 12-0 of the BCM are set LOW.
3-1 LBPD(2:0) 0 Local block Programming Data.
These bits refer to the value loaded into the Local Connection Memory (LCM),
when the Memory Block Programming feature is activated. When the MBP bit in
the Control Register is set HIGH and the BPE is set HIGH, the contents of Bits
LBPD2-0 are loaded into Bits 15-13, respectively, of the LCM.
Bits 12-0 of the LCM are set LOW.
0 BPE 0 Block Programming Enable.
A LOW to HIGH transition of this bit enables the Memory Block Programming
function. A LOW will be returned after 125 us, upon completion of
programming.
Set LOW to abort the programming operation.
Table 14 - Block Programming Register Bits
Bit Name RESET Description
15-12 Reserved 0 Reserved.
11 LOCKB 0 Backplane Lock (READ ONLY).
This bit is automatically set HIGH when the receiver has locked to the
incoming data sequence. The bit is reset by a LOW to HIGH transition on
SBERRXB.
10 PRSTB 0 PBER Reset for Backplane.
A LOW to HIGH transition initializes the Backplane BER generator to the
seed value.
Table 15 - Bit Error Rate Test Control Register (BERCR) Bits
MT90871 Data Sheet
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Zarlink Semiconductor Inc.
9 CBERB 0 Clear Bit Error Rate Register for Backplane.
A LOW to HIGH transition in this bit resets the Backplane internal bit error
counter and the Backplane bit error (BBERR) register to zero.
8 SBERRXB 0 Start Bit Error Rate Receiver for Backplane.
A LOW to HIGH transition enables the Backplane BER receiver. The receiver
monitors incoming data for reception of the seed value. When detected, the
LOCK state is indicated (LOCKB) and the receiver compares the incoming bits
with the reference generator for bit equality and increments the Backplane Bit
error Register (BBCR) on each failure. When set LOW, bit comparison is
disabled and the error count is frozen. The error count is stored in the
Backplane Bit Error Register (BBCR).
7 SBERTXB 0 Start Bit Error Rate Transmitter for Backplane.
A LOW to HIGH transition starts the BER transmission. When set LOW,
transmission is disabled.
6 PRBSB 0 BER Mode Select for Backplane.
When set HIGH, a PRBS sequence of length 223-1 is selected for the
Backplane port. When set LOW, a PRBS sequence of length 215-1 is selected
for the Backplane port.
5LOCKL 0 Local Lock (READ ONLY).
This bit is automatically set HIGH when the receiver has locked to the
incoming data sequence. The bit is reset by a LOW to HIGH transition on
SBERRXL
4PRSTL 0 PBER Reset for Local.
A LOW to HIGH transition initializes the Local BER generator to the seed
value.
3 CBERL 0 Clear Bit Error Rate Register for Local.
A LOW to HIGH transition resets the Local internal bit error counter and the
Local bit error (LBERR) register to zero.
2 SBERRXL 0 Start Bit Error Rate Receiver for Local.
A LOW to HIGH transition enables the Local BER receiver. The receiver
monitors incoming data for reception of the seed value. When detected, the
LOCK state is indicated (LOCKL) and the receiver compares the incoming bits
with the reference generator for bit equality and increments the Local Bit error
Register (LBCR) on each failure. When set LOW, bit comparison is disabled
and the error count is frozen. The error count is stored in the Local Bit Error
Register (LBCR).
1 SBERTXL 0 Start Bit Error Rate Transmitter for Local.
A LOW to HIGH transition enables the Local BER transmission. When set
LOW, transmission is disabled.
0 PRBSL 0 BER Mode Select for Local.
When set HIGH, a PRBS sequence of length 223-1 is selected for the Local
port. When set LOW, a PRBS sequence of length 215-1 is selected for the
Local port.
Bit Name RESET Description
Table 15 - Bit Error Rate Test Control Register (BERCR) Bits (continued)
MT90871 Data Sheet
40
Zarlink Semiconductor Inc.
13.4 Local Input Channel Delay Registers (LCDR0 to LCDR15)
Address 0003h to 0012h.
Sixteen Local input channel delay registers (LCDR0 to LCDR15) allow users to program the input channel delay
for the Local input data streams LSTi0-15. The possible adjustment is 255 channels and the LCDR0 to LCDR15
registers are configured as follows:
:
13.4.1 Local Channel Delay Bits 7-0 (LCD7 - LCD0)
These eight bits define the delay, in channel numbers, the serial interface receiver takes to store the channel
data from the Local stream input pins. The input channel delay can be set to 255 (16 Mb/s streams), 127
(8 Mb/s streams), 63 (4 Mb/s streams) or 31 (2 Mb/s streams) from the frame boundary.
13.5 Local Input Bit Delay Registers (LIDR0 to LIDR15)
Address 0023h to 0032h.
Sixteen Local input delay registers (LIDR0 to LIDR15) allow users to program the input bit delay for the Local input
data streams LSTi0-15. The possible adjustment is up to 7 3/4 of the data rate, advancing forward with a resolution
of 1/4 of the data rate. The data rate can be either 2 Mb/s, 4 Mb/s, 8 Mb/s or 16 Mb/s.
LCDRn Bit
(where n = 0 to 15) Name Reset Description
15-8 Reserved 0 Reserved
7-0 LCD(7:0) 0 Local Channel Delay Register
The binary value of these bits refers to the channel delay value for the
Local input stream.
Table 16 - Local Channel Delay Register (LCDRn) Bits
Input Stream
Channel Delay
Corresponding
Delay Bits
LCD7-LCD0
0 Channel (Default) 0000 0000
1 Channel 0000 0001
2 Channels 0000 0010
3 Channels 0000 0011
4 Channels 0000 0100
5 Channels 0000 0101
... ...
... ...
253 Channels 1111 1101
254 Channels 1111 1110
255 Channels 1111 1111
Table 17 - Local Input Channel Delay Programming Table
MT90871 Data Sheet
41
Zarlink Semiconductor Inc.
The LIDR0 to LIDR15 registers are configured as follows:
13.5.1 Local Input Delay Bits 4-0 (LID4 - LID0)
These five bits define the delay from the bit boundary that the receiver uses to sample each input. Input bit delay
adjustment can range up to 73/4 bit periods forward, with resolution of 1/4 bit period.
This can be described as: LIDn(4:0) = (no. of bits delay) / 4.
For example, if LIDn(4:0) is set to 10011 (19), the input bit delay = 19 * 1/4 = 43/4.
Table 19 "Local Input Bit Delay Programming Table" illustrates the bit delay selection.
LIDRn Bit
(where n = 0 to 15) Name Reset Description
15-5 Reserved 0 Reserved
4-0 LIDn(4:0) 0 Local Input Bit Delay Register
The binary value of these bits refers to the input bit delay value for the
Local input stream
Table 18 - Local Channel Delay Register (LIDRn) Bits
Corresponding Delay Bits
Data Rate LID4 LID3 LID2 LID1 LID0
0 (Default) 00000
1/4 00001
1/2 00010
3/4 00011
1 00100
1 1/4 00101
1 1/2 00110
1 3/4 00111
2 01000
2 1/4 01001
2 1/2 01010
2 3/4 01011
3 01100
3 1/4 01101
3 1/2 01110
3 3/4 01111
4 10000
4 1/4 10001
Table 19 - Local Input Bit Delay Programming Table
MT90871 Data Sheet
42
Zarlink Semiconductor Inc.
13.6 Backplane Input Channel Delay Registers (BCDR0 to BCDR15)
Address 0043h to 0052h
Sixteen Backplane input channel delay registers (BCDR0 to BCDR15) allow users to program the input channel
delay for the Backplane input data streams BSTi0-15. The possible adjustment is 255 channels and the BCDR0 to
BCDR15 registers are configured as follows:
13.6.1 Backplane Channel Delay Bits 8-0 (BCDn8 - BCDn0)
These eight bits define the delay, in channel numbers, the serial interface receiver takes to store the channel data
from the Backplane stream input pins. The input channel delay can be set to 255 (16 Mb/s streams), 127 (8 Mb/s
streams), 63 (4 Mb/s streams) or 31 (2 Mb/s streams) from the frame boundary.
4 1/2 10010
4 3/4 10011
5 10100
5 1/4 10101
5 1/2 10110
5 3/4 10111
6 11000
6 1/4 11001
6 1/2 11010
6 3/4 11011
7 11100
7 1/4 11101
7 1/2 11110
7 3/4 11111
BCDRn Bit
(where n = 0 to 15 ) Name Reset Description
15-8 Reserved 0 Reserved
7-0 BCD(7:0) 0 Backplane Channel Delay Register
The binary value of these bits refers to the channel
delay value for the Backplane input stream
Table 20 - Backplane Channel Delay Register (BCDRn) Bits
Corresponding Delay Bits
Data Rate LID4 LID3 LID2 LID1 LID0
Table 19 - Local Input Bit Delay Programming Table (continued)
MT90871 Data Sheet
43
Zarlink Semiconductor Inc.
13.7 Backplane Input Bit Delay Registers (BIDR0 to BIDR15)
Address 0063h to 0072h
Sixteen Backplane input delay registers (BIDR0 to BIDR15) allow users to program the input bit delay for the
Backplane input data streams BSTi0-15. The possible adjustment is 7 3/4 of the data rate, in steps of 1/4 of the data
rate. The data rate can be either 2 Mb/s, 4 Mb/s, 8 Mb/s, or 16 Mb/s.
The BIDR0 to BIDR15 registers are configured as follows:
13.7.1 Backplane Input Delay Bits 4-0 (BID4 - BID0 )
These five bits define how long in the cycle the serial interface receiver takes to recognize and stores the bit 0 from
the BSTi input pins: i.e., start assuming a new frame. Input bit delay adjustment can range up to 73/4 bit periods
forward with resolution of 1/4 bit period.
This can be described as BIDn(4:0) = (no. of bits delay) / 4
For example, if BID(4:0) is set to 10011 (19), the input bit delay = 19 * 1/4 = 43/4.
Table 23 illustrates the bit delay selection.
Input Stream
Channel Delay
Corresponding Delay Bits
BCD7-BCD0
0 Channel (Default) 0000 0000
1 Channel 0000 0001
2 Channels 0000 0010
3 Channels 0000 0011
4 Channels 0000 0100
5 Channels 0000 0101
... ...
... ...
253 Channels 1111 1101
254 Channels 1111 1110
255 Channels 1111 1111
Table 21 - Backplane Input Channel Delay (BCD) Programming Table
BIDRn Bit
(where n = 0 to 15) Name Reset Description
15-5 Reserved 0 Reserved
4-0 BID(4:0) 0 Backplane Input Bit Delay Register
The binary value of these bits refers to the input
bit delay value for the Backplane input stream
Table 22 - Backplane Input Bit Delay Register (BIDRn) Bits
MT90871 Data Sheet
44
Zarlink Semiconductor Inc.
Corresponding Delay Bits
Data Rate BID4 BID3 BID2 BID1 BID0
0 (Default) 0 0 0 0 0
1/4 00001
1/2 00010
3/4 00011
1 00100
1 1/4 00101
1 1/2 00110
1 3/4 00111
2 01000
2 1/4 01001
2 1/2 01010
2 3/4 01011
3 01100
3 1/4 01101
3 1/2 01110
3 3/4 01111
4 10000
4 1/4 10001
4 1/2 10010
4 3/4 10011
5 10100
5 1/4 10101
5 1/2 10110
5 3/4 10111
6 11000
6 1/4 11001
6 1/2 11010
6 3/4 11011
7 11100
7 1/4 11101
7 1/2 11110
7 3/4 11111
Table 23 - Backplane Input Bit Delay Programming Table
MT90871 Data Sheet
45
Zarlink Semiconductor Inc.
13.8 Local Output Advancement Registers (LOAR0 to LOAR15)
Address 0083h to 0092h.
Sixteen Local output advancement registers (LOAR0 to LOAR15) allow users to program the output advancement
for output data streams LSTo0 to LSTo15. The possible adjustment is -2, -4 or -6 cycles of the internal system clock
(131.072 MHz).
The LOAR0 to LOAR15 registers are configured as follows:
13.8.1 Local Output Advancement Bits 1-0 (LOA1-LOA0)
The binary value of these two bits is the amount of offset that a particular stream output can be advanced. When
the advancement is 0, the serial output stream has the normal alignment with the Local frame pulse.
13.9 Backplane Output Advancement Registers (BOAR0 - 15)
Address 00A3h to 00B2h
Sixteen Backplane Output Advancement Registers (BOAR0 to BOAR15) allow users to program the output
advancement for output data streams BSTo0 to BSTo15. For 2 Mb/s, 4 Mb/s, 8 Mb/s and 16 Mb/s stream operation
the possible adjustment is -2, -4 or -6 cycles of the internal system clock (131.072 MHz).
The BOAR0 to BOAR15 registers are configured as follows:
LOARn Bit
(where n = 0 to 15) Name Reset Description
15-2 Reserved 0 Reserved
1-0 LOA(1:0) 0 Local Output Advancement Register
Table 24 - Local Output Advancement Register (LOARn) Bits
Local Output Advancement Corresponding Advancement Bits
Clock Rate 131.072 MHz LOA1 LOA0
0 (Default) 0 0
-2 cycle 0 1
-4 cycles 1 0
-6 cycles 1 1
Table 25 - Local Output Advancement (LOAR) Programming Table
BOARn Bit
(where n = 0 to 15 ) Name Reset Description
15-2 Reserved 0 Reserved
1:0 BOA(1:0) 0 Backplane Output Advancement Register
Table 26 - Backplane Output Advancement Register (BOAR) Bits
MT90871 Data Sheet
46
Zarlink Semiconductor Inc.
13.9.1 Backplane Output Advancement Bits 1-0 (BOA1-BOA0)
The binary value of these two bits is the amount of offset that a particular stream output can be advanced. When
the advancement is 0, the serial output stream has the normal alignment with the Backplane frame pulse.
13.10 Local Bit Error Rate (BER) Registers
13.10.1 Local BER Start Send Register (LBSSR)
Address 00C3h.
Local BER Start Send Register defines the output channel and the stream in which the BER sequence starts to
be transmitted. The LBSSR register is configured as follows:
13.10.2 Local Transmit BER Length Register (LTXBLR)
Address 00C4h
Local BER Transmit Length Register (LTXBLR) defines how many channels the BER sequence will be transmitted
during each frame. The LTXBLR register is configured as follows:
Backplane Output Advancement For
2 Mb/s, 4 Mb/s, 8 Mb/s & 16 Mb/s
Corresponding
Advancement Bits
Clock Rate 131.072 MHz BOA1 BOA0
0 (Default) 0 0
-2 cycle 0 1
-4 cycles 1 0
-6 cycles 1 1
Table 27 - Backplane Output Advancement (BOAR) Programming Table
Bit Name Reset Description
15-13 Reserved 0 Reserved.
12-8 LBSSA(4:0) 0 Local BER Send Stream Address Bits.
The binary value of these bits refers to the Local output stream
which carries the BER data.
7-0 LBSCA(7:0) 0 Local BER Send Channel Address Bits.
The binary value of these bits refers to the Local output channel in
which the BER data starts to be sent.
Table 28 - Local BER Start Send Register (LBSSR) Bits
Bit Name Reset Description
15-8 Reserved 0 Reserved.
Table 29 - Local Transmit BER Length Register (LTXBLR) Bits
MT90871 Data Sheet
47
Zarlink Semiconductor Inc.
13.10.3 Local Receive BER Length Register (LRXBLR)
Address 00C5h
Local BER Receive Length Register (LRXBLR) defines how many channels the BER sequence will be received
during each frame. The LRXBLR register is configured as follows:
13.10.4 Local BER Start Receive Register (LBSRR)
Address 00C6h
Local BER Start Receive Register defines the Input Stream and Start Channel and the stream in which the BER
sequence shall be received. The LBSRR register is configured as follows:
7-0 LTXBL(7:0) 0
Local Transmit BER Length Bits
The binary value of these bits define the number of channels in addition to the
Start Channel that the BER data will be transmitted on. (i.e., Total Channels =
Start Channel + LTXBL value)
Bit Name Reset Description
15-8 Reserved 0 Reserved.
7-0 LRXBL(7:0) 0 Local Receive BER Length Bits
The binary value of these bits define the number of channels in addition to the
Start Channel allocated for the BER receiver. (i.e., Total Channels = Start
Channel + LRXBL value)
Table 30 - Local Receive BER Length Register (LRXBLR) Bits
Bit Name Reset Description
15-13 Reserved 0 Reserved.
12-8 LBRSA(4:0) 0
Local BER Receive Stream Address Bits
The binary value of these bits refers to the Local input stream to receive
the BER data.
7-0 LBRCA(7:0) 0
Local BER Receive Channel Address Bits
The binary value of these bits refers to the Local input Start Channel in
which the BER data will be received.
Table 31 - Local BER Start Receive Register (LBSRR) Bits
Bit Name Reset Description
Table 29 - Local Transmit BER Length Register (LTXBLR) Bits
MT90871 Data Sheet
48
Zarlink Semiconductor Inc.
13.10.5 Local BER Count Register (LBCR)
Address 00C7h
Local BER Count Register contains the number of counted errors. This register is read only. The LBCR register is
configured as follows:
13.11 Backplane Bit Error Rate (BER) Registers
13.11.1 Backplane BER Start Send Register (BBSSR)
Address 00C8h
Backplane BER Start Send Register defines the output channel and the stream in which the BER sequence is
transmitted. The BBSSR register is configured as follows:
13.11.2 Backplane Transmit BER Length Register (BTXBLR)
Address 00C9h
Backplane Transmit BER Length Register (BTXBLR) defines how many channels in each frame the BER sequence
will be transmitted. The BTXBLR register is configured as follows:
Bit Name Reset Description
15-0 LBC(15:0) 0
Local Bit Error Rate Count
The binary value of the bits define the Local Bit Error count.
Table 32 - Local BER Count Register (LBCR) Bits
Bit Name Reset Description
15-13 Reserved 0 Reserved.
12-9 BBSSA(3:0) 0
Backplane BER Send Stream Address Bits
The binary value of these bits define the Backplane output stream to
transmit the BER data.
8-0 BBSCA(8:0) 0
Backplane BER Send Channel Address Bits
The binary value of these bits define the Backplane output Start
Channel in which the BER data is transmitted.
Table 33 - Backplane BER Start Send Register (BBSSR) Bits
Bit Name Reset Description
15-8 Reserved 0 Reserved.
7-0 BTXBL(7:0) 0
Backplane Transmit BER Length Bits
The binary value of these bits define the number of channels in addition to the
Start Channel allocated for the BER Transmitter. (i.e., Total Channels = Start
Channel + BTXBL value)
Table 34 - Backplane Transmit BER Length (BTXBLR) Bits
MT90871 Data Sheet
49
Zarlink Semiconductor Inc.
13.11.3 Backplane Receive BER Length Register (BRXBLR)
Address 00CAh
Backplane Receive BER Length Register (BRXBLR) defines how many channels in each frame the BER sequence
will be transmitted. The BRXBLR register is configured as follows:
13.11.4 Backplane BER Start Receive Register (BBSRR)
Address 00CBh
Backplane BER Start Receive Register defines the Input Stream and the Start Channel in which the BER sequence
shall be received. The BBSRR register is configured as follows:
13.11.5 Backplane BER Count Register (BBCR)
Address 00CCh
Backplane BER Count Register contains the number of counted errors. This register is read only. The BBCR
register is configured as follows:
Bit Name Reset Description
15-8 Reserved 0 Reserved.
7-0 BRXBL(7:0) 0
Backplane Receive BER Length Bits
The binary value of these bits define the number of channels in addition to
the Start Channel allocated for the BER receiver. (i.e., Total Channels = Start
Channel + BRXBL value)
Table 35 - Backplane Receive BER Length (BRXBLR) Bits
Bit Name Reset Description
15-13 Reserved 0 Reserved.
12-9 BBRSA(3:0) 0
Backplane BER Receive Stream Address Bits
The binary value of these bits defines the Backplane input stream that
receives the BER data.
8-0 BBRCA(8:0) 0
Backplane BER Receive Channel Address Bits
The binary value of these bits define the Backplane input Start Channel in
which the BER data will be received.
Table 36 - Backplane BER Start Receive Register (BBSRR) Bits
Bit Name Reset Description
15-0 BBC(15:0) 0
Backplane Bit Error Rate Count
The binary value of these bits define the Backplane Bit Error count.
Table 37 - Backplane BER Count Register (BBCR) Bits
MT90871 Data Sheet
50
Zarlink Semiconductor Inc.
13.12 Local Bit Rate Registers
13.12.1 Local Input Bit Rate Registers (LIBRR0-15)
Address 00CDh to 00DCh.
Sixteen Local Input Bit Rate Registers allow the bit rate for each individual stream to be set to 2, 4, 8 or
16 Mb/s. The LIBRR registers are configured as follows:
13.12.2 Local Output Bit Rate Resisters (LOBRR0-15)
Address 00EDh to 00FCh.
Sixteen Local Output Bit Rate Registers allow the bit rate for each individual stream to be set to 2, 4, 8 or 16 Mb/s.
The LOBRR registers are configured as follows:
LIBRn
(for n=0 to 15) Name Reset Description
15-2 Reserved 0 Reserved
1-0 LIBR(1:0) 0 Local Input Bit Rate
Table 38 - Local Input Bit Rate Register (LIBRRn) Bits
LIBR1 LIBR0 Bit rate for stream n
00 2 Mb/s
01 4 Mb/s
10 8 Mb/s
11 16 Mb/s
Table 39 - Local Input Bit Rate (LIBR) Programming Table
LOBRn Bit
(where n = 0 to 15) Name Reset Description
15-2 Reserved 0 Reserved
1-0 LOBR(1:0) 0 Local Output Bit Rate
Table 40 - Local Output Bit Rate Register (LOBRRn) Bits
LOBR1 LOBR0 Bit rate for stream n
00 2Mb/s
01 4Mb/s
10 8Mb/s
11 16Mb/s
Table 41 - Output BitRate (LOBR) Programming Register
MT90871 Data Sheet
51
Zarlink Semiconductor Inc.
13.13 Backplane Bit Rate Registers
13.13.1 Backplane Input Bit Rate Registers (BIBRR0-15)
Address 010Dh to 011Ch
Sixteen Backplane Input Bit Rate Registers allow the bit rate for each individual stream to be set to 2, 4, 8 or
16 Mb/s. The BIBRR registers are configured as follows:
13.13.2 Backplane Output Bit Rate Registers (BOBRR0-15)
Address 012Dh to 013Ch
Sixteen Backplane Output Bit Rate Registers allow the bit rate for each individual stream to be set to 2, 4, 8 or
16 Mb/s. The BOBRR registers are configured as follows:
BIBRn Bit
(for n=0 to 15) Name Reset Description
15-2 Reserved 0 Reserved
1-0 BIBR(1:0) 0
Backplane Input Bit Rate
Table 42 - Backplane Input Bit Rate Register (BIBRRn) Bits
BIBR1 BIBR0 Bit rate for stream n
00 2Mb/s
01 4Mb/s
10 8Mb/s
11 16Mb/s
Table 43 - Backplane Input Bit Rate (BIBR) Programming Table
BOBRn Bit
(for n=0 to 15) Name Reset Description
15-2 Reserved 0 Reserved
1-0 BOBR(1:0) 0 Backplane Output Bit Rate
Table 44 - Backplane Output Bit Rate Register (BOBRRn) Bits
BOBR1 BOBR0 Bit rate for stream n
00 2 Mb/s
01 4 Mb/s
10 8 Mb/s
11 16 Mb/s
Table 45 - Backplane Output Bit Rate (BOBRR) Programming Table
MT90871 Data Sheet
52
Zarlink Semiconductor Inc.
13.14 Memory BIST Register
Address 014Dh
The Memory BIST register enables the built-in-self-test function for the on-chip memory testing. Two consecutive
write operations are required to start MBIST. The first with only Bit 12 (LV_TM) set High (i.e., 1000h), the second
with Bit 12 maintained High but with the required start bit(s) set High.
The MBISTR register is configured as follows:
Bit Name Reset Description
15-13 Reserved 0 Reserved.
12 LV_TM 0
MBIST Test enable.
High for MBIST mode, Low for scan mode.
11 BISTSDB 0
Backplane Data Memory Start BIST sequence.
Sequence enabled on LOW to HIGH transition.
10 BISTCDB 0
Backplane Data Memory BIST sequence completed. (Read only).
High indicates completion of Memory BIST sequence.
9BISTPDB 0
Backplane Data Memory Pass/Fail Bit (Read only).
This bit indicates the Pass/Fail status following completion of the Memory BIST
sequence. A HIGH indicates Pass, a LOW indicates Fail.
8BISTSDL 0
Local Data Memory Start BIST sequence.
Sequence enabled on LOW to HIGH transition.
7 BISTCDL 0
Local Data Memory BIST sequence completed. (Read only).
High indicates completion of Memory BIST sequence.
6BISTPDL 0
Local Data Memory Pass/Fail Bit (Read only).
This bit indicates the Pass/Fail status following completion of the Memory BIST
sequence. A HIGH indicates Pass, a LOW indicates Fail.
5BISTSCB 0
Backplane Connection Memory Start BIST sequence.
Sequence enabled on LOW to HIGH transition.
4 BISTCCB 0
Backplane Connection Memory BIST sequence completed. (Read only).
High indicates completion of Memory BIST sequence.
3BISTPCB 0
Backplane Connection Memory Pass/Fail Bit (Read only).
This bit indicates the Pass/Fail status following completion of the Memory BIST
sequence. A HIGH indicates Pass, a LOW indicates Fail.
2BISTSCL 0
Local Connection Memory Start BIST sequence.
Sequence enabled on LOW to HIGH transition.
1 BISTCCL 0
Local Connection Memory BIST sequence completed. (Read only).
High indicates completion of Memory BIST sequence.
0BISTPCL 0
Local Connection Memory Pass/Fail Bit (Read only).
This bit indicates the Pass/Fail status following completion of the Memory BIST
sequence. A HIGH indicates Pass, a LOW indicates Fail.
Table 46 - Memory BIST Register (MBISTR) Bits
MT90871 Data Sheet
53
Zarlink Semiconductor Inc.
13.15 Revision Control Register
Address 3FFFh
The revision control register stores the binary value of the silicon revision number. This register is read only.
The RCR register is configured as follows:
Bit Name Reset Value Description
15-4 Reserved 0 Reserved.
3-0 RC(3:0) defined by silicon
Revision Control Bits.
Table 47 - Revision Control Register (RCR) Bits
MT90871 Data Sheet
54
Zarlink Semiconductor Inc.
DC Electrical Characteristics
*
Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Voltages are with respect to ground (VSS) unless otherwise stated.
Absolute Maximum Ratings*
Parameter Symbol Min. Max. Units
1 I/O Supply Voltage VDD_IO -0.5 5.0 V
2 Core Supply Voltage VDD_CORE -0.5 2.5 V
3 PLL Supply Voltage VDD_PLL -0.5 2.5 V
4 Input Voltage (non-5 V tolerant inputs) VI-0.5 VDD_IO +0.5 V
5 Input Voltage (5 V tolerant inputs) VI_5V -0.5 7.0 V
6 Continuous Current at digital outputs IO15 mA
7 Package power dissipation PD2W
8 Storage temperature TS- 55 +125 °C
Recommended Operating Conditions
Characteristics Sym. Min. Typ. Max. Units
1 Operating Temperature TOP -40 25 +85 °C
2 Positive Supply VDD_IO 3.0 3.3 3.6 V
3 Positive Supply VDD_CORE 1.62 1.8 1.98 V
4 Positive Supply VDD_PLL 1.62 1.8 1.98 V
5 Input Voltage VI03.3V
DD_IO V
6 Input Voltage on 5 V Tolerant Inputs VI_5V 055.5V
MT90871 Data Sheet
55
Zarlink Semiconductor Inc.
Voltages are with respect to ground (Vss) unless otherwise stated.
DC Electrical Parameters
Characteristics Sym. Min. Typ. Max. Units Test Conditions
1
S
U
P
P
L
I
E
S
Static Core Supply Current IDD-Core 4mAStatic I
DD_Core and
PLL current
2 Operating Core Supply Current IDD-Core 160 200 mA Applied clock
C8i = 8.192 MHz
3 Static Periphery Supply Current IDD_IO 100 µAStatic I
DD_IO
4 Operating Periphery Supply
Current
IDD_IO 55 mA IAV with all output
streams at max.
data-rate.
CLOAD = 50pF
5
I
N
P
U
T
S
Input High Voltage VIH 2.0 V
6 Input Low Voltage VIL 0.8 V
7
Input Leakage (input pins)
Input Leakage (bi-directional pins)
IIL
IBL
5
5
µA
µA
0 < VI < VDD_IO
8 Weak Pullup Current IPU -200 µA Input at 0V
9 Weak Pulldown Current IPD 200 µA Input at Vin = 5.5V
10 Input Pin Capacitance CI5pF
11 O
U
T
P
U
T
S
Output High Voltage VOH 2.4 V IOH = 10mA
12 Output Low Voltage VOL 0.4 V IOL = 10mA
13 High Impedance Leakage IOZ 5µA0 < V
O < VDD_IO
14 Output Pin Capacitance CO5pF
AC Electrical Characteristics Timing Parameter Measurement: Voltage Levels
Characteristics Sym. Level Units Conditions
1 CMOS Threshold VCT 0.5VDD_IO V 3.0V < VDD_IO < 3.6V
2 Rise/Fall Threshold Voltage High VHM 0.7VDD_IO V 3.0V < VDD_IO < 3.6V
3 Rise/Fall Threshold Voltage Low VLM 0.3VDD_IO V 3.0V < VDD_IO < 3.6V
MT90871 Data Sheet
56
Zarlink Semiconductor Inc.
Backplane and Local Clock Timing
Characteristic Sym. Min. Typ. Max. Units Notes
1 Backplane Frame Pulse Width tBFPW244
tBFPW122
tBGFPW
210
10
10
244
122
122
350
220
220
ns Fig. 19 &
Fig. 20
2 Backplane Frame Pulse Setup Time
before C8i clock rising edge
tBFPS244
tBFPS122
tBGFPS
5
5
5
110
110
110
ns
3 Backplane Frame Pulse Hold Time
from C8i clock rising edge
tBFPH244
tBFPH122
tBGFPH
5
5
5
110
110
110
ns
4C8i
Clock Period tBCP8 120 122 124 ns
5C8i
Clock Pulse Width High tBCH8 50 61 70 ns
6C8i
Clock Pulse Width Low tBCL8 50 61 70 ns
7C8i
Clock Rise/Fall Time trBC8i, tfBC8i 023ns
8C8i
Cycle to Cycle Variation tCVC8i 3ns
9 Local Frame Boundary Offset tLFBOS 7.5 ns CL=60pF
10 FP8o Width tLFPW8
tGFPW8
117
117
122
122
127
127
ns
CL=60pF
11 FP8o Output Delay
from edge to Local Frame Boundary
tFODF8
tGFPS8o
56
56
68
56
ns
12 FP8o Output Delay
from Local Frame Boundary to Edge
tFODR8
tGFPH8o
59
59
61
61
ns
13 C8o Clock Period tLCP8 117 127 ns
CL=60pF
14 C8o Clock Pulse Width High tLCH8 56 68 ns
15 C8o Clock Pulse Width Low tLCL8 59 61 ns
16 C8o Clock Rise/Fall Time trLC8o, tfLC8o 37ns
17 FP16o Width tFPW16 62 66 ns
CL=60pF
18 FP16o Output Delay
from Falling edge to Local Frame Boundary
tFODF16 -29 -36 ns
19 FP16o Output Delay
from Local Frame Boundary to Rising edge
tFODR16 30 33 ns
20 C16o Clock Period tLCP16 62 66 ns
CL=60pF
21 C16o Clock Pulse Width High tLCH16 29 36 ns
22 C16o Clock Pulse Width Low tLCL16 30 33 ns
23 C16o Clock Rise/Fall Time trLC16o,
tfLC16o
05ns
MT90871 Data Sheet
57
Zarlink Semiconductor Inc.
Figure 19 - Backplane and Local Clock Timing Diagram for ST-BUS
tBFPW122
tBFPH122
tBFPS122
CK_int *
tLFODR8
tLFODF8
tFODR16
tFODF16
tLCL8
tLCH8
tLCH16 tLCL16
tLCP8
tLCP16
trLC8o
tfLC8o
tfLC16o trLC16o
tLFBOS
* CK_int is the internal clock signal of 131.072 MHz
FP8o
C8o
FP16o
C16o
FP8i
C8i
tBCL8
tBCH8 tBCP8
trBC8i
tfBC8i
tLFPW8_244
tFODR8_244
tFODF8_244
tBFPW244
tBFPH244
tBFPS244
FP8i
FP8o
(244ns)
(122 ns)
(244 ns)
(122 ns)
t
LFPW8
tFPW16
MT90871 Data Sheet
58
Zarlink Semiconductor Inc.
Figure 20 - Backplane and Local Clock Timing for GCI-BUS
t
BGFPW
t
fBCi
t
BCH8
t
BCL8
t
rBCi
CK_int*
t
GFPW8
t
GFPH8o
t
GFPS8o
t
FRH16o
t
FRS16o
t
LCH8
t
LCL8
t
LCH16
t
LCL16
t
FPW16
t
LCP8
t
LCP16
t
BCP8
t
fLC8o
t
rLC8o
t
rLC16o
t
fLC16o
t
LFBOS
* CK_int is the internal clock signal of 131.072 MHz
FP8o
C8o
FP16o
C16o
FP8i
C8i
t
BGFPH
t
BGFPS
MT90871 Data Sheet
59
Zarlink Semiconductor Inc.
Figure 21 - ST-BUS Backplane Data Timing Diagram (8 Mb/s, 4 Mb/s, 2 Mb/s)
Backplane Data Timing
Characteristic Sym. Min. Typ. Max. Units Notes
1 Backplane Input data sampling
point
tBIDS16
tBIDS8
tBIDS4
tBIDS2
41
87
178
361
46
92
183
366
51
97
188
371
ns
2 Backplane Serial Input Set-up Time tBSIS16
tBSIS8
tBSIS4
tBSIS2
2.1
2.1
2.1
2.1
ns
3 Backplane Serial Input Hold Time tBSIH16
tBSIH8
tBSIH4
tBSIH2
3
3
3
3
ns
4 Backplane Serial Output Delay tBSOD16
tBSOD8
tBSOD4
tBSOD2
10.5
10.5
10.5
10.5
ns CL=50pF
CK_int *
BSTi0 - 15
BSTo0 - 15
tBIDS8
8.192 Mb/s
8.192 Mb/s
* CK_int is the internal clock signal of 131.072 MHz
FP8i
C8i
tBIDS4
tBIDS2
tBSIH8
tBSIS8
tBSIH4
tBSIS4
tBSIH2
tBSIS2
tBSOD2
tBSOD4
tBSOD8
BSTo0 - 15
4.096 Mb/s
BSTo0 - 15
2.048 Mb/s
BSTi0 - 15
4.096 Mb/s
BSTi0 - 15
2.048 Mb/s
Bit7
Ch0
Bit6
Ch0
Bit7
Ch0
Bit6
Ch0
Bit0
Ch31
Bit0
Ch63
Bit7
Ch0
Bit6
Ch0
Bit5
Ch0
Bit4
Ch0
Bit7
Ch0
Bit6
Ch0
Bit0
Ch31
Bit5
Ch0
Bit4
Ch0
Bit6
Ch0
Bit7
Ch0
Bit0
Ch63
Bit1
Ch127
Bit0
Ch127
Bit5
Ch0
Bit4
Ch0
Bit3
Ch0
Bit2
Ch0
Bit1
Ch0
65
04321
17
MT90871 Data Sheet
60
Zarlink Semiconductor Inc.
Figure 22 - ST-BUS Backplane Data Timing Diagram (16 Mb/s)
CK_int *
FP8i
C8i
tBIDS16
tBSIH16
tBSIS16
tBSOD16
BSTo0 - 15
16.384 Mb/s
BSTi0 - 15
16.384 Mb/s
Bit0
Ch255
Bit7
Ch0
Bit6
Ch0
Bit5
Ch0
Bit5
Ch0
Bit6
Ch0
Bit7
Ch0
Bit0
* CK_int is the internal clock signal of 131.072 MHz
Bit1
Ch 255
Ch 255
MT90871 Data Sheet
61
Zarlink Semiconductor Inc.
Figure 23 - GCI BUS Backplane Data Timing Diagram (8 Mb/s, 4 Mb/s, 2 Mb/s)
CK_int
*
BSTi0 - 15
BSTo0 - 15
t
BIDS8
8.192 Mb/s
8.192 Mb/s
* CK_int is the internal clock signal of 131.072 MHz
FP8i
C8i
t
BIDS4
t
BIDS2
t
BSIH8
t
BSIS8
t
BSIH4
t
BSIS4
t
BSIH2
t
BSIS2
t
BSOD2
t
BSOD4
t
BSOD8
BSTo0 - 15
4.096 Mb/s
BSTo0 - 15
2.048 Mb/s
BSTi0 - 15
4.096 Mb/s
BSTi0 - 15
2.048 Mb/s
Bit0
Ch0
Bit1
Ch0
Bit0
Ch0
Bit1
Ch0
Bit7
Ch31
Bit7
Ch63
Bit0
Ch0
Bit1
Ch0
Bit2
Ch0
Bit3
Ch0
Bit0
Ch0
Bit1
Ch0
Bit7
Ch31
Bit2
Ch0
Bit3
Ch0
Bit1
Ch0
Bit0
Ch0
Bit7
Ch63
Bit6
Ch127
Bit7
Ch127
Bit2
Ch0
Bit3
Ch0
Bit4
Ch0
Bit5
Ch0
Bit6
Ch0
12
73456
60
MT90871 Data Sheet
62
Zarlink Semiconductor Inc.
Figure 24 - GCI BUS Backplane Data Timing Diagram (16 Mb/s)
Local Clock Data Timing
Characteristic Sym. Min. Typ. Max. Units Notes
1 Local Frame Boundary Offset tLFBOS 15 ns CL=50pF
2 Input data sampling point tLIDS16
tLIDS8
tLIDS4
tLIDS2
41
87
178
361
46
92
183
366
51
97
188
371
ns
3 Local Serial Input Set-up Time tLSIS16
tLSIS8
tLSIS4
tLSIS2
2.1
2.1
2.1
2.1
ns
4 Local Serial Input Hold Time tLSIH16
tLSIH8
tLSIH4
tLSIH2
3
3
3
3
ns
5 Local Serial Output Delay tLSOD16
tLSOD8
tLSOD4
tLSOD2
10.5
10.5
10.5
10.5
ns CL=50pF
CK_int *
FP8i
C8i
t
BIDS16
t
BSIH16
t
BSIS16
t
BSOD16
BSTo0 - 15
16.384 Mb/s
BSTi0 - 15
16.384 Mb/s
Bit7
Ch255
Bit0
Ch0
Bit1
Ch0
Bit2
Ch0
Bit2
Ch0
Bit1
Ch0
Bit0
Ch0
* CK_int is the internal clock signal of 131.072 MHz
Ch255Ch255
Bit6 Bit7
MT90871 Data Sheet
63
Zarlink Semiconductor Inc.
Figure 25 - ST-BUS Local Timing Diagram (8 Mb/s, 4 Mb/s, 2 Mb/s)
CK_int *
LSTi0 - 15
LSTo0 - 15
tLIDS8
8.192 Mb/s
8.192 Mb/s
tLFBOS
FP8i
C8i
tLIDS4
tLIDS2
tLSIH8
tLSIS8
tLSIH4
tLSIS4
tLSIH2
tLSIS2
tLSOD2
tLSOD4
tLSOD8
LSTo0 - 15
4.096 Mb/s
LSTo0 - 15
2.048 Mb/s
LSTi0 - 15
4.096 Mb/s
LSTi0 - 15
2.048 Mb/s
Bit7
Ch0
Bit6
Ch0
Bit7
Ch0
Bit6
Ch0
Bit0
Ch31
Bit0
Ch63
Bit7
Ch0
Bit6
Ch0
Bit5
Ch0
Bit4
Ch0
Bit7
Ch0
Bit6
Ch0
Bit0
Ch31
Bit5
Ch0
Bit4
Ch0
Bit6
Ch0
Bit7
Ch0
Bit0
Ch63
Bit1
Ch127
Bit0
Ch127
Bit5
Ch0
Bit4
Ch0
Bit3
Ch0
Bit2
Ch0
Bit1
Ch0
65
04321
17
* CK_int is the internal clock signal of 131.072 MHz
MT90871 Data Sheet
64
Zarlink Semiconductor Inc.
Figure 26 - ST-BUS Local Data Timing Diagram (16 Mb/s)
Note 1: High Impedance is measured by pulling to mid-rail with RL = 1K/1K potential divider, with timing corrected to cancel time taken
to discharge CL.
Figure 27 - Serial Output and External Control
Figure 28 - Output Driver Enable (ODE)
Backplane and Local Output High-Impedance Timing
Characteristic Sym. Min. Typ. Max. Units Test Conditions
1 STo delay - Active to High-Z
- High-Z to Active
tDZ
tZD
4
4
ns
ns
RL=1K, CL=50pF, See Note 1
2 Output Driver Enable (ODE)
Delay to Active Data
Output Driver Enable (ODE)
Delay to High-Impedance
tODE
tODZ
15
14
ns
ns
RL=1K, CL=50pF, See Note 1
RL=1K, CL=50pF, See Note 1
CK_int *
FP8i
C8i
tLIDS16
tLSIH16
tLSIS16
tLSOD16
LSTo0 - 15
16.384 Mb/s
LSTi0 - 15
16.384 Mb/s
Bit0
Ch255
Bit7
Ch0
Bit6
Ch0
Bit5
Ch0
Bit5
Ch0
Bit6
Ch0
Bit7
Ch0
Bit0
* CK_int is the internal clock signal of 131.072 MHz
Bit1
tLFBOS
Ch255
Ch255
tDZ
STo
tZD
STo
CLK VTT
VTT
HiZ
Valid Data
VTT
HiZ Valid Data
VTT
Hi-Z
Hi-Z
STo
ODE
tODZ
tODE
Valid Data
VTT
MT90871 Data Sheet
65
Zarlink Semiconductor Inc.
Note 1: High impedance is measured by pulling to mid-rail with RL = 1K/1K potential divider, with timing corrected to cancel time taken
to discharge CL.
Figure 29 - Motorola Non-Multiplexed Bus Timing
Note: There must be a minimum of 30 ns between CPU accesses, to allow the MT90869 device to recognize the
accesses as separate (i.e., a minimum of 30 ns must separate the de-assertion of DTA (to high) and the assertion
of CS and/or DS (to initiate the next access).
Non-Multiplexed Microprocessor Port Timing
Characteristics Sym. Min. Typ. Max. Units Test Conditions
1CS
setup from DS falling tCSS 0ns
2R/W
setup from DS falling tRWS 8ns
3 Address setup from DS falling tADS 8ns
4CS
hold after DS rising tCSH 0ns
5R/W
hold after DS rising tRWH 8ns
6 Address hold after DS rising tADH 8ns
7 Data setup from DTA Low on Read tDDR 14 ns CL=60pF
8 Data hold on read tDHR 30 ns CL=60pF, RL=1K, Note 1
9 Data setup on write tWDS 8ns
10 Data hold on write tDHW 8ns
11 Acknowledgment Delay:
Reading/Writing Registers
Reading/Writing Memory
tAKD
85
70
ns
ns
CL=60pF
CL=60pF
12 Acknowledgment Hold Time tAKH 12 ns CL=60pF, RL=1K, Note 1
A0-A14
D0-D15
D0-D15
READ
WRITE
tCSS tCSH
tADH
tDHR
tRWS
tADS
tRWH
tDHW
tAKD
tWDS
t
DDR
tAKH
V
TT
V
TT
V
TT
V
TT
V
TT
V
TT
V
TT
VALID ADDRESS
VALID READ DATA
VALID WRITE DATA
DTA
R/W
CS
DS
c Zarlink Semiconductor 2003 All rights reserved.
APPRD.
ISSUE
DATE
ACN
Package Code
Previous package codes:
Conforms to JEDEC MS - 034
Except dimensions 'A1' and 'b'.
2 LAYERS (4 LAYERS)
1. Controlling dimensions are in MM.
2. Seating plane is defined by the spherical crown of
3. Not to scale.
4. Ball arrangement: 14 x 14 array
the solder balls.
NOTES:-
A2
TOP VIEW
J
BOTTOM VIEW
SIDE VIEW
I
J
b
N
e
E
E1
I
D
D1
DIMENSION
A
A1 0.850.75
0.600.40
1.0 REF.
1.00 BSC
196
15.00 BSC
15.00 BSC
1.0 REF.
12.95
12.95
13.70
13.70
MIN
1.35 (1.55)
0.30
MAX
0.50
1.75 (1.97)
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