SN74HC74-Q1 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET SCLS577A - MARCH 2004 - REVISED APRIL 2008 D D D D D D D Qualified for Automotive Applications Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-A Max ICC Typical tpd = 15 ns 4-mA Output Drive at 5 V Low Input Current of 1 A Max D OR PW PACKAGE (TOP VIEW) 1CLR 1D 1CLK 1PRE 1Q 1Q GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE 2Q 2Q description/ordering information The SN74HC74 device contains two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. ORDERING INFORMATION{ -40C 40C to 125C ORDERABLE PART NUMBER PACKAGE TA TOP-SIDE MARKING SOIC - D Reel of 2500 SN74HC74QDRQ1 HC74Q TSSOP - PW Reel of 2000 SN74HC74QPWRQ1 HC74Q For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. FUNCTION TABLE INPUTS OUTPUTS PRE CLR CLK D Q Q L H X X H L H L X X L H L L X X H H H H H H L H H L L H H H L X Q0 Q0 This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2008, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN74HC74-Q1 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET SCLS577A - MARCH 2004 - REVISED APRIL 2008 logic diagram (positive logic) PRE CLK C C Q TG C C C C C D TG TG TG Q C C C CLR absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) VCC Supply voltage VIH High-level High level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V MIN NOM MAX 2 5 6 V 4.2 0.5 VCC = 4.5 V Low-level Low level input voltage V 1.5 3.15 VCC = 2 V VIL UNIT 1.35 VCC = 6 V V 1.8 VI Input voltage 0 VCC V VO Output voltage 0 VCC V t/v Input transition rise/fall time VCC = 2 V TA 1000 VCC = 4.5 V 500 VCC = 6 V 400 Operating free-air temperature -40 125 ns C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74HC74-Q1 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET SCLS577A - MARCH 2004 - REVISED APRIL 2008 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = -20 20 A VOH VI = VIH or VIL IOH = -4 mA IOH = -5.2 mA IOL = 20 A VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II VI = VCC or 0 ICC VI = VCC or 0, TA = 25C VCC IO = 0 MIN TYP MAX 2V 1.9 1.998 1.9 4.5 V 4.4 4.499 4.4 6V 5.9 5.999 5.9 4.5 V 3.98 4.3 3.7 6V 5.48 5.8 MAX UNIT V 5.2 2V 0.002 0.1 0.1 4.5 V 0.001 0.1 0.1 6V 0.001 0.1 0.1 4.5 V 0.17 0.26 0.4 6V 0.15 0.26 0.4 6V 0.1 100 1000 nA 4 80 A 3 10 10 pF 6V Ci MIN 2 V to 6 V V timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock Clock frequency PRE or CLR low tw Data tsu th 2V 6 31 Hold time,, data after CLK POST OFFICE BOX 655303 6V 0 36 MIN 21 0 2V 100 150 20 30 6V 17 25 2V 80 120 4.5 V 16 24 6V 14 20 2V 100 150 4.5 V 20 30 6V 17 25 2V 25 40 4.5 V 5 8 6V 4 7 2V 0 0 4.5 V 0 0 6V 0 0 * DALLAS, TEXAS 75265 MAX UNIT 4.2 4.5 V Setup time before CLK PRE or CLR inactive MAX 4.5 V Pulse duration CLK high or low TA = 25C MIN MHz 25 ns ns ns 3 SN74HC74-Q1 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET SCLS577A - MARCH 2004 - REVISED APRIL 2008 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax PRE or CLR Q or Q tpd CLK Q or Q tt Q or Q VCC TA = 25C MIN TYP MAX MIN 2V 6 10 4.2 4.5 V 31 50 21 6V 36 60 25 MAX UNIT MHz 2V 70 230 345 4.5 V 20 46 69 6V 15 39 59 2V 70 175 250 4.5 V 20 35 50 6V 15 30 42 2V 28 75 110 4.5 V 8 15 22 6V 6 13 19 ns ns operating characteristics, TA = 25C PARAMETER Cpd 4 TEST CONDITIONS Power dissipation capacitance per flip-flop POST OFFICE BOX 655303 No load * DALLAS, TEXAS 75265 TYP 35 UNIT pF SN74HC74-Q1 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET SCLS577A - MARCH 2004 - REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point VCC High-Level Pulse 50% 50% 0V CL = 50 pF (see Note A) tw VCC Low-Level Pulse LOAD CIRCUIT 50% 50% 0V VOLTAGE WAVEFORMS PULSE DURATIONS VCC VCC Reference Input 50% Input 50% 50% 0V 0V tsu Data Input 50% 10% 90% tr th tPLH 90% VCC 50% 10% 0 V In-Phase Output 90% 90% tr tf VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES 50% 10% tPHL tPHL Out-of-Phase Output 90% VOH 50% 10% VOL tf tPLH 50% 10% tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 12-Oct-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp SN74HC74QDRG4Q1 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC74QDRQ1 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC74QPWRG4Q1 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC74QPWRQ1 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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OTHER QUALIFIED VERSIONS OF SN74HC74-Q1 : Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 12-Oct-2011 * Catalog: SN74HC74 * Enhanced Product: SN74HC74-EP * Military: SN54HC74 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product * Enhanced Product - Supports Defense, Aerospace and Medical Applications * Military - QML certified for Military and Defense Applications Addendum-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. 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