SN74HC74-Q1
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOP
WITH CLEAR AND PRESET
SCLS577A − MARCH 2004 − REVISED APRIL 2008
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DQualified for Automotive Applications
DWide Operating Voltage Range of 2 V to 6 V
DOutputs Can Drive Up To 10 LSTTL Loads
DLow Power Consumption, 80-µA Max ICC
DTypical tpd = 15 ns
D±4-mA Output Drive at 5 V
DLow Input Current of 1 µA Max
description/ordering information
The SN74HC74 device contains two independent D-type positive-edge-triggered flip-flops. A low level at the
preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When
PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred
to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and
is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed
without affecting the levels at the outputs.
ORDERING INFORMATION{
TAPACKAGE‡ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
40°C to 125°C
SOIC − D Reel of 2500 SN74HC74QDRQ1 HC74Q
−40°C to 125°CTSSOP − PW Reel of 2000 SN74HC74QPWRQ1 HC74Q
†For the most current package and ordering information, see the Package Option Addendum at the end of
this document, or see the TI web site at http://www.ti.com.
‡Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
FUNCTION TABLE
INPUTS OUTPUTS
PRE CLR CLK D Q Q
L H X X H L
HLXXLH
LLXXH
†H†
H H ↑HHL
H H ↑LLH
H H L X Q0Q0
†This configuration is nonstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
VCC
2CLR
2D
2CLK
2PRE
2Q
2Q
D OR PW PACKAGE
(TOP VIEW)
Copyright 2008, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74HC74-Q1
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOP
WITH CLEAR AND PRESET
SCLS577A − MARCH 2004 − REVISED APRIL 2008
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
PRE
CLK
D
CLR
Q
Q
C
C
C
C
C
C
C
C
C
C
TG
TG TG TG
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN NOM MAX UNIT
VCC Supply voltage 2 5 6 V
VCC = 2 V 1.5
VIH High-level input voltage VCC = 4.5 V 3.15 V
VIH
High level
input
voltage
VCC = 6 V 4.2
V
VCC = 2 V 0.5
VIL Low-level input voltage VCC = 4.5 V 1.35 V
VIL
Low level
input
voltage
VCC = 6 V 1.8
V
VIInput voltage 0 VCC V
VOOutput voltage 0 VCC V
VCC = 2 V 1000
∆t/∆vInput transition rise/fall time VCC = 4.5 V 500 ns
∆t/∆v
Input
transition
rise/fall
time
VCC = 6 V 400
ns
TAOperating free-air temperature −40 125 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74HC74-Q1
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOP
WITH CLEAR AND PRESET
SCLS577A − MARCH 2004 − REVISED APRIL 2008
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
V
TA = 25°C
MIN
MAX
UNIT
PARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX UNIT
2 V 1.9 1.998 1.9
IOH = −20 µA4.5 V 4.4 4.499 4.4
VOH VI = VIH or VIL
IOH
20
µA
6 V 5.9 5.999 5.9 V
VOH
VI
VIH
or
VIL
IOH = −4 mA 4.5 V 3.98 4.3 3.7
V
IOH = −5.2 mA 6 V 5.48 5.8 5.2
2 V 0.002 0.1 0.1
IOL = 20 µA4.5 V 0.001 0.1 0.1
VOL VI = VIH or VIL
IOL
20
µA
6 V 0.001 0.1 0.1 V
VOL
VI
VIH
or
VIL
IOL = 4 mA 4.5 V 0.17 0.26 0.4
V
IOL = 5.2 mA 6 V 0.15 0.26 0.4
IIVI = VCC or 0 6 V ±0.1 ±100 ±1000 nA
ICC VI = VCC or 0, IO = 0 6 V 4 80 µA
Ci2 V to 6 V 3 10 10 pF
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
V
TA = 25°C
MIN
MAX
UNIT
VCC MIN MAX MIN MAX UNIT
2 V 6 4.2
fclock Clock frequency 4.5 V 31 21 MHz
fclock
Clock
frequency
6 V 0 36 0 25
MHz
2 V 100 150
PRE or CLR low 4.5 V 20 30
t
Pulse duration
PRE
or
CLR
low
6 V 17 25
ns
twPulse duration 2 V 80 120 ns
CLK high or low 4.5 V 16 24
CLK
high
or
low
6 V 14 20
2 V 100 150
Data 4.5 V 20 30
t
Setup time before CLK↑
Data
6 V 17 25
ns
tsu Setup time before CLK↑2 V 25 40 ns
PRE or CLR inactive 4.5 V 5 8
PRE
or
CLR
inactive
6 V 4 7
2 V 0 0
thHold time, data after CLK↑4.5 V 0 0 ns
h
,
6 V 0 0
SN74HC74-Q1
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOP
WITH CLEAR AND PRESET
SCLS577A − MARCH 2004 − REVISED APRIL 2008
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO
V
TA = 25°C
MIN
MAX
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT) VCC MIN TYP MAX MIN MAX UNIT
2 V 6 10 4.2
fmax 4.5 V 31 50 21 MHz
fmax
6 V 36 60 25
MHz
2 V 70 230 345
PRE or CLR Q or Q 4.5 V 20 46 69
t
PRE
or
CLR
Q
or
Q
6 V 15 39 59
ns
tpd 2 V 70 175 250 ns
CLK Q or Q 4.5 V 20 35 50
CLK
Q
or
Q
6 V 15 30 42
2 V 28 75 110
ttQ or Q 4.5 V 8 15 22 ns
t
QQ
6 V 6 13 19
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance per flip-flop No load 35 pF
SN74HC74-Q1
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOP
WITH CLEAR AND PRESET
SCLS577A − MARCH 2004 − REVISED APRIL 2008
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
th
tsu
50%
50%50% 10%10%
90% 90%
VCC
VCC
0 V
0 V
trtf
Reference
Input
Data
Input
50%
High-Level
Pulse 50%
VCC
0 V
50% 50%
VCC
0 V
tw
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
50%50% 10%10%
90% 90%
VCC
VOH
VOL
0 V
trtf
Input
In-Phase
Output
50%
tPLH tPHL
50% 50%
10% 10%
90%90% VOH
VOL
tr
tf
tPHL tPLH
Out-of-Phase
Output
Test
Point
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 12-Oct-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74HC74QDRG4Q1 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC74QDRQ1 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC74QPWRG4Q1 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC74QPWRQ1 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74HC74-Q1 :
PACKAGE OPTION ADDENDUM
www.ti.com 12-Oct-2011
Addendum-Page 2
•Catalog: SN74HC74
•Enhanced Product: SN74HC74-EP
•Military: SN54HC74
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
•Military - QML certified for Military and Defense Applications
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