© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 8
1Publication Order Number:
MC14516B/D
MC14516B
Binary Up/Down Counter
The MC14516B synchronous up/down binary counter is
constructed with MOS P−channel and N−channel enhancement mode
devices in a monolithic structure.
This counter can be preset by applying the desired value, in binary,
to the Preset inputs (P0, P1, P2, P3) and then bringing the Preset
Enable (PE) high. The direction of counting is controlled by applying
a high (for up counting) or a low (for down counting) to the
UP/DOWN input. The state of the counter changes on the positive
transition of the clock input.
Cascading can be accomplished by connecting the Carry Out to the
Carry In of the next stage while clocking each counter in parallel. The
outputs (Q0, Q1, Q2, Q3) can be reset to a low state by applying a high
to the reset (R) pin.
This CMOS counter finds primary use in up/down and difference
counting. Other applications include: (1) Frequency synthesizer
applications where low power dissipation and/or high noise immunity
is desired, (2) Analog−to−Digital and Digital−to−Analog conversions,
and (3) Magnitude and sign generation.
Features
•Diode Protection on All Inputs
•Supply Voltage Range = 3.0 Vdc to 18 Vdc
•Internally Synchronous for High Speed
•Logic Edge−Clocked Design — Count Occurs on Positive Going
Edge of Clock
•Single Pin Reset
•Asynchronous Preset Enable Operation
•Capable of Driving Two Low−Power TTL Loads or One
Low−Power Schottky Load Over the Rated Temperature Range
•These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter Symbol Value Unit
DC Supply Voltage Range VDD −0.5 to +18.0 V
Input or Output Voltage Range
(DC or Transient)
Vin, Vout −0.5 to VDD
+ 0.5
V
Input or Output Current (DC or Transient)
per Pin
Iin, Iout ±10 mA
Power Dissipation, per Package (Note 1) PD500 mW
Ambient Temperature Range TA−55 to +125 °C
Storage Temperature Range Tstg −65 to +150 °C
Lead Temperature (8−Second Soldering) TL260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard
against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated
voltages to this high−impedance circuit. For proper
operation, Vin and Vout should be constrained to the
range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate
logic voltage level (e.g., either VSS or VDD). Unused
outputs must be left open.
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See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free Package
MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
SOIC−16
D SUFFIX
CASE 751B 1
16
14516BG
AWLYWW
SOEIAJ−16
F SUFFIX
CASE 966
1
16
MC14516B
ALYWG
16
1
MC14516BCP
AWLYYWWG
1
1
1
MC14516B
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2
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
P1
P2
Q2
C
VDD
R
U/D
Q1
P0
P3
Q3
PE
VSS
CARRY OUT
Q0
CARRY IN
BLOCK DIAGRAM
VDD = PIN 16
VSS = PIN 8
6
11
14
2
7
Q0
Q1
Q2
Q3
CARRY
OUT
PE
CARRY IN
RESET
UP/DOWN
CLOCK
P0
P1
P2
P3
1
5
9
10
15
4
12
13
3
TRUTH TABLE
Carry In Up/Down Preset Enable Reset Clock Action
1 X 0 0 X No Count
0 1 0 0 Count Up
0 0 0 0 Count Down
X X 1 0 X Preset
X X X 1 X Reset
X = Don’t Care
NOTE: When counting up, the Carry Out signal is normally high and is low only when Q0 through Q3 are high and Carry In is low. When
counting down, Carry Out is low only when Q0 through Q3 and Carry In are low.
ORDERING INFORMATION
Device Package Shipping†
MC14516BCPG PDIP−16
(Pb−Free) 25 Units / Rail
MC14516BDG SOIC−16
(Pb−Free) 48 Units / Rail
MC14516BDR2G SOIC−16
(Pb−Free) 2500 / Tape & Reel
MC14516BFG SOEIAJ−16
(Pb−Free) 50 Units / Rail
MC14516BFELG SOEIAJ−16
(Pb−Free) 2000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MC14516B
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol
VDD
Vdc
− 55_C 25_C 125_C
Unit
Min Max Min
Typ
(Note 2) Max Min Max
Output Voltage “0” Level
Vin = VDD or 0
“1” Level
Vin = 0 or VDD
VOL 5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
VOH 5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Input Voltage “0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIL 5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
Vdc
VIH 5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOH 5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
−
−
−
−
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
−
−
−
−
– 1.7
– 0.36
– 0.9
– 2.4
−
−
−
−
mAdc
IOL 5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
Input Current Iin 15 −± 0.1 −±0.00001 ± 0.1 −± 1.0 mAdc
Input Capacitance (Vin = 0) Cin − − − − 5.0 7.5 − − pF
Quiescent Current (Per Package) IDD 5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mAdc
Total Supply Current (Note 3, 4)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
IT5.0
10
15
IT = (0.58 mA/kHz) f + IDD
IT = (1.20 mA/kHz) f + IDD
IT = (1.70 mA/kHz) f + IDD
mAdc
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in mA (per package), CL in pF,
V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
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SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD
All Types
Unit
Min Typ (Note 6) Max
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL 5.0
10
15
−
−
−
100
50
40
200
100
80
ns
Propagation Delay Time
Clock to Q
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
Clock to Carry Out
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
Carry In to Carry Out
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
Preset or Reset to Q
tPLH, tPHL = (1.7 ns/pF) CL + 230 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
Preset or Reset to Carry Out
tPLH, tPHL = (1.7 ns/pF) CL + 465 ns
tPLH, tPHL = (0.66 ns/pF) CL + 192 ns
tPLH, tPHL = (0.5 ns/pF) CL + 125 ns
tPLH,
tPHL 5.0
10
15
−
−
−
315
130
100
630
260
200
ns
tPLH,
tPHL 5.0
10
15
−
−
−
315
130
100
630
260
200
ns
tPLH,
tPHL 5.0
10
15
−
−
−
180
80
60
360
160
120
ns
tPLH,
tPHL 5.0
10
15
−
−
−
315
130
100
630
360
200
ns
tPLH,
tPHL 5.0
10
15
−
−
−
550
225
150
1100
450
300
ns
Reset Pulse Width tw5.0
10
15
380
200
160
190
100
80
−
−
−
ns
Clock Pulse Width tWH 5.0
10
15
350
170
140
200
100
75
−
−
−
ns
Clock Pulse Frequency fcl 5.0
10
15
−
−
−
3.0
6.0
8.0
1.5
3.0
4.0
MHz
Preset or Reset Removal Time
The Preset or Reset signal must be low prior to a
positive−going transition of the clock.
trem 5.0
10
15
650
230
180
325
115
90
−
−
ns
Clock Rise and Fall Time tTLH,
tTHL
5.0
10
15
−
−
−
−
−
−
15
5
4
ms
Setup Time
Carry In to Clock
tsu 5.0
10
15
260
120
100
130
60
50
−
−
−
ns
Hold Time
Clock to Carry In
th5.0
10
15
0
20
20
– 60
– 20
0
−
−
−
ns
Setup Time
Up/Down to Clock
tsu 5.0
10
15
500
200
150
250
100
75
−
−
−
ns
Hold Time
Clock to Up/Down
th5.0
10
15
– 70
– 10
0
– 160
– 60
– 40
−
−
−
ns
Setup Time
Pn to PE
tsu 5.0
10
15
– 40
– 30
– 25
– 120
– 70
– 50
−
−
−
ns
Hold Time
PE to Pn
th5.0
10
15
480
420
420
240
210
210
−
−
−
ns
Preset Enable Pulse Width tWH 5.0
10
15
200
100
80
100
50
40
−
−
−
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an Indication of the IC’s potential performance.
MC14516B
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5
Figure 1. Power Dissipation Test Circuit and Waveform
PULSE
GENERATOR CL
CL
CL
CL
VDD
VARIABLE
WIDTH
VDD
VSS
CLOCK
ID0.01 mF
CERAMIC
20 ns
20 ns
10%
50% 90%
500 pF
Q0
Q1
Q2
Q3
CARRY
OUT
PE
CARRY IN
R
UP/DOWN
CLOCK
P0
P1
P2
P3
CL
LOGIC DIAGRAM
PE
C
T
Q
Q
PPE
C
T
Q
Q
PPE
C
T
Q
Q
PPE
C
T
Q
Q
P
Q2
14
P2
13
Q1
11
P3
3
Q3
2
P0
4
Q0
6
P1
12
CARRY OUT
CLOCK
PRESET
ENABLE
RESET
CARRY IN
UP/DOWN
9
1
15
7
5
10
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6
TOGGLE FLIP−FLOP
PE
C
T
Q
Q
P
PARALLEL IN
FLIP−FLOP FUNCTIONAL TRUTH TABLE
Preset
Enable Clock T Qn+1
1 X X Parallel In
0 0 Qn
0 1 Qn
0 X Qn
X = Don’t Care
Figure 2. Switching Time Waveforms
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VOL
VOH
RESET
PRESET ENABLE
CARRY IN OR
UP/DOWN
CLOCK
Q0 OR CARRY OUT
trem
tsu trem
th
tTLH
tPLH
tPHL
tPLH
tTHL
50%
50%
90%
10%
50%
90%
10%
CARRY OUT ONLY
tw(H) tw(H)
tw
1
fcl
PIN DESCRIPTIONS
INPUTS
P0, P1, P2, P3, Preset Inputs (Pins 4, 12, 13, 3) — Data
on these inputs is loaded into the counter when PE is taken
high.
Carry In, (Pin 5) — This active−low input is used when
Cascading stages. Carry In is usually connected to Carry Out
of the previous stage. While high, Clock is inhibited.
Clock, (Pin 15) — Binary data is incremented or
decremented, depending on the direction of count, on the
positive transition of this input.
OUTPUTS
Q0, Q1, Q2, Q3, Binary outputs (Pins 6, 11, 14, 2) —
Binary data is present on these outputs with Q0
corresponding to the least significant bit.
Carry Out, (Pin 7) — Used when cascading stages, Carry
Out is usually connected to Carry In of the next stage. This
synchronous output is active low and may also be used to
indicate terminal count.
CONTROLS
PE, Preset Enable, (Pin 1) — Asynchronously loads data
on the Preset Inputs. This pin is active high and inhibits the
clock when high.
R, Reset, (Pin 9) — Asynchronously resets the Q out−
puts to a low state. This pin is active high and inhibits the
clock when high.
Up/Down, (Pin 10) — Controls the direction of count,
high for up count, low for down count.
SUPPLY PINS
VSS, Negative Supply Voltage, (Pin 8) — This pin is
usually connected to ground.
VDD, Positive Supply Voltage, (Pin 16) — This pin is
connected to a positive supply voltage ranging from 3.0 V
to 18 V.
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7
Figure 3. Presettable Cascaded 8−Bit Up/Down Counter
NOTE: The Least Significant Digit (L.S.D.) counts from a preset value once Preset Enable (PE) goes low. The Most Significant
Digit (M.S.D.) is disabled while Cin is high. When the count of the L.S.D. reaches 0 (count down mode) or reaches 15 (count
up mode), Cout goes low for one complete clock cycle, thus allowing the next counter to decrement/increment one count.
(See Timing Diagram) The L.S.D. now counts through another cycle (15 clock pulses) and the above cycle is repeated.
L.S.D.
MC14516B
Cout
Q0 Q1 Q2 Q3
P0 P1 P2 P3
PE
R
U/D
CLOCK
Cin M.S.D.
MC14516B
Cout
Q0 Q1 Q2 Q3
P0 P1 P2 P3
PE
R
U/D
CLOCK
Cin
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
TERMINAL COUNT
INDICATOR
P0 P1 P2 P3 P4 P5 P6 P7
THUMBWHEEL SWITCHES
(OPEN FOR “0")
+VDD
+VDD
+VDD
OPEN = COUNT
CLOCK
RESET
RESISTORS = 10 kW
0 = COUNT
1 = PRESET
1 = UP
0 = DOWN
PRESET
ENABLE
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8
TIMING DIAGRAM FOR THE PRESETTABLE CASCADED 8−BIT UP/DOWN COUNTER
CLOCK
UP/DOWN
CARRY IN
(MSD)
PE
P7
P6
P5
P4
P3
P2
P1
P0
CARRY OUT
(MSD)
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
CARRY OUT
(LSD)
RESET
COUNT
PRESET ENABLE
UP COUNT DOWN COUNT UP COUNT DOWN
COUNT
PRESET
ENABLE RESET
13 14 15 16 17 18 18 17 16 15 14 13
19 251 252 253 254 255 0 1 2 2 13 012
UP COUNT
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9
Figure 4. Programmable Cascaded Frequency Divider
NOTE: The programmable frequency divider can be set by applying the desired divide ratio, in binary, to the preset inputs. For example,
the maximum divide ratio of 255 may be obtained by applying a 1111 1111 to the preset inputs P0 to P7. For this divide operation,
both counters should be configured in the count down mode. The divide ratio of zero is an undefined state and should be avoided.
BUFFER
fout
M.S.D.
MC14516B
L.S.D.
MC14516B
THUMBWHEEL SWITCHES
(OPEN FOR “0")
+VDD
+VDD
Cout
+VDD
OPEN = COUNT
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Q0 Q1 Q2 Q3
P0 P1 P2 P3
P0 P1 P2 P3
PE
R
U/D
CLOCK
Cin Cout
Q0 Q1 Q2 Q3
P0 P1 P2 P3
PE
R
U/D
CLOCK
Cin
P4 P5 P6 P7
CLOCK (fin)
RESET
RESISTORS = 10 kW
fout = fin
n
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10
PACKAGE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
B
FC
S
H
GD
J
L
M
16 PL
SEATING
18
916
K
PLANE
−T−
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
____
PDIP−16
CASE 648−08
ISSUE T
SOEIAJ−16
CASE 966−01
ISSUE A
HE
A1
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.10 0.20 0.007 0.011
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 0.78 --- 0.031
A1
HE
Q1
LE
_10 _0
_10 _
LE
Q1
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
L
DETAIL P
VIEW P
c
A
b
e
M
0.13 (0.005) 0.10 (0.004)
1
16 9
8
D
Z
E
A
b
c
D
E
e
L
M
Z
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11
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45_
G
8 PLP
−B−
−A−
M
0.25 (0.010) B S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
6.40
16X
0.58
16X 1.12
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
16
89
8X
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