ISP1362_5 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 05 — 8 May 2007 148 of 152
continued >>
NXP Semiconductors ISP1362
Single-chip USB OTG Controller
Table 91. HcINTLPTDSkipMap register: bit description 101
Table 92. HcINTLLastPTD register: bit description . . . .101
Table 93. HcINTLCurrentActivePTD register:
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .101
Table 94. HcINTLCurrentActivePTD register:
bit description . . . . . . . . . . . . . . . . . . . . . . . .102
Table 95. HcATLBufferSize register: bit description . . .102
Table 96. HcATLBufferPort register: bit description . . . .102
Table 97. HcATLBlkSize register: bit allocation . . . . . . .103
Table 98. HcATLBlkSize register: bit description . . . . . .103
Table 99. HcATLPTDDoneMap register: bit description 103
Table 100.HcATLPTDSkipMap register: bit description .104
Table 101.HcATLLastPTD register: bit description . . . . .104
Table 102.HcATLCurrentActivePTD register:
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .104
Table 103.HcATLCurrentActivePTD register:
bit description . . . . . . . . . . . . . . . . . . . . . . . .104
Table 104.HcATLPTDDoneThresholdCount register:
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .105
Table 105.HcATLPTDDoneThresholdCount register:
bit description . . . . . . . . . . . . . . . . . . . . . . . .105
Table 106.HcATLPTDDoneThresholdTimeOut register:
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .105
Table 107.HcATLPTDDoneThresholdTimeOut register:
bit description . . . . . . . . . . . . . . . . . . . . . . . .106
Table 108.Peripheral Controller command and register
overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Table 109.DcEndpointConfiguration register:
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .109
Table 110.DcEndpointConfiguration register:
bit description . . . . . . . . . . . . . . . . . . . . . . . .109
Table 111.DcAddress register: bit allocation . . . . . . . . .109
Table 112.DcAddress register: bit description . . . . . . . .109
Table 113.DcMode register: bit allocation . . . . . . . . . . .110
Table 114.DcMode register: bit description . . . . . . . . . .110
Table 115.DcHardwareConfiguration register:
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .110
Table 116.DcHardwareConfiguration register:
bit description . . . . . . . . . . . . . . . . . . . . . . . .111
Table 117.DcInterruptEnable register: bit allocation . . . .112
Table 118.DcInterruptEnable register: bit description . .112
Table 119.DcDMAConfiguration register: bit allocation .113
Table 120.DcDMAConfiguration register: bit description 113
Table 121.DcDMACounter register: bit allocation . . . . . .114
Table 122.DcDMACounter register: bit description . . . .114
Table 123.Endpoint buffer memory organization . . . . . .115
Table 124.Example of endpoint buffer memory access .116
Table 125.DcEndpointStatus register: bit allocation . . . .116
Table 126.DcEndpointStatus register: bit description . . .116
Table 127.DcEndpointStatusImage register:
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .118
Table 128.DcEndpointStatusImage register:
bit description . . . . . . . . . . . . . . . . . . . . . . . .118
Table 129.DcErrorCode register: bit allocation . . . . . . .119
Table 130.DcErrorCode register: bit description . . . . . .119
Table 131.Transaction error codes . . . . . . . . . . . . . . . . .119
Table 132.DcLock register: bit allocation . . . . . . . . . . . .120
Table 133.DcLock register: bit description . . . . . . . . . . .120
Table 134.DcScratch Information register: bit allocation 120
Table 135.DcScratch Information register:
bit description . . . . . . . . . . . . . . . . . . . . . . . .121
Table 136.DcFrameNumber register: bit allocation . . . .121
Table 137.DcFrameNumber register: bit description . . .121
Table 138.Example of the DcFrameNumber
register access . . . . . . . . . . . . . . . . . . . . . . .121
Table 139.DcChipID register: bit allocation . . . . . . . . . .122
Table 140.DcChipID register: bit description . . . . . . . . .122
Table 141.DcInterrupt register: bit allocation . . . . . . . . .122
Table 142.DcInterrupt register: bit description . . . . . . . .123
Table 143.Limiting values . . . . . . . . . . . . . . . . . . . . . . . .124
Table 144.Recommended operating conditions . . . . . . .124
Table 145.Static characteristics: supply pins . . . . . . . . .125
Table 146.Static characteristics: digital pins . . . . . . . . .125
Table 147.Static characteristics: analog I/O pins
(D+, D−) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Table 148.Static characteristics: charge pump . . . . . . .126
Table 149.Dynamic characteristics . . . . . . . . . . . . . . . .129
Table 150.Dynamic characteristics: analog I/O
lines (D+, D−) . . . . . . . . . . . . . . . . . . . . . . . .129
Table 151.Dynamic characteristics: charge pump . . . . .129
Table 152.Dynamic characteristics: Host Controller
programmed interface timing . . . . . . . . . . . . .130
Table 153.Dynamic characteristics: Peripheral
Controller programmed interface timing . . . .131
Table 154.Dynamic characteristics: Host Controller
single-cycle DMA timing . . . . . . . . . . . . . . . .133
Table 155.Dynamic characteristics: Host Controller burst
mode DMA timing . . . . . . . . . . . . . . . . . . . . .134
Table 156.Dynamic characteristics: Peripheral Controller
single-cycle DMA timing (8237 mode) . . . . .135
Table 157.Dynamic characteristics: Peripheral
Controller single-cycle DMA read timing in
DACK-only mode . . . . . . . . . . . . . . . . . . . . . .135
Table 158.Dynamic characteristics: Peripheral
Controller single-cycle DMA write timing in
DACK-only mode . . . . . . . . . . . . . . . . . . . . . .136
Table 159.Dynamic characteristics: Peripheral
Controller burst mode DMA timing . . . . . . . .137
Table 160.SnPb eutectic process (from J-STD-020C) . .141
Table 161.Lead-free process (from J-STD-020C) . . . . .141
Table 162.Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .142
Table 163.Revision history . . . . . . . . . . . . . . . . . . . . . . .144