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PRELIMINARY DATA
April 2003
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Rev. 3.0
PSD813F2/3/4/5, PSD833F2
PSD834F2, PSD853F2, PSD854F2
Fl ash In -S ystem Progra m m able
(ISP) Peripherals For 8-bit MCUs
FEATURES SUMMARY
■5V±10% Single Supply Voltage
■Up to 2Mbit of Primar y Flash Memory (8 uniform
sect o rs, 3 2K x 8)
■Up to 256Kbit Secondary Flash Memo ry (4
uni form secto rs)
■Up to 2 5 6Kbit SRAM
■Over 3,000 Gates of PLD: DPLD and CPLD
■27 Reconfigurable I/O ports
■Enhanced JTAG S erial Port
■Program mable power man agem ent
■High Endurance:
– 100,000 Erase/WRITE Cycles of Fl ash
Memory
– 1,000 Eras e/W RITE Cycles of PLD
Figure 1. 52-pin, Plastic, Quad, Fl at Package
Figure 2. 52-lead, Plastic-Lead Chip Carrier
PQFP52 (T)
PLCC52 (K)
PSD8XXF2/3/4/5
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TABLE OF CONT ENTS
SUMMARY DESCRIPT ION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 1. Product Range (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
KEY FEAT URES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3. PSD8XXFX Block Diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PSD8XXFX ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2. PLD I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
I/O Po rts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
MCU Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
JTAG Por t. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
In-System Prog ramming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Power Management Un it (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. JT A G SIgnal s on Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Met hods of Program ming Different Functional Blocks of the PSD8XX FX. . . . . . . . . . . . . 12
DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 4. PSDsoft Express Development Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. Pi n Description (for the PLCC52 package - Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PSD8XXFX Register Descrip tion and Address Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. I/O Port Latched Address Output Assignments (Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. Register Address Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7
DETAILED OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
MEMORY BLO CKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Primary Flash Memory and Secondary Flash m emory Description. . . . . . . . . . . . . . . . . . . . . 18
Memory Block Select Sig nals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 8. Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power-down Instruction and Power-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. Status Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1
Programming Flash Memor y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 5. Data Polli ng Flowcha rt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 6. Data Toggle Flo wchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Erasin g Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4
Specific Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10. Sector Protection/Secu rity Bit Definition – Flash Protection Register . . . . . . . . . . . . . . . 25
Table 11. Sector Protection/Secu rity Bit Definition – PSD/EE Protection Register. . . . . . . . . . . . . 25
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6
Sector Select and SRAM Se lect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 7. Priority Level of Memory and I/O Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 12. VM Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 8. 8031 Memory Mod ules – Separate Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 9. 8031 Memory Mod ules – Combined Sp ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 10. Page Re gister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PLDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 13. DPLD and CPLD Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
The Turbo Bit in PSD8XXFX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0
Figure 11. PLD Dia gram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2
Figure 12. DPLD Logic Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3
Figure 13. Macrocell and I/O Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3
Output Macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 14. Output Mac rocell Port and Data Bit Assignme nts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Product Term Allocator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5
Figure 14. CPLD Output Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Input M acroc ells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 15. Input Macrocell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 16. Handshaking Communicat ion Using Input Macroc ells. . . . . . . . . . . . . . . . . . . . . . . . . . 39
MCU BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 15. MCUs and their Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 17. An Examp le of a Typical 8-bit Multiplexed Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 18. An Example of a Typical 8-bi t Non-M ultiplexed Bus Interface . . . . . . . . . . . . . . . . . . . . 42
Table 16. Eight-Bit Data Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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MCU Bus Interface Exampl es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 19. Interfacing the PSD8XXFX with an 80C31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 17. 80C251 Configuratio ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3
Table 18. Interfacing the PSD8XXFX with the 80C251, with One READ Input. . . . . . . . . . . . . . . . 44
Figure 20. Interfacing the PSD8XXFX with the 80C251, with RD and PSEN Inputs. . . . . . . . . . . . 45
Figure 21. Interfacing the PSD8XXFX with the 80 C51X, 8-bit D ata Bus. . . . . . . . . . . . . . . . . . . . . 46
Figure 22. Interfacing the PSD8XXFX with a 68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
I/O PORTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
General Port Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 23. General I/O Port Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Port O perating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
MCU I/O M ode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
PLD I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
A ddr ess Ou t Mod e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 19. Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0
Table 20. Port Operating Mode Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 21. I/O Port Latched Address Output Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
A ddress In Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Data Po rt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Peripheral I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
JTAG In-System Programming (ISP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 24. Peripheral I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1
Port Co nfiguration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 22 . Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 23. Port Pin Direction Control, Output Enable P.T. Not Defined . . . . . . . . . . . . . . . . . . . . . . 52
Table 24. Port Pin Direct i on Control, Output Enable P.T. Def i ned . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 25. Port Direction Assignm ent Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 26. Drive Re giste r Pin Assignme nt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Port Da ta Reg isters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 27. Port Data Reg isters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Ports A and B – Func tionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 25. Port A and Port B Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Port C – Functionality a nd Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 26. Port C Stru cture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Port D – Functionality a nd Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 27. Port D Stru cture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
External Ch ip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7
Figure 28. Port D External Chip Select Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
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Table 28. Power-down Mo de’s Effect on Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 29. APD Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 29. PSD8XXFX Timin g and Stand-by Current during Power-do wn Mode. . . . . . . . . . . . . . . 59
Figure 30. Enable Power-down Flow Chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
PLD Power Managemen t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 30. Power Manageme nt Mode Regist ers PMMR0 (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 31. Power Manageme nt Mode Regist ers PMMR2 (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . 61
PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Input Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 32. APD Counter Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
RESET T IMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
W arm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
I/O Pin, Register and PLD Status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
R eset of Flash Memory Erase an d Program Cycles (on the PSD834Fx) . . . . . . . . . . . . . . . . . 63
Figure 31. Reset (RESET) Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3
Table 33. Status Du ring Power-On Reset, Warm Reset a nd Power-down Mod e . . . . . . . . . . . . . . 64
PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . 65
Standar d JTAG Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5
Table 34. JT A G Port Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5
JTAG Extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Security a nd Flash memory Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
INITIAL DELIVERY STAT E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 35. JTAG Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 32. PLD ICC /Freq uency Consumption (5 V range). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 33. PLD ICC /Freq uency Consumption (3 V range). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 36. Example of PSD8XXFX Typical Power Calculation at VCC = 5. 0 V (Turbo Mode On) . . 69
Table 37. Example of PSD8XXFX Typical Power Calculation at VCC = 5. 0 V (Turbo Mode Of f) . . 70
MAXIMU M RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 38. Abso lute Maximum Ra tings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
PSD8XXF2/3/4/5
6/103
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 39. Operating Conditions (5V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 40. Operating Conditions (3V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 41. AC M easurem ent Con ditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 34. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 35. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 42. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 43. AC Symbols for PLD Timi ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 36. Switching Waveforms – Key. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 44 . DC Characteristics (5V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 45 . DC Characteristics (3V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 37. Input to Output Disable / Enabl e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 46. CPLD Co mbinatorial Timing (5V devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 47. CPLD Co mbinatorial Timing (3V devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 38. Synchronous Clock Mode Timing – PLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 48. CPLD Macrocell Synchronous Clock Mode Timing (5V devices) . . . . . . . . . . . . . . . . . . 77
Table 49. CPLD Macrocell Synchronous Clock Mode Timing (3V devices) . . . . . . . . . . . . . . . . . . 78
Figure 39. Asynchronous Reset / Preset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 40. Asynchronous Clock Mode Timing (product term clock) . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 50. CPLD Macrocell Asynch ronous Clock Mode Timi ng (5V devices) . . . . . . . . . . . . . . . . . 80
Table 51. CPLD Macrocell Asynch ronous Clock Mode Timi ng (3V devices) . . . . . . . . . . . . . . . . . 81
Figure 41. Input Ma crocell Timing (product term clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 52. Input Macro cell Tim ing (5V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 53. Input Macro cell Tim ing (3V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 42. READ Tim ing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 54. READ Timing (5V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Table 55. READ Timing (3V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Figure 43. WRITE T iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 56. WRITE Timing (5V de vices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 57. WRITE Timing (3V de vices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 58. Prog ram, WRITE an d Erase Times (5V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 59. Prog ram, WRITE an d Erase Times (3V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 44. Peripheral I/O REA D Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 60. Port A Peripheral Data Mode READ Timing (5V devices). . . . . . . . . . . . . . . . . . . . . . . . 90
Table 61. Port A Peripheral Data Mode READ Timing (3V devices). . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 45. Peripheral I/O WRITE Timin g. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 62. Port A Peripheral Data Mode WRITE Timing (5V devices) . . . . . . . . . . . . . . . . . . . . . . . 92
Table 63. Port A Peripheral Data Mode WRITE Timing (3V devices) . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 46. Reset (RESET) Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3
Table 64. Reset (RESET) Timing (5V devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 65. Reset (RESET) Timing (3V devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 66. VSTBYON Timing (5V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 67. VSTBYON Timing (3V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7/103
PSD8XXF2/3/4/5
Figure 47. ISC Tim ing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 68. ISC Timing (5V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 69. ISC Timing (3V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 70. Power-down Timing (5V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 71. Power-down Timing (3V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 48. PQFP52 Conne ctions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6
Figure 49. PLCC52 Connec tions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 50. PQFP52 - 52-pin Plastic, Quad, Flat Package M ec hanical Drawing . . . . . . . . . . . . . . . 96
Table 72. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechani cal Dimensions . . . . . . . . . . . . . 97
Figure 51. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Drawing . . . . . . . . 98
Table 73. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechani cal Dimensions . . . . . . 98
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 74. Ordering Information Schem e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
APPENDIX A. PQFP52 PI N ASSIGNMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
APPENDIX B. PLCC52 PIN ASSIGNMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
PSD8XXF2/3/4/5
8/103
SUMMARY DESCRIPTION
The PS D8XXFX f amily of memory syst ems for mi-
crocontrollers (MCUs) brings I n-System -Program-
mability (ISP) to Flash memory and programmable
logic. The result is a simple and flexible solution for
embedded de signs . PSD 8XX FX dev ices co mbine
many of the peripheral functions found in MCU
based applicatio ns.
Table 1 summarizes all the devices in the
PSD834F2, PSD853F 2, PSD854F2.
The CP LD i n the P S D8XX FX devices features an
optimized macrocell logic architecture. The PSD
macrocell was created to address the unique re-
quirements of embedded system designs. It al-
lows direct connection between the system
address/data bus, and the internal PSD8XXFX
registers, to simplify communication between the
MCU and other supporting devices.
The PSD8XXFX device includes a JTAG Serial
Programming interface, to allow In-System Pro-
gramming (ISP) of the
entire device
. This feature
reduces development time, simplifies the manu-
facturing flow, and dramatically lowers the cost of
field upgrades. Using ST’s special Fast-JTAG pro-
gramming, a design can be rapidly programmed
into the PSD8 XXF X in as little as seven seconds.
The innovative PSD8XXFX family solves key
problems faced by designers when managing dis-
crete Flash memory devices, such as:
– First-time In-System Programmi ng (ISP)
– Complex addres s dec oding
– Simultaneous read and write to the device.
The JTAG Serial I nt erface block allows In-System
Programming (ISP), and eliminates the need for
an external Boot EPROM, or an ext ernal program-
mer. To simplify Flash m emory updates, program
execution is performed from a secondary Flash
memory while the primary Flash mem ory is being
updated. This solution avoids the complicated
hardware and software overhead necessary to im-
plement IAP.
ST make s availabl e a software developm ent tool,
PSDsoft Express, that ge nerates ANSI-C compli-
ant code f or us e with y our t arget M CU. T his code
allows you to ma nipulate the non-volatile me mory
(NVM) within th e PSD8XXFX. Code examples are
also provided for:
– Flash memory IAP via the UART of the host
MCU
– Memory paging to execute code across several
PSD8XXF X mem ory pages
– Loading, reading, and manipulation of
PSD8XXF X mac rocells by the MCU.
Table 1. Product Rang e (Note 1)
Note : 1. All pr oducts support: JTA G seria l I SP, MCU p arallel I SP, ISP Flash mem ory, ISP CPLD, Security fe atures, Power M anagement
Unit (P MU), Automatic Pow er-down (APD )
2. SRAM may be backed up using an ext ernal ba tt ery.
Part Number Primary Flash
Memory
(8 Sectors)
Secondary
Flash Memory
(4 Sectors) SRAM2I/O Ports
Number of
Macrocells Serial
ISP
JTAG/
ISC Port
Turbo
Mode
Input Output
PSD813F2 1 Mbit 256 Kbit 16 Kbit 27 24 16 yes yes
PSD813F3 1 Mbit none 16 Kbit 27 24 16 yes yes
PSD813F4 1 Mbit 256 Kbit none 27 24 16 yes yes
PSD813F5 1 Mbit none none 27 24 16 yes yes
PSD833F2 1 Mbit 256 Kbit 64 Kbit 27 24 16 yes yes
PSD834F2 2 Mbit 256 Kbit 64 Kbit 27 24 16 yes yes
PSD853F2 1 Mbit 256 Kbit 256 Kbit 27 24 16 yes yes
PSD854F2 2 Mbit 256 Kbit 256 Kbit 27 24 16 yes yes
9/103
PSD8XXF2/3/4/5
KEY FEATURES
■A simple interface to 8-bit microcontrollers t hat
use either multiplexed or non-mult i plexed
busses. The bus interface logic uses the control
signals generated by the microcontroll er
automat ically when the address is decoded and
a READ or WRITE is perf ormed. A partial list of
the MCU families supported include:
– Intel 8031, 80196, 80186, 80C251, and
80386EX
– Motorola 68HC11 , 68HC16, 68HC12, and
683XX
– Philips 8031 and 8051X A
– Zilog Z80 and Z8
■Internal 1 or 2 Mbit Flash memory. This is the
main Fl ash memory. It is divided into eight
equal-siz ed blocks that can be accessed with
user-specified addresses .
■Internal secondary 256 Kbit Flash boot memory.
It i s divided into f our equal-sized blocks that can
be accessed with user-specified addresses.
Th is secondary memo ry brings th e abilit y to
execute code and update the main Fl ash
concurrently
.
■Optional 16, 64 or 256 Kbit SRAM. The SRAM’s
content s can be protected from a power failure
by connecting an ex ternal battery.
■CPLD with 16 Out put Micro Cells (OMCs) and
24 Input Micro Cel ls (IMCs). T he CPLD may be
used t o efficiently implement a variety of l ogic
functions for internal and external control.
Examp les include state ma chines, loadable
shift registers, and loadable counters.
■Decode PLD (DPLD ) that decodes address for
selection of internal memory blocks.
■27 individually configurab le I/O port pins that
can be used for the following functions:
– MCU I/Os
–PLD I/Os
– Latched MCU address output
– Special f unct ion I/Os.
– 16 of the I/O ports may be configur ed as
open-drain out puts.
■Standby cur rent as low as 50 µA for 5 V devices.
■Built-in JTAG compliant serial port allows full-
chip In-System Programmability (ISP). With it,
you can program a blank device or reprogram a
device in the factory or the field.
■Internal page register that can be used to
expand t he microcontroller address space by a
factor of 256.
■Internal programmable Power Management
Unit (PMU) that s up ports a low power mode
called Power Down Mode. The PMU can
autom atically detect a lack of microcontroller
activity and put t he PSD8XXF into Power-down
mode.
■Erase/W RITE cycles:
– Flash memory – 100,0 00 minimum
– PLD – 1,000 minimu m
– Data Retention: 15 year minimum (for Main
Flash memory, Boot, PLD and Configuration
bits)
PSD8XXF2/3/4/5
10/103
Figure 3 . PSD8XXFX Block Diagra m
PROG.
MCU BUS
INTRF.
ADIO
PORT
CNTL0,
CNTL1,
CNTL2
AD0 – AD15
CLKIN
(PD1)
CLKIN
CLKIN
PLD
INPUT
BUS
PROG.
PORT
PORT
A
PROG.
PORT
PORT
B
POWER
MANGMT
UNIT
1 OR 2 MBIT PRIMARY
FLASH MEMORY
8 SECTORS
VSTDBY
PA0 – PA7
PB0 – PB7
PROG.
PORT
PORT
C
PROG.
PORT
PORT
D
PC0 – PC7
PD0 – PD2
ADDRESS/DATA/CONTROL BUS
PORT A ,B & C
3 EXT CS TO PORT D
24 INPUT MACROCELLS
PORT A ,B & C
73
73
256 KBIT SECONDARY
NON-VOLATILE MEMORY
(BOOT OR DATA)
4 SECTORS
256 KBIT BATTERY
BACKUP SRAM
RUNTIME CONTROL
AND I/O REGISTERS
SRAM SELECT
PERIP I/O MODE SELECTS
MACROCELL FEEDBACK OR PORT INPUT
CSIOP
FLASH ISP CPLD
(CPLD) 16 OUTPUT MACROCELLS
FLASH DECODE
PLD (DPLD)
PLD, CONFIGURATION
& FLASH MEMORY
LOADER
JTAG
SERIAL
CHANNEL
(PC2)
PAGE
REGISTER EMBEDDED
ALGORITHM
SECTOR
SELECTS
SECTOR
SELECTS
GLOBAL
CONFIG. &
SECURITY
AI02861E
8
11/103
PSD8XXF2/3/4/5
PSD8XXFX ARCHITECTURAL OVERVIEW
PSD8XXFX devices contain several major func-
tional blocks. Figure 3 shows the architecture of
the PSD8XXFX device family. The functions of
each block are described briefly in the following
sections. Many of the blocks perform multiple
functions and are user configurable.
Memory
Each of the memory blocks is briefly discussed in
the following paragrap hs. A m ore det ailed di scus-
sion can be found i n the section entit led “MEMO-
RY BLOCKS“ on page 18.
The 1 Mbit or 2 Mbit (128K x 8, or 256K x 8) Flash
memory is the primary memory of the PSD8XXFX.
It is divided into 8 equall y-sized sect or s that are in-
dividually selectable.
The optional 256 Kbit (32K x 8) secondary Flash
memory is divided into 4 equally-sized sectors.
Each sector is individually selectable.
The optional SRAM is intended for use as a
scratch-pad memory or as an extension to the
MCU SRAM. If an external battery is connected to
Voltage Stand-by (VSTBY, PC2), data is retained in
the event of power failure.
Each secto r of m em ory can be located in a differ-
ent address space as defined by t he user. The ac-
cess times for all memory types includes the
address lat ching and DPLD decoding time.
Page Regi s te r
The 8-bit Page Register expands the address
range of the MCU by up to 256 times. The pa ged
address can be used as part of the address space
to access external memory and peripherals, or in-
ternal memory and I/O. The Page Register can
also be used to change the address mapping of
sectors of the Flash memories into different m em-
ory spaces for IA P .
PLDs
The device contains two PLDs, the Decode PLD
(DPLD) and the Complex PLD (CPLD), as shown
in Table 2 , eac h op timized f or a di fferent fun ction.
The functional partitioning of the PLDs reduces
power consumption, optimizes cost/performance,
and eases design entry.
Table 2. PL D I/O
The DPLD is used to decode addresses and to
generate Sector Select signals for the PSD8XXF X
internal memory and registers. The DPLD has
combinatorial outputs. The CPLD has 16 Output
Macrocells (OMC) and 3 combinatorial outputs.
The PSD8XXFX also has 24 Input Macrocells
(IMC) that can be configured as inputs to the
PLDs. The PLDs r eceive thei r inputs from the PLD
Input Bus and are differentiated by their output
destinations, number of product terms, and mac-
rocells.
The PLDs consume minimal power. The speed
and power consumption of the PLD is controlled
by the Turbo bit in PMMR0 and other bits in the
PMMR2. These registers are set by the MCU at
run-time. There is a slight penalty to PLD pr opaga-
tion time when invoking the power management
features.
I/O Port s
The PSD8XXFX has 27 individually configurabl e I/
O pins dist ri buted over the four ports (Port A , B, C,
and D). Each I /O pin can be individually configured
for different functions. Ports can be conf igured as
standard MCU I/O ports, PLD I/O, or latched ad-
dress outputs for MCUs using multiplexed ad-
dress/data buses.
The JTAG pins can be enabled on Port C for In-
System Program ming (ISP ).
Ports A and B can also be configured as a data
port for a non-m ultipl exed bus.
MCU Bus Inter face
PSD8XXFX interfaces easily with most 8-bit
MCUs that have either multiplexed or non-multi-
plexed addre ss/data b uses. The de vice is conf ig-
ured to respond to the MCU’s control signals,
which are also used as inputs to the PLDs. F or ex-
amples, please see the secti on entitled “M CU Bus
Interface Examples“ on page 43.
Name Inputs Outputs Product
Terms
Decode PLD (DPLD) 73 17 42
Complex PLD (CPLD) 73 19 140
PSD8XXF2/3/4/5
12/103
JTAG Port
In-System Programming (ISP) can be performed
through the JTAG signals on Port C. This serial i n-
terface allows compl ete progr ammi ng of t he entire
PSD8XXFX device. A blank device can be com-
pletely programmed. The JTAG signals (TMS,
TCK, TSTAT, TERR, TDI, TDO) can be multi-
plexed with ot her functions on Port C. Table 3 in-
dicates the JTAG pin assignm ents .
In-System Prog r a mming ( ISP)
Using the JTAG signals on Port C, the entire
PSD8XXFX device can be programmed or erased
without the use of the MCU. The primary Flash
memory can also be programmed in-system by
the MCU executing the programming algorithms
out of the secondary memory, or SRAM. The sec-
ondary memory can be programmed the same
way by exec uting out of the primary Flash memo-
ry. The PLD or other PSD8XXFX Configuration
blo cks can be pr ogrammed thro ugh the JTAG port
or a device programmer. Table 4 indicates which
programming methods can program different func-
tio nal blocks of the PSD8XXFX.
Power Management Unit (PMU)
The Power Management Unit (PMU) gives the
user control of the power consumption on selected
functional blocks based on system requirements.
The PMU includes an Automatic Power-down
(APD) Unit that turns off device functions during
MCU inactivity. The APD Unit has a Power-down
m ode t hat helps reduc e pow er c ons umpt ion.
The PSD8X XFX als o has some bi ts that are con-
figured at run-time by the MCU to reduce power
consumption of the CPLD. The Turbo bit in
PMMR0 can be reset to 0 and t he CPLD latches its
outputs and g oes to sleep until the nex t transition
on its inputs.
Additionally, bits in PMMR2 can be set by the
MCU to block signals from entering the CPLD to
reduce power consumption. Please see the sec-
tion entitled “POWER MANAGEMENT” on page
58 for m ore details.
Table 3. JTAG SIgnals on Port C
Tabl e 4. Methods of Programming Different Functional Blocks of the PSD8XXFX
Port C Pins JTAG Signal
PC0 TMS
PC1 TCK
PC3 TSTAT
PC4 TERR
PC5 TDI
PC6 TDO
Functional Block JTAG Programming Device Programmer IAP
Primary Flash Memory Yes Yes Yes
Secondary Flash Memory Yes Yes Yes
PLD Array (DPLD and CPLD) Yes Yes No
PSD8X XFX Config urati on Yes Yes No
13/103
PSD8XXF2/3/4/5
DE VELOPMENT SYSTEM
The PSD8XXFX family is supported by PSDsoft
Express, a Windows-based software development
tool. A PSD8XXFX design is quickly and easily
produced in a point and click envir onment. The de-
signer does not need to enter Hardware Descrip-
tion Language (HDL) equations, unles s desired, to
define PSD8XXFX pin functi ons and memory map
information. The general design flow is shown in
Figure 4. PSDsoft Express is available from our
web site (t he address is given on the back page of
this data sheet) or other distribution channels.
PSDsoft Express directly supports two low cost
device programmers form ST: PSDpro and
FlashLINK (JTAG). Both of these programmers
may be purchased through your local distributor/
representative, or directly f rom our web s ite us ing
a credit card. The PSD8XXFX is also supported by
third party device programmers. See our w eb site
for the current list.
Figure 4. PSDsoft Exp ress Developmen t Tool
PSD Configuration
PSD Fitter
PSD Simulator PSD Programmer
*.OBJ FILE
PLD DESCRIPTION
CONFIGURE MCU BUS
INTERFACE AND OTHER
PSD ATTRIBUTES
LOGIC SYNTHESIS
AND FITTING
PSDsilos III
DEVICE SIMULATION
(OPTIONAL)
PSDPro, or
FlashLINK (JTAG)
ADDRESS TRANSLATION
AND MEMORY MAPPING
PSDabel
MODIFY ABEL TEMPLATE FILE
OR GENERATE NEW FILE
PSD TOOLS
GENERATE C CODE
SPECIFIC TO PSD
FUNCTIONS
USER'S CHOICE OF
MICROCONTROLLER
COMPILER/LINKER
*.OBJ AND *.SVF
FILES AVAILABLE
FOR 3rd PARTY
PROGRAMMERS
(CONVENTIONAL or
JTAG-ISC)
FIRMWARE
HEX OR S-RECORD
FORMAT
AI04918
PSD8XXF2/3/4/5
14/103
PIN DESCRIP TION
Table 5 describes the signal names and signal
functions of the PSD8XX FX.
Table 5. Pin Descriptio n (for the PLCC52 package - Note 1)
Pin Name Pin Type Description
ADIO0-7 30-37 I/O
This is the lower Address/Data port. Connect your MCU address or address/data bus
according to the following rules:
1. If your MCU has a multiplexed address/data bus where the data is multiplexed with the
lower address bits, connect AD0-AD7 to this port.
2. If your MCU does not have a multiplexed address/data bus, or you are using an
80C251 in page mode, connect A0-A7 to this port.
3. If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this
port.
ALE or AS latches the address. The PSD8XXFX drives data out only if the READ signal is
active and one of the PSD8XXFX functional blocks was selected. The addresses on this
port are passed to the PLDs.
ADIO8-15 39-46 I/O
This is the upper Address/Data port. Connect your MCU address or address/data bus
according to the following rules:
1. If your MCU has a multiplexed address/data bus where the data is multiplexed with the
lower address bits, connect A8-A15 to this port.
2. If your MCU does not have a multiplexed address/data bus, connect A8-A15 to this
port.
3. If you are using an 80C251 in page mode, connect AD8-AD15 to this port.
4. If you are using an 80C51XA in burst mode, connect A12/D8 through A19/D15 to this
port.
ALE or AS latches the address. The PSD8XXFX drives data out only if the READ signal is
active and one of the PSD8XXFX functional blocks was selected. The addresses on this
port are passed to the PLDs.
CNTL0 47 I
The following control signals can be connected to this port, based on your MCU:
1. WR – active Low Write Strobe input.
2. R_W – active High READ/active Low write input.
This port is connected to the PLDs. Therefore, these signals can be used in decode and
other logic equations.
CNTL1 50 I
The following control signals can be connected to this port, based on your MCU:
1. RD – active Low Read Strobe input.
2. E – E clock input.
3. DS – active Low Data Strobe input.
4. PSEN – connect PSEN to this port when it is being used as an active Low READ
signal. For example, when the 80C251 outputs more than 16 address bits, PSEN is
actually the READ signal.
This port is connected to the PLDs. Therefore, these signals can be used in decode and
other logic equations.
CNTL2 49 I
This port can be used to input the PSEN (Program Select Enable) signal from any MCU
that uses this signal for code exclusively. If your MCU does not output a Program Select
Enable signal, this port can be used as a generic input. This port is connected to the
PLDs.
Reset 48 I Resets I/O Ports, PLD macrocells and some of the Configuration Registers. Must be Low
at Power -up.
15/103
PSD8XXF2/3/4/5
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
29
28
27
25
24
23
22
21
I/O
These pins make up Port A. These port pins are configurable and can have the following
functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellAB0-7) outputs.
3. Inputs to the PLDs.
4. Latched address outputs (see Table 6).
5. Address inputs. For example, PA0-3 could be used for A0-A3 when using an 80C51XA
in burst mode.
6. As the data bus inputs D0-D7 for non-multiplexed address/data bus MCUs.
7. D0/A16-D3/A19 in M37702M2 mode.
8. Peripheral I/O mode.
Note: PA0-PA3 can only output CMOS signals with an option for high slew rate. However,
PA4-PA7 can be configured as CMOS or Open Drain Outputs.
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
7
6
5
4
3
2
52
51
I/O
These pins make up Port B. These port pins are configurable and can have the following
functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellAB0-7 or McellBC0-7) outputs.
3. Inputs to the PLDs.
4. Latched address outputs (see Table 6).
Note: PB0-PB3 can only output CMOS signals with an option for high slew rate. However ,
PB4-PB7 can be configured as CMOS or Open Drain Outputs.
PC0 20 I/O
PC0 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC0) output.
3. Input to the PLDs.
4. TMS Input2 for the JTAG Serial Interface.
This pin can be configured as a CMOS or Open Drain output.
PC1 19 I/O
PC1 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC1) output.
3. Input to the PLDs.
4. TCK Input2 for the JTAG Serial Interface.
This pin can be configured as a CMOS or Open Drain output.
PC2 18 I/O
PC2 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC2) output.
3. Input to the PLDs.
4. VSTBY – SRAM stand-by voltage input for SRAM battery backup.
This pin can be configured as a CMOS or Open Drain output.
PC3 17 I/O
PC3 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC3) output.
3. Input to the PLDs.
4. TSTAT output2 for the JTAG Serial Interface.
5. Ready/Busy output for parallel In-System Programming (ISP).
This pin can be configured as a CMOS or Open Drain output.
PC4 14 I/O
PC4 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC4) output.
3. Input to the PLDs.
4. TERR output2 for the JTAG Serial Interface.
5. Battery-on Indicator (VBATON). Goes High when power is being drawn from the
external batte ry.
This pin can be configured as a CMOS or Open Drain output.
Pin Name Pin Type Description
PSD8XXF2/3/4/5
16/103
Note: 1. The pin numbe rs in thi s t abl e are for t he PLCC packa ge only. S ee the package informati on, on page 98 onwards, for pin numbers
on other pack age type s.
2. These functi ons can be multiplexed with othe r f unctions .
PSD8XXFX REG IS TER DESCRIPTION AND ADDRESS OFFSET
Table 7 shows the offset addresses to the
PSD8XXFX registers relative to the CSIOP base
address. The CSIOP space is the 256 bytes of ad-
dress that is allocated by the user to the internal
PSD8XXFX registers. Table 7 provides brief de-
scriptions of the registers in CSIOP s pace. The fol-
lowing section gives a more detailed description.
PC5 13 I/O
PC5 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC5) output.
3. Input to the PLDs.
4. TDI input2 for the JTAG Serial Interface.
This pin can be configured as a CMOS or Open Drain output.
PC6 12 I/O
PC6 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC6) output.
3. Input to the PLDs.
4. TDO output2 for the JTAG Serial Interface.
This pin can be configured as a CMOS or Open Drain output.
PC7 11 I/O
PC7 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. CPLD macrocell (McellBC7) output.
3. Input to the PLDs.
4. DBE – active Low Data Byte Enable input from 68HC912 type MCUs.
This pin can be configured as a CMOS or Open Drain output.
PD0 10 I/O
PD0 pin of Port D. This port pin can be configured to have the following functions:
1. ALE/AS input latches address output from the MCU.
2. MCU I/O – write or read from a standard output or input port.
3. Input to the PLDs.
4. CPLD output (External Chip Select).
PD1 9 I/O
PD1 pin of Port D. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. Input to the PLDs.
3. CPLD output (External Chip Select).
4. CLKIN – clock input to the CPLD macrocells, the APD Unit’s Power-down counter , and
the CPLD AND Array.
PD2 8 I/O
PD2 pin of Port D. This port pin can be configured to have the following functions:
1. MCU I/O – write to or read from a standard output or input port.
2. Input to the PLDs.
3. CPLD output (External Chip Select).
4. PSD Chip Select Input (CSI). When Low, the MCU can access the PSD8XXFX
memory and I/O. When High, the PSD8XXFX memory blocks are disabled to conserve
power.
VCC 15, 38 Supply Voltage
GND 1, 16,
26 Ground pins
Pin Name Pin Type Description
17/103
PSD8XXF2/3/4/5
Table 6. I/O Port Latche d Address Ou tput Assignm ents (Note1)
No te : 1. See th e section entitle d “I /O PORTS”, on page 48, on how to en abl e the Latched Address Output function.
2. N/A = Not Applicable
Table 7. Register Address Offset
Note: 1. Other registers that are not part of the I/O ports.
MCU Port A Port B
Port A (3:0) Port A (7:4) Port B (3:0) Port B (7:4)
8051XA (8-bit) N/A Address a7-a4 Address a11-a8 N/A
80C251 (page mode) N/A N/A Address a11-a8 Address a15-a12
All other 8-bit multiplexed Address a3-a0 Address a7-a4 Address a3-a0 Address a7-a4
8-bit non-multiplexed bus N/A N/A Address a3-a0 Address a7-a4
Register Name Port A Port B Port C Port D Other1 Description
Data In 00 01 10 11 Reads Port pin as input, MCU I/O input mode
Control 02 03 Selects mode between MCU I/O or Address Out
Data Out 04 05 12 13 S tores data for output to Port pins, MCU I/O output
mode
Direction 06 07 14 15 Configures Port pin as input or output
Drive Select 08 09 16 17 Configures Port pins as either CMOS or Open
Drain on some pins, while selecting high slew rate
on other pins.
Input Macrocell 0A 0B 18 Reads Input Macrocells
Enable Out 0C 0D 1A 1B Reads the status of the output enable to the I/O
Port driver
Output Macrocells
AB 20 20 READ – reads output of macrocells AB
WRITE – loads macrocell flip-flops
Output Macrocells
BC 21 21 READ – reads output of macrocells BC
WRITE – loads macrocell flip-flops
Mask Macrocells AB 22 22 Blocks writing to the Output Macrocells AB
Mask Macrocells BC 23 23 Blocks writing to the Output Macrocells BC
Primary Flash
Protection C0 Read only – Primary Flash Sector Protection
Secondary Flash
memory Protection C2 Read only – PSD8XXFX Security and Secondary
Flash memory Sector Protection
JTAG Enable C7 Enables JTAG Port
PMMR0 B0 Power Management Register 0
PMMR2 B4 Power Management Register 2
Page E0 Page Register
VM E2
Places PSD8XXFX memory areas in Program
and/or Data space on an individual basis.
PSD8XXF2/3/4/5
18/103
DETAIL ED OPERATIO N
As shown in Figure 3, the PS D8X XFX c onsi sts of
six major types of functional blocks:
■Memory Blocks
■PLD Blocks
■MCU Bus I n terface
■I/O Ports
■Power Managem ent Unit (PMU)
■JTAG Interface
The functions of each block are described in the
following sections. Many of the blocks perform
multiple functions, and are user configurable.
MEMORY BLOCKS
The PSD8XXFX has the following memory blocks:
– Primary Flash memory
– Optional Secondary Flash memory
– Opt io nal SRA M
The Memory Select signals for these blocks origi-
nate from the De code PLD (DP LD) and are user-
defined in PSDsoft Express.
Primary Flash Me m ory and Sec ondary F lash
memor y Descript ion
The primary Flash memory is divided evenly into
eight equal sectors . The secondary Flash memory
is divided into four equal sectors. Each sector of
either memory block can be sepa ra tely protected
from Program and Erase cycles.
Flash memory may be erased on a sector-by-sec-
tor basis. F lash sector erasure may be suspended
while data is read from other sectors of the block
and then resumed after reading.
During a Program or Erase cycle in Flash memory,
the status can be output on Ready/Busy (PC3).
This pin is set up using PSDsof t Express Configu-
ration.
Memory Block Select Signals
The DPLD g enerates the Select sig nals for all the
internal memory blocks (see the section entitled
“PLDS”, on page 30). Eac h o f the eight sectors of
the primary Flash memory has a Select signal
(FS0-FS7) which can contain up to three product
terms. Each of the four sectors of the secondary
Flash memory has a Select signal (CSBOOT0-
CSBOOT3) which can contai n up to three product
terms. Having three produc t terms for each Selec t
signal allows a given sector to be mapped in differ-
ent areas of syste m memory. When using a MCU
with separate Program and Data space, these
flexible Select signals allow dynamic re-mapping
of sectors fr om one memory spac e to the other.
Ready/Busy (PC3 ). This signal can be used to
output the Ready/Busy status of the PSD 8XXFX.
The output on Ready/Busy (PC3) is a 0 (Busy)
when Flash memory is being written to,
or
when
Flash memory is being erased. The output is a 1
(Ready) when no WRITE or Erase cycle is in
progress.
Mem ory Op eration . The primary Flash memory
and secondary Flash memory are addressed
through the MCU Bus I nterface. T he MCU c an ac-
cess these memories in one of two ways:
■The MCU can execute a typical bus WRITE or
READ
operation
just as it would if accessin g a
RAM or ROM device using standard bus cycles.
■The MCU can execute a s pecific instruction that
consists of several WRITE and READ
operations. This involves writing specific data
patterns to special addresses within the Flash
memory to invok e an embedded algorithm.
These instructions are summarized in Table 8.
Typically, the MCU c an read F lash memory using
READ operations, just as it would read a ROM de-
vice. However, Flash m em ory can only be altered
using specific Erase and Progr am instructions. For
example, the MCU cannot write a single byte di-
rectly to Flash m emory as it would write a byte to
RAM. To program a byte into Flash memory, the
MCU must execute a Program instruction, then
test the status of the Program cycle. This status
test is achieved by a READ operation or polling
Ready/Busy (PC3).
Flash memory can also be read by using special
instructions to retrieve particular Flash device in-
formation (sector protect status and ID).
19/103
PSD8XXF2/3/4/5
Table 8. Instructions
No te : 1. All bus cycles are WRI T E bus cycles, ex cept the ones with t he “READ” label
2. All val ues are i n hexadec i m al:
X = Don’t Care. Addres ses of the fo rm XXXXh, in this table, must be even addresses
RA = Ad dress of the memor y l ocation to be read
RD = Dat a read from location RA during the READ cyc le
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of Write Strobe (WR, CNTL0) .
PA is an even ad dress fo r P SD in word programmin g mode.
PD = Dat a word to be program med at loc ation PA. Data is l atche d on the rising edge of Write S trobe (WR, CNTL0)
SA = Addres s of the se ctor to be erased or verified. Th e Sector Selec t (FS0- FS7 or CSBOOT0-CSBO OT3) of the se ctor to be
era sed, or verified, must be Active (Hig h).
3. Sector Select (FS 0 to FS7 or CSB OOT 0 to CSBOOT3) si gnals are act i ve High , and are def i ned in PSD soft Express.
4. Only address bits A11-A0 are used in i nstruction decoding.
5. No Unl ock or ins tructio n cycles are requir ed when the dev i ce is in the READ Mo de
6. The Reset instruction is required to return to t he RE AD Mode after reading the Flash ID, or after reading the Sector Protection Sta-
tus, or i f the Er ror Flag (D Q5/DQ13) bit goes High.
7. Additional sec tors to b e erased must be wr i tten at the end of the Sector Eras e i nstru ct i on withi n 80µs.
8. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and
(A1,A0)=(1,0)
9. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction.
10. The U nl ock Bypass Reset Flash in st ruction is required to retu rn to reading m em ory dat a when the dev i ce is in th e Unlock Bypass
mode.
11. The system may perform REA D and Program cycles in non-erasing sectors, read the Flash ID or read the Sect or Protection Status
when i n the Suspend Sec tor Erase m ode. The S uspend S ector Erase inst ruction i s valid onl y duri ng a S ector Erase cycl e.
12. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode.
1 3. The MCU can not inv oke the se i n stru ction s wh ile exe cutin g cod e from the sa me Fla sh me mory as t hat fo r whic h the ins truc tio n is
intended. The MCU must fetch, for example, t he code f rom the secondary Flash memory when reading the Sec tor Protection Status
of t h e primary Flash mem o ry.
Instruction FS0-FS7 or
CSBOOT0-
CSBOOT3 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7
READ51“READ”
RD @ RA
Read Main
Flash ID61AAh@
X555h 55h@
XAAAh 90h@
X555h Read identifier
(A6,A1,A0 = 0,0,1)
Read Sector
Protection6,8,13 1AAh@
X555h 55h@
XAAAh 90h@
X555h Read identifier
(A6,A1,A0 = 0,1,0)
Program a
Flash B yte13 1AAh@
X555h 55h @
XAAAh A 0h@
X555h PD@ PA
Flash Sector
Erase7,13 1AAh@
X555h 55h@
XAAAh 80h@
X555h AAh@ XAAA h 55h@
XAAAh 30h @
SA 30h7@
next SA
Flash Bulk
Erase13 1AAh@
X555h 55h@
XAAAh 80h@
X555h AAh@ XAAA h 55h@
XAAAh 10h @
X555h
Suspen d
Sector Erase 11 1B0 h@
XXXXh
Resum e
Sector Erase 12 130 h@
XXXXh
Reset61F0h@
XXXXh
Unlock Bypass 1 AAh@
X555h 55h@
XAAAh 20h@
X555h
Unlock Bypass
Program91A0h@
XXXXh PD @ PA
Unlock Bypass
Reset10 190h@
XXXXh 00h@
XXXXh
PSD8XXF2/3/4/5
20/103
INSTRUCTIONS
An instruction consists of a sequence of specific
operations. Each received byte is sequenti ally de-
coded by the PSD8XXFX and not executed as a
standard WRITE operation. The instr uction is exe-
cuted when the c orrect numbe r of bytes are prop-
erly received and the time between two
consecutive by tes is shorter t han the time-out pe-
riod. Some instructions are structured to include
READ operations after the initial WRITE opera-
tions.
The instruction must be followed exactly. Any in-
valid combination of instruction bytes or time-out
between two consecutive bytes while addressing
Flash memory resets the device logic into READ
Mode (Fl ash memory is read like a ROM device).
The PSD8XXFX supports the inst ructions sum ma-
rized in Tabl e 8:
Flash memory:
■Erase memory by chip or sector
■Suspend or resume sector erase
■Program a Byte
■Reset to READ Mode
■Read primary Flash Identifier value
■Read Secto r Protection Status
■Bypass (on the PSD833F 2, PSD834F 2,
PSD853F 2 and PSD854F2)
These inst ruc tions are detailed i n T able 8. F or ef-
ficient decoding of the instructions, the first two
bytes of an instruction are the coded cycles and
are followed by an instruction byte or confi rmation
byte. The coded cycles consist of writing the data
AAh to address X555h during the first cycle and
data 55h to address XAAA h d u r i ng the second c y-
cle. Address signals A 15-A 12 are Do n’t Care dur-
ing the instruction WRITE cycles. However, the
appropriate Sector Select (FS0-FS7 or
CSBOOT 0-CSBO OT3 ) m us t be selected.
The primary and secondary Flash memorie s have
the same instruction set (exce pt for Read Primary
Flash Identifier). The Sector Select signals deter-
mine which Flash memory is to receive and exe-
cute the i ns truction. The primary Flash memory is
selected if any one of Secto r Select (FS0-FS7) is
High, and the secondary Flash memory is selected
if any one of Sector Select (CSBOOT0-
CSBOOT3) i s High.
Power-down Instruction and Power-up Mode
Power-up Mode. The PSD8XXFX internal logic
is reset upon Power-up t o the READ Mode. Sec tor
Select (FS0-FS7 and CSBOOT0-CSBOOT3)
must be hel d Low, and Write Str obe (WR, CNTL0)
High, during Power-up for maximum security of
the data contents and to re move the poss ibility of
a byte being written on the first edge of Write
Strobe (WR, CNTL0). Any WRITE cycle initiation
is locked when VCC is b elo w V LKO.
READ
Under typical conditions, the MCU may read the
primary Flash memory or the secondary Flash
memory using REA D operations just as it would a
ROM or RAM device. Alternately, the MCU may
use REA D operations t o ob tain s tatus informat ion
about a Program or Erase cycle that is currently in
progress. Lastly, the MCU may use instructions to
read special data from these m em ory blocks. The
following sections describe these READ functions.
Read Memory Contents. Pr ima ry F lash memory
and secondary Flash memory are placed in the
READ Mode af ter Power-up, chip reset, or a Res et
Flash instruction (see Table 8). The MCU can read
the memory contents of t he primary Flash memory
or the secondary Flash memory by using READ
operations any time the READ operation is not
part of an instruction.
Read Primary Flash I dentifier. The primary
Flash memory identi fier is read with an instruction
composed of 4 operations: 3 specific WRITE oper-
ations an d a READ operation (s ee Table 8). Dur-
ing the READ operation , address bits A6, A1, and
A0 must be 0,0,1, respectively, and the a ppropri-
ate Sector Select (FS0-FS7) must be High. The
identifier for the PSD813F2/3/4/5 is E4h, and for
the PSD83xF2 or PSD85 xF2 it is E7 h.
Read Memory Sector Protection Statu s. The
primary Flash memory Sector Protect ion Status is
read with an instruction composed of 4 operations:
3 specific WRITE operations and a READ opera-
tion (see Table 8). During the READ operation, ad-
dress bits A6, A1, and A0 must be 0,1,0,
respectively, while Sector Select (FS0-FS7 or
CSBOOT0-CSBOOT3) designates the Flash
memory sector whose protection has to be veri-
fied. The READ operation produces 01h if the
Flash memory sector is protected, or 00h if the
sector is not protected.
The sector protection status for all NVM blocks
(primary Flash memory or second ary Flash mem -
ory) can also be read by the MCU accessing the
Flash Protection reg isters in PSD I/O sp ace. See
the section entitled “Flash Memory Sector Pro-
tect”, on page 25, f or register definitions.
21/103
PSD8XXF2/3/4/5
Reading the Erase/Pr ogram Status Bits. The
PSD8XXFX provides several status bits to be
used by the MC U to confirm th e compl etion of an
Erase or Program cycle of Flash memory. These
status bits minimize the t ime t hat the M CU spends
performing these tasks and are defined in Table 9.
The status bits can be read as many times as
needed.
For Flash memory, the MCU can perform a READ
operation to obtain these status bits while an
Erase or Program inst ruction is being executed by
the embedded algo ri thm. See t he section entitled
“Programming Flash Memory”, on page 22, f or de-
tails.
Data Polling Flag (DQ7). When erasing or pro-
gramming in Flash mem ory, the Data Polling Flag
(DQ7) bit outputs the complem ent of the bit bei ng
entered for programming/writing on the DQ7 bit.
Once the Program instruc tion or the WRITE oper-
ation is complet ed, the true logic value i s rea d on
the Data Polling Flag (DQ7) bit (in a REA D opera-
tion).
■Data Polling is effective after the fourth WRITE
pulse (for a Program in struction) or aft er the
sixth WRITE pulse (for an Erase instruction). It
must be performed at the address being
programmed or at an address within the Flash
memo ry sector being erased.
■Durin g an Erase cycle, th e Data Polli n g Flag
(DQ7) bit outputs a 0. After completion of the
cycle, the Data Polling Flag (DQ7) bi t outputs
the last bit programmed (it is a 1 after erasing).
■If the byte to be program me d is in a protected
Flash mem ory sector, the instruction is ignored.
■If all the Flash memory sectors to be erased are
prot e c ted , the D ata Polling Flag ( DQ7 ) b it is
reset to 0 for about 100µs , and t hen returns to
the previous addressed byte. No erasure is
performed.
Toggl e Fl ag (D Q6) . The PSD8XXFX offers an-
othe r w a y f or de t er mi n in g wh en t he F l as h m em o r y
Program cycle is completed. During the internal
WRITE operat ion and when eit her the F S0-FS 7 or
CSBOOT0-CSBOOT3 is true, the Toggle Flag
(DQ6) bit toggles from 0 to 1 and 1 to 0 on subse-
quent attempts to read any byte of the memory.
When the internal cycle is complete, the toggling
stops and the dat a read on the Data Bus D0-D7 i s
the addressed memory byte. The device is now
accessible for a new READ or WRITE operation.
The cycle is fi ni shed when two succ essive READs
yield the same output data.
■The Toggle Flag (DQ6) bit is effective after the
fourth WRITE pulse (for a Progra m instruction)
or after t he sixth WRITE pulse (for an Erase
instruction).
■If the byte to be program me d belongs to a
protected Flash memory sector, the instruction
is ignored.
■If all th e Flash me mory sectors selected for
erasure are protected, the Toggle Flag (DQ6) bit
toggles to 0 for about 100µs and then returns to
the previous addressed byte.
Error Flag (DQ5). During a normal Program or
Erase cycle , the Error Flag (DQ5) bit is to 0. T his
bit is set to 1 when there is a failure during Flash
memory Byte Program, Sector Erase, or Bulk
Erase cycle.
In the c as e of Flash memory programming, the Er-
ror Flag (DQ5) bit indicates the attempt to program
a Flash memory bit from the programmed state, 0,
to t he erased state, 1, whi ch is not valid. The Error
Flag (DQ5) bit may also indicate a Time-out condi-
tion while att empting to program a byte.
In case of an error in a Flash memory Sector Erase
or By te Program cycle, t he Flash m emory sector in
which the error occurred or to which the pro-
grammed byte belongs must no longer be used.
Other Flash memory sectors may still be used.
The Error Flag (DQ5) bit is reset after a Reset
Flash instruction.
Erase Time-out Flag (DQ3). The Erase Time-
out Flag (DQ 3) bit reflects the time-out period al-
lowed between two consecutive Sector Erase in-
structions. The Erase Time-out Flag (DQ3) bit is
reset to 0 after a Sector Erase c ycle for a time pe-
riod of 100µs + 20% unless an additional Sector
Erase instruction is decoded. After this time peri-
od, or when the additional Sector Erase ins truction
is decoded, the Erase Time-out Flag (DQ3) bit is
set to 1.
Table 9. Status Bit
Note: 1. X = Not guaranteed value, can be read either 1 o r 0.
2. DQ7-DQ0 represent the Data Bus bits, D7-D0.
3. FS0-F S7 and CSBOOT 0-CSB OOT3 are act i ve High.
Functi onal Block FS0-FS7/CSBOOT0-
CSBOOT3 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Flash Memory VIH Data
Polling Toggle
Flag Error
Flag XErase
Time-
out XXX
PSD8XXF2/3/4/5
22/103
Programming Flash Memory
Flash memory m ust be erased prior to being pro-
grammed. A byte of Flash memory is erased to all
1s (FFh), and is programmed by setting selected
bits t o 0. The MCU may erase Flash memory all at
once or by-secto r, but no t byte-by-by te. Howe ver,
the MCU may program Flash memory byte-by-
byte.
The primary and secondary Flash memories re-
quire the MCU to send an instruction to program a
byte or to erase sectors (see Table 8).
Once the MCU issues a Flash m emory Program or
Erase instruction, it m ust check for the statu s bits
for completion. The embedded algorithms that are
invoked inside the PSD8XXFX support several
means to provide status to the MCU. Status may
be checked using any of three methods: Data Poll-
ing, Data Toggle, or Ready/Busy (PC3).
Data Polling. Polling on the Data Polling Flag
(DQ7) bit is a method of checking whether a Pro-
gram or Erase cy cle i s in progress or has complet -
ed. Figure 5 sho ws the Data Polling algorithm.
When th e MCU issue s a Program i nstruction, t he
embedded algorithm within the PSD8XXFX be-
gins. The MCU then reads the location of the byte
to be programmed in Flash memory to check sta-
tus. The Data Polling Flag (DQ7) bit of this location
becomes t he complement of b7 of the original data
byte to be programmed. The MCU continues to
poll this location, compa ring t he Data P olling Fl ag
(DQ7) bit and monitoring t he Error Fl ag (DQ5) bit .
When the Data Polling Flag (DQ7) bit matches b7
of the original data, and the Error Flag (DQ5) bit
remains 0, the embedded algorithm is complete. If
the Error Flag (DQ5) bit is 1, the MCU should test
the Data Polling Flag (DQ7) bit again since the
Data Polling Flag (DQ7) bi t may have changed si -
multaneously with the Error Flag (DQ5) bit (see
Figure 5).
The Error Flag (DQ5) bit is set if either an internal
time-out occurred while the embedded algorithm
attempted to program the byte or if the MCU at-
tempted to program a 1 to a bit that was not erased
(not erased is logic 0).
It is suggest ed (as with all Flash memories) to read
the location again after the embedded program-
ming algorithm has completed, to compare the
byte t hat was wri tten to the Flas h memory with the
byte that was intended to be written.
When using the Data Polling method during an
Erase cycle, Figure 5 still applies. However, the
Data Polling Flag (DQ7) bit is 0 unti l the Erase c y-
cle is complete. A 1 on the Error Flag (DQ5) bit in-
dicates a time-out condition on the Erase cycle; a
0 indicates no error. The MCU can rea d any loca-
tion within the sector being erased to get the Data
Polling Flag (DQ7) bit and the Error Flag (DQ5) bit.
PSDsoft Express generates ANSI C code func-
tions which implement these Data Polling algo-
rithms.
Figu re 5. Da ta Po lli ng Flowchart
READ DQ5 & DQ7
at VALID ADDRESS
START
READ DQ7
FAIL PASS
AI01369B
DQ7
=
DATA YES
NO
YES
NO
DQ5
= 1
DQ7
=
DATA YES
NO
23/103
PSD8XXF2/3/4/5
Da ta Toggle. Check ing the Toggle Flag (DQ6) bit
is a method of determining wh eth er a P rogram or
Erase cycle is in progress or has completed. Fig-
ure 6 shows the Data Toggle algorithm.
When th e MCU issue s a Program instruction, the
embedded algorithm within the PSD8XXFX be-
gins. The MCU then reads the location of the byte
to be programmed in Flash memory to check sta-
tus. The Toggle Flag (DQ6) bit of this location tog-
gles each time the MCU reads this location until
the embedded algorithm is complete. The MCU
continues t o read this location, check ing the Tog-
gle Flag (DQ6) bit and monitoring the Error Flag
(DQ5) bit. When the Toggle Flag (DQ6) bit stops
toggling (two consecutive reads yield the same
value), and the Error Flag (DQ5) bit remains 0, the
embedded al gorithm is complete. If the Error Flag
(DQ5) bit is 1, the MCU should test the Toggle
Flag (DQ6) bit again, since the Toggle F lag (DQ6)
bit may have changed simultaneously with the Er-
ror Flag (DQ5) bit (see Figure 6).
Figu re 6. Da ta To ggl e Fl owchar t
The Error Flag (DQ5) bit is set if either an internal
time-out occurred while the embedded algorithm
attempted to program the byte, or if the MCU at-
tempted to program a 1 to a bit that was not erased
(not erased is logic 0).
It is suggest ed (as with all Flash memories) to read
the location again after the embedded program-
ming algorithm has completed, to compare the
byte that was written to Flash memory with the
byte that was intended to be written.
When using the Data Toggle method after an
Erase cycle, Figure 6 still applies. the Toggle Flag
(DQ6) bit toggles unt il the Erase cycle is complet e.
A 1 on the Error Flag (DQ5) bit indicates a time-out
condition on the Erase cycle; a 0 indicates no er-
ror. The MCU can read any location within the sec-
tor being eras ed to get the To ggle Flag (DQ 6) bit
and the Error F lag (DQ5) bit.
PSDsoft Express generates ANSI C code func-
tions which im plement these Data Toggling algo-
rithms.
Unlock Bypass (PSD833F2x, PSD834F2x,
PSD853F2x, PSD85 4F2x). The Unlock Bypass
instructions allow the system to program bytes to
the Flash memories faster than using the standard
Prog ram instruction. The Unlock Bypass mode is
enter ed by fi rst ini tiati ng two Unl ock cycle s. This is
followed by a third WRITE cycle containing the Un-
lock Bypass code, 20h (as shown in Table 8).
The Flash memory then enters the Unl ock Bypass
mode. A two-cycle Unlock Bypass Program in-
struction is all that is required to program in this
mode. The first cycle in this instruction contains
the Unlock Bypass Program code, A0h . The sec-
ond cycle contains the program address and data.
Additional data is programmed in the same man-
ner. These instructions dispense with the initial
two Unlock cycles required in the standard Pro-
gram instruction, resulting in faster total Flash
memory programmi ng.
During the Unlock Bypass mode, only the Unlock
Bypass Program and Unlock Bypas s Res et Flash
instructions are valid.
To e xi t the Unlo ck Bypass mode, the system must
issue the two -cycle Un lock Bypass Reset F lash in-
struction. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are
Don’t Care for both cycles. The Flash memory
then returns to READ Mode.
READ
DQ5 & DQ6
START
READ DQ6
FAIL PASS
AI01370B
DQ6
=
TOGGLE NO
NO
YES
YES
DQ5
= 1
NO
YES
DQ6
=
TOGGLE
PSD8XXF2/3/4/5
24/103
Erasing Flash Memory
Flash Bulk Erase. The Flash B ulk E rase instruc-
tion uses six WRITE operations followed by a
READ operation of the status register, as de-
scribed in T able 8. If any byte of the Bulk Erase in-
struction is wrong, the Bulk Erase instruction
aborts and the device is reset to the Read Flash
memory status.
During a Bulk Erase, the memory status may be
checked by reading the Error Flag (DQ5) bit, the
Toggle Flag (DQ6) bit, and the Data Polling Flag
(DQ7) bit, a s detailed in t he section ent itled “Pro-
gramming Fl ash Me mory”, on page 22. The Error
Flag (DQ5) bit returns a 1 if there has been an
Erase Failure (maximum number of Erase cycles
have been execute d).
It is not necessary to program the memory with
00h because the PSD8XXFX automatically does
this before erasing to 0FFh.
During execut ion of the Bulk Erase instruction, the
Flash mem ory does not accept any instructions.
Flash Sector Erase . The Sector Erase instruc-
tion uses six WRITE operations, as described in
Table 8. Additiona l Flash Secto r Erase codes and
Flash memory sector addresses can be written
subsequently to erase other Flash memory sec-
tors in parallel, without further coded cycles, i f the
additional bytes are transmitted in a shorter time
than the ti me-out period of about 100µs. The input
of a new Sector Erase co de restarts the time-out
period.
The status of the interna l timer can be monitored
through the level of the Erase Time-out Flag (DQ3)
bit. If the Erase Time-out Flag (DQ3) bit is 0, the
Sector Erase instruction has been received and
the time-out perio d is count ing. If the E rase Time-
out Flag (DQ3) bit is 1, the time-out period has ex-
pired and the PSD8XXFX is busy erasing the
Flash memory s ect or(s). Before and during Erase
time-out, any instruction other than Suspend Sec-
tor Erase and Resume Sector Erase instructions
abort the cycle that is current ly in progress, and re-
set the dev ice to READ Mod e. It is not necessary
to program the Flash memory sector with 00h as
the PSD8XXFX does this automatically before
erasing (byte = FFh).
During a Sector Erase, the memory status may be
checked by reading the Error Flag (DQ5) bit, the
Toggle Flag (DQ6) bit, and the Data Polling Flag
(DQ7) bit, a s detailed in t he section ent itled “Pro-
gramming Flash Memory”, on page 22.
During execution of the Erase cycle, the Flash
memory accepts only Reset and Susp end Se ctor
Erase instructions. Erasure of one F lash memory
sector may be suspended, in order to read data
from another Flash memory sector, and then re-
sumed.
Suspend Sector Erase. When a Sector Erase
cycle is in progress, the Suspend Sector Erase in-
struction can be used to suspend the cycle by writ -
ing 0B0h to any address when an appropriate
Sec tor Select (F S0-FS7 or CSBO OT 0-CSBOOT3)
is High. (See Table 8). This allows reading of data
from another Flash memory sector af ter t he Erase
cycle has been suspended. Suspend Sector
Erase is accep ted only during an E rase c ycle and
defaults to READ Mode. A Suspend S ect or Erase
instruction executed during an Erase time -o ut pe-
riod, in addition to suspending the Erase cycle, ter-
minates the time out period.
The Toggle Flag (DQ6) bit stops toggling when the
PSD8XXFX internal logic is suspended. The sta-
tus of this bit must be monitored at an address
within the F lash memory sector bei ng erased. The
Toggle Flag (DQ6) bit stops toggling between
0.1 µ s a nd 15 µ s a fter the Su spend Sect or Erase
instruction has been executed. The PSD8XXF X i s
then automatically set to READ Mode.
If an Suspend Sector Erase instruction was exe-
cuted, the following rules apply:
– Attempting to read from a Flas h memory sector
that was being erased outputs invalid data.
– Reading from a Flash sect or that was
not
being
erased is valid.
– The Flash memory
cannot
be programmed, and
only responds to Resume Sector Erase and
Reset Flash i nstructions (READ i s an operat ion
and is allowed).
– If a Res et Flash i nstruction i s received, data in
the Flash memory sector that was being er ased
is inv a lid.
Resume Sector Erase. If a Suspend Sector
Erase instruction was previously executed, the
erase cycle may be resumed wi th this instruction.
The Resume Sector Erase instruction consists of
writing 030h to a ny address while an appropriate
Sec tor Select (F S0-FS7 or CSBO OT 0-CSBOOT3)
is High. (See Table 8.)
25/103
PSD8XXF2/3/4/5
Specific Features
Flash Memory Sector Protect. Each primary
and secondar y Flash memory sector can be sepa-
rately protected against Program and Erase cy-
cles. Sector Protection provides additional data
security because it disables all Program or Erase
cycles. This mode can be activated through the
JTAG Port or a Device Programmer.
Sector protection c an be selected for each sector
using the PSDsoft Express Configuration pro-
gram. This automatically protec ts selected sectors
when the device is progr ammed through the JTAG
Port or a Devi ce Programmer. Flash memory sec-
tors can be unprotected t o allow updat ing of t heir
contents using the JTAG Port or a Device Pro-
grammer. The MCU can read (but cannot c hange)
the sector protection bi ts.
Any att empt to progr am or erase a protected Flash
memory sector is ignored by the dev ice. The V erify
operation results in a READ of the protected dat a.
This allows a guarantee of the r etention of the Pro-
tection status.
The sector protection status can be read by the
MCU through the Flash memory protection and
PSD/EE protection registers (in the CSIOP block).
See Table 10 and Table 11.
Table 10. Sector Protection/Secu rity Bit Definition – Flash Protection Register
No te: 1. Bit Defin it i ons:
Sec<i>_Prot 1 = Primary Flash memory or secondary Flash memory Sector <i> is write protected.
Sec<i>_Prot 0 = Pr imary Flash memor y or secondary Fla sh m emory S ector <i> is not write protected.
Table 11. Sec tor Protection/Security Bit Definition – PSD/EE Protection Register
No te: 1. Bit Defin it i ons:
Sec<i>_Prot 1 = Secondary Flash memory Sector <i> is write protected.
Sec<i>_Prot 0 = Secondary Flash memory Sector <i> is not write protected.
Secu rity_Bit 0 = Securi ty Bit in device has not been set.
1 = Secu ri ty Bit in de vi ce has be en set .
Reset Flash. The Reset Flash instruction con-
sists of one WRITE cycle (see Table 8). It can also
be optionally preceded by the standard two
WRITE decoding cycles (writing A Ah to 555h and
55h to AAAh). It mus t be executed after:
– Reading the Flash Protection Stat us or Flash ID
– An Error condition has occurred (and the device
has set the Error F lag (DQ5) bit to 1) during a
Flash memory Program or Erase cycle.
On the PSD 813F2 /3/4/5, the Reset Fla sh instruc-
tion puts the Flash memory back into normal
READ Mo de. It ma y ta ke t he F lash me mory up t o
a few milliseconds to complete the Reset cycle.
The Reset Flash instruction is ignored when it is is-
sued d uring a P rogram or B ulk E ras e cycle of the
Flash memory. The Reset Flash instruction aborts
any on-going Sector Erase cycle, an d returns the
Flash memory to the normal READ M ode within a
few m illiseco n ds .
On the PSD8 3xF2 or PSD85xF 2, the Res et Flash
instruction puts the Flash memory back into nor-
mal READ Mode. If an Error condition has oc-
curred (and the device has set the Error Flag
(DQ5) bit to 1) the Flash m emory is p ut back into
normal READ Mode within 25 µs of the Reset
Flash instruction having been issued. The Reset
Flash instruction is ignored when it is issued dur-
ing a Program or Bulk Erase cycle of the Flash
memory. The Reset Flash instruction aborts any
on-going Sector Erase cycle, and returns the
Flash memory to the normal READ Mode within
25 µs.
Reset (RESET) Signal (on the PSD83xF2 and
PSD85xF2). A pulse on Reset (RESET) aborts
any cycle that is in progress, a nd rese ts the Flash
memory to the READ Mode. When the reset oc-
curs during a Program or Erase cycle, the Flash
memory takes up to 25 µs to return to the READ
Mode. It is recomm ended that the Reset (RESET)
pulse (except for Power On Reset, as described
on page 63) be at least 25µs so that the Flash
memory is always ready for the MCU to fetch the
bootstrap instructions after the Reset cycle is c om-
plete.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Sec7_Prot Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Security_Bit not used not used not used Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
PSD8XXF2/3/4/5
26/103
SRAM
The SRAM is enabled when SRAM Sele ct (RS0)
from the DPLD is High. SRAM Select (RS0) can
contain up to two product terms, allowing flexible
mem o ry map p ing .
The SRAM can be backed up using an external
battery. The external battery should be connected
to Voltage S tand-by (VSTBY, PC2). I f you hav e an
external battery connected to the PSD8XXFX, the
contents of the SRAM are ret ained in the event of
a power loss. The contents of the SRAM are re-
tained so long as the battery voltage remains at
2 V or greater. If the supply voltage fall s below the
battery voltage, an internal power switch-over to
the battery occurs.
PC4 can be conf igured as an output that indicates
when pow er is being drawn from the ex ternal ba t-
tery. Battery-on In dicator (VB ATON, P C4) is Hi gh
with the supply vol tage falls below the battery volt -
age and the battery on Voltage Stand-by (VSTBY,
PC2) is supplying power to the internal SRAM.
SRAM Select (RS0), Voltage Stand-by (VSTBY,
PC2) and Battery-on Indicator (VBATON, PC4)
are all configured using PSDsoft Express Confi gu-
ration.
Sector Select and SRAM Select
Sector Select (FS0-FS7, CSBOOT0-CSBOOT3)
and SRAM Select (RS0) are all outputs of the
DPLD. They are setup by writing equations for
them in P SD abel . The f ollowing rules apply t o the
equations for these signals:
1. Primary Flash memory and secondary Flash
memory Sector Select signals m ust
not
be
larger than the physical sector size.
2. A ny primary Flash mem ory sector must
not
be
mapped in the same memory space as another
Flash memory sector.
3. A seconda ry Flash memo ry sector must
not
be
mapped in the same memory space as another
secondary Flash mem ory sector.
4. SRAM, I/O, and Peripheral I/O spaces must
not
overlap.
5. A secondary Flash memory sector
may
over l ap
a primary Flash memory sector. In case of
overlap, priority is gi ven t o the s econdary Flash
memory sector.
6. S RA M, I/O, and Peripheral I/O spaces
may
overlap any other memory sector. Priority is
given to the SRAM, I/O, or Peripheral I/O.
Example. FS0 is val id when the address is in the
range of 8000h to BFF Fh, CSBOOT0 is valid from
8000h to 9FFFh, and RS0 is valid from 8000h to
87FFh. Any address in the range of RS0 always
accesses the SRAM . Any address in th e rang e of
CSBOOT0 greater than 87FFh (and less than
9FFFh) automa tically addre sses seco ndary Flash
memory segment 0. Any address greater than
9FFFh accesses the primary Flash memory seg-
ment 0. You can see that half of the prim ary Flash
memory segment 0 and one-fourth of secondary
Flash memory segment 0 cannot be accessed in
this example. Also note tha t a n equation that de-
fined FS1 to anywhere in the range of 8000h to
BFFFh would
not
be valid.
Figure 7 shows the priority levels for all memory
components . Any component on a higher level can
overlap and has priority over any component on a
lower level. Components on the same level must
not
over lap. Level one has the hi ghest priority and
level 3 has t he lowest.
Figure 7. Priority Level of Memory and I/O
Components
Level 1
SRAM, I/O, or
Peripheral I/O
Level 2
Secondary
Non-Volatile Memory
Highest Priority
Lowest Priority
Level 3
Primary Flash Memory
AI02867D
27/103
PSD8XXF2/3/4/5
Memory Select Configuration for MCUs with
Separa te Program an d Data Spaces. The 8031
and compatible family of MCUs, which includes
the 80C51, 80C151, 80C251, and 80C51XA , have
separate address spaces for Program memory
(selected using Program Select Enable (PSEN,
CNTL2)) and Data memory (selected using Read
Strobe (RD, CNT L1)). Any of the memories within
the PSD8XXFX can reside in either space or both
spaces. This is controlled through manipulation of
the VM register that res ides in the CSIOP space.
The VM register is set using PSDsoft Express to
have an initial value. It can subsequently be
changed by the MCU so that memory mapping
can be changed on-t he-fly.
For example, you may wish to have SRAM and pri-
mary Flash memory in the Data spac e at Boot-up,
and secondary Flash memory in the Program
space at B oot -up, and later swap the primary and
secondary Flash memories. This is easily done
with the VM register by using PSDsoft Express
Configuration to configure it for Boot-up and hav-
ing the MCU change it when desired. Table 12 de-
scribes the VM Register.
Table 12. VM Register
Configuration Modes for MCUs with Separate
Program and Data Spaces. Separate Space
Modes. Program space is separated from Data
space. For example, Program Select Enable
(PSEN, CNTL2) is used to access the program
code from the primary Flash m emory, whi le Read
Strobe (RD, CNTL1) is used to access data from
the secondary Flash memory, SRAM and I/O Port
blocks. This configuration requires the VM regis ter
to be set to 0Ch (see F igure 8).
Figure 8. 8031 Memor y Mod ules – Separate S pac e
Bit 7
PIO_EN Bit 6 Bit 5 Bit 4
Primary
FL_Data
Bit 3
Secondary
EE_Data
Bit 2
Primary
FL_Code
Bit 1
Secon dary
EE_Code
Bit 0
SRAM_Code
0 = disable
PIO mode not used not used
0 = RD
can’t
access
Flash
memory
0 = RD can’t
access Secondary
Flash memory
0 = PSEN
can’t
access
Flash
memory
0 = PSEN can’t
access Secondary
Flash memory
0 = PSEN
can’t
access
SRAM
1= enable
PIO mode not used not used
1 = RD
access
Flash
memory
1 = RD access
Secondary Flash
memory
1 = PSEN
access
Flash
memory
1 = PSEN access
Secondary Flash
memory
1 = PSEN
access
SRAM
Primary
Flash
Memory
DPLD Secondary
Flash
Memory
SRAM
RS0
CSBOOT0-3
FS0-FS7 CS CSCS
OE OE
RD
PSEN
OE
AI02869C
PSD8XXF2/3/4/5
28/103
Combined Space Mo des. The Program and
Data spaces are combined into one memory
space that al lows the prim ary Flash memory, sec-
ondary Flash memory, and S RAM to be accessed
by either Progra m Select Enable (PSEN, CNTL2)
or Read Strobe (RD, CNTL1). For example, to
configure the primary F lash m em ory in Combi ned
space, bits b2 and b4 of the VM regist er are set to
1 (see Figure 9).
Figure 9. 8031 Memor y Mod ules – Combi ne d Space
Primary
Flash
Memory
DPLD Secondary
Flash
Memory
SRAM
RS0
CSBOOT0-3
FS0-FS7
RD
CS CSCS
RD
OE OE
VM REG BIT 2
PSEN
VM REG BIT 0
VM REG BIT 1
VM REG BIT 3
VM REG BIT 4
OE
AI02870C
29/103
PSD8XXF2/3/4/5
Page Re gi st er
The 8-bit Page Register increas es the addressing
capability of the MCU by a fact or of up to 256. The
contents of the register can also be read by the
MCU. The outputs of the Page Register (PGR0-
PGR7) are inputs to the DPLD decoder and can be
included in the Sector Select (FS0-FS7,
CSBOOT0-CSBOOT3), and SRAM Select (RS0)
equations.
If memory pagi ng is not needed, or if not all 8 page
register bits are needed for memory paging, then
these bits may be used in the CPLD for general
logic. See Application Note
AN1154
.
Figure 10 s hows the Page Register. The ei ght flip-
flops in the register are connected to the internal
data bus D0-D7. The MCU can write to or read
from the Page Register. The Page Register can be
accessed at address loc ati on CSIOP + E0h.
Figure 10. Page Register
RESET
D0-D7
R/W
D0 Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D1
D2
D3
D4
D5
D6
D7
PAGE
REGISTER
PGR0
PGR1
PGR2
PGR3 DPLD
AND
CPLD
INTERNAL
SELECTS
AND LOGIC
PLD
PGR4
PGR5
PGR6
PGR7
AI02871B
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PLDS
The PLDs bring programmable logic functionality
to the PSD8XXFX. After specifying the logic for the
PLDs using the PSDabel tool in PSDsof t Express,
the logic is program med into the device and avail-
able upon Power-up.
The PSD8XXFX contains two PLDs: the Decode
PLD (DPLD), and the Co mplex P LD (CP LD). T he
PLDs are briefly discussed in the next few para-
graphs, and in more detail in the section entitled
“Decode PLD (DPLD)”, on page 32, and the sec-
tion entitl ed “Complex PLD (CPLD)”, also on page
33. Figure 11 shows the configuration of t he PLDs.
The DPLD performs address decoding for Select
signals for internal co mponent s, such as memory,
registers, and I/O ports.
The CPLD can be us ed for logic funct ions, such as
loadable counters and shift registers, state ma-
chines, and encoding and decoding logic. These
logic functions can be constructed using the 16
Output Macrocells (OMC), 24 Input Macrocells
(IMC), and the AND Array. The CPLD can also be
used to generate External Chip Select (ECS0-
ECS2) signals.
The AND Array is used to form product terms.
These product terms are specified using PSDabel.
An I nput Bus consisting of 73 si gnal s is connected
to the P LDs. The signals are shown in Table 13.
The Turb o B it in PS D 8X X FX
The PLDs in the PS D8XXFX can minimize power
consump tio n by sw itching of f when i nputs rema in
unchanged for an extended time of about 70ns.
Resetting the Turbo bit to 0 (Bit 3 of PMMR0 ) au-
tomatically places the PL Ds into standby if no in-
puts are changing. Turning the Turbo mode off
increases propagation delays while reducing pow-
er consumpt ion. See the section enti tled “P OWER
MANAGEMENT”, on page 58, on how to set the
Turbo bit.
Additionally, five bits are available in PMMR2 to
block MCU contr ol signals from entering t he PLDs.
This reduces power consumption and can be used
only when these MCU control signals are not used
in PLD logic equations.
Each of the two PLDs has unique characteristics
suited for its applications. They are described in
the following sections.
Tab le 13. D PL D and C P LD I nputs
Note: 1. The ad dress inputs are A19-A4 in 80C51XA m ode.
Input Source Input Name Number
of
Signals
MCU Address Bus1A15-A0 16
MCU Control Signals CNTL2-CNTL0 3
Reset RST 1
Power-down PDN 1
Port A Input
Macrocells PA7-PA0 8
Port B Input
Macrocells PB7-PB0 8
Port C Input
Macrocells PC7-PC0 8
Port D Inputs PD2-PD0 3
Page Register PGR7-PGR0 8
Macrocell AB
Feedback MCELLAB.FB7-
FB0 8
Macrocell BC
Feedback MCELLBC.FB7-
FB0 8
Secondary Flash
memory Program
Status Bit Ready/Busy 1
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PSD8XXF2/3/4/5
Figure 11. PLD Diagram
PLD INPUT BUS
8
INPUT MACROCELL & INPUT PORTS
DIRECT MACROCELL INPUT TO MCU DATA BUS
CSIOP SELECT
SRAM SELECT
SECONDARY NON-VOLATILE MEMORY SELECTS
DECODE PLD
PAGE
REGISTER
PERIPHERAL SELECTS
JTAG SELECT
CPLD
PT
ALLOC.
MACROCELL
ALLOC.
MCELLAB
MCELLBC
DIRECT MACROCELL ACCESS FROM MCU DATA BUS
24 INPUT MACROCELL
(PORT A,B,C)
16 OUTPUT
MACROCELL
I/O PORTS
PRIMARY FLASH MEMORY SELECTS
3PORT D INPUTS
TO PORT A OR B
TO PORT B OR C
DATA
BUS
8
8
8
4
1
1
2
1
EXTERNAL CHIP SELECTS
TO PORT D
3
73
16
73
24
OUTPUT MACROCELL FEEDBACK
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Decode PLD (DPLD)
The DPLD, shown in Figure 12, is used for decod-
ing the address for internal and external compo-
nents. The DPLD can be used to generate the
following decode signals:
■8 Sector Select (FS0-FS7) signals for the
primary Flash memory (three product terms
each)
■4 Sector Select (CSBOOT0-CS BOOT3) signals
for t he secondary Flash memory ( three product
terms each)
■1 internal SRAM Select (RS0) sig nal (two
product terms)
■1 internal CSIOP Select (PSD Configuration
Register) signal
■1 JTAG Select signal (enables JTA G on Port C)
■2 internal Peripheral Select signals
(Peripheral I/O mode).
Figure 12. DPLD Logic Array
(INPUTS)
(24)
(8)
(16)
(1)
PDN (APD OUTPUT)
I/O PORTS (PORT A,B,C)
(8)
PGR0 -PGR7
(8)
MCELLAB.FB [7:0] (FEEDBACKS)
MCELLBC.FB [7:0] (FEEDBACKS)
A[15:0]
*
(3)
(3)
PD[2:0] (ALE,CLKIN,CSI)
CNTRL[2:0] (READ/WRITE CONTROL SIGNALS)
(1)
(1)
RESET
RD_BSY
RS0
CSIOP
PSEL0
PSEL1
8 PRIMARY FLASH
MEMORY SECTOR SELECTS
SRAM SELECT
I/O DECODER
SELECT
PERIPHERAL I/O MODE
SELECT
CSBOOT 0
CSBOOT 1
CSBOOT 2
CSBOOT 3
FS0
FS7
3
3
3
3
3
3
3
3
3
3
3
3
2
JTAGSEL
AI02873D
FS1
FS2
FS3
FS6
FS5
FS4
1
1
1
1
33/103
PSD8XXF2/3/4/5
Complex PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable count ers and shift reg-
isters, system m ailboxes, ha ndshaking protocols,
state machines, and random logic. The CPLD can
also be us ed to gene ra te three External C hip Se-
lect (ECS0-ECS2), rout ed to Port D.
Although External Chip Select (ECS0-ECS2) can
be produced by any Output Macrocell (OMC),
th ese th ree Exte rnal Ch ip Se lect ( EC S0-ECS2) on
Port D do not consume any Output Macrocells
(OMC).
As shown in Figure 11, the CPLD has the following
blocks:
■24 Input Macroc ells (IMC)
■16 Output Macroc ells (OMC )
■Ma c ro ce ll Al lo c at o r
■Product Term A llocator
■AND Array capable of generating up to 137
product terms
■Four I/O Ports .
Each of the blocks are described in the sections
that follo w .
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the PSD8XXFX internal
data bus and can be directly accessed by the
MCU. This enables t he MCU software to load data
into the Output Macrocells (OMC) or read data
from both the Input and Output Macrocells (IMC
and OMC).
This feature allows efficient implementation of sy s-
tem logic an d eliminates the need to connect the
data bus to the AND Array as required in most
standard PLD macrocell architectures.
Figure 13. Macrocell and I/O Port
I/O PORTS
CPLD MACROCELLS
INPUT MACROCELLS
LATCHED
ADDRESS OUT
MUX
MUX
MUX
MUX MUX
D
D
Q
Q
Q
G
D
QD
WR
WR
PDR
DATA
PRODUCT TERM
ALLOCATOR
DIR
REG.
SELECT
INPUT
PRODUCT TERMS
FROM OTHER
MACROCELLS
POLARITY
SELECT
UP TO 10
PRODUCT TERMS
CLOCK
SELECT
PR DI LD
D/T
CK
CL
Q
D/T/JK FF
SELECT
PT CLEAR
PT
CLOCK
GLOBAL
CLOCK
PT OUTPUT ENABLE (OE)
MACROCELL FEEDBACK
I/O PORT INPUT
ALE/AS
PT INPUT LATCH GATE/CLOCK
MCU LOAD
PT PRESET MCU DATA IN
COMB.
/REG
SELECT MACROCELL
TO
I/O PORT
ALLOC.
CPLD
OUTPUT
TO OTHER I/O PORTS
PLD INPUT BUSPLD INPUT BUS
MCU ADDRESS / DATA BUS
MACROCELL
OUT TO
MCU
DATA
LOAD
CONTROL
AND ARRAY
CPLD OUTPUT
I/O PIN
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Outp ut Macrocell (OMC )
Eight of the Output Macrocells (OMC) are con-
nected to Ports A and B pins and are named as
McellAB0-McellAB7. The other eight macrocells
are connected to Ports B and C pins and are
named as McellBC0-Mcell BC7. If an McellAB out-
put is not assigned to a specific pin in PSDabel,
the Macrocell Allocator block assigns it to either
Port A or B . The same is true for a M cellBC output
on Port B or C. Table 14 shows the macrocells and
port assignment.
The Output Macrocell (OMC) architecture is
shown in Figure 1 4. As shown in the figure, there
are native product terms available from the AND
Array, and borrowed product terms available (if
unused) from other Output Macrocells (OMC). The
polarity of the product term is controlled by the
XOR gate. The Output Macrocell (OMC) can im-
plement either sequential logic, using the flip-flop
element, or combinatorial logic. The multiplexer
selects between the sequential or combinatorial
logic outputs. The multiplexer output can drive a
port pin and has a feedback path t o the AND Array
inputs.
The flip-flop i n the Output Mac rocell (OM C) block
can be configured as a D, T, JK, or SR type in the
PSDabel program. The flip-flop’s clock, preset,
and clear inputs may be driven from a product
term of the AND Arr ay. Alternatively, CLKIN (PD1)
can be used for the clock input t o the flip-flop. The
flip-flop is clocked on the rising edge of CLKIN
(PD1). The preset and clear are active High inputs.
Each clear input can use up to two product terms.
Table 14. Outp ut Macrocell Port and Data Bit Assignme nts
Output
Macrocell Port
Assignment Native Product Terms Maximum Borrowed
Product Terms Data Bit for Loading or
Reading
McellAB0 Port A0, B0 3 6 D0
McellAB1 Port A1, B1 3 6 D1
McellAB2 Port A2, B2 3 6 D2
McellAB3 Port A3, B3 3 6 D3
McellAB4 Port A4, B4 3 6 D4
McellAB5 Port A5, B5 3 6 D5
McellAB6 Port A6, B6 3 6 D6
McellAB7 Port A7, B7 3 6 D7
McellBC0 Port B0, C0 4 5 D0
McellBC1 Port B1, C1 4 5 D1
McellBC2 Port B2, C2 4 5 D2
McellBC3 Port B3, C3 4 5 D3
McellBC4 Port B4, C4 4 6 D4
McellBC5 Port B5, C5 4 6 D5
McellBC6 Port B6, C6 4 6 D6
McellBC7 Port B7, C7 4 6 D7
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PSD8XXF2/3/4/5
Product Term A l lo cat or
The CPLD has a Product Term Allocator. The PS-
Dabel compiler uses the Product Term Allocator to
borrow and pl ace produ ct term s from one mac ro-
cell to another. The following list summarizes how
product terms are allocated:
■McellAB0-McellAB 7 all hav e three native
product terms and may borrow up to six more
■McellBC0-McellBC3 all have four native product
terms and may borrow up to five more
■McellBC4-McellBC7 all have four native product
terms and may borrow up to six m ore.
Each macrocell may only borrow product terms
from certain other macrocells. Product terms al-
ready in use by one macrocell are not available for
another m acroc ell.
If an equation requires more product terms than
are available to it, then “external” product terms
are required, which consum e other Output Macro-
cells (OMC). If external product terms are used,
extra delay is added for the equation that required
the extra product terms.
This is called product term expansion. PSDsoft
Express performs this expansio n as neede d.
Loading and Reading the Output Macrocells
(OMC). The Output Macrocells (OMC) block oc-
cupies a memory location in the MCU address
space, as defined by the CSIOP block (see the
section entitled “I/O PORTS”, on page 48). The
flip-flops in each of the 16 Output Macrocells
(OMC) can be loaded from the data bus by a MCU.
Loading the Output Macrocells (OMC) with data
from the MCU takes priority over internal func-
tions. As such, th e preset, clear, and clock inputs
to the flip-flop can be overridden by the MCU. The
ability to load t he flip-flops and read them back is
useful in such applications as loadable counters
and shift registers, mailboxes, and handshaking
protocols.
Data can be loaded to the Output Macrocells
(OMC) on the trailing edge of Write Strobe (WR,
CNTL0) (edge loading) or during the time that
Write Strobe (WR, CNTL0) is active (level load-
ing). The method of loading is specified in PSDsoft
Express Configuration.
PSD8XXF2/3/4/5
36/103
Figu re 14. CP LD Output M acrocell
PT
ALLOCATOR
MASK
REG.
PT CLK
PT
PT
PT
CLKIN
FEEDBACK (.FB)
PORT INPUT
AND ARRAY
PLD INPUT BUS
MUX
MUX
POLARITY
SELECT
LD
IN
CLR
Q
PRDIN
COMB/REG
SELECT
PORT
DRIVER
INPUT
MACROCELL
I/O PIN
MACROCELL
ALLOCATOR
INTERNAL DATA BUS D[7:0]
DIRECTION
REGISTER
CLEAR (.RE)
PROGRAMMABLE
FF (D/T/JK/SR)
WR
ENABLE (.OE)
PRESET(.PR)
RD
MACROCELL CS
AI02875B
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PSD8XXF2/3/4/5
The OMC Mask Register. There is one Mask
Register for each of t he two groups of eight Output
Macrocells (OMC). The Mask Registers can be
used to block the loading of data to individual Out-
put Macrocells (OMC). The default value for the
Mask Registers is 00h, which allows loadi ng of the
Output Macrocells (OMC). When a given bit in a
Mask Register is set to a 1, the MCU is blocked
from writing to the associated Output Macrocells
(OMC). For example, suppose McellAB0-
McellAB3 are bei ng us ed for a state machi ne. You
would not want a MCU write to McellAB to over-
write the state machine registers. Therefore, you
would want to l oad the Mask Register for M c ellAB
(Mask M acrocell AB) wit h the value 0Fh.
The Outp ut Enable of the OM C. The Output
Macrocells (OMC) block can be connected to an I /
O port p in as a P LD output. The output enab le of
each port pi n driver is controlled by a single prod-
uct term from the AND Array, ORed with the Direc-
tion Register output. The pin is enabled upon
Power-up if no output enable equation is defined
and if th e pin is declared as a PLD output in PSD-
soft Express.
If the Output Macrocell (OMC) output is declared
as an internal node and not as a port p in output in
the PSDabel file, the port pin can be used for other
I/O functions. The internal node feedback can be
routed as an input to the AND Array.
Input Macro cells (IMC)
The CPLD has 24 Input Macroc ells (IMC), one for
each pin on Ports A, B, and C. The archi tecture of
the Input Macroce lls (IMC) is shown in Figure 15.
The Input Mac rocells (IMC) are indi vidual ly config-
urable, and can be used as a latch, register, or t o
pass incoming Port signals prior to driving them
onto the PLD input bus. The outputs of the Input
Macrocells (IMC) can be read by the MCU through
the internal data bus.
The enable for t he latch a nd c lock f or the regi ster
are driven by a multiplexer whose inputs are a
product term from the CPLD AND Array or the
MCU Address Strobe (ALE/AS). Each product
term output is used to latch or clock four Input
Macrocells (IMC). Port inputs 3-0 can be con-
trolled by one product term and 7-4 by another.
Configurations for the Input Macrocells (IMC) are
specified by equations written in PSDabel (see Ap-
plication Note
AN1171
). Outputs of the Input Mac-
rocells (IMC) can be read by the MCU via the IMC
buffer. See the section entitled “I/O PORTS”, on
page 48.
Input Macrocells (IMC) can use Address Strobe
(ALE/AS, PD0) to latch address bits higher than
A15. Any latched addresses are routed to the
PLDs as inputs.
Input Macrocells (IMC) are particularly us eful with
handshaking communication applications where
two processors pass data back and fo rth th ro ugh
a common mailbox. Figure 16 shows a typical con-
figuration where the Master MCU writes to t he Port
A Data Out Register. This, in turn, can be read by
the Slave MCU via the activation of the “Slave-
Read” output enable product term.
The Slave can also write to t he Port A Input Mac-
rocells (IMC) and the Master can then read the In-
put Macrocell s (IMC) direct ly.
Note that the “Slave-Read” and “Slave-Wr” signals
are product terms that are derived from the Slave
MCU inputs Read Strobe (RD, CNTL1), Write
Strobe (WR, CNTL0), and Slave_CS .
PSD8XXF2/3/4/5
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Figure 15. Input Macrocell
OUTPUT
MACROCELLS BC
AND
MACROCELL AB
PT
PT
FEEDBACK
AND ARRAY
PLD INPUT BUS
PORT
DRIVER
I/O PIN
INTERNAL DATA BUS D[7:0]
DIRECTION
REGISTER
MUX
MUX
ALE/AS
PT
Q
Q
D
D
G
LATCH INPUT MACROCELL
ENABLE (.OE)
D FF
INPUT MACROCELL _ RD
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PSD8XXF2/3/4/5
Figure 16. Handshaking Communication Using Input Macrocells
MASTER
MCU
MCU-RD
MCU-RD
MCU-WR
SLAVE–WR
SLAVE–CS
MCU-WR
D[7:0]
D[7:0]
CPLD DQ
QD
PORT A
DATA OUT
REGISTER
PORT A
INPUT
MACROCELL
PORT A
SLAVE–READ
SLAVE
MCU
RD
WR
AI02877C
PSD
PSD8XXF2/3/4/5
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MCU BUS INTERFACE
The “no-glue logic” MCU Bus Interface block can
be directly connected to most popular MCUs and
their control signals. Key 8-bit MCUs, with their
bus types and c ontrol signal s, are shown i n Tab le
15. The interface typ e is specified usin g the PSD-
soft Express Configuration.
PSD8XXFX Interface to a Multiplexed 8-Bit
Bus. Fi gure 17 shows an example of a system us-
ing a MCU with an 8-bit multiplexed bus and a
PSD8XXFX. The ADIO port on the PSD8XXFX is
connected directly to the MCU address/data bus.
Address Strobe (ALE/AS, PD0) latches the ad-
dress signals internally. Latched addresses can
be brought out to Port A or B. The PSD8XXFX
drives the ADIO data bus only when one of its in-
ternal resources is accessed and Read Strobe
(RD, CNTL1) i s active. Should the system address
bus exceed sixteen bits, Ports A, B, C, or D may
be used as additional address inputs.
Table 15. MCUs and their Control Signals
No te : 1. Unused CNTL 2 pin ca n be configured as CP LD inpu t. Other unused pi ns (PC7, PD0, PA3-0) can be confi gured for other I/ O func-
tions.
2. ALE /A S i nput is optional f or MCU s wi t h a non-multipl exed bus
MCU Data Bus
Width CNTL0 CNTL1 CNTL2 PC7 PD02ADIO0 PA3-PA0 PA7-PA3
8031 8 WR RD PSEN (Note 1)ALE A0 (Note 1) (Note 1)
80C51XA 8 WR RD PSEN (Note 1)ALE A4 A3-A0 (Note 1)
80C251 8 WR PSEN (Note 1) (Note 1)ALE A0 (Note 1) (Note 1)
80C251 8 WR RD PSEN (Note 1)ALE A0 (Note 1) (Note 1)
80198 8 WR RD (Note 1) (Note 1)ALE A0 (Note 1) (Note 1)
68HC11 8 R/W E(Note 1) (Note 1)AS A0 (Note 1) (Note 1)
68HC912 8 R/W E(Note 1)DBE AS A0 (Note 1) (Note 1)
Z80 8 WR RD (Note 1) (Note 1) (Note 1)A0 D3-D0 D7-D4
Z8 8 R/W DS (Note 1) (Note 1)AS A0 (Note 1) (Note 1)
68330 8 R/W DS (Note 1) (Note 1)AS A0 (Note 1) (Note 1)
M37702M2 8 R/W E(Note 1) (Note 1)ALE A0 D3-D0 D7-D4
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PSD8XXF2/3/4/5
Figure 17. An Example of a Typical 8-bit Multiplexed Bus Interface
MCU
WR
RD
BHE
ALE
RESET
AD[7:0]
A[15:8]
A[15:8]
A[7:0]
ADIO
PORT
PORT
A
PORT
B
PORT
C
WR (CNTRL0)
RD (CNTRL1)
BHE (CNTRL2)
RST
ALE (PD0)
PORT D
(OPTIONAL)
(OPTIONAL)
PSD
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PSD8XXFX Interf ace to a Non-Multiplexed 8-Bi t
Bus. Fi gure 18 shows an example of a system us-
ing a MCU with an 8-bit non-multiplexed bus and
a PSD8XXFX. The address bus is connected to
the ADIO Port, and the data bus is connected to
Port A. Port A is in tri-state mode when the
PSD8XXFX is not accessed by the MCU. Should
the system address bus exceed sixteen bits, Ports
B, C, or D may be us ed for additional address in-
puts.
Data Byte Enable Referen ce. MCUs have differ-
ent data byte orientations. Table 16 shows how
the PSD8XXFX interprets byte/wo rd operations in
different bus WRITE configurati ons. Even-byte re-
fers to locations with address A0 equal to 0 and
odd byte as locations with A0 equal to 1.
Table 16. Eight-Bit Data Bus
Figure 18. An Example of a Typical 8-bit Non-Multiplexed Bus Interface
BHE A0 D7-D0
X 0 Even Byte
X 1 Odd Byte
MCU
WR
RD
BHE
ALE
RESET
D[7:0]
A[15:0]
A[23:16]
D[7:0]
ADIO
PORT
PORT
A
PORT
B
PORT
C
WR (CNTRL0)
RD (CNTRL1)
BHE (CNTRL2)
RST
ALE (PD0)
PORT D
(OPTIONAL)
PSD
AI02879C
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PSD8XXF2/3/4/5
MCU Bus Interface Exa mples
Figure 19 to Figure 22 show examples of the basic
connections between the PSD8XXFX and some
popular MCUs. The PSD8XXFX Control input pins
are labeled as to the MC U fu nction for which they
are configured. The MCU bus interface is specified
using the PSDsoft Express Configuration.
80C31. Figure 19 shows the bus interface f or the
80C31, which has an 8-bit multiplexed address/
data bus. The lower address byte is multiplexed
with the data bus. The MCU control signals Pro-
gram Select Enable (PSE N, CNTL2), Read Strobe
(RD, CNTL1), and Writ e Strobe (WR, CNTL0) may
be use d for accessing the internal m emory and I/
O Ports blocks. Address Strobe (ALE/AS, PD0)
latches the address.
80C251. The Intel 80C251 M CU features a user-
configurable bus interface with four possible bus
configurations, as shown in Table 17.
Figure 19. Interfacing the PSD8XXFX wit h an 80C31
Table 17. 80C251 Configurations
Configuration 80C 251 READ /WRI TE
Pins Connecting to PSD8XXFX Pins Page Mode
1 WR
RD
PSEN
CNTL0
CNTL1
CNTL2
Non-Page Mode, 80C31
compatible A7-A0 multiplex with
D7-D0
2 WR
PSEN only CNTL0
CNTL1 Non-Page Mode
A7-A0 multiplex with D7-D0
3 WR
PSEN only CNTL0
CNTL1 Page Mode
A15-A8 multiplex with D7-D0
4 WR
RD
PSEN
CNTL0
CNTL1
CNTL2
Page Mode
A15-A8 multiplex with D7-D0
EA/VP
X1
X2
RESET
RESET
INT0
INT1
T0
T1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC2
PC1
PC3
PC4
PC5
PC6
PC7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
CNTL0(WR)
CNTL1(RD)
CNTL2(PSEN)
PD0-ALE
PD1
PD2
RESET
RD
WR
PSEN
ALE/P
TXD
RXD
RESET
29
28
27
25
24
23
22
21
30
39
31
19
18
9
12
13
14
15
1
2
3
4
5
6
7
8
38
37
36
35
34
33
32
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
31
32
33
34
35
36
37
39
40
41
42
43
44
45
46
47
48
50
49
10
9
8
7
6
5
4
3
2
52
51
PSD
80C31
AD7-AD0 AD[7:0]
21
22
23
24
25
26
27
28
17
16
29
30
A8
A9
A10
A11
A12
A13
A14
A15
RD
WR
PSEN
ALE
11
10
RESET
20
19
18
17
14
13
12
11
AI02880C
PSD8XXF2/3/4/5
44/103
The first configuration is 80C31-compatible, and
the bus interface to the PS D8XXFX is ident ical to
that shown in Figure 19. The second and third con-
figurations have the same bus connection as
shown in Figure 18. Ther e is only one Read Strobe
(PSEN) con nected t o CNTL1 on the PSD 8XXFX.
The A16 connection to PA0 allows for a larger ad-
dress input to the PSD8XXFX. The fourth configu-
ration is s hown in Figu re 20. Read Strobe (RD) is
connected to CNTL1 and Program Select Enable
(PSEN) is connected to CNTL2.
The 80C251 has two major operating modes:
Page mode and Non-page mode. In Non-page
mode, the data is multiplexed with the lower ad-
dress byte, and Address Strobe (ALE/ AS, PD0) is
act ive in eve ry bus cycle. I n Pag e mode, da ta (D7-
D0) is multiplexed wit h address (A15-A8). In a bus
cycle where there is a Page hit, Address Strobe
(ALE/AS, PD0) is not active and only addresses
(A7-A0) are changing. The PSD8XXFX supports
both modes. In Page Mode, the PSD bus timing is
identical to Non-Page Mode except the address
hold time and setup time with respect to Address
Strobe (ALE/AS, PD0) is not required. The PSD
access time is measured from address (A7-A0)
valid to dat a in va lid.
Table 18. Interfacing the PSD8XXF X with the 80C251, with One READ Input
No te : 1. The A16 and A17 connections are opt i onal.
2. In non-Page -M ode, AD7-AD0 connects to ADIO7-ADIO0.
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
CNTL0(WR)
CNTL1(RD)
CNTL2(PSEN)
PD0-ALE
PD1
PD2
RESET
32
26
43
42
41
40
39
38
37
36
24
25
27
28
29
30
31
33
A0
A1
A2
A3
A4
A5
A6
A7
AD8
AD9
AD10
AD14
AD15
AD13
AD11
AD12
A0
A1
A2
A3
A4
A5
A6
A7
AD8
AD9
AD10
AD11
AD15
ALE
WR
A16
RD
AD14
AD12
AD13
14
9
2
3
4
5
6
7
8
21
20
11
13
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P3.0/RXD
P3.1/TXD
P3.2/INT0
X2
X1
P3.3/INT1
RST
EA
A161
P0.1
P0.0
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
ALE
PSEN
WR
RD/A16
PC0
PC1
PC3
PC4
PC5
PC6
PC7
19
18
30
31
32
33
34
35
36
37
39
40
41
42
43
44
45
46
48
8
9
10
49
50
47
29
28
27
25
24
23
22
21
20
19
18
17
14
13
12
11
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
7
6
5
4
3
2
52
51
80C251SB PSD
RESET
RESET
35
P3.4/T0
P3.5/T1
16
15
17
10
RESET
PC2
AI02881C
A171
45/103
PSD8XXF2/3/4/5
Figure 20. Interfacing the PSD8XX FX wi th the 80C251, with RD and PSEN Inp uts
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
CNTL0(WR)
CNTL1(RD)
CNTL2(PSEN)
PD0-ALE
PD1
PD2
RESET
32
26
43
42
41
40
39
38
37
36
24
25
27
28
29
30
31
33
A0
A1
A2
A3
A4
A5
A6
A7
AD8
AD9
AD10
AD14
AD15
AD13
AD11
AD12
A0
A1
A2
A3
A4
A5
A6
A7
AD8
AD9
AD10
AD11
AD15
ALE
WR
PSEN
RD
AD14
AD12
AD13
14
9
2
3
4
5
6
7
8
21
20
11
13
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P3.0/RXD
P3.1/TXD
P3.2/INT0
X2
X1
P3.3/INT1
RST
EA
P0.1
P0.0
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
ALE
PSEN
WR
RD/A16
PC0
PC1
PC3
PC4
PC5
PC6
PC7
19
18
30
31
32
33
34
35
36
37
39
40
41
42
43
44
45
46
48
8
9
10
49
50
47
29
28
27
25
24
23
22
21
20
19
18
17
14
13
12
11
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
7
6
5
4
3
2
52
51
80C251SB PSD
RESET
RESET
35
P3.4/T0
P3.5/T1
16
15
17
10
RESET
PC2
AI02882C
PSD8XXF2/3/4/5
46/103
80C51XA. The Philips 80C51XA MCU family sup-
ports an 8- or 16- bit m ultiplexed bus that can have
burst cycles. Address bits (A3-A0) are not multi-
plexed, while (A19-A4) are multiplexed with data
bits (D15-D0) in 16-bit mode. In 8-bit mode, (A11-
A4) are multiplexed with data bits (D7-D0).
The 80C51XA can be configured to operate in
eight-bit data mode (as shown in Fi gure 21).
The 80C51XA improves bus throughput and per-
formance by execut ing burst cycles for code fetch-
es. In Burst Mode, address A19-A4 are latched
internally by the PSD8XXFX, while the 80C51XA
changes the A3-A0 signals to fetch up to 16 by tes
of code. The PSD access time is then measured
from address A3-A0 valid to data in valid. The PSD
bus timing require ment in Bu rst Mode is identical
to the normal bus cycl e, except the address setup
and hold time with respect to Address Strobe
(ALE/AS, PD0 ) does not apply.
Figure 21. Interfacing the PSD8XXFX with the 80C51X, 8-bit Data Bus
ADIO0
ADIO1
ADIO2
ADIO3
AD104
AD105
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
AD1012
AD1013
ADIO14
ADIO15
CNTL0(WR)
CNTL1(RD)
CNTL2(PSEN)
PD0-ALE
PD1
PD2
RESET
31
33
36
2
3
4
5
43
42
41
40
39
38
37
24
25
26
27
28
29
30
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
A12
A13
A14
A18
A19
A17
A15
A16
A0
A1
A2
A3
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
A12
A16
A17
A18
A19
A15
A13
A14
TXD1
T2EX
T2
T0
RST
EA/WAIT
BUSW
A1
A0/WRH
A2
A3
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
A12D8
A13D9
A14D10
A15D11
A16D12
A17D13
A18D14
A19D15
PSEN
RD
WRL
PC0
PC1
PC3
PC4
PC5
PC6
PC7
ALE
PSEN
RD
WR
ALE
32
19
18
30
31
32
33
34
35
36
37
39
40
41
42
43
44
45
46
48
8
9
10
49
50
47
7
9
8
16
XTAL1
XTAL2
RXD0
TXD0
RXD1
21
20
11
13
6
29
28
27
25
24
23
22
21
20
19
18
17
14
13
12
11
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
7
6
5
4
3
2
52
51
A0
A1
A2
A3
80C51XA PSD
RESET
RESET
35
17
INT0
INT1
14
10
15
PC2
AI02883C
47/103
PSD8XXF2/3/4/5
68HC11. Figure 22 shows a bus interface to a
68HC11 where the PSD8X XFX is confi gured in 8-
bit multiplexed mode with E and R/W settings. The
DPLD can be used to generate the READ and WR
signals for external devices.
Fig ur e 22. In t e rfacin g the PSD 8 XXFX with a 68HC11
9
10
11
12
13
14
15
16
ADIO0
ADIO1
ADIO2
ADIO3
AD104
AD105
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
AD1012
AD1013
ADIO14
ADIO15
CNTL0(R_W)
CNTL1(E)
CNTL2
PD0–AS
PD1
PD2
RESET
20
21
22
23
24
25
3
5
4
6
42
41
40
39
38
37
36
35
AD0
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A8
A9
A10
A14
A15
A13
A11
A12
AD1
AD2
AD3
AD4
AD5
AD6
AD7
E
AS
R/W
XT
EX
RESET
IRQ
XIRQ
PA0
PA1
PA2
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
VRH
VRL
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC0
PC1
PC3
PC4
PC5
PC6
PC7
PD0
PD1
PD2
PD3
PD4
PD5
MODA
E
AS
R/W
31
30
31
32
33
34
35
36
37
39
40
41
42
43
44
45
46
48
8
9
10
49
50
47
8
7
17
19
18
34
33
32
43
44
45
46
47
48
49
50
52
51
30
29
28
27
29
28
27
25
24
23
22
21
20
19
18
17
14
13
12
11
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
7
6
5
4
3
2
52
51
MODB
2
68HC11
PSD
RESET
RESET
AD7-AD0
AD7-AD0
PC2
AI02884C
PSD8XXF2/3/4/5
48/103
I/O POR TS
There are four programmable I/O ports: Ports A, B,
C, and D. Each of the ports is eight bits except Port
D, which is 3 bits. Eac h port pin is indi vidual ly user
configurable, thus allowing multiple functions per
port. The ports are configured using PSDsoft Ex-
press Configuration or by the MCU writing to on-
chip re giste rs in the CSIOP spa ce.
The topics discussed in this section are:
■Gen e ra l Po rt a rch itecture
■Port operating modes
■Port Configuration Registers (P CR)
■Port Data Re gisters
■Individual Port functi onality.
General Port Architecture
The general architecture of the I/O Port block is
shown in Figure 23. Individual Port architectures
are shown in Figure 25 to Figure 28. In general,
once the purpos e for a port pin has been defined,
that pin is no longer available fo r other purposes.
Exception s are noted.
As shown in Figure 23, the ports cont ain an out put
multiplexer whose select signals are driven by the
configuration bits in the Control Registers (P orts A
and B only) and PSDsoft Express Configuration.
Inputs to the m ul tiplexer include the following:
■Output data from the Data Out register
■Latched address outputs
■CPLD m acrocell output
■External Chip Select (ECS 0-ECS2) from the
CPLD.
The Port Data B uf fer (PDB) is a tri-state buffer t hat
allows only one source at a time to be read. The
Port Data Buffer (PDB) is connected to the Int ernal
Data Bus for feedback and can be read by the
MCU. The Data Out and macrocel l outputs, Direc-
tion and Control Registers, and port pin input are
all connected to the P ort Data Buffer (PDB).
Figu re 2 3. Ge nera l I/O P ort A rchi tec ture
INTERNAL DATA BUS
DATA OUT
REG.
DQ
D
G
Q
DQ
DQ
WR
WR
WR
ADDRESS
MACROCELL OUTPUTS
ENABLE PRODUCT TERM (.OE)
EXT CS
ALE
READ MUX
P
D
B
CPLD-INPUT
CONTROL REG.
DIR REG.
INPUT
MACROCELL
ENABLE OUT
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT PIN
DATA OUT
ADDRESS
AI02885
49/103
PSD8XXF2/3/4/5
The Port pin’s tri-state output driver enable is con-
trolled by a two input OR gate whose inputs come
from the CPLD AND Array enable product term
and the Direction Register. If the enable product
term of any of the Array outputs are not defined
and that port pin is no t defined as a CPLD output
in the PSDabel file, then the Direction Register has
sole control of t he buf fer that drives the port p in.
The conten ts of these registers can be alt ered by
the MCU. The Port Data Buffer (PDB) feedback
path a llows the M CU to che ck the contents of t he
registers.
Ports A, B, and C have embedded Input Macro-
cells (IMC). The Input Macrocells (IMC) can be
configured as lat ches, registers, or direct i nputs to
the PLDs. The latches and registers are clocked
by Address Strobe (ALE/AS, PD0) or a product
term from the PLD AND Array. The outputs from
the Input Macrocells (IMC) drive the PLD input bus
and can be read by the MCU. See the section en-
titled “Input Macrocell”, on page 38.
Port Operating Mode s
The I/O Ports have several modes of operation.
Some modes can be defined using PSDabel,
some by the MCU writing to the Control Registers
in CSIOP space, and some by both. The modes
that can only be defined using PSDsoft Express
must be programmed into the device and cannot
be changed unless the device is reprogrammed.
The modes that can be changed by t he MCU can
be done so dynam ically at run-time . The P LD I/O,
Data Port, Address Input, and Peripheral I/O
modes are the only modes that must be defined
before programming the device. All other modes
can be change d by the MCU at run-tim e. See Ap-
plication Note
AN1171
for m ore detail.
Table 19 summarizes which modes a re available
on each port. Table 22 shows ho w and where t he
different modes are configured. Each of the port
operating modes are described in the following
sections.
MCU I/O Mode
In t he MCU I/O m ode, the MCU uses the I /O Ports
block to expand its own I/O ports. By setting up the
CSIOP space, the ports on the PSD8XXFX are
mapped into the MCU address space. The ad-
dresses of the ports are listed in Table 7.
A port pin can be put into MCU I/O mode by writing
a 0 to the corresponding bit in the Control Regis-
ter. The MCU I/O direction may be changed by
writing to the corresponding bit in the Direction
Register, or by the output enable product term.
See the section entitled “Pe ripheral I/O Mode ”, on
page 51. When the pin is confi gured as an output,
the content of the Data Out Register drives the pin.
When configured as an input, the MCU can read
the port input through the Data In buf fer. See F ig-
ure 23.
Ports C and D do not have Control Registers, and
are in MCU I/O mode by default. They can be used
for PLD I/O if equations are written for them in P S-
Dabel.
PL D I/ O Mode
The P LD I/O Mode uses a po rt as an i nput to the
CPLD’s Input M acroc ells (IMC), and/ or as an out-
put from the CPLD’s Output Macrocells (OMC).
The output can be tri-stated with a control signal.
This output enable control signal can be defined
by a product ter m from the PLD, or by resett ing the
corresponding bit in the Direction Register to 0.
The corresponding bit in the Direction Register
must not be set to 1 if the pin is define d for a PLD
input signal in PSDabel. The PLD I/O mode is
specified in PSDabel by declaring the port pins,
and the n writing an equation assigning th e PLD I/
O to a port.
Address Out Mode
For MCUs with a multiplexed address/data bus,
Address Out Mode can be used to drive latched
addresses on to the port pins. These port pins can,
in turn, drive external devices. Either the output
enable or the corresponding bi ts of both t he Direc-
tion Register and Control Registe r must be set to
a 1 for pins to use Address Out M ode. This must
be done by the MCU at run-time. See Table 21 for
the address output pin assignments on Ports A
and B for v arious MCUs.
For non-mu lti plexed 8-bit bus m ode, address sig-
nals (A7-A0) are available to Port B in Address Out
Mode.
Note: Do not drive address signals with Address
Out M ode t o an external memory device if it is in-
tended for the MCU to B oot from the external de-
vice. The MCU must first Boot from PSD8XXFX
memory so the Direct ion and Control reg ister bits
can be set.
PSD8XXF2/3/4/5
50/103
Table 19. Port Operating Modes
No te : 1. Can be m ul tiple xed with other I/O functi ons.
Table 20. Port Op erating Mod e Settings
Not e: 1 . N/A = Not Applica b le
2. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product
term (.oe) from the CPLD AND Ar ray.
3. Any of these three methods enables the JTAG pins on Por t C.
Port Mode Port A Port B Port C Port D
MCU I/O Yes Yes Yes Yes
PLD I/O
McellAB Outputs
McellBC Outputs
Additional Ext. CS Outputs
PLD Inputs
Yes
No
No
Yes
Yes
Yes
No
Yes
No
Yes
No
Yes
No
No
Yes
Yes
Address Out Yes (A7 – 0) Yes (A7 – 0)
or (A15 – 8) No No
Address In Yes Yes Yes Yes
Data Port Yes (D7 – 0) No No No
Peripheral I/O Yes No No No
JTAG ISP No No Yes1 No
Mode Defined in
PSDabel
Defined in
PSD8XXFX
Configuration
Control
Register
Setting
Direction
Register
Setting
VM
Register
Setting JTAG Enable
MCU I/O Declare pins only N/A1 01 = output,
0 = input
(Note 2)N/A N/A
PLD I/O Logic equations N/A N/A (Note 2)N/A N/A
Data Port (Port A) N/A Specify bus type N/A N/A N/A N/A
Address Out
(Port A,B) Declare pins only N/A 1 1 (Note 2)N/A N/A
Address In
(Port A,B,C,D) Logic for equation
Input Macrocells N/A N/A N/A N/A N/A
Peripheral I/O
(Port A) Logic equations
(PSEL0 & 1) N/A N/A N/A PIO bit = 1 N/A
JTAG ISP (Note 3)JTAGSEL JTAG
Configuration N/A N/A N/A JTAG_Enable
51/103
PSD8XXF2/3/4/5
Table 21. I/O Port Latched Address Outpu t Assignments
Not e: 1 . N/A = Not Applica b le.
Address In Mode
For MCUs that have more than 16 address sig-
nals, the higher addresses can be connected to
Port A, B, C, and D. The address input can be
latched in the Input Macrocell (IMC) by Address
Strobe (ALE/AS, PD 0). Any input that is included
in the DPLD equations for the SRAM, or primary or
secondary Flash memory is considered to be an
address input.
Data Port Mode
Port A can be used as a data bus po rt for a MCU
with a non-multiplexed address/data bus. The
Data Port is connected to the data bus of the MCU.
The general I/O func t ions a re disabled in Port A if
the port is configured as a Data Port .
Peripheral I/ O M od e
Peripheral I/O mode can be used to interface with
external peripherals. In this mode, all of Port A
serves as a tri-state, bi-directional data buffer for
the MCU. Peripheral I/O Mode is enabled by set-
ting Bit 7 of the VM Register to a 1. Figure 24
shows how Port A acts as a bi-directional buffer for
the MCU data bus if Peripheral I/O Mode is en-
abled. An equation for PSEL0 and/or PSEL 1 mu st
be written in PSDabel. The buffer is tri-stated
when PSEL0 or PSEL1 is not active.
JTAG In-System Program mi ng (ISP)
Port C is JTAG compliant, and can be used for In-
System Programming (ISP). You can multiplex
JTAG operations with other functions on Port C
because In-System Program ming (ISP) is not per-
formed in normal Operating mode. For more infor-
mation on the JTAG Port, see th e sec tion entitled
“PROGRAMMING IN-CIRCUIT USING THE
JTAG SERIAL INTERFACE”, on page 65.
Figure 24. Peripheral I/O Mode
MCU Port A (PA3-PA0) Port A (PA7-PA4) Port B (PB3-PB0) Port B (PB7-PB4)
8051XA (8-Bit) N/A1 Address a7-a4 Address a11-a8 N/A
80C251
(Page Mode) N/A N/A Address a11-a8 Address a15-a12
All Other
8-Bit Multiplexed Address a3-a0 Address a7-a4 Address a3-a0 Address a7-a4
8-Bit
Non-Multiplexed Bus N/A N/A Address a3-a0 Address a7-a4
RD
PSEL0
PSEL1
PSEL
VM REGISTER BIT 7
WR
PA0-PA7
D0-D7
DATA BUS
AI02886
PSD8XXF2/3/4/5
52/103
Port Conf i guration R e g ist ers (PCR)
Each Port has a set of Port Configuration Regis-
ters (PCR) used for confi guration. The contents of
the registers can be accessed by the MCU through
normal READ/WRITE bus cycles at the addresses
given in Table 7. T he addresses i n T able 7 are the
offsets in hexadecimal from the base of the CSIOP
register.
The pins of a port are individually configurable and
each bit in the register controls its respective pin.
For example, Bit 0 in a r egister refers to Bit 0 of it s
port. The three Port Configuration Registers
(PCR), shown in Ta bl e 22, are used for setting the
Port configurations. The default Power-up state for
each register in Table 22 is 00h .
Control Register. Any bit reset t o 0 in t he Control
Register sets t he correspondi ng port pin to MCU I /
O Mode, and a 1 set s it to Address Out Mode. The
default mode is MCU I/O. Only Ports A and B have
an associated Control Regis ter.
Direction Register. The Direction Register, in
conjunction with the out put enable (except for Port
D), controls the direction of data flow in the I/O
Ports. Any bit set to 1 in the Direction Register
causes the corresponding pin t o be an output, and
any bit set to 0 causes it to be an input. The default
mode for all port pi ns is input.
Figure 25, page 54 a nd Figure 26 , page 55 show
the Port Architecture diagrams for Ports A/B and
C, respectively. The direction of data flow for Port s
A, B, and C are controlled not only by the direction
register, but also by the output enable product
term from the PLD AND Array. If the output enable
product term is not active, the Direction Register
has sole control of a given pi n’s direction.
An example of a configuration for a Port with the
three least significant bit s set to output and the re-
mainder set to input is shown in Table 25. Since
Port D only contains three pins (shown in Figure
28), the Direction Reg ister for Port D ha s only the
three least significant bit s active.
Drive Select Register. The Drive Select Register
configures the pi n driver as Open Drain or CM OS
for some port pins, and controls the slew rate for
the other port pins. An external pull-up resistor
should be used f or pi ns configured as Open Drain.
A pin can be configured as Open Drai n if its corre-
sponding bit in the Drive Select Register is set to a
1. The default pin drive is CMOS.
Note that the slew rate is a measurement of the
rise and fall times of an output. A higher slew rate
means a faster output response and may create
more electrical noise. A pin operates in a high slew
rate when the correspo nding bit in the Drive Reg-
ister is set to 1. T he def ault rate is slow slew.
Table 26 shows the Drive Regist er for P ort s A , B,
C, and D. It summarizes which pi ns can be config-
ured as Open Drain outputs and which pins the
slew rate can be set for.
Table 22. Port Configuration Registers (PCR)
No te : 1. See Ta ble 26 for Drive Regis te r bi t defi ni t ion.
Table 23. Port Pin Direction Control, Output
Enable P.T. Not Defined
Table 24. Port Pin Direction Control, Output
Enable P.T. Defined
Table 25. Port Direction Assignment Example
Register Name Por t MCU Access
Control A,B WRITE/READ
Direction A,B,C,D WRITE/READ
Drive Select1A,B,C,D WRITE/READ
Direction Register Bit Port Pin Mode
0 Input
1 Output
Direction
Register Bit Output Enable
P.T. Port Pin Mode
0 0 Input
0 1 Output
1 0 Output
1 1 Output
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 0 0 0 0 1 1 1
53/103
PSD8XXF2/3/4/5
Table 26. Drive Register Pin Assig nment
Note: 1. NA = Not Applicable.
Port Data Registers
The Port Data Registers, shown in Table 27, are
used by the MCU to write data to or read data f rom
the ports. Table 27 shows the register name, the
ports having each register type, and MCU a ccess
for each register type. The registers are described
below.
Data In. Port pins are connected directly to the
Data In buff er. In MCU I/O inpu t mode , the pin in-
put is read through t he Dat a In buffer.
Data Out Register. S tores output dat a written by
the MCU in the MCU I/O output mode. The con-
tents of the Register are driven out to the pins if the
Direction Register or the output enable product
term is set to 1. The contents of the register can
also be read bac k by the MCU.
Outp ut Macrocells (O MC). The CPLD Output
Macrocells (OMC) occupy a location in the MCU’s
address space. The MCU can read the output of
the Output Macrocells (OMC). If the OMC Mask
Register bits are not set, writing to the macrocell
loads data to the macrocell fli p-flops. See the sec-
tion entitled “PLDS”, on page 30.
OMC Mask Register. Each OMC Mask Register
bit corresponds to an Output Macrocell (OMC) flip-
flop. When the O MC Mask Regi ster bit is set to a
1, loading data into the Output Macrocell (OMC)
flip-flop is blocked. The default value is 0 or un-
blocked.
Input Macrocel ls (IMC). The Input Macrocells
(IMC) can be used to latch or store external inputs.
The outputs of the Input Macrocells (IMC) are rout-
ed to the PLD input bus, and can b e read by the
MCU. See the section entitled “PLDS”, on page
30.
Enable Out. The Enable Out register can be read
by the MCU. It contains the output enable values
for a given port . A 1 indicates the dri ver is in output
mode. A 0 indicates the driver is in tri-state and the
pin is in input mode.
Table 27. Port Data Registers
Drive
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Port A Open
Drain Open
Drain Open
Drain Open
Drain Slew
Rate Slew
Rate Slew
Rate Slew
Rate
Port B Open
Drain Open
Drain Open
Drain Open
Drain Slew
Rate Slew
Rate Slew
Rate Slew
Rate
Port C Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain
Port D NA1NA1NA1NA1NA1Slew
Rate Slew
Rate Slew
Rate
Register Name Port MCU Access
Data In A,B,C,D READ – input on pin
Data Out A,B,C,D WRITE/READ
Output Macrocell A,B,C READ – outputs of macrocells
WRITE – loading macrocells flip-flop
Mask Macrocell A,B,C WRITE/READ – prevents loading into a given
macrocell
Input Macrocell A,B,C READ – outputs of the Input Macrocells
Enable Out A,B,C READ – the output enable control of the port driver
PSD8XXF2/3/4/5
54/103
Ports A and B – F un ctionality and Structur e
Ports A and B have simi lar functionality and struc-
ture, as shown in Figure 25. The two ports can be
configured to perform one or more of the foll owing
functions:
■MCU I/O Mode
■CPLD Output – Macrocells Mc ellAB7-McellAB0
can be c onnected to Port A or Port B. McellBC7-
McellBC0 can be connected to Port B or Port C.
■CPLD Input – Via the Input Macro cells (IMC).
■Latched Ad dress output – Provide latched
address output as per Table 21.
■Address In – Additional high addre ss inputs
using the Input Mac rocells (IMC).
■Open Drain/ Slew Rat e – pi ns PA3-PA0 and
PB3-PB0 can be con figured to fast s l ew rate,
pins PA7-PA4 and PB7-P B4 can be configured
to Open Drain Mode.
■Data Port – Port A to D7-D0 for 8 bit non -
multiplexed bus
■Multiplexed Address/Dat a port for certain types
of MCU bus interfaces.
■Peripheral Mode – Port A only
Figure 25. Port A and Port B Structure
INTERNAL DATA BUS
DATA OUT
REG.
DQ
D
G
Q
DQ
DQ
WR
WR
WR
ADDRESS
MACROCELL OUTPUTS
ENABLE PRODUCT TERM (.OE)
ALE
READ MUX
P
D
B
CPLD-INPUT
CONTROL REG.
DIR REG.
INPUT
MACROCELL
ENABLE OUT
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT
A OR B PIN
DATA OUT
ADDRESS
A[7:0] OR A[15:8]
AI02887
55/103
PSD8XXF2/3/4/5
Port C – Function ality and Structure
Port C can be configured to perform one or more
of the f ollowing f unctions (see Figure 26):
■MCU I/O Mode
■CPLD Output – McellBC7-McellBC0 outputs
can be connected to Port B or P ort C .
■CPLD Input – via the Input Macroce lls (IMC)
■Address In – Additional high addre ss inputs
using the Input Mac rocells (IMC).
■In-System Programming (ISP) – JTAG port can
be enabled for programming/ erase of the
PSD 8XXF X dev ice. (See the section entitled
“PROGRAMMING IN-CIRCUIT USING THE
JTAG SER IAL INTERFA CE” , on page 65, for
more inf ormation on JTAG programming.)
■Open Drain – Port C pins can be configur ed in
Open Drain Mode
■Battery Backup features – PC2 can be
configured for a battery input supply, Voltage
Stand-by (VSTBY).
PC4 can be configured as a Battery-on Indicator
(VBATON), indicating when VCC is less than
VBAT.
Port C do es not support Address Out mode, and
therefore no Control Register is required.
Pin PC7 may be configured as the DBE input in
certain MCU bus interfaces.
Figure 26. Port C Structure
INTERNAL DATA BUS
DATA OUT
REG.
DQ
DQ
WR
WR
MCELLBC[7:0]
ENABLE PRODUCT TERM (.OE)
READ MUX
P
D
B
CPLD-INPUT
DIR REG.
INPUT
MACROCELL
ENABLE OUT
SPECIAL FUNCTION1
SPECIAL FUNCTION1
CONFIGURATION
BIT
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT C PIN
DATA OUT
AI02888B
PSD8XXF2/3/4/5
56/103
Port D – Function ality and Structure
Port D has t hree I/O pins. S ee F igure 27 and Fig-
ure 28. This port does not support Address Out
mode, and therefore no Control Register is re-
quired. Port D can be configur ed to perform one or
more of the following functions:
■MCU I/O Mode
■CPLD Output – Ext ernal Chip Select (ECS0-
ECS2)
■CPLD Input – direct input to the CPLD, no Input
Macroc ells ( IMC )
■Slew rate – pins can be set up for fast slew rate
Port D pins can be configured in PS Dsoft Express
as input pins for ot her dedicat ed func tions:
■Address Strobe (ALE/ AS, PD0)
■CLKIN (PD1) as input to the macrocells fl i p-
flops and APD counter
■PSD Chip Se lect Input (CSI , PD2 ) . Driving this
signal High disables the Flash memory, SRAM
and CSIOP.
Figure 27. Port D Structure
INTERNAL DATA BUS
DATA OUT
REG.
DQ
DQ
WR
WR
ECS[2:0]
READ MUX
P
D
B
CPLD-INPUT
DIR REG.
DATA IN
ENABLE PRODUCT
TERM (.OE)
OUTPUT
SELECT
OUTPUT
MUX
PORT D PIN
DATA OUT
AI02889
57/103
PSD8XXF2/3/4/5
External Chip Se lect
The CPLD also provides th ree External Chip Se-
lect (ECS0-ECS2) outputs on Port D pins that can
be used t o sele ct ext ernal devices . Eac h Ex te rnal
Chip Select (ECS0-ECS2) consists of one product
term that can be configured active High or Low.
The output enable of the pin is controlled by either
the output enable product term or the Direction
Register. (See Figure 28.)
Figure 28. Port D External Chi p Select Signals
PLD INPUT BUS
POLARITY
BIT
PD2 PIN
PT2 ECS2
DIRECTION
REGISTER
POLARITY
BIT
PD1 PIN
PT1 ECS1
ENABLE (.OE)
ENABLE (.OE) DIRECTION
REGISTER
POLARITY
BIT
PD0 PIN
PT0 ECS0
ENABLE (.OE) DIRECTION
REGISTER
CPLD AND ARRAY
AI02890
PSD8XXF2/3/4/5
58/103
POWER MANAGEMENT
All PSD8XXFX devices offer configurable power
saving options. These options may be used indi-
vidually or in co mbi nations, as follows:
■All memory blocks in a PSD8XXFX (primary and
secondary Flash memory, and SRAM) are built
with power management technology. In addition
to using special silicon design met hodolo gy,
power managem ent techno logy puts the
memories into standby mode when address/
data inputs are not changi ng (zero DC curr ent ).
As soon as a transition occurs on an input, the
affected m emory “wakes up”, changes and
latches its outputs, then goes back to standby .
The designer does
not
have to do anything
special to ac hieve memor y standby mode when
no inputs are changing— it happens
automatically.
The PLD sections can also achieve Stand-by
mode when its inputs are not changing, as
described in the sections on the Power
Managem ent Mod e Registers (PMMR ).
■As with the Power M anagement mode, the
Automatic Power Down (A PD) block allows the
PSD8XXF X to reduc e to stand-by current
autom atically. The APD Unit can also block
MCU address/data signals from reaching the
memories and PLDs. This feature is available
on all the devices of the PSD8XXFX family. The
APD Unit is des cribed in more detail in the
sections entitled “Automatic Power-down (APD)
Unit and Power-down Mode”, on page 59.
Built in logic monitors the Address Strobe of the
MCU for activity. If the re is no activity for a
certain time period (MCU is asleep), the APD
Unit i ni tiates Power-down mode (if enabled).
Once in Power-down mode, all address/data
signals are blocked from reaching PSD8X XFX
memo ry and PLDs, and the memories are
deselected internally. This allows the memory
and PLDs to remain in standby mode even if the
address/data signals are changing state
externally (noise, other devices on the MCU
bus, etc.). Keep in mind that any unblocked PLD
input signals that are changing states keeps the
PLD out of Stand-by mode, but not the
memories.
■PSD Chi p Se l e ct Input ( CSI, PD2) can be used
to disable the int ernal memori es, placing them
in standby mode even if inputs are changin g.
This feature does not block any i nternal signals
or disable the PLDs. This is a good alternative
to using the APD Unit. There is a slight penalty
in memo ry access time wh en PSD Chip Select
Input (CSI, PD2) makes its initial transition from
deselected to selected.
■The PMMR s can be written by the MC U at run-
time to manage power. All PSD8XXFX supports
“blocking bit s” in these registers that are set to
block designated signals from reachi ng bot h
PLDs. Current consumption of the PLDs is
directly related to the composite frequency of
the changes on thei r i nputs (see Figure 32 and
Figure 33). Significant power savings can be
achieved by blocking signals that are not used
in DPLD or CPLD logic equations.
PSD 8XXF X dev ices hav e a Turbo bit in
PMMR0. This bit can be set to turn the Turbo
mode off (the defaul t is with Turbo mode turned
on). While Turbo mode is off, the PLDs can
achieve standby current when no PLD inputs
are changing (zero DC current). Even when
inputs do change, significant power can be
saved at lower frequencies (AC current),
compared to when Turbo mode is on. When the
Turbo mode is on, there is a significant DC
current componen t and the AC compo nent is
higher.
59/103
PSD8XXF2/3/4/5
Automatic Power-d own (APD) Unit and Power-
down Mode. T he APD Unit, shown in F igure 29,
puts the PSD8XXFX into Power-down mode by
monitoring the activity of Address St robe (ALE/AS,
PD0). If the APD Unit is enabled, as soon as activ-
ity on Address Strobe (ALE/AS, PD0) stops, a four
bit counter starts counting. If Address Strobe
(ALE/AS, PD0) remains inactive for fifteen clock
periods of CLKIN (PD1), Power -down (PDN) goes
High, and the PSD8XXFX enters Power-down
mode, as discussed next.
Po we r-down Mode . By default, i f you enable the
APD Unit, Power-down mode is automatically en-
abled. The device enters P ower-down mode if Ad-
dress Strobe (ALE/AS, PD0) remains inactive for
fifteen periods of CLKIN (PD1).
The following should be kept in mind when the
PS D8 XXFX i s in Po w er-down mo d e:
■If Address Strobe (ALE/AS, PD0) starts pul sing
again, the PSD8XX FX returns to normal
Operating mode. The PSD8XXFX als o returns
to normal Operating mode if either PSD Chip
Select Input (CSI, PD2) is Low or the Reset
(RESET) input is High.
■The MCU address/data bus is blocked from all
memory and PLDs.
■Various signal s can be blocked (prior to Power-
down mode) from entering the PLDs by setting
the appropriate bits in the PMMR registers. The
blocked signa ls include MCU control signals
and the common CLK IN (PD1). Note that
blocking CLKIN (PD1) from the PLDs does not
block CLKIN (PD1) from the APD Unit.
■All PSD8XXF X memories enter Standby mode
and are drawing standby current. However, the
PLD and I/O ports blocks do
not
go into Standby
Mode because you don’t want to have to wait for
the logic and I/O to “wake-up” before thei r
outputs can change. See Table 28 for Power-
down mode ef fects on PSD8X XFX ports.
■Typical standby current is of the order of
microam peres . These standby cu rrent values
assume that there are no transitions on any PLD
input.
Tab le 28. Po wer- d own Mode ’ s Effe ct on Ports
Figure 29. APD Unit
Tab le 29. PSD 8XXFX Ti m in g and Sta n d- by C u rre n t du ri ng Pow e r-down Mod e
Note: 1. Powe r-down does not aff ect the operation of t he PLD. The PLD o peration in this mo de is based only on the Turbo bit.
2. Typi cal current consum ption assumi ng no PLD inputs ar e changing state and the PL D T urbo bi t is 0.
Port Function Pin Level
MCU I/O No Change
PLD Out No Change
Address Out Undefined
Data Port Tri-State
Peripheral I/O Tri-State
Mode PLD Propagation
Delay Memory
Access Time Access Recovery Time
to Normal Access
Typical Stand-by Current
5V VCC 3V VCC
Power-down Normal tPD (Note 1)No Access tLVDV 75 µA (Note 2) 25 µA (Note 2)
APD EN
PMMR0 BIT 1=1
ALE
RESET
CSI
CLKIN
TRANSITION
DETECTION
EDGE
DETECT
APD
COUNTER
POWER DOWN
(PDN)
DISABLE BUS
INTERFACE
EEPROM SELECT
FLASH SELECT
SRAM SELECT
PD
CLR
PD
DISABLE
FLASH/EEPROM/SRAM
PLD
SELECT
AI02891
PSD8XXF2/3/4/5
60/103
For Users of the HC11 (or compatible ). The
HC11 turns off its E clock when it sleeps. There-
fore, if you are using an HC11 (or compatible) in
your design, and you wish to use the Power-down
mode, you must not connect the E clock to CLKIN
(PD1). You should i nstead connect a crystal oscil-
lator to CLKIN (PD1). The crystal oscillator fre-
quency mu st be
less than
15 times t he frequency
of AS. The reason for this is that if the frequency is
greater than 15 times the frequency of AS, the
PSD8XXFX keeps going into Power-down mode.
Othe r Po wer S aving Options. The PSD8XXFX
offers other reduced power saving options that are
independent of the P ower-down m ode. Except for
the SRAM Stand-by and PSD Chip Select Input
(CSI, PD2) features, they are enabled by setting
bits in PMMR0 and PMMR2.
Figure 30. Enable Power-down Flow Chart
Enable APD
Set PMMR0 Bit 1 = 1
PSD in Power
Down Mode
ALE/AS idle
for 15 CLKIN
clocks?
RESET
Yes
No
OPTIONAL
Disable desired inputs to PLD
by setting PMMR0 bits 4 and 5
and PMMR2 bits 2 through 6.
AI02892
61/103
PSD8XXF2/3/4/5
PL D Power Manage m e nt
The power and spee d of the PLDs are con trolled
by the Turb o bit (bit 3) in PMMR0. By setting the
bit to 1, the Turbo mode is of f and the P LDs con-
sume the spe cifie d stan d-by current when the in-
puts are not switching for an extended time of
70ns. The propaga tion d elay time is increased by
10ns after the Turbo bit is set to 1 (turned off) when
the inputs change at a composite frequency of less
than 15 MHz. When the Turbo bit is reset to 0
(turned on), the PLDs run at full power and speed.
The Turbo bit affects the PLD’s DC power, AC
power, and propagation delay.
Blocking MCU control signals with the bits of
PMMR2 can further reduce PLD AC power con-
sumption.
Table 30. Power Management Mode Registers PMMR0 (Note 1)
Note: 1. The bits of this register a re clear ed to zero following Power-up. Subsequent Re set (RESET) pulses do not clear the reg i st ers.
Table 31. Power Management Mode Registers PMMR2 (Note 1)
Note: 1. The bits of this register a re clear ed to zero following Power-up. Subsequent Re set (RESET) pulses do not clear the reg i st ers.
Bit 0 X 0 Not used, and should be set to zero.
Bit 1 APD Enable 0 = off Automatic Power-down (APD) is disabled.
1 = on Automatic Power-down (APD) is enabled.
Bit 2 X 0 Not used, and should be set to zero.
Bit 3 PLD Turbo 0 = on PLD Turbo mode is on
1 = off PLD Turbo mode is off, saving power.
Bit 4 PLD Array clk 0 = on CLKIN (PD1) input to the PLD AND Array is connected. Every change of CLKIN
(PD1) Powers-up the PLD when Turbo bit is 0.
1 = off CLKIN (PD1) input to PLD AND Array is disconnected, saving power.
Bit 5 PLD MCell clk 0 = on CLKIN (PD1) input to the PLD macrocells is connected.
1 = off CLKIN (PD1) input to PLD macrocells is disconnected, saving power.
Bit 6 X 0 Not used, and should be set to zero.
Bit 7 X 0 Not used, and should be set to zero.
Bit 0 X 0 Not used, and should be set to zero.
Bit 1 X 0 Not used, and should be set to zero.
Bit 2 PLD Array
CNTL0 0 = on Cntl0 input to the PLD AND Array is connected.
1 = off Cntl0 input to PLD AND Array is disconnected, saving power.
Bit 3 PLD Array
CNTL1 0 = on Cntl1 input to the PLD AND Array is connected.
1 = off Cntl1 input to PLD AND Array is disconnected, saving power.
Bit 4 PLD Array
CNTL2 0 = on Cntl2 input to the PLD AND Array is connected.
1 = off Cntl2 input to PLD AND Array is disconnected, saving power.
Bit 5 PLD Array
ALE 0 = on ALE input to the PLD AND Array is connected.
1 = off ALE input to PLD AND Array is disconnected, saving power.
Bit 6 PLD Array
DBE 0 = on DBE input to the PLD AND Array is connected.
1 = off DBE input to PLD AND Array is disconnected, saving power.
Bit 7 X 0 Not used, and should be set to zero.
PSD8XXF2/3/4/5
62/103
SRAM Stand by Mode (Battery Backup). The
PSD8XXFX supports a battery backup mode in
which the content s of the SRAM are ret ained in the
event of a power loss. The SRAM has Voltage
Stand-by (VSTBY, PC2) that can be connected to
an external battery. When VCC becomes lower
than VSTBY then the PSD8XXFX automatically
connects to Voltage Stand-by (VSTBY, PC2) as a
power source to the SRAM. The SRAM Standby
Current (ISTBY) is typically 0.5 µA. The SRAM data
retention vol tage is 2 V minimu m. The Battery-on
Indicator (VBATON) can be routed to PC4. This
signal indicates when the VCC has dropped below
VSTBY.
PSD Chip Select Input (CSI, PD2 )
PD2 of Port D can be configured in PSDsoft Ex-
press as PSD Chip Select Input (CSI). When Low,
the signal selects and enables the internal Flash
memory, EEPROM, SRAM, and I/O blocks for
READ or WRITE operations involving the
PSD8XXFX. A High on PSD Chip Select Input
(CSI, PD2) disables t he Flash memory, EEPROM,
and SRAM, and reduces the PSD8XXFX power
consumption. However, the PLD and I/O signals
remain operational when PSD Chip Select Input
(CSI, PD2) is High.
There may be a timing penalty when using PSD
Chip Select Input (CSI, PD2) depending on the
speed grade of the PSD8X XFX that you are using.
See the timing parameter tSLQV in Table 60 or Ta-
ble 61.
Inpu t Cl oc k
The PSD8XXFX provides the option to turn off
CLKIN (PD1) to the PLD to save AC power con-
sumption. CLKIN (PD1) is an input to the PLD
AND Array and the Output Macrocells (OMC).
During Power-down mode, or, if CLKIN (PD1) is
not being used a s part of the PLD logic equation,
the clock should be disabled to save AC power.
CLKIN (PD1) is disconnected from the PLD AND
Array or the Macrocel l s block by setting bits 4 or 5
to a 1 in PMMR0.
Inpu t Control Si gn a l s
The PSD8XXFX provides the option to turn off the
input control signals (CNTL0, CNTL1, CNTL2, Ad-
dress Strobe (A LE/AS , PD0) and DBE) to t he PLD
to save AC power consumption. These control sig-
nals are inputs to the PLD AND Array. During
Power-down mode, or, if any of them ar e not being
used as part of the PLD logic equation, these con-
trol signals should be di sa bled to s ave AC power.
They are disconnected from the PLD AND Array
by setting bits 2, 3, 4, 5, and 6 to a 1 in PMMR2.
Table 32. A PD Counter Opera tion
APD Enable Bit ALE PD Polarity ALE Level APD Counter
0 X X Not Counting
1 X Pulsing Not Counting
1 1 1 Counting (Generates PDN after 15 Clocks)
1 0 0 Counting (Generates PDN after 15 Clocks)
63/103
PSD8XXF2/3/4/5
RESET TIMING AND DEVICE STATUS AT RESET
Upon Power-up, the PSD8XXFX requires a Reset
(RESET) pulse of duration tNLNH-PO after VCC is
steady. Du ri ng this period, the dev ice loads in ter-
nal configurations, clears some of the registers
and sets t he Flash me mory into Op erating m ode.
After the rising edge of Reset (RESET), the
PSD8XXFX r emains in the Reset m ode for an ad-
ditional period, tOPR, before the first memory ac-
cess is a llow ed.
The Flash memory is reset to the READ Mode
upon Power-up. Sector Select (FS0-FS7 and
CSBOOT0-CSBOOT3) must all be Low, Write
Strobe (WR, CNTL0) High, during Power On Re-
set for maximum security of the data contents and
to remove the possibility of a byte being written on
the first edge of Write Strobe (WR, CNTL0). Any
Fl ash memory WRIT E cycl e i n it iation is preven ted
automatically when VCC is be low V LKO.
Warm Reset
Once the device is up and running, the devi ce can
be reset with a pulse of a much shorter duration,
tNLNH. The same tOPR period is needed before the
device is operational after warm reset. Figure 31
shows the ti ming of the P ower-up and warm reset .
I/O Pin, Register and PLD Status at Reset
Table 33 shows t he I/O p in, register and PL D sta-
tus during Power On Reset, warm reset and Pow-
er-down mode. PLD outputs are always valid
during warm reset, and they are valid in Power On
Reset once the internal PSD8XXFX Configurati on
bits are loaded. This loading of PSD8XXFX is
completed typical ly long before th e VCC ramps up
to operating level. Once the PLD is active, the
state of the outputs are determined by the PSDa-
bel equations.
Reset of Flash Memory Erase and Program
Cycles (on the PSD834Fx )
A Reset (RESET) also resets the internal Flash
memory state machine. During a Flash memory
Program or Erase cycle, Reset (RESET) termi-
nates the cycle and returns the Flash memory to
the Read Mode within a period of tNLNH-A.
Figure 31. Reset (RESET) Timing
tNLNH-PO tOPR
AI02866b
RESET
tNLNH
tNLNH-A tOPR
VCC VCC(min)
Power-On Reset Warm Reset
PSD8XXF2/3/4/5
64/103
Table 33. Status During Power-On Reset, Warm Reset and Power-down Mode
No te : 1. The SR_cod and PeriphMode bits in t he VM Reg i st er are al ways cleared to 0 on P ower-On Reset or Warm Re set.
Port Configuration Power-On Reset Warm Reset Power-down Mode
MCU I/O Input mode Input mode Unchanged
PLD Output Valid after internal PSD
configuration bits are
loaded Valid Depends on inputs to PLD
(addresses are blocked in
PD mode)
Address Out Tri-stated Tri-stated Not defined
Data Port Tri-stated Tri-stated Tri-stated
Peripheral I/O Tri-stated Tri-stated Tri-stated
Register Power-On Reset Warm Reset Power-down Mode
PMMR0 and PMMR2 Cleared to 0 Unchanged Unchanged
Macrocells flip-flop status Cleared to 0 by internal
Power-On Reset Depends on .re and .pr
equations Depends on .re and .pr
equations
VM Register1Initialized, based on the
selection in PSDsoft
Configuration menu
Initialized, based on the
selection in PSDsoft
Configur ation menu Unchanged
All other registers Cleared to 0 Cleared to 0 Unchanged
65/103
PSD8XXF2/3/4/5
PROGRAMMING IN-CIRCUIT USING T HE JTAG SERIAL I NTERFACE
The JTAG Serial Interface block can be enabled
on Port C (see Table 34). All memory blocks (pri-
mary and secondary Flash memory), PLD logic,
and PSD8XXFX Configuration Register bits may
be programmed t hrough the JTAG Seri al Interface
block. A blank device can be mounted on a printed
circuit board and programmed using JTAG.
The standard JTAG signals (IEEE 1149.1) are
TMS, TCK, T DI, and TDO. Two addit i onal signals,
TSTAT a nd TERR , are opt ional JTAG ext ensions
used to speed up Program and Erase cycles.
By default, on a blank PSD8XXFX (as shipped
from the factory or af ter erasure), f our pins on Port
C are enabled for the basic JTAG signals TMS,
TCK, TDI, and TDO
.
See Application Note
AN1153
for more details on
JTAG In-System Programm ing (ISP).
Standard JTAG Sign als
The standard JTAG signa ls (T MS, TCK, TDI, and
TDO) can be enabled by any of three different con-
ditions that are logically ORed. When enabled,
TDI, TDO, TCK, and TMS are inputs, waiting for a
JTAG serial command from an external JTAG con-
troller device (such as FlashLINK or Automated
Test Equipm ent ). When t he enabling com ma nd is
received, TDO beco mes an ou tput and t he JTAG
channel is fully functional inside the PSD8XXFX.
The same command that enables the JTAG chan-
nel may optionally enable the two additional JTAG
signals, T STA T and TERR.
The following s ymbolic logic equat ion specifies the
conditions enabling the four basic JTAG signals
(TMS, TCK, TDI, and TDO) on their respective
Port C pins. For purposes of discuss ion, the l ogic
label JTAG_ON is used. When JTAG_ON is true,
the four pins are enabled for JTAG. When
JTAG_ON is false, the four pins can be used for
general PSD8XXFX I/ O.
JTAG_ON = PSDsoft_enabled +
/* An NVM configuration bit inside
the PSD is set by the designer in
the PSDsoft Express Configuration
utility. This dedicates the pins
for JTAG at all times (compliant
with IEEE 1149.1 */
Microcontroller_enabled +
/* The microcontroller can set a
bit at run-time by writing to the
PSD register, JTAG Enable. This
register is located at address
CSIOP + offset C7h. Setting the
JTAG_ENABLE bit in this register
will enable the pins for JTAG use.
This bit is cleared by a PSD reset
or the microcontroller. See Table
35 for bit definition. */
PSD_product_term_enabled;
/* A dedicated product term (PT)
inside the PSD can be used to en-
able the JTAG pins. This PT has
the reserved name JTAGSEL. Once
defined as a node in PSDabel, the
designer can write an equation for
JTAGSEL. This method is used when
the Port C JTAG pins are multi-
plexed with other I/O signals. It
is recommended to logically tie
the node JTAGSEL to the JEN\ sig-
nal on the Flashlink cable when
multiplexing JTAG signals. See Ap-
plication Note 1153 for details.
*/
The state of the PSD Reset (RESET) signal does
not interrupt (or prevent) JTAG operations if the
JTAG pins are dedicated by an NVM c onf iguration
bit (via PSDsoft Express). However, Reset (RE-
SET) will prevent or interrupt JTAG operations if
the JTAG enable register is used to enable the
JTAG pins.
The PSD8XXFX supports JTAG In-System-Con-
figuration (ISC) commands, but not Boundary
Scan. The PSDsoft Express software tool and
FlashLINK JTAG programming cable implement
the JTAG In-System-Configuration (ISC) com-
mands. A definition of these JTAG In-System-
Configuration (I SC) comman ds and seq uences is
defined in a supplemental document available
from ST. This document is needed only as a r efer-
ence for designers who use a FlashLINK to pro-
gram their PSD8XXFX.
Table 34. JTAG Port Signals
Port C Pin JTAG Signals Description
PC0 TMS Mode Select
PC1 TCK Clock
PC3 TSTAT Status
PC4 TERR Error Flag
PC5 TDI Serial Data In
PC6 TDO Serial Data Out
PSD8XXF2/3/4/5
66/103
JTAG Extensions
TSTAT and TERR are two JTAG extension signals
enabled by an “ISC_ENA BLE” command received
over the four standard JT AG signals (TMS, TCK,
TDI, and TDO). They are used to speed Program
and Erase cycles by indicating status on
PSD8XXFX signals in stead of having to scan the
status out s eri ally u sing t he standa rd J TAG chan-
nel. See Application Not e
AN1153
.
TERR indicates if an error has occurred when
erasing a sector or programming a byte in Flash
memory. This signal goes Low (active) when an
Error condition occurs, and stays Low until an
“ISC_CLEAR” command is executed or a chip Re-
set (RESET) pulse is received after an
“ISC_DISABLE” command.
TSTAT behaves the same as Ready/Busy de-
scribed in the section entitled “Ready/Busy (PC3)”,
on page 18. T S TAT i s H igh when the PSD 8XX FX
device is in READ M ode (primary and secondary
Flash memory contents can be read). TSTAT is
Low when Flash memory P rogram or Erase cycles
are in progre ss, and also when dat a is being writ-
ten to t he secondary Flash mem ory.
TSTAT and TERR can be configured as open-
drain type signa ls duri ng an “ISC_E NABLE” com-
mand. This facilitates a wired-OR connection of
TSTAT sign als from m ultiple PSD8XXFX devices
and a wired-OR connection of TERR signals from
those same devices. This is useful when several
PSD8XXFX devices are “chained” together in a
JTAG environm ent.
Securit y an d Flash mem ory Protec tion
When the security bit is set, the device cannot be
read on a Device Programmer or through the
JTAG Port. When using the JTAG Port, onl y a F ull
Chip Erase command is allowed.
All other Program, Erase and Verify commands
are blocked. Full Chip Erase returns the p art to a
non-secured blank state. The Security Bit can be
set in PSDs oft Express Configuration.
All primary and secondary Flash memory sectors
can individually be sector protected against era-
sures. The sector protect bits can be set in PSD-
soft Express Configuration.
INITIAL DELIVERY STATE
When delivered from ST, the PSD8XXFX device
has all bits in the m em ory and P LDs s et to 1 . The
PSD8XXFX Configuration R egister bits are set t o
0. The code, configuration, and PLD logic are
loaded using the programming procedure. Infor-
mation for programming the devi ce is available di-
rectly from ST. Please contact your local sales
representative.
Table 35. JTAG Enable Register
Not e: 1. The state of Reset (RESET) does not interrupt (or prevent) JTA G operati ons if the JTAG signals are dedicated by an NVM Config-
uration bit (via PSDsoft Express). H owever, Reset (RESET) p revents or interrupts JT A G operations i f the JTA G enable register is
used t o enable the JTAG signals.
Bit 0 JTAG_Enable 0 = off JTAG port is disabled.
1 = on JTAG port is enabled.
Bit 1 X 0 Not used, and should be set to zero.
Bit 2 X 0 Not used, and should be set to zero.
Bit 3 X 0 Not used, and should be set to zero.
Bit 4 X 0 Not used, and should be set to zero.
Bit 5 X 0 Not used, and should be set to zero.
Bit 6 X 0 Not used, and should be set to zero.
Bit 7 X 0 Not used, and should be set to zero.
67/103
PSD8XXF2/3/4/5
AC/DC PARAMETERS
These tables describe the AD and DC parameters
of the PSD8X X FX:
❏ DC Elect ri cal Specificati on
❏ AC Timing Specification
■PLD Timing
– Combi nato rial Timing
– Synchronous Clock Mod e
– Async hronous Clock Mode
– Input Macrocell Timing
■MCU Ti ming
– READ Timing
–WRITE Timing
– Peripheral Mode Timing
– Power-down and Reset Timing
The following are issues concerning the parame-
ters presented:
■In the DC s pe cification the supply current is
given for different modes of oper ation. Befor e
calculatin g the total power consumpt ion,
determi ne the percentage of ti me that the
PSD 8XXF X is in each mod e. Also, the supply
power is considerably different if the Turbo bit is
0.
■The AC power component gives the PLD, Flash
memory, and SRAM mA/MHz specification.
Figure 32 and Figure 33 show the PLD mA/MHz
as a function of the numb er of Product Term s
(P T) used .
■In the PLD timing parameters, add the required
delay when Turbo bit is 0.
Figure 32. PLD ICC /Frequency Consumption (5 V range)
0
10
20
30
40
60
70
80
90
100
110
VCC = 5V
50
010155 20 25
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
ICC – (mA)
TURBO ON (100%)
TURBO ON (25%)
TURBO OFF
TURBO OFF
PT 100%
PT 25%
AI02894
PSD8XXF2/3/4/5
68/103
Figure 33. PLD ICC /Frequency Consumption (3 V range)
0
10
20
30
40
50
60 VCC = 3V
010155 20 25
ICC – (mA)
TURBO ON (100%)
TURBO ON (25%)
TURBO OFF
TURBO OFF
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
PT 100%
PT 25%
AI03100
69/103
PSD8XXF2/3/4/5
Table 36. Examp le of PSD8XXFX Typical Power Calculatio n at VCC = 5.0 V (Turb o Mode On)
Conditions
Highest Composite PLD input frequency
(Freq PLD) = 8 MHz
MCU ALE frequency (Freq ALE) = 4 MHz
% Flash memory
Access = 80%
% SRAM access = 15%
% I/O access = 5% (no additional power above base)
Operat ional Mode s
% Normal = 10%
% Power-down Mode = 90%
Number of product terms used
(from fitter report) = 45 PT
% of total product terms = 45/182 = 24.7%
Turbo Mode = ON
Calculation (using typical values)
ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))
= Ipwrdown x %pwrdown + % normal x (%flash x 2.5 mA/MHz x Freq ALE
+ %SRAM x 1.5 mA/MHz x Freq ALE
+ % PLD x 2 mA/MHz x Freq PLD
+ #PT x 400 µA/PT)
= 50 µA x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz
+ 0.15 x 1.5 mA/MHz x 4 MHz
+ 2 mA/MHz x 8 MHz
+ 45 x 0.4 mA/PT)
= 45 µA + 0.1 x (8 + 0.9 + 16 + 18 mA)
= 45 µA + 0.1 x 42.9
= 45 µA + 4.29 mA
= 4.34 mA
This is the operating power with no EEPROM WRITE or Flash memory Erase cycles in progress. Calculation is based
on IOUT = 0 mA.
PSD8XXF2/3/4/5
70/103
Table 37. Examp le of PSD8XXFX Typical Power Calculatio n at VCC = 5.0 V (Turbo Mo de Off)
Conditions
Highest Composite PLD input frequency
(Freq PLD) = 8 MHz
MCU ALE frequency (Freq ALE) = 4 MHz
% Flash memory
Access = 80%
% SRAM access = 15%
% I/O access = 5% (no additional power above base)
Operat ional Mode s
% Normal = 10%
% Power-down Mode = 90%
Number of product terms used
(from fitter report) = 45 PT
% of total product terms = 45/182 = 24.7%
Turbo Mode = Off
Calculation (using typical values)
ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))
= Ipwrdown x %pwrdown + % normal x (%flash x 2.5 mA/MHz x Freq ALE
+ %SRAM x 1.5 mA/MHz x Freq ALE
+ % PLD x (from graph using Freq PLD))
= 50 µA x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz
+ 0.15 x 1.5 mA/MHz x 4 MHz
+ 24 mA)
= 45 µA + 0.1 x (8 + 0.9 + 24)
= 45 µA + 0.1 x 32.9
= 45 µA + 3.29 mA
= 3.34 mA
This is the operating power with no EEPROM WRITE or Flash memory Erase cycles in progress. Calculation is based
on IOUT = 0 mA.
71/103
PSD8XXF2/3/4/5
MAX I MUM R AT I N G
Stressing the device ab ove t he rati ng l isted in t he
Absolute Maximum Rat i ngs” table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at t hes e or
any other con ditions ab ove those i ndicated i n the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 38. Absolute Maximum Rating s
Not e: 1. I PC/ JEDEC J- STD-02 0 A
2. JED EC Std JESD22-A11 4A (C1=1 00 pF, R1=1500 Ω, R2=500 Ω)
Symbol Parameter Min. Max. Unit
TSTG Storage Temperature –65 125 °C
TLEAD Lead Temperature during Soldering (20 seconds max.)1235 °C
VIO Input and Output Voltage (Q = VOH or Hi-Z) –0.6 7.0 V
VCC Supply Voltage –0.6 7.0 V
VPP Device Programmer Supply Voltage –0.6 14.0 V
VESD Electrostatic Discharge Voltage (Human Body model) 2–2000 2000 V
PSD8XXF2/3/4/5
72/103
DC AND AC PARAMETERS
This section summarizes the operating and m ea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Des igners shoul d c heck that the operating
conditions i n their circuit match the meas urement
conditions when relying on the quoted parame-
ters.
Table 39. Operating Conditions (5V devices)
Table 40. Operating Conditions (3V devices)
Table 41. AC Measurement Conditions
Note: 1. Output Hi-Z i s defined as the point where da ta out is no l onger dri ven.
Figu re 34 . AC Measurement I/O W aveform Figure 35. AC Measure m ent Load Cir cui t
Table 42. Capacitance
Not e: 1. Sampled only, not 100% tested.
2. Typ i cal value s are for TA = 25°C and nom i nal suppl y voltages.
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 4.5 5.5 V
TAAmbient Operating Temperature (industrial) –40 85 °C
Ambient Operating Temperature (commercial) 0 70 °C
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 3.0 3.6 V
TAAmbient Operating Temperature (industrial) –40 85 °C
Ambient Operating Temperature (commercial) 0 70 °C
Symbol Parameter Min. Max. Unit
CLLoad Capacitance 30 pF
3.0V
0V
Test Point 1.5V
AI03103b
Device
Under Test
2.01 V
195 Ω
CL = 30 pF
(Including Scope and
Jig Capacitance) AI03104b
Symbol Parameter Test Condition Typ.2Max. Unit
CIN Input Capacitance (for input pins) VIN = 0V 46pF
COUT Output Capacitance (for input/
output pins) VOUT = 0V 812
pF
CVPP Capacitance (for CNTL2/VPP)V
PP = 0V 18 25 pF
73/103
PSD8XXF2/3/4/5
Table 43. AC Symbols for PLD Timing
Example : tAVLX – Time from Address Valid to ALE Invalid.
Figure 36. Switchin g Wavefo rms – Key
Signal Letters Signal Behavior
A Address Input t Time
C CEout Output L Logic Level Low or ALE
D Input Data H Logic Level High
E E Input V Valid
G Internal WDOG_ON signal X No Longer a Valid Logic Level
I Interrupt Input Z Float
L ALE Input PW Pulse Width
N Reset Input or Output
P Port Signal Output
Q Output Data
RWR
, UDS, L DS, DS, IORD, PSEN Inputs
S Chip Select Input
TR/W
Input
W Internal PDN Signal
BVSTBY Output
M Output Macrocell
WAVEFORMS INPUTS OUTPUTS
STEADY INPUT
MAY CHANGE FROM
HI TO LO
MAY CHANGE FROM
LO TO HI
DON'T CARE
OUTPUTS ONLY
STEADY OUTPUT
WILL BE CHANGING
FROM HI TO LO
WILL BE CHANGING
LO TO HI
CHANGING, STATE
UNKNOWN
CENTER LINE IS
TRI-STATE
AI03102
PSD8XXF2/3/4/5
74/103
Table 44. DC Characteristics (5V d evices)
No te: 1. Reset (RESET ) has hy s teresis. V IL1 is valid at or below 0.2VCC –0.1. VIH1 is vali d at or above 0. 8VCC.
2. CSI deselected or in ternal Power-down mode is active.
3. PLD is in non-Turbo mode, and none of the inputs are switching.
4. Plea se see Fi gure 32 for the PLD c urrent c al culati on.
5. IOUT = 0 mA
Symbol Parameter Test Condition
(in addition to those in
Table 39) Min. Typ. Max. Unit
VIH Input High Voltage 4.5 V < VCC < 5.5 V 2VCC +0.5 V
VIL Input Low Voltage 4.5 V < VCC < 5.5 V –0.5 0.8 V
VIH1 Reset High Level Input Voltage (Note 1)0.8VCC VCC +0.5 V
VIL1 Reset Low Level Input Voltage (Note 1)–0.5 0.2VCC –0.1 V
VHYS Reset Pin Hysteresis 0.3 V
VLKO VCC (min) for Flash Erase and
Program 2.5 4.2 V
VOL Output Low Voltage IOL = 20 µA, VCC = 4.5 V 0.01 0.1 V
IOL = 8 mA, VCC = 4.5 V 0.25 0.45 V
VOH Output High Voltage Except
VSTBY On IOH = –20 µA, VCC = 4.5 V 4.4 4.49 V
IOH = –2 mA, VCC = 4.5 V 2.4 3.9 V
VOH1 Output High Voltage VSTBY On IOH1 = 1 µA VSTBY – 0.8 V
VSTBY SRAM Stand-by Voltage 2.0 VCC V
ISTBY SRAM Stand-by Current VCC = 0 V 0.5 1 µA
IIDLE Idle Current (VSTBY input) VCC > VSTBY –0.1 0.1 µA
VDF SRAM Data Retention Voltage Only on VSTBY 2V
I
SB Stand-by Supply Current
for Power-down Mode CSI >VCC –0.3 V (No tes 2,3)50 200 µA
ILI Input Leakage Current VSS < VIN < VCC –1 ±0.1 1 µA
ILO Output Leakage Current 0.45 < VOUT < VCC –10 ±5 10 µA
ICC (DC)
(Note 5)
Operating
Supply
Current
PLD Only
PLD_TU RBO = Off,
f = 0 MHz (Note 5)0 µA/PT
PLD_TURBO = On,
f = 0 MHz 400 700 µA/PT
Flash memory During Flash memory
WRITE/Erase Only 15 30 mA
Read only, f = 0 MHz 0 0 mA
SRAM f = 0 MHz 0 0 mA
ICC (AC)
(Note 5)
PLD AC Adder note 4
Flash memory AC Adder 2.5 3.5 mA/
MHz
SRAM AC Adder 1.5 3.0 mA/
MHz
75/103
PSD8XXF2/3/4/5
Table 45. DC Characteristics (3V d evices)
No te: 1. Reset (RESET ) has hy s teresis. V IL1 is valid at or below 0.2VCC –0.1. VIH1 is vali d at or above 0. 8VCC.
2. CSI deselected or intern al PD i s ac tive.
3. PLD is in non-Turbo mode, and none of the inputs are switching.
4. Plea se see Fi gure 33 for the PLD c urrent c al culati on.
5. IOUT = 0 mA
Symbol Parameter Conditions Min. Typ. Max. Unit
VIH High Level Input Voltage 3.0 V < VCC < 3.6 V 0.7VCC VCC +0.5 V
VIL Low Level Input Voltage 3.0 V < VCC < 3.6 V –0.5 0.8 V
VIH1 Reset High Level Input Voltage (Note 1)0.8VCC VCC +0.5 V
VIL1 Reset Low Level Input Voltage (Note 1)–0.5 0.2VCC –0.1 V
VHYS Reset Pin Hysteresis 0.3 V
VLKO VCC (min) for Flash Erase and
Program 1.5 2.2 V
VOL Output Low Voltage IOL = 20 µA, VCC = 3.0 V 0.01 0.1 V
IOL = 4 mA, VCC = 3.0 V 0.15 0.45 V
VOH Output High Voltage Except
VSTBY On IOH = –20 µA, VCC = 3.0 V 2.9 2.99 V
IOH = –1 mA, VCC = 3.0 V 2.7 2.8 V
VOH1 Output High Voltage VSTBY On IOH1 = 1 µA VSTBY – 0.8 V
VSTBY SRAM Stand-by Voltage 2.0 VCC V
ISTBY SRAM Stand-by Current VCC = 0 V 0.5 1 µA
IIDLE Idle Current (VSTBY input) VCC > VSTBY –0.1 0.1 µA
VDF SRAM Data Retention Voltage Only on VSTBY 2V
I
SB Stand-by Supply Current
for Power-down Mode CSI >VCC –0.3 V (No tes 2,3)25 100 µA
ILI Input Leaka ge Curren t VSS < VIN < VCC –1 ±0.1 1 µA
ILO Output Leakage Current 0.45 < VIN < VCC –10 ±5 10 µA
ICC (DC)
(Note 5)
Operating
Supply
Current
PLD Only
PLD_TU RBO = Off,
f = 0 MHz (Note 3)0 µA/PT
PLD_TURBO = On,
f = 0 MHz 200 400 µA/PT
Flash memory During Flash memory
WRITE/Erase Only 10 25 mA
Read only, f = 0 MHz 0 0 mA
SRAM f = 0 MHz 0 0 mA
ICC (AC)
(Note 5)
PLD AC Adder note 4
Flash memory AC Adder 1.5 2.0 mA/
MHz
SRAM AC Adder 0.8 1.5 mA/
MHz
PSD8XXF2/3/4/5
76/103
Figure 37. Input to Output Disable / Enable
Table 46. CPLD Combina torial Timing (5V devices)
No te : 1. Fas t Sl ew Rate output avai lable on PA3-PA 0, PB3-PB0, and PD2-P D0. Decrement times by given amount.
Table 47. CPLD Combina torial Timing (3V devices)
No te : 1. Fas t Sl ew Rate output avai lable on PA3-PA 0, PB3-PB0, and PD2-P D0. Decrement times by given amount .
Symbol Parameter Conditions -70 -90 -15 Fast
PT
Aloc
Turbo
Off Slew
rate1Unit
Min Max Min Max Min Max
tPD CPLD Input Pin/
Feedback to CPLD
Combinatorial Output 20 25 32 + 2 + 10 – 2 ns
tEA CPLD Input to CPLD
Output Enable 21 26 32 + 10 – 2 ns
tER CPLD Input to CPLD
Output Disable 21 26 32 + 10 – 2 ns
tARP CPLD Register Clear
or Preset Delay 21 26 33 + 10 – 2 ns
tARPW CPLD Register Clear
or Preset Pulse Width 10 20 29 + 10 ns
tARD CPLD Array Delay Any
macrocell 11 16 22 + 2 ns
Symbol Parameter Conditions -12 -15 -20 PT
Aloc Turbo
Off Slew
rate1Unit
Min Max Min Max Min Max
tPD CPLD Input Pin/
Feedback to CPLD
Combinatorial Output 40 45 50 + 4 + 20 – 6 ns
tEA CPLD Input to CPLD
Output Enable 43 45 50 + 20 – 6 ns
tER CPLD Input to CPLD
Output Disable 43 45 50 + 20 – 6 ns
tARP CPLD Register Clear
or
Preset Delay 40 43 48 + 20 – 6 ns
tARPW CPLD Register Clear
or
Preset Pulse Width 25 30 35 + 20 ns
tARD CPLD Array Delay Any
macrocell 25 29 33 + 4 ns
tER tEA
INPUT
INPUT TO
OUTPUT
ENABLE/DISABLE
AI02863
77/103
PSD8XXF2/3/4/5
Figu re 38 . Sy nchronous Cloc k Mode Tim i ng – PLD
Table 48. CPLD Macrocell Synchr onous Clock Mode Timing (5V devices)
No te : 1. Fas t Sl ew Rate output avai lable on PA3-PA 0, PB3-PB0, and PD2-P D0. Decrement times by given amount .
2. C LKIN (P D1) tCLCL = tCH + tCL.
Symbol Parameter Conditions -70 -90 -15 F ast
PT
Aloc
Turbo
Off Slew
rate1Unit
Min Max Min Max Min Max
fMAX
Maximum
Frequency
External
Feedback
1/(tS+tCO)40.0 30.30 25.00 MHz
Maximum
Frequency
Internal
Feedback
(fCNT)
1/(tS+tCO–10) 66.6 43.48 31.25 MHz
Maximum
Frequency
Pipelined Data 1/(tCH+tCL)83.3 50.00 35.71 MHz
tSInput Setup
Time 12 15 20 + 2 + 10 ns
tHInput Hold Time 0 0 0 ns
tCH Clock High Time Clock Input 6 10 15 ns
tCL Clock Low Time Clock Input 6 10 15 ns
tCO Clock to Output
Delay Clock Input 13 18 22 – 2 ns
tARD CPLD Array
Delay Any macro cell 11 16 22 + 2 ns
tMIN Minimum Clock
Period 2 tCH+tCL 12 20 30 ns
tCH tCL
tCO
tH
tS
CLKIN
INPUT
REGISTERED
OUTPUT
AI02860
PSD8XXF2/3/4/5
78/103
Table 49. CPLD Macrocell Synchr onous Clock Mode Timing (3V devices)
No te : 1. Fas t Sl ew Rate output avai lable on PA3-PA 0, PB3-PB0, and PD2-P D0. Decrement times by given amount .
2. C LKIN (P D1) tCLCL = tCH + tCL.
Symbol Parameter Conditions -12 -15 -20 PT
Aloc Turbo
Off Slew
rate1Unit
Min Max Min Max Min Max
fMAX
Maximum
Frequency
External Feedback 1/(tS+tCO)22.2 18.8 15.8 MHz
Maximum
Frequency
Internal Feedback
(fCNT)
1/(tS+tCO–10) 28.5 23.2 18.8 MHz
Maximum
Frequency
Pipelined Data 1/(tCH+tCL)40.0 33.3 31.2 MHz
tSInput Setup Time 20 25 30 + 4 + 20 ns
tHInput Hold Time 0 0 0 ns
tCH Clock High Time Clock Input 1 5 15 16 ns
tCL Clock Low Time Clock Input 10 15 16 ns
tCO Clock to Output
Delay Clock Input 25 28 33 – 6 ns
tARD CPLD Array Delay Any macrocell 25 29 33 + 4 ns
tMIN Minimum Clock
Period2tCH+tCL 25 29 32 ns
79/103
PSD8XXF2/3/4/5
Figure 39. Asynchron ous Reset / Preset
Figure 40. Asynchronous Clock Mode Ti ming (product term clock)
tARP
REGISTER
OUTPUT
tARPW
RESET/PRESET
INPUT
AI02864
tCHA tCLA
tCOA
tHAtSA
CLOCK
INPUT
REGISTERED
OUTPUT
AI02859
PSD8XXF2/3/4/5
80/103
Table 50. CPLD Macr ocell Asynch ronou s Clock Mod e Timin g (5V devices)
Symbol Parameter Conditions -70 -90 -15 PT
Aloc Turbo
Off Slew
Rate Unit
Min Max Min Max Min Max
fMAXA
Maximum
Frequency
External
Feedback
1/(tSA+tCOA)38.4 26.32 21.27 MHz
Maximum
Frequency
Internal
Feedback
(fCNTA)
1/(tSA+tCOA–10) 62.5 35.71 27.78 MHz
Maximum
Frequency
Pipelined
Data
1/(tCHA+tCLA)71.4 41.67 35.71 MHz
tSA Input Setup
Time 7 8 12 + 2 + 10 ns
tHA Input Hold
Time 81214 ns
t
CHA Clock Input
High Time 9 12 15 + 10 ns
tCLA C lock Input
Low Time 9 12 15 + 10 ns
tCOA C lock to
Output Delay 21 30 37 + 10 – 2 ns
tARDA CPLD Array
Delay Any macrocell 11 16 22 + 2 ns
tMINA Minimum
Clock Perio d 1/fCNTA 16 28 39 ns
81/103
PSD8XXF2/3/4/5
Table 51. CPLD Macr ocell Asynch ronou s Clock Mod e Timin g (3V devices)
Symbol Parameter Conditions -12 -15 -20 PT
Aloc Turbo
Off Slew
Rate Unit
Min Max Min Max Min Max
fMAXA
Maximum
Frequency
External
Feedback
1/(tSA+tCOA)21.7 19.2 16.9 MHz
Maximum
Frequency
Internal
Feedback
(fCNTA)
1/(tSA+tCOA–10) 27.8 23.8 20.4 MHz
Maximum
Frequency
Pipelined Data 1/(tCHA+tCLA)33.3 27 24.4 MHz
tSA Input Setup
Time 10 12 13 + 4 + 20 ns
tHA Input Hold Time 12 15 17 ns
tCHA Clock High Time 17 22 25 + 20 ns
tCLA Clock Low Time 13 15 16 + 20 ns
tCOA C lock to Output
Delay 36 40 46 + 20 – 6 ns
tARD CPLD Array
Delay Any macrocell 25 29 33 + 4 ns
tMINA Minimum Clock
Period 1/fCNTA 36 42 49 ns
PSD8XXF2/3/4/5
82/103
Figure 41. Input Macrocell Timing (product term clock)
Table 52. Input Macroc ell Timin g (5V devices)
No te : 1. Input s from Port A, B, and C rel ative to registe r/ l atch c l ock from t he P LD. ALE/ AS latc h t i mings ref er to tAVLX an d t LXAX.
Table 53. Input Macroc ell Timin g (3 V device s)
Note : 1. Inputs from Port A, B, and C relative to register/latch clock from the PL D. ALE latch timings refer to tAVLX and tLXAX.
Symbol Parameter Conditions -70 -90 -15 PT
Aloc Turbo
Off Unit
Min Max Min Max Min Max
tIS Input Setup Time (Note 1)000 ns
t
IH Input Hold Time (Note 1)15 20 26 + 10 ns
tINH NIB Input High Time (Note 1)91218 ns
t
INL NIB Input Low Time (Note 1)91218 ns
t
INO NIB Input to Combinatorial
Delay (Note 1)34 46 59 + 2 + 10 ns
Symbol Parameter Conditions -12 -15 -20 PT
Aloc Turbo
Off Unit
Min Max Min Max Min Max
tIS Input Setup Time (Note 1)000 ns
t
IH Input Hold Time (Note 1)25 25 30 + 20 ns
tINH NIB Input High Time (Note 1)12 13 15 ns
tINL NIB Input Low Time (Note 1)12 13 15 ns
tINO NIB Input to Combinatorial
Delay (Note 1)46 62 70 + 4 + 20 ns
tINH tINL
tINO
tIH
tIS
PT CLOCK
INPUT
OUTPUT
AI03101
83/103
PSD8XXF2/3/4/5
Figure 42. READ Timing
Note: 1. tAVLX and tLXAX are not required for 80C251 in Page Mode or 80C51XA in Burst Mode.
tAVLX tLXAX
1
tLVLX
tAVQV
tSLQV
tRLQV tRHQX
tRHQZ
tELTL
tEHEL
tRLRH
tTHEH
tAVPV
ADDRESS
VALID
ADDRESS
VALID
DATA
VALID
DATA
VALID
ADDRESS OUT
ALE/AS
A/D
MULTIPLEXED
BUS
ADDRESS
NON-MULTIPLEXED
BUS
DATA
NON-MULTIPLEXED
BUS
CSI
RD
(PSEN, DS)
E
R/W
AI02895
PSD8XXF2/3/4/5
84/103
Table 54. READ Timing (5V devices)
Note: 1. RD timing has th e sam e timin g as DS, L DS, UDS , an d PSEN signal s.
2. RD an d PSEN have the same timing.
3. Any input use d to select an interna l PSD8XXFX function .
4. In mu l tiplexed m ode, latc hed addresses generated from A DI O delay to a ddress output on any Port.
5. RD timing has th e same tim in g as DS, LDS, and UDS signals.
Symbol Parameter Conditions -70 -90 -15 Turbo
Off Unit
Min Max Min Max Min Max
tLVLX ALE or AS Pulse Width 15 20 28 ns
tAVLX Address Setup Time (Note 3)4 6 10 ns
tLXAX Address Hold Time (Note 3)7811 ns
t
AVQV Address Valid to Data Valid (Note 3)70 90 150 + 10 ns
tSLQV CS Valid to Data Valid 75 100 150 ns
tRLQV
RD to Data Valid 8-Bit Bus (Note 5)24 32 40 ns
RD or PSEN to Data Valid
8-Bit Bus, 8031, 80251 (Note 2)31 38 45 ns
tRHQX RD Data Hold Time (Note 1)000 ns
t
RLRH RD Pulse Width (Note 1)27 32 38 ns
tRHQZ RD to Data High-Z (Note 1)20 25 30 ns
tEHEL E Pulse Width 27 32 38 ns
tTHEH R/W Setup Time to Enable 6 10 18 ns
tELTL R/W Hold Time After Enable 0 0 0 ns
tAVPV Address Input Valid to
Address Output Delay (Note 4)20 25 30 ns
85/103
PSD8XXF2/3/4/5
Table 55. READ Timing (3V devices)
Note: 1. RD timing has th e sam e timin g as DS, L DS, UDS , an d PSEN signal s.
2. RD an d PSEN have the same tim i ng for 8031.
3. Any input use d to select an interna l PSD8XXFX function .
4. In multipl exed mode latched address generated from ADIO delay to address output on any Port.
5. RD timing has th e same tim in g as DS, LDS, and UDS signals.
Symbol Parameter Conditions -12 -15 -20 Turbo
Off Unit
Min Max Min Max Min Max
tLVLX ALE or AS Pulse Width 26 26 30 ns
tAVLX Address Setup Time (Note 3)91012 ns
t
LXAX Address Hold Time (Note 3)91214 ns
t
AVQV Address Valid to Data Valid (Note 3)120 150 200 + 20 ns
tSLQV CS Valid to Data Valid 120 150 200 ns
tRLQV
RD to Data Valid 8-Bit Bus (Note 5)35 35 40 ns
RD or PSEN to Data Valid 8-Bit Bus,
8031, 80251 (Note 2)45 50 55 ns
tRHQX RD Data Hold Time (Note 1)000 ns
t
RLRH RD Pulse Width 38 40 45 ns
tRHQZ RD to Data High-Z (Note 1)38 40 45 ns
tEHEL E Pulse Width 40 45 52 ns
tTHEH R/W Setup Time to Enable 15 18 20 ns
tELTL R/W Hold Time After Enable 0 0 0 ns
tAVPV Address Input Valid to
Address Output Delay (Note 4)33 35 40 ns
PSD8XXF2/3/4/5
86/103
Figure 43. WRITE Timing
tAVLX tLXAX
tLVLX
tAVWL
tSLWL
tWHDX
tWHAX
tELTL
tEHEL
tWLMV
tWLWH
tDVWH
tTHEH
tAVPV
ADDRESS
VALID
ADDRESS
VALID
DATA
VALID
DATA
VALID
ADDRESS OUT
tWHPV
STANDARD
MCU I/O OUT
ALE/AS
A/D
MULTIPLEXED
BUS
ADDRESS
NON-MULTIPLEXED
BUS
DATA
NON-MULTIPLEXED
BUS
CSI
WR
(DS)
E
R/ W
AI02896
87/103
PSD8XXF2/3/4/5
Table 56. WRITE Timing (5V devices)
Note: 1. Any input used to select an internal PSD8XXFX function.
2. In mu l tiplexed m ode, latc hed address generate d from ADIO delay to a ddress output on any port .
3. WR has the sam e t i m i ng as E, LDS, UDS, WRL, an d WRH sign al s.
4. Assuming data is stable before active WRITE signal.
5. Assuming WRITE is active before data be comes valid.
6. TWHA X2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD8XXFX memory.
Symbol Parameter Conditions -70 -90 -15 Unit
Min Max Min Max Min Max
tLVLX ALE or AS Pulse Width 15 20 28 ns
tAVLX Address Setup Time (Note 1)4 6 10 ns
tLXAX Address Hold Time (Note 1)7811ns
t
AVWL Address Valid to Leading
Edge of WR (Notes 1,3)81520ns
t
SLWL CS Valid to Leading Edge of WR (Note 3)12 15 20 ns
tDVWH WR Data Setup Time (Note 3)25 35 45 ns
tWHDX WR Data Hold Time (Note 3)455ns
t
WLWH WR Pulse Width (Note 3)31 35 45 ns
tWHAX1 Trailing Edge of WR to Address Invalid (Note 3)6 8 10 ns
tWHAX2 Trailing Edge of WR to DPLD Address
Invalid (Note 3,6)000ns
t
WHPV Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register (Note 3)27 30 38 ns
tDVMV Data Valid to Port Output Valid
Using Macro cell Regist er
Preset/Clear (Notes 3,5)42 55 65 ns
tAVPV Address Input Valid to Address
Output Delay (Note 2)20 25 30 ns
tWLMV WR Valid to Port Output Valid Using
Macrocell Register Preset/Clear (Notes 3,4)48 55 65 ns
PSD8XXF2/3/4/5
88/103
Table 57. WRITE Timing (3V devices)
Note: 1. Any input used to select an internal PSD8XXFX function.
2. In mu l tiplexed m ode, latc hed address generate d from ADIO delay to a ddress output on any port .
3. WR has the sam e t i m i ng as E, LDS, UDS, WRL, an d WRH sign al s.
4. Assuming data is stable before active WRITE signal.
5. Assuming WRITE is active before data be comes valid.
6. TWHA X2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD8XXFX memory.
Symbol Parameter Conditions -12 -15 -20 Unit
Min Max Min Max Min Max
tLVLX ALE or AS Pulse Width 26 26 30
tAVLX Address Setup Time (Note 1)91012ns
t
LXAX Address Hold Time (Note 1)91214ns
t
AVWL Address Valid to Leading
Edge of WR (Notes 1,3)17 20 25 ns
tSLWL CS Valid to Leading Edge of WR (Note 3)17 20 25 ns
tDVWH WR Data Setup Time (Note 3)45 45 50 ns
tWHDX WR Data Hold Time (Note 3)7 8 10 ns
tWLWH WR Pulse Width (Note 3)46 48 53 ns
tWHAX1 Trailing Edge of WR to Address Invalid (Note 3)10 12 17 ns
tWHAX2 Trailing Edge of WR to DPLD Address
Invalid (Note 3,6)000ns
t
WHPV Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register (Note 3)33 35 40 ns
tDVMV Data Valid to Port Output Valid
Using Macrocell Register Preset/Clear (Notes 3,5)70 70 80 ns
tAVPV Address Input Valid to Address
Output Delay (Note 2)33 35 40 ns
tWLMV WR Valid to Port Output Valid Using
Macrocell Register Preset/Clear (Notes 3,4)70 70 80 ns
89/103
PSD8XXF2/3/4/5
Table 58. Program, WRITE and Erase Times (5V devices)
Not e: 1. Programmed t o all zero before erase.
2. The po l l i ng statu s, DQ7, is vali d tQ7VQV tim e units bef ore the data byte, DQ0- DQ7, is vali d for readi ng.
Table 59. Program, WRITE and Erase Times (3V devices)
Not e: 1. Programmed t o all zero before erase.
2. The po l l i ng statu s, DQ7, is vali d tQ7VQV tim e units bef ore the data byte, DQ0- DQ7, is vali d for readi ng.
Symbol Parameter Min. Typ. Max. Unit
Flash Progr am 8.5 s
Flash Bulk Erase1 (pre-programmed) 330s
Flash Bulk Erase (not pre-program med ) 5 s
tWHQV3 Sector Erase (pre-programmed) 1 30 s
tWHQV2 Sector Erase (not pre-programmed) 2.2 s
tWHQV1 Byte Program 14 1200 µs
Program / Erase Cycles (per Sector) 100,000 cycles
tWHWLO Sector Erase Time-Out 100 µs
tQ7VQV DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)230 ns
Symbol Parameter Min. Typ. Max. Unit
Flash Progr am 8.5 s
Flash Bulk Erase1 (pre-programmed) 330s
Flash Bulk Erase (not pre-program med ) 5 s
tWHQV3 Sector Erase (pre-programmed) 1 30 s
tWHQV2 Sector Erase (not pre-programmed) 2.2 s
tWHQV1 Byte Program 14 1200 µs
Program / Erase Cycles (per Sector) 100,000 cycles
tWHWLO Sector Erase Time-Out 100 µs
tQ7VQV DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)230 ns
PSD8XXF2/3/4/5
90/103
Figure 44. Peripheral I/O READ Timing
Table 60. Port A Peripheral Data Mode READ Timing (5V devices)
Symbol Parameter Conditions -70 -90 -15 Turbo
Off Unit
Min Max Min Max Min Max
tAVQV–PA Address Valid to Data
Valid (Note 3)37 39 45 + 10 ns
tSLQV–PA CSI Valid to Data Valid 27 35 45 + 10 ns
tRLQV–PA RD to Data Valid (Notes 1,4)21 32 40 ns
RD to Data Valid 8031 Mode 32 38 45 ns
tDVQV–PA Data In to Data Out Valid 22 30 38 ns
tQXRH–PA RD Data Hold Time 0 0 0 ns
tRLRH–PA RD Pulse Width (Note 1)27 32 38 ns
tRHQZ–PA RD to Data High-Z (Note 1)23 25 30 ns
tQXRH (PA)
tRLQV (PA)
tRLRH (PA)
tDVQV (PA)
tRHQZ (PA)
tSLQV (PA)
tAVQV (PA)
ADDRESS DATA VALID
ALE/AS
A/D BUS
RD
DATA ON PORT A
CSI
AI02897
91/103
PSD8XXF2/3/4/5
Table 61. Port A Peripheral Data Mode READ Timing (3V devices)
Symbol Parameter Conditions -12 -15 -20 Turbo
Off Unit
Min Max Min Max Min Max
tAVQV–PA Address Valid to Data Valid (Note 3)50 50 50 + 20 ns
tSLQV–PA CSI Valid to Data Valid 37 45 50 + 20 ns
tRLQV–PA RD to Data Valid (Notes 1,4)37 40 45 ns
RD to Data Valid 8031 Mode 45 45 50 ns
tDVQV–PA Data In to Data Out Valid 38 40 45 ns
tQXRH–PA RD Data Hold Time 0 0 0 ns
tRLRH–PA RD Pulse Width (Note 1)36 36 46 ns
tRHQZ–PA RD to Data High-Z (Note 1)36 40 45 ns
PSD8XXF2/3/4/5
92/103
Figure 45. Peripheral I/O WRITE Timing
Table 62. Port A Peripheral Data Mode WRITE Timing (5V devices)
Note: 1. RD has the sam e t i m i n g as DS , LDS, U D S, and PSEN (in 8031 combined mode).
2. WR has the same timing as the E, LDS, UD S, WRL, and WRH signals.
3. Any input use d to select Port A Data Peripheral mode.
4. Data i s alrea dy stab le on Port A.
5. Data stable on ADIO pins to data on Port A.
Table 63. Port A Peripheral Data Mode WRITE Timing (3V devices)
Note: 1. RD has the sam e t i m i n g as DS , LDS, U D S, and PSEN (in 8031 combined mode).
2. WR has the same timing as the E, LDS, UD S, WRL, and WRH signals.
3. Any input use d to select Port A Data Peripheral mode.
4. Data i s alrea dy stab le on Port A.
5. Data stable on ADIO pins to data on Port A.
Symbol Parameter Conditions -70 -90 -15 Unit
Min Max Min Max Min Max
tWLQV–PA WR to Data Propagation Delay (Note 2)25 35 40 ns
tDVQV–PA Data to Port A Data Propagation Delay (Note 5)22 30 38 ns
tWHQZ–PA WR Invalid to Port A Tri-state (Note 2)20 25 33 ns
Symbol Parameter Conditions -12 -15 -20 Unit
Min Max Min Max Min Max
tWLQV–PA WR to Data Propagation Delay (Note 2)42 45 55 ns
tDVQV–PA Data to Port A Data Propagation Delay (Note 5)38 40 45 ns
tWHQZ–PA WR Invalid to Port A Tri-state (Note 2)33 33 35 ns
tDVQV (PA)
tWLQV (PA) tWHQZ (PA)
ADDRESS DATA OUT
A/ D BUS
WR
PORT A
DATA OUT
ALE/AS
AI02898
93/103
PSD8XXF2/3/4/5
Figure 46. Reset (RESET) Timing
Table 64. Reset (RESET) Timing (5V devices)
No te: 1. Reset (RESET ) does not re set Flash m em ory Pr ogram or Er ase cycl es.
2. Warm reset abo rts Flash m emory Pr ogram or Erase cycles, an d puts the device in RE A D M ode.
Table 65. Reset (RESET) Timing (3V devices)
No te: 1. Reset (RESET ) does not re set Flash m em ory Pr ogram or Er ase cycl es.
2. Warm reset abo rts Flash m emory Pr ogram or Erase cycles, an d puts the device in RE A D M ode.
Table 66. VSTBYON Ti ming (5V devic es)
Note: 1. VSTBYON timing is measured at VCC ramp rate of 2 ms.
Table 67. VSTBYON Ti ming (3V devic es)
Note: 1. VSTBYON timing is measured at VCC ramp rate of 2 ms.
Symbol Parameter Conditions Min Max Unit
tNLNH RESET Active Low Time 1150 ns
tNLNH–PO Power On Reset Active Low Time 1 ms
tNLNH–A Warm Reset (on the PSD834Fx) 225 µs
tOPR RESET High to Operational Device 120 ns
Symbol Parameter Conditions Min Max Unit
tNLNH RESET Active Low Time 1300 ns
tNLNH–PO Power On Reset Active Low Time 1 ms
tNLNH–A Warm Reset (on the PSD834Fx) 225 µs
tOPR RESET High to Operational Device 300 ns
Symbol Parameter Conditions Min Typ Max Unit
tBVBH VSTBY Detection to VSTBYON Output High (Note 1)20 µs
tBXBL VSTBY Off Detection to VSTBYON Output
Low (Note 1)20 µs
Symbol Parameter Conditions Min Typ Max Unit
tBVBH VSTBY Detection to VSTBYON Output High (Note 1)20 µs
tBXBL VSTBY Off Detection to VSTBYON Output
Low (Note 1)20 µs
tNLNH-PO tOPR
AI02866b
RESET
tNLNH
tNLNH-A tOPR
VCC VCC(min)
Power-On Reset Warm Reset
PSD8XXF2/3/4/5
94/103
Figure 47. ISC Timing
Table 68. ISC Tim ing (5V devices)
No te : 1. For no n-PLD P rogram ming, E rase or in IS C by-pass mode.
2. For Program or Erase PLD only.
Symbol Parameter Conditions -70 -90 -15 Unit
Min Max Min Max Min Max
tISCCF Clock (TCK, PC1) Frequency (except for
PLD) (Note 1)20 18 14 MHz
tISCCH Clock (TCK, PC1) High Time (except for
PLD) (Note 1)23 26 31 ns
tISCCL Clock (TCK, PC1) Low Time (except for
PLD) (Note 1)23 26 31 ns
tISCCFP Clock (TCK, PC1) Frequency (PLD only) (Note 2)2 2 2 MHz
tISCCHP Clock (TCK, PC1) High Time (PLD only) (Note 2)240 240 240 ns
tISCCLP Clock (TCK, PC1) Low Time (PLD only) (Note 2)240 240 240 ns
tISCPSU ISC Port Set Up Time 7 8 10 ns
tISCPH ISC Port Hold Up Time 5 5 5 ns
tISCPCO ISC Port Clock to Output 21 23 25 ns
tISCPZV ISC Port High-Impedance to Valid Output 21 23 25 ns
tISCPVZ ISC Port Valid Output to
High-Impedance 21 23 25 ns
ISCCH
TCK
TDI/TMS
ISC OUTPUTS/TDO
ISC OUTPUTS/TDO
t
ISCCL
t
ISCPH
t
ISCPSU
t
ISCPVZ
t
ISCPZV
tISCPCO
t
AI02865
95/103
PSD8XXF2/3/4/5
Table 69. ISC Tim ing (3 V device s)
No te : 1. For no n-PLD P rogram ming, E rase or in IS C by-pass mode.
2. For Program or Erase PLD only.
Table 70. Power-d ow n Timing (5V devices)
Note: 1. tCLCL is the period of CLKIN (PD1).
Table 71. Power-d ow n Timing (3V devices)
Note: 1. tCLCL is the period of CLKIN (PD1).
Symbol Parameter Conditions -12 -15 -20 Unit
Min Max Min Max Min Max
tISCCF Clock (TCK, PC1) Frequency (except for
PLD) (Note 1)12 10 9 MHz
tISCCH Clock (TCK, PC1) High Time (except for
PLD) (Note 1)40 45 51 ns
tISCCL Clock (TCK, PC1) Low Time (except for
PLD) (Note 1)40 45 51 ns
tISCCFP Clock (TCK, PC1) Frequency (PLD only) (Note 2)2 2 2 MHz
tISCCHP Clock (TCK, PC1) High Time (PLD only) (Note 2)240 240 240 ns
tISCCLP Clock (TCK, PC1) Low Time (PLD only) (Note 2)240 240 240 ns
tISCPSU ISC Port Set Up Time 12 13 15 ns
tISCPH ISC Port Hold Up Time 5 5 5 ns
tISCPCO ISC Port Clock to Output 30 36 40 ns
tISCPZV ISC Port High-Impedance to Valid Output 30 36 40 ns
tISCPVZ ISC Port Valid Output to
High-Impedance 30 36 40 ns
Symbol Parameter Conditions -70 -90 -15 Unit
Min Max Min Max Min Max
tLVDV ALE Access Time from Power-down 80 90 150 ns
tCLWH Maximum Delay from
APD Enable to Internal PDN Valid
Signal
Using CLKIN
(PD1) 15 * tCLCL1µs
Symbol Parameter Conditions -12 -15 -20 Unit
Min Max Min Max Min Max
tLVDV ALE Access Time from Power-down 145 150 200 ns
tCLWH Maximum Delay from APD Enable to
Internal PDN Valid Signal Using CLKIN
(PD1) 15 * tCLCL1µs
PSD8XXF2/3/4/5
96/103
PACKAGE MECHANICAL
Figure 48. PQFP52 Connections Figure 49. PLCC52 Connections
Figure 50. PQF P52 - 52-pin Plastic, Quad, Flat Package M echanical Drawing
Not e: Drawing is not to scale.
39 AD15
38 AD14
37 AD13
36 AD12
35 AD11
34 AD10
33 AD9
32 AD8
31 VCC
30 AD7
29 AD6
28 AD5
27 AD4
PD2
PD1
PD0
PC7
PC6
PC5
PC4
VCC
GND
PC3
PC2
PC1
PC0
1
2
3
4
5
6
7
8
9
10
11
12
13
52
51
50
49
48
47
46
45
44
43
42
41
40
PB0
PB1
PB2
PB3
PB4
PB5
GND
PB6
PB7
CNTL1
CNTL2
RESET
CNTLO
14
15
16
17
18
19
20
21
22
23
24
25
26
PA7
PA6
PA5
PA4
PA3
GND
PA2
PA1
PA0
AD0
AD1
AD2
AD3
AI02858
PB0
PB1
PB2
PB3
PB4
PB5
GND
PB6
PB7
CNTL1
CNTL2
RESET
CNTL0
PA7
PA6
PA5
PA4
PA3
GND
PA2
PA1
PA0
AD0
AD1
AD2
AD3
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
VCC
AD7
AD6
AD5
AD4
PD2
PD1
PD0
PC7
PC6
PC5
PC4
VCC
GND
PC3
PC2
PC1
PC0
8
9
10
11
12
13
14
15
16
17
18
19
20
46
45
44
43
42
41
40
39
38
37
36
35
34
21
22
23
24
25
26
27
28
29
30
31
32
33
47
48
49
50
51
52
1
2
3
4
5
6
7
AI02857
QFP-A
Nd
E1
CP
b
e
A2
A
N
LA1 α
D1
D
1
E
Ne
c
D2
E2
L1
97/103
PSD8XXF2/3/4/5
Table 72. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Dimensions
Symb. mm inches
Typ. Min. Max. Typ. Min. Max.
A 2.35 0.093
A1 0.25 0.010
A2 2.00 1.80 2.10 0.079 0.077 0.083
b 0.22 0.38 0.009 0.015
c 0.11 0.23 0.004 0.009
D 13.20 13.15 13.25 0.520 0.518 0.522
D1 10.00 9.95 10.05 0.394 0.392 0.396
D2 7.80 – – 0.307 – –
E 13.20 13.15 13.25 0.520 0.518 0.522
E1 10.00 9.95 10.05 0.394 0.392 0.396
E2 7.80 – – 0.307 – –
e 0.65 – – 0.026
L 0.88 0.73 1.03 0.035 0.029 0.041
L1 1.60 – – 0.063
α0° 7° 0° 7°
N52 52
Nd 13 13
Ne 13 13
CP 0.10 0.004
PSD8XXF2/3/4/5
98/103
Figure 51. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechan ical Draw ing
Not e: Drawing is not to scale.
Table 73. PLCC52 - 52-lead Plasti c Lead, Chip Carrier Package Mechanical Dimensi ons
Symbol mm inches
Typ. Min. Max. Typ. Min. Max.
A 4.19 4.57 0.165 0.180
A1 2.54 2.79 0.100 0.110
A2 – 0.91 – 0.036
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
C 0.246 0.261 0.0097 0.0103
D 19.94 20.19 0.785 0.795
D1 19.05 19.15 0.750 0.754
D2 17.53 18.54 0.690 0.730
E 19.94 20.19 0.785 0.795
E1 19.05 19.15 0.750 0.754
E2 17.53 18.54 0.690 0.730
e 1.27 – – 0.050 – –
R 0.89 – – 0.035 – –
N52 52
Nd 13 13
Ne 13 13
PLCC-B
D
E1 E
1 N
D1
CP
b
D2/E2 e
b1
A1
A
A2
D3/E3
M
L1
L
C
M1
99/103
PSD8XXF2/3/4/5
PART NUMBERING
Table 74. Ordering Information Scheme
For a list of available options (e.g., speed, package) or for further information on any aspect of this devic e,
please contact your nearest ST Sales Office.
Example: PSD8 1 3 F 2 V – 15 J 1 T
Device Type
PSD8 = 8-bit PSD with Register Logic
PSD9 = 8-bit PSD with Combinatorial Logic
SRAM Capacity
1 = 16 Kbit
3 = 64 Kbit
5 = 256 Kbit
Flash Memory Capacity
3 = 1 Mbit (128K x 8)
4 = 2 Mbit (256K x 8)
2nd Flash Memory
2 = 256 Kbit Flash memory + SRAM
3 = SRAM but no Flash memory
4 = 256 Kbit Flash memory but no SRAM
5 = no Flash memory + no SRAM
Operating Voltage
blank = VCC = 4.5 to 5.5V
V = VCC = 3.0 to 3.6V
Speed
70 = 70ns
90 = 90ns
12 = 120ns
15 = 150ns
20 = 200ns
Package
J = PLCC52
M = PQFP52
Tempera ture Rang e
blank = 0 to 70°C (commercial)
I = –40 to 85°C (industrial)
Option
T = Tape & Reel Packing
PSD8XXF2/3/4/5
100/103
APPENDIX A. PQFP52 PIN ASSIGNMENTS
Table 75. PQFP52 Connection s (Figur e 48)
Pin Number Pin Assignments
1 PD2
2 PD1
3 PD0
4 PC7
5 PC6
6 PC5
7 PC4
8VCC
9 GND
10 PC3
11 PC2
12 PC1
13 PC0
14 PA7
15 PA6
16 PA5
17 PA4
18 PA3
19 GND
20 PA2
21 PA1
22 PA0
23 AD0
24 AD1
25 AD2
Pin Number Pin Assignments
26 AD3
27 AD4
30 AD5
31 AD6
32 AD7
33 VCC
34 AD8
35 AD9
36 AD10
37 AD11
38 AD12
39 AD13
40 AD14
41 AD15
42 CNTL2
43 CNTL1
44 PB7
45 PB6
46 GND
47 PB5
48 PB4
49 PB3
50 PB2
51 PB1
52 PB0
101/103
PSD8XXF2/3/4/5
APPENDIX B. PLCC52 PIN ASSIGNMENTS
Table 76. PLCC52 Connection s (Figure 49)
Pin Number Pin Assignments
1GND
2PB5
3PB4
4PB3
5PB2
6PB1
7PB0
8PD2
9PD1
10 PD0
11 PC7
12 PC6
13 PC5
14 PC4
15 VCC
16 GND
17 PC3
18 PC2 (VSTBY)
19 PC1
20 PC0
21 PA7
22 PA6
23 PA5
24 PA4
25 PA3
26 GND
Pin Number Pin Assignments
27 PA2
28 PA1
29 PA0
30 AD0
31 AD1
32 AD2
33 AD3
34 AD4
35 AD5
36 AD6
37 AD7
38 VCC
39 AD8
40 AD9
41 AD10
42 AD11
43 AD12
44 AD13
45 AD14
46 AD15
47 CNTL0
48 RESET
49 CNTL2
50 CNTL1
51 PB7
52 PB6
PSD8XXF2/3/4/5
102/103
RE VISION HISTORY
Table 77. Document Revisio n History
Date Rev. Description of Revision
15-Oct-99 1.0 Initial release as a WSI document
27-Oct-00 1.1 Port A Peripheral Data Mode Read Timing, changed to 50
30-Nov-00 1.2 PSD85xF2 added
23-Oct-01 2.0 Document rewritten using the ST template
07-Apr-03 3.0 v2.2 Template applied; voltage correction (Table 74)
103/103
PSD8XXF2/3/4/5
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