September 1995
Revised April 1999
74VHC112 Dual J-K Flip-Flops with Preset and Clear
© 1999 Fairchild Semicond uctor Corpor ation DS012123.prf www.fairchildsemi.com
74VHC112
Dual J-K Flip-Flops with Preset and Clear
General Descript ion
The VHC112 is an advanced high speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation.
The VHC1 12 contains two independent, high-speed JK flip-
flops with Direct Set and Clear inputs. Synchronous state
changes are initiate d by the falling edge of the clock. Trig-
gering occurs at a voltage level of the clock and is not
directly related to transition time. The J and K inputs can
change when the clock is in either state without affecting
the flip-f lop, p ro vi ded tha t th ey ar e in the desir ed s t ate du r-
ing the r ecommended setup and hold tim es relative to the
falling edge of the clock. The LOW signal on PR or CLR
prevents cl ocking and forces Q and Q HIGH, respectively.
Simultaneous LOW signals on PR and CLR force both Q
and Q HIGH.
An input protection circuit ensures that 0V to 7V can be
applied to the inp ut pins with out regard to the sup ply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit pr eve nts dev ic e d estr uct ion due to m i sma tche d s upp l y
and input voltages.
Features
■High speed: fMAX = 200 MHz (ty p) at VCC = 5.0V
■Low power dissipation: ICC = 2 µA (max) at TA = 25°C
■High noise immunity: VNIH = VNIL = 28% VCC (min)
■Power down protection is provided on all inputs
■Pin and function compatible with 74HC112
Ordering Code:
Surface m ount pa c k ages are als o availa ble on Ta pe and Reel. Specify by appendi ng the suffix let te r “X” to the or dering co de.
Connection Diagram Pin Descriptions
Order Number Package Number Package Description
74VHC1 12M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74VHC1 12SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC1 12MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC1 12N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
J1, J2, K1, K2Data Inputs
CLK1, CLK2Clock Pulse Inputs (Active Falling Edge)
CLR1, CLR2Direct Clear Inputs (Active LOW)
PR1, PR2Direct Preset Inputs (Active LOW)
Q1, Q2, Q1, Q2Outputs
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74VHC112
Truth Table
H (h) = HIGH Voltage Level
L (l) = LOW Voltage Level
X = Immaterial
= HIGH-to-LOW C loc k Transit ion
Q0 (Q0) = Before HIGH-to-LOW Transition of Clock
Lowe r c as e letters indicate the state of th e ref erenced input o r output one setup time prior t o t he H I GH-to-L OW cloc k tra ns it ion.
Logic Diagram
(One Half S hown)
Inputs Outputs
PR CLR CP JKQ Q
LHXXXHL
HLXXXLH
LLXXXHH
HH
hhQ
0Q0
HH
lhL H
HH
hlH L
HH
llQ
0Q0
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74VHC112
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions (Note 2)
Note 1: Absolute Maximum Ratings are values beyond which the device
may be da maged or ha ve its useful life impaire d. The datab ook specific a-
tions should be met, without exception, to ensure that the system design is
reliable over its pow er supply, temperatu re, and output/input loa ding vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Supply Voltage (VCC) −0.5V to +7.0V
DC In put Voltage ( VIN) −0.5V to +7.0V
DC Output Voltage (VOUT) −0.5V to VCC + 0.5V
Input Diode Current (IIK) −20 mA
Output Diode Current (IOK) ±20 mA
DC Output Current (IOUT) ±25 mA
DC VCC/GND Current (ICC) ±50 mA
Storage Temperature (TSTG) −65°C to +150°C
Lead Temperature (TL)
(Soldering , 10 seconds) 260 °C
Supply Voltage (VCC) 2.0V to +5.5V
Input Voltage (VIN) 0V to +5.5V
Output Voltage (VOUT) 0V to VCC
Operating Temperature (TOPR) −40°C to +85°C
Input Rise and Fall Time (tr, tf)
V
CC = 3.3V ± 0.3V 0 ∼ 100 ns/V
V
CC = 5.0V ± 0.5V 0 ∼ 20 ns/V
Symbol Parameter VCC
(V)
TA = 25°C T
A = −40°C to +85°CUnits Conditions
Min Typ Max Min Max
VIH HIGH Level 2.0 1.50 1.50 V
Input V oltag e 3.0 − 5.5 0.7 VCC 0.7 VCC
VIL LOW Level 2.0 0.50 0.50 V
Input V oltag e 3.0 − 5.5 0.3 VCC 0.3 VCC
VOH HIGH Level 2.0 1.9 2.0 1.9 VIN = VIH IOH = −50 µA
Output Voltage 3.0 2.9 3.0 2.9 V or VIL
4.5 4.4 4.5 4.4
3.0 2.58 2.48 V IOH = −4 mA
4.5 3.94 3.80 IOH = −8 mA
VOL LOW Level 2.0 0.0 0.1 0.1 VIN = VIH IOL = 50 µA
Output Voltage 3.0 0.0 0.1 0.1 V or VIL
4.5 0.0 0.1 0.1
3.0 0.36 0.44 V IOL = 4 mA
4.5 0.36 0.44 IOL = 8 mA
IIN Input Leakage Current 0 − 5.5 ±0.1 ±1.0 µA V
IN = 5.5V or GND
ICC Quiescent Supply Current 5.5 2.0 20.0 µA V
IN = VCC or GND
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74VHC112
AC Electrical Characteristics
Note 3: CPD is defined as th e v alue of th e interna l equivalent capacitance which is calculated fro m t he operating cur rent cons umptio n w it hout loa d. Av erage
operat ing curr ent can be ob ta ined from the equ at ion: ICC (opr.) = CPD * VCC * fIN + ICC/4 (per F/F), and the total CPD when n pcs of the Flip-Flo p operat e c an
be cal cu lated by t he followin g equat ion: CPD (total) = 30 + 14 • n
AC Operating Requirements
Note 4: VCC is 3.3 ± 0.3V or 5.0 ± 0.5V
Symbol Parameter VCC
(V)
TA = 25°C T
A = −40°C to +85°CUnits Conditions
Min Typ Max Min Max
fMAX Maximum Clock 3.3 ± 0.3 110 150 100 MHz CL = 15 pF
Frequency 90 120 80 CL = 50 pF
5.0 ± 0.5 150 200 135 MHz CL = 15 pF
120 185 110 CL = 50 pF
tPLH Propagation Delay 3.3 ± 0.3 8.5 11.0 1.0 13.4 ns CL = 15 pF
tPHL Time (CP to Qn or Qn) 10.0 15.0 1.0 16.5 CL = 50 pF
5.0 ± 0.5 5.1 7.3 1.0 8.8
ns CL = 15 pF
6.3 10.5 1.0 12.0 CL = 50 pF
tPLH Propagation Delay Time 3.3 ± 0.3 6.7 10.2 1.0 11.7 ns CL = 15 pF
tPHL (PR or CLR to Qn or Qn) 9.7 13.5 1.0 15.0 CL = 50 pF
5.0 ± 0.5 4.6 6.7 1.0 8.0
ns CL = 15 pF
6.4 9.5 1.0 11.0 C
L = 50 pF
CIN Input Capacitance 4 10 10 pF VCC = Open
CPD Power Dissipation 18 pF (Note 3)
Capacitance
Symbol Parameter VCC
(Note 4)
(V)
TA = 25°C T
A = −40°C to +85°CUnits
Typ Guaranteed Minimum
tW Minimum Pulse Width 3.3 5.0 5.0 ns
(CP or CLR or PR) 5.0 5.0 5.0
tS Minimum Setup Time 3.3 5.0 5.0 ns
(Jn or Kn to CPn) 5.0 4.0 4.0
tH Minimum Hold Time 3.3 1.0 1.0 ns
(Jn or Kn to CPn) 5.0 1.0 1.0
tREC Minimum Recovery Time 3.3 6.0 6.0 ns
(CLR or PR to CP) 5.0 5.0 5.0
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74VHC112
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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74VHC112
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
74VHC112 Dual J-K Flip-Flops with Preset and Clear
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r syst ems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instruct ions fo r use pr ovi de d in the labe l ing, can be re a-
sonably expected to result in a significant injury to the
user.
2. A criti cal com ponen t in any compo nent o f a l ife supp ort
device or system whose failure to perform can be rea-
sonabl y e xpec ted to c ause th e fa i lure of the li fe s upp or t
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
