Errata SLAZ055B - June 2009 - Revised May 2011 MSP430F41x2 Device Erratasheet 1 Current Version See Appendix A for prior silicon revisions. Rev: CPU4 CPU19 FLASH19 FLASH24 FLASH27 FLL3 LCDA3 LCDA5 TA12 TA16 TA18 TA22 USCI20 USCI22 USCI23 USCI24 USCI25 USCI26 USCI28 USCI30 XOSC5 XOSC8 XOSC9 The checkmark means that the issue is present in the specified revision. MSP430F4132 A MSP430F4152 A Devices 2 Package Markings PM64 LQFP (PM), 64 Pin RGZ48 QFN (RGZ), 48 Pin SLAZ055B - June 2009 - Revised May 2011 Submit Documentation Feedback MSP430F41x2 Device Erratasheet Copyright (c) 2009-2011, Texas Instruments Incorporated 1 Detailed Bug Description 3 www.ti.com Detailed Bug Description CPU4 CPU Module Function PUSH #4, PUSH #8 Description The single operand instruction PUSH cannot use the internal constants (CG) 4 and 8. The other internal constants (0, 1, 2, -1) can be used. The number of clock cycles is different: PUSH #CG uses address mode 00, requiring 3 cycles, 1-word instruction PUSH #4/#8 uses address mode 11, requiring 5 cycles, 2-word instruction Workaround Workaround implemented in assembler. No fix planned. CPU19 CPU Module Function CPUOFF can change register values Description If a CPUOFF command is followed by an instruction with an indirect addressed operand (for example, mov @R8, R9, and RET), an unintentional register-read operation can occur during the wakeup of the CPU. If the unintentional read occurs to a read-sensitive register (for example, UCB0RXBUF or TAIV), which changes its value or the value of other registers (IFGs), the bug leads to lost interrupts or wrong register read values. Workaround Insert a NOP instruction after each CPUOFF instruction. FLASH19 Flash Module Function EEI feature does not work for code execution from RAM Description When the program is executed from RAM, the flash controller EEI feature does not work. The erase cycle is suspended, and the interrupt is serviced, but there is a problem while resuming with the erase cycle. Addresses applied to flash are different from the actual values while resuming erase cycle after ISR execution. Workaround 2 None MSP430F41x2 Device Erratasheet Copyright (c) 2009-2011, Texas Instruments Incorporated SLAZ055B - June 2009 - Revised May 2011 Submit Documentation Feedback Detailed Bug Description www.ti.com FLASH24 Flash Module Function Write or erase emergency exit can cause failures Description When a flash write or erase is abruptly terminated, the following flash accesses by the CPU may be unreliable and result in erroneous code execution. The abrupt termination can be the result of one the following events: 1. The Flash Controller Clock is configured to be sourced by an external crystal. An oscillator fault occurs thus stopping this clock abruptly. or 2. The Emergency Exit bit (EMEX in FCTL3) when set forces a write or an erase operation to be terminated before normal completion. or 3. The Enable Emergency Interrupt Exit bit (EEIEX in FCTL1) when set with GIE = 1 can lead to an interrupt causing an emergency exit during a Flash operation. Workaround 1. Use the internal DCO as the flash controller clock provided from MCLK or SMCLK. or 2. After setting EMEX = 1, wait for a sufficient amount of time before flash is accessed again. or 3. No workaround. Do not use EEIEX bit. FLASH27 Flash Module Function EEI feature can disrupt segment erase Description When a flash segment erase operation is active with EEI feature selected (EEI = 1 in FLCTL1) and GIE = 0, the following can occur: An interrupt event causes the flash erase to be stopped, and the flash controller expects an RETI to resume the erase. Because GIE = 0, interrupts are not serviced and RETI never happens. Workaround * * Do not set bit EEI = 1 when GIE = 0. or Force an RETI instruction during the erase operation during the check for BUSY=1 (FCLTL3). Sample Code: LOOP: SUB_RETI: SLAZ055B - June 2009 - Revised May 2011 Submit Documentation Feedback MOV BIT JMP JNZ R5, 0(R5) #BUSY, &FCTL3 SUB_RETI LOOP PUSH RETI SR ; ; ; ; Dummy write, erase segment test busy bit Force RETI instruction loop while BUSY=1 MSP430F41x2 Device Erratasheet Copyright (c) 2009-2011, Texas Instruments Incorporated 3 Detailed Bug Description www.ti.com FLL3 FLL+ Module Function FLLDx = 11 for /8 may generate an unstable MCLK frequency Description When setting the FLL to higher frequencies using FLLDx = 11 (/8), the output frequency of the FLL may have a larger frequency variation (for example, averaged over 2 seconds) and a lower average output frequency than expected when compared to the other FLLDx bit settings. Workaround None LCDA3 LCD_A Module Function Charge pump voltage Description The charge pump output voltage has an offset of approximately -200 mV. This reduces the LCD voltage levels specified in the data sheet for LCD_A by the same amount and should be accounted for when selecting a charge pump voltage. The following table shows the actual values: LCD_A PARAMETER TEST CONDITIONS VCC MIN VCC(LCD) Supply voltage Charge pump enabled (LCDCPEN = 1; VLCDx > 0000) 2.2 CLCD Capacitor on LCDCAP (see Note 1) Charge pump enabled (LCDCPEN = 1; VLCDx > 0000) 4.7 ICC(LCD) Average supply current (see Note 2) VLCD(typ)=3V; LCDCPEN = 1; VLCDx= 1000, all segments on fLCD= fACLK/32 no LCD connected (see Note 2) TA = 25C fLCD LCD frequency VLCD 2.2 V MAX VLCDx = 0000 VCC VLCDx = 0001 2.50 VLCDx = 0010 2.56 VLCDx = 0011 2.61 VLCDx = 0100 2.67 VLCDx = 0101 2.72 VLCDx = 0110 2.78 VLCDx = 0111 2.83 VLCDx = 1000 2.89 VLCDx = 1001 2.94 VLCDx = 1010 3.00 VLCDx = 1011 3.05 VLCDx = 1100 3.11 VLCDx = 1101 3.16 A VLCD = 3V; LCDCPEN = 1; VLCDx = 1000, ILOAD = 10A kHz V 3.22 VLCDx = 1111 LCD driver output impedance V F 3.8 VLCDx = 1110 UNIT 3.6 1.1 LCD voltage RLCD TYP 3.12 2.2 V 3.27 3.42 10 k NOTES: 1. Enabling the internal charge pump with an external capacitor smaller than the minimum specified might damage the device. 2. Connecting an actual display will increase the current consumption depending on the size of the LCD. Workaround 4 None MSP430F41x2 Device Erratasheet Copyright (c) 2009-2011, Texas Instruments Incorporated SLAZ055B - June 2009 - Revised May 2011 Submit Documentation Feedback Detailed Bug Description www.ti.com LCDA5 LCD_A Module Function Wrong cycle time for first cycle of COMx/Sx signals Description The time of the first cycle of COMx/Sx signals after enabling the LCD_A module is only half of the selected value. All following cycles are correct. Workaround Not required, because it does not influence the LCD function. TA12 Timer_A Module Function Interrupt is lost (slow ACLK) Description Timer_A counter is running with slow clock (external TACLK or ACLK) compared to MCLK. The compare mode is selected for the capture/compare channel and the CCRx register is incremented by one with the occurring compare interrupt (if TAR = CCRx). Due to the fast MCLK, the CCRx register increment (CCRx = CCRx + 1) happens before the Timer_A counter has incremented again. Therefore, the next compare interrupt should happen at once with the next Timer_A counter increment (if TAR = CCRx + 1). This interrupt is lost. Workaround Switch capture/compare mode to capture mode before the CCRx register increment. Switch back to compare mode afterward. TA16 Timer_A Module Function First increment of TAR erroneous when IDx > 00 Description The first increment of TAR after any timer clear event (POR/TACLR) happens immediately following the first positive edge of the selected clock source (INCLK, SMCLK, ACLK, or TACLK). This is independent of the clock input divider settings (ID0, ID1). All following TAR increments are performed correctly with the selected IDx settings. Workaround None TA18 Timer_A Module Function MOV to TACTL may clear TAR Description When TACTL is modified with a MOV instruction, the contents of TAR may be cleared, even when TACLR is not set. Workaround Use BIS or BIC instructions to modify TACTL. NOTE: A DMA transfer must not occur while these BIS and BIC instructions execute. This can be prevented by disabling the DMA prior to these instructions, or by using the DMAONFETCH bit to align DMA transfers to instruction fetch boundaries. SLAZ055B - June 2009 - Revised May 2011 Submit Documentation Feedback MSP430F41x2 Device Erratasheet Copyright (c) 2009-2011, Texas Instruments Incorporated 5 Detailed Bug Description www.ti.com TA22 Timer_A Module Function Timer_A register modification after watchdog timer PUC Description Unwanted modification of the Timer_A registers TACTL and TAIV can occur when a PUC is generated by the watchdog timer (WDT) in watchdog mode and any Timer_A counter register TACCRx is incremented/decremented (Timer_A does not need to be running). Workaround Initialize TACTL register after the reset occurs using a MOV instruction (BIS or BIC may not fully initialize the register). TAIV is automatically cleared following this initialization. Example MOV.W #VAL, &TACTL Where VAL = 0, if Timer is not used in application; otherwise, user defined per desired function. USCI20 USCI Module Function I2C mode multi-master transmitter issue Description When configured for I2C master-transmitter mode and used in a multi-master environment, the USCI module can cause unpredictable bus behavior if all of the following conditions are true: 1. Two masters are generating SCL. and 2. The slave is stretching the SCL low phase of an ACK period while outputting NACK on SDA. and 3. The slave drives ACK on SDA after the USCI has already released SCL, and then the SCL bus line is released. and 4. The transmit buffer has not been loaded before the other master continues communication by driving SCL low. The USCI remains in the SCL high phase until the transmit buffer is written. After the transmit buffer has been written, the USCI interferes with the current bus activity and may cause unpredictable bus behavior. Workaround * * * 6 Ensure that slave does not stretch the SCL low phase of an ACK period. or Ensure that the transmit buffer is loaded in time. or Do not use the multi-master transmitter mode. MSP430F41x2 Device Erratasheet Copyright (c) 2009-2011, Texas Instruments Incorporated SLAZ055B - June 2009 - Revised May 2011 Submit Documentation Feedback Detailed Bug Description www.ti.com USCI22 USCI Module Function I2C master receiver with 10-bit slave addressing Description Unexpected behavior of the USCI_B can occur when configured in I2C master receive mode with 10-bit slave addressing under the following conditions: 1. The USCI sends first byte of slave address, the slave sends an ACK and when second address byte is sent, the slave sends a NACK. 2. Master sends a repeat start condition (if UCTXSTT = 1). 3. The first address byte following the repeated start is acknowledged. However, the second address byte is not sent; instead, the master incorrectly starts to receive data and sets UCBxRXIFG = 1. Workaround Do not use a repeated start condition; instead, set the stop condition UCTXSTP = 1 in the NACK ISR prior to the following start condition (USTXSTT = 1). USCI23 USCI Module Function UART transmit mode with automatic baud rate detection Description Erroneous behavior of the USCI_A can occur when configured in UART transmit mode with automatic baud rate detection. During transmission if a "Transmit break" is initiated (UCTXBRK = 1), the USCI_A does not deliver a stop bit of logic high; instead, it sends a logic low during the subsequent synch period. Workaround * * Follow user's guide instructions for transmitting a break/synch field following UCSWRST = 1. or Set UCTXBRK = 1 before an active transmission; that is, check for bit UCBUSY = 0 and then set UCTXBRK = 1. USCI24 USCI Module Function Incorrect baud rate information during UART automatic baud rate detection mode Description Erroneous behavior of the USCI_A can occur when configured in UART mode with automatic baud rate detection. After automatic baud rate measurement is complete, the UART updates UCAxBR0 and UCAxBR1. Under oversampling mode (UCOS16 = 1), for baud rates that should result in UCAxBRx = 0x0002, the UART incorrectly reports it as UCAxBRx = 0x5555. Workaround When break/synch is detected following the automatic baud rate detection, the flag UCBRK flag is set to 1. Check if UCAxBRx = 0x5555 and correct it to 0x0002. USCI25 USCI Module Function TXIFG is not reset when NACK is received in I2C mode Description When the USCI_B module is configured as an I2C master transmitter, the TXIFG is not reset after a NACK is received if the master is configured to send a restart (UCTXSTT = 1 and UCTXSTP = 0). Workaround Reset TXIFG in software within the NACKIFG interrupt service routine. SLAZ055B - June 2009 - Revised May 2011 Submit Documentation Feedback MSP430F41x2 Device Erratasheet Copyright (c) 2009-2011, Texas Instruments Incorporated 7 Detailed Bug Description www.ti.com USCI26 USCI Module Function tbuf parameter violation in I2C multi-master mode Description In multi-master I2C systems, the timing parameter tbuf (bus free time between a stop condition and the following start) is not ensured to match the I2C specification of 4.7 s in standard mode and 1.3 s in fast mode. If the UCTXSTT bit is set during a running I2C transaction, the USCI module waits and issues the start condition on bus release, causing the violation to occur. NOTE: It is recommended to check if UCBBUSY bit is cleared before setting UCTXSTT = 1. Workaround None USCI28 USCI Module Function Timing of USCI interrupts may cause device reset due to automatic clear of an IFG. Description When certain USCI I2C interrupt flags (IFGs) are set and an automatic flag-clearing event on the I2C bus occurs, it results in an errant ISR call to the reset vector. This happens only when the IFG is cleared within a critical time window (~6 CPU clock cycles) after a USCI interrupt request occurs and before the interrupt servicing is initiated. The affected interrupts are UCBxTXIFG, UCSTPIFG, UCSTTIFG, and UCNACKIFG. The automatic flag-clearing scenarios occur in the following situations: * A pending UCBxTXIFG interrupt request is cleared on the falling SCL clock edge following a NACK. * A pending UCSTPIFG, UCSTTIFG, or UCNACKIFG interrupt request is cleared by a following Start condition. Workaround * * * Poll the affected flags instead of enabling the interrupts. or Ensure the above mentioned flag-clearing events occur after a time delay of 6 CPU clock cycles has elapsed since the interrupt request occurred and was accepted. or At program start, check any applicable enabled IE bits such as UCBxTXIE, UCBxRXIE, UCSTTIE, UCSTPIE, or UCNACKIE for a reset (A PUC clears all of the IE bits of interest). If no PUC occurred, then the device ran into the above mentioned errant condition, and the program counter needs to be restored using an RETI instruction. ; ------- Workaround (3) example for TXIFG -----------NOTE: For assembly code, use code shown here and insert prior to user code. main bit.b #UCBxTXIE ,&IE2 jz start_normal reti start_normal ... 8 ; if TXIE is set, errant call occurred ; if not start main program ; else return from interrupt call ; Application code continues MSP430F41x2 Device Erratasheet Copyright (c) 2009-2011, Texas Instruments Incorporated SLAZ055B - June 2009 - Revised May 2011 Submit Documentation Feedback Detailed Bug Description www.ti.com NOTE: For C code, the workaround needs to be executed prior to the CSTARTUP routine. The steps for modifying the CSTARTUP routine are IDE dependent. Examples for Code Composer and IAR Embedded Workbench are shown. IAR Embedded Workbench 1. The file cstartup.s43 is found at: ...\IAR Systems\<Current Embedded Workbench Version>\430\src\lib\430 2. Create a local copy of this file and link it to the project. Do not rename the file. 3. In the copy, insert the following code prior to stack pointer initialization: #define IE2 (0x0001) BIT.B #0x08,&IE2 ; if TXIE is set, errant call occurred JZ Start_Normal ; if not start main program RETI ; else return from interrupt call // Initialize SP to point to the top of the stack. Start_Normal MOV #SFE(CSTACK), SP // Ensure that main is called. Code Composer 1. The file boot.c is found at ...\Texas Instruments\<Current Code Composer Version> \tools\compiler\MSP430\lib\rtssrc.zip 2. Extract the file from rtssrc.zip and create a local copy. Link the copy to the project. Do not rename this file. 3. In the copy, insert the following code prior to stack pointer initialization: __asm("\t BIT.B\t #0x08,&0x0001"); // if TXIE is set, errant call occurred __asm("\t JZ\t Start_Normal"); // if not start main program __asm("\t RETI"); // else return from interrupt call __asm("Start_Normal"); // insert label /*------------------------------------------------------------------ */ /* Initialize stack pointer. Stack grows toward lower memory*/ /*-------------------------------------------------------------------*/ SLAZ055B - June 2009 - Revised May 2011 Submit Documentation Feedback MSP430F41x2 Device Erratasheet Copyright (c) 2009-2011, Texas Instruments Incorporated 9 Detailed Bug Description www.ti.com USCI30 USCI Module Function I2C mode master receiver / slave receiver Description The USCI I2C module, when configured as a receiver (master or slave), performs a double-buffered receive operation. For example, in a transaction of two bytes, after the first byte is moved from the receive shift register to the receive buffer, the byte is acknowledged and the state machine allows the reception of the next byte. If the receive buffer has not been cleared of its contents by reading the UCBxRXBUF register by the time the seventh bit of the following data byte is received, an error condition may occur on the I2C bus. Depending on the USCI configuration, the following may occur: * If the USCI is configured as an I2C master receiver, an unintentional repeated start condition can be triggered or the master can switch into an idle state (I2C communication aborted). The reception of the current data byte is not successful in this case. * If the USCI is configured as I2C slave receiver, the slave can switch to an idle state, stalling I2C communication. The reception of the current data byte is not successful in this case. The USCI I2C state machine notifies the master of the aborted reception with a NACK. Note that the error condition described above occurs only within a limited window of the seventh bit of the current byte being received. If the receive buffer is read outside of this window (before or after), then the error condition does not occur. Workaround The error condition can be avoided by servicing the UCBxRXIFG in a timely manner. This can be done by (a) servicing the interrupt and ensuring UCBxRXBUF is read promptly or (b) using the DMA to automatically read bytes from receive buffer upon UCBxRXIFG being set. OR If the receive buffer cannot be read out in time, test the I2C clock line before the UCBxRXBUF is read out to ensure that the critical window has elapsed. This is done by checking if the clock line low status indicator bit UCSCLLOW is set for at least three USCI bit clock cycles; that is, 3 x tBitClock. NOTE: The last byte of the transaction must be read directly from UCBxRXBUF. For all other bytes, follow the workaround. Code flow for workaround: 1. Enter RX ISR for reading receiving bytes 2. Check if UCSCLLOW.UCBxSTAT == 1 3. If no, repeat step 2 until set. 4. If yes, repeat step 2 for a time period > 3 x tBitClock, where tBitClock = 1/ fBitClock 5. If window of 3 x tBitClock cycles has elapsed, it is safe to read UCBxRXBUF. 10 MSP430F41x2 Device Erratasheet Copyright (c) 2009-2011, Texas Instruments Incorporated SLAZ055B - June 2009 - Revised May 2011 Submit Documentation Feedback Detailed Bug Description www.ti.com XOSC5 LFXT1 Module Function LF crystal failures may not be properly detected by the oscillator fault circuitry Description The oscillator fault error detection of the LFXT1 oscillator in low-frequency mode (XTS = 0) may not work reliably, causing a failing crystal to go undetected by the CPU; that is, OFIFG is not set. Workaround None XOSC8 LFXT1 Module Function ACLK failure when crystal ESR is below 40 k Description When ACLK is sourced by a low-frequency crystal with an ESR below 40 k, the duty cycle of ACLK may fall below the specification; the OFIFG may become set or, in some instances, ACLK may stop completely. Workaround See the application report XOSC8 Guidance (SLAA423) for information regarding working with this erratum. XOSC9 LFXT1 Module Function XT1 oscillator may not function as expected in high-frequency (HF) mode Description XT1 oscillator does not work correctly in high-frequency mode at supply voltages below 2 V with crystal frequency > 4 MHz. Workaround None. When XT1 oscillator is used in HF mode with crystal frequency > 4 MHz, ensure a supply voltage > 2.2 V. SLAZ055B - June 2009 - Revised May 2011 Submit Documentation Feedback MSP430F41x2 Device Erratasheet Copyright (c) 2009-2011, Texas Instruments Incorporated 11 12 MSP430F41x2 Device Erratasheet Copyright (c) 2009-2011, Texas Instruments Incorporated SLAZ055B - June 2009 - Revised May 2011 Submit Documentation Feedback Appendix A www.ti.com Appendix A Prior Revisions None SLAZ055B - June 2009 - Revised May 2011 Submit Documentation Feedback Prior Revisions Copyright (c) 2009-2011, Texas Instruments Incorporated 13 Revision History www.ti.com Revision History Changes from A Revision (January 2010) to B Revision ............................................................................................... Page * * Changed FLASH24 ...................................................................................................................... 3 Added USCI30 .......................................................................................................................... 10 NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 14 Revision History Copyright (c) 2009-2011, Texas Instruments Incorporated SLAZ055B - June 2009 - Revised May 2011 Submit Documentation Feedback IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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